target/linux/ramips/patches-3.10/0016-MIPS-ralink-mt7620-fix-usb-issue-during-frequency-sc.patch

   1 From 011f4bdba0dd4d1dff6d33b1a65541fc4f09c78e Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Fri, 24 May 2013 21:28:08 +0200
   4 Subject: [PATCH 16/25] MIPS: ralink: mt7620: fix usb issue during frequency
   5  scaling
   6
   7 If the USB HCD is running and the cpu is scaled too low, then the USB stops
   8 working. Increase the idle speed of the core to fix this if the kernel is
   9 built with USB support.
  10
  11 The values are taken from the Ralink SDK Kernel.
  12
  13 Signed-off-by: John Crispin <blogic@openwrt.org>
  14 ---
  15  arch/mips/include/asm/mach-ralink/mt7620.h |    1 +
  16  arch/mips/ralink/mt7620.c                  |   19 +++++++++++++++++++
  17  2 files changed, 20 insertions(+)
  18
  19 --- a/arch/mips/include/asm/mach-ralink/mt7620.h
  20 +++ b/arch/mips/include/asm/mach-ralink/mt7620.h
  21 @@ -20,6 +20,7 @@
  22  #define SYSC_REG_CHIP_REV              0x0c
  23  #define SYSC_REG_SYSTEM_CONFIG0                0x10
  24  #define SYSC_REG_SYSTEM_CONFIG1                0x14
  25 +#define SYSC_REG_CPU_SYS_CLKCFG                0x3c
  26  #define SYSC_REG_CPLL_CONFIG0          0x54
  27  #define SYSC_REG_CPLL_CONFIG1          0x58
  28
  29 --- a/arch/mips/ralink/mt7620.c
  30 +++ b/arch/mips/ralink/mt7620.c
  31 @@ -20,6 +20,12 @@
  32
  33  #include "common.h"
  34
  35 +/* clock scaling */
  36 +#define CLKCFG_FDIV_MASK       0x1f00
  37 +#define CLKCFG_FDIV_USB_VAL    0x0300
  38 +#define CLKCFG_FFRAC_MASK      0x001f
  39 +#define CLKCFG_FFRAC_USB_VAL   0x0003
  40 +
  41  /* does the board have sdram or ddram */
  42  static int dram_type;
  43
  44 @@ -170,6 +176,19 @@ void __init ralink_clk_init(void)
  45         ralink_clk_add("10000500.uart", 40000000);
  46         ralink_clk_add("10000b00.spi", 40000000);
  47         ralink_clk_add("10000c00.uartlite", 40000000);
  48 +
  49 +       if (IS_ENABLED(CONFIG_USB)) {
  50 +               /*
  51 +                * When the CPU goes into sleep mode, the BUS clock will be too low for
  52 +                * USB to function properly
  53 +                */
  54 +               u32 val = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
  55 +
  56 +               val &= ~(CLKCFG_FDIV_MASK | CLKCFG_FFRAC_MASK);
  57 +               val |= CLKCFG_FDIV_USB_VAL | CLKCFG_FFRAC_USB_VAL;
  58 +
  59 +               rt_sysc_w32(val, SYSC_REG_CPU_SYS_CLKCFG);
  60 +       }
  61  }
  62
  63  void __init ralink_of_remap(void)