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ralink: add missing header file to mt7530 driver
[openwrt/openwrt.git] / target / linux / ramips / patches-3.10 / 0111-NET-MIPS-add-ralink-SoC-ethernet-driver.patch
1 From ad11aedcc16574c0b3d3f5e40c67227d1846b94e Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Mon, 22 Apr 2013 23:20:03 +0200
4 Subject: [PATCH 16/33] NET: MIPS: add ralink SoC ethernet driver
5
6 Add support for Ralink FE and ESW.
7
8 Signed-off-by: John Crispin <blogic@openwrt.org>
9 ---
10 .../include/asm/mach-ralink/rt305x_esw_platform.h | 27 +
11 arch/mips/ralink/rt305x.c | 1 +
12 drivers/net/ethernet/Kconfig | 1 +
13 drivers/net/ethernet/Makefile | 1 +
14 drivers/net/ethernet/ralink/Kconfig | 31 +
15 drivers/net/ethernet/ralink/Makefile | 18 +
16 drivers/net/ethernet/ralink/esw_rt3052.c | 1463 ++++++++++++++++++++
17 drivers/net/ethernet/ralink/esw_rt3052.h | 32 +
18 drivers/net/ethernet/ralink/gsw_mt7620a.c | 1027 ++++++++++++++
19 drivers/net/ethernet/ralink/gsw_mt7620a.h | 29 +
20 drivers/net/ethernet/ralink/mdio.c | 245 ++++
21 drivers/net/ethernet/ralink/mdio.h | 29 +
22 drivers/net/ethernet/ralink/mdio_rt2880.c | 232 ++++
23 drivers/net/ethernet/ralink/mdio_rt2880.h | 26 +
24 drivers/net/ethernet/ralink/ralink_soc_eth.c | 735 ++++++++++
25 drivers/net/ethernet/ralink/ralink_soc_eth.h | 374 +++++
26 drivers/net/ethernet/ralink/soc_mt7620.c | 111 ++
27 drivers/net/ethernet/ralink/soc_rt2880.c | 51 +
28 drivers/net/ethernet/ralink/soc_rt305x.c | 113 ++
29 drivers/net/ethernet/ralink/soc_rt3883.c | 60 +
30 20 files changed, 4606 insertions(+)
31 create mode 100644 arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h
32 create mode 100644 drivers/net/ethernet/ralink/Kconfig
33 create mode 100644 drivers/net/ethernet/ralink/Makefile
34 create mode 100644 drivers/net/ethernet/ralink/esw_rt3052.c
35 create mode 100644 drivers/net/ethernet/ralink/esw_rt3052.h
36 create mode 100644 drivers/net/ethernet/ralink/gsw_mt7620a.c
37 create mode 100644 drivers/net/ethernet/ralink/gsw_mt7620a.h
38 create mode 100644 drivers/net/ethernet/ralink/mdio.c
39 create mode 100644 drivers/net/ethernet/ralink/mdio.h
40 create mode 100644 drivers/net/ethernet/ralink/mdio_rt2880.c
41 create mode 100644 drivers/net/ethernet/ralink/mdio_rt2880.h
42 create mode 100644 drivers/net/ethernet/ralink/ralink_soc_eth.c
43 create mode 100644 drivers/net/ethernet/ralink/ralink_soc_eth.h
44 create mode 100644 drivers/net/ethernet/ralink/soc_mt7620.c
45 create mode 100644 drivers/net/ethernet/ralink/soc_rt2880.c
46 create mode 100644 drivers/net/ethernet/ralink/soc_rt305x.c
47 create mode 100644 drivers/net/ethernet/ralink/soc_rt3883.c
48
49 Index: linux-3.10.13/arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h
50 ===================================================================
51 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
52 +++ linux-3.10.13/arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h 2013-10-08 17:26:47.060172632 +0200
53 @@ -0,0 +1,27 @@
54 +/*
55 + * Ralink RT305x SoC platform device registration
56 + *
57 + * Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
58 + *
59 + * This program is free software; you can redistribute it and/or modify it
60 + * under the terms of the GNU General Public License version 2 as published
61 + * by the Free Software Foundation.
62 + */
63 +
64 +#ifndef _RT305X_ESW_PLATFORM_H
65 +#define _RT305X_ESW_PLATFORM_H
66 +
67 +enum {
68 + RT305X_ESW_VLAN_CONFIG_NONE = 0,
69 + RT305X_ESW_VLAN_CONFIG_LLLLW,
70 + RT305X_ESW_VLAN_CONFIG_WLLLL,
71 +};
72 +
73 +struct rt305x_esw_platform_data
74 +{
75 + u8 vlan_config;
76 + u32 reg_initval_fct2;
77 + u32 reg_initval_fpa2;
78 +};
79 +
80 +#endif /* _RT305X_ESW_PLATFORM_H */
81 Index: linux-3.10.13/arch/mips/ralink/rt305x.c
82 ===================================================================
83 --- linux-3.10.13.orig/arch/mips/ralink/rt305x.c 2013-10-08 17:26:43.276172503 +0200
84 +++ linux-3.10.13/arch/mips/ralink/rt305x.c 2013-10-08 17:26:47.060172632 +0200
85 @@ -221,6 +221,7 @@
86 }
87
88 ralink_clk_add("cpu", cpu_rate);
89 + ralink_clk_add("sys", sys_rate);
90 ralink_clk_add("10000b00.spi", sys_rate);
91 ralink_clk_add("10000100.timer", wdt_rate);
92 ralink_clk_add("10000120.watchdog", wdt_rate);
93 Index: linux-3.10.13/drivers/net/ethernet/Kconfig
94 ===================================================================
95 --- linux-3.10.13.orig/drivers/net/ethernet/Kconfig 2013-10-08 17:26:43.276172503 +0200
96 +++ linux-3.10.13/drivers/net/ethernet/Kconfig 2013-10-08 17:26:47.064172635 +0200
97 @@ -135,6 +135,7 @@
98 source "drivers/net/ethernet/packetengines/Kconfig"
99 source "drivers/net/ethernet/pasemi/Kconfig"
100 source "drivers/net/ethernet/qlogic/Kconfig"
101 +source "drivers/net/ethernet/ralink/Kconfig"
102 source "drivers/net/ethernet/realtek/Kconfig"
103 source "drivers/net/ethernet/renesas/Kconfig"
104 source "drivers/net/ethernet/rdc/Kconfig"
105 Index: linux-3.10.13/drivers/net/ethernet/Makefile
106 ===================================================================
107 --- linux-3.10.13.orig/drivers/net/ethernet/Makefile 2013-10-08 17:26:43.276172503 +0200
108 +++ linux-3.10.13/drivers/net/ethernet/Makefile 2013-10-08 17:26:47.064172635 +0200
109 @@ -53,6 +53,7 @@
110 obj-$(CONFIG_NET_PACKET_ENGINE) += packetengines/
111 obj-$(CONFIG_NET_VENDOR_PASEMI) += pasemi/
112 obj-$(CONFIG_NET_VENDOR_QLOGIC) += qlogic/
113 +obj-$(CONFIG_NET_RALINK) += ralink/
114 obj-$(CONFIG_NET_VENDOR_REALTEK) += realtek/
115 obj-$(CONFIG_SH_ETH) += renesas/
116 obj-$(CONFIG_NET_VENDOR_RDC) += rdc/
117 Index: linux-3.10.13/drivers/net/ethernet/ralink/Kconfig
118 ===================================================================
119 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
120 +++ linux-3.10.13/drivers/net/ethernet/ralink/Kconfig 2013-10-08 17:26:47.064172635 +0200
121 @@ -0,0 +1,31 @@
122 +config NET_RALINK
123 + tristate "Ralink RT288X/RT3X5X/RT3662/RT3883/MT7620 ethernet driver"
124 + depends on RALINK
125 + help
126 + This driver supports the ethernet mac inside the ralink wisocs
127 +
128 +if NET_RALINK
129 +
130 +config NET_RALINK_MDIO
131 + def_bool NET_RALINK
132 + depends on (SOC_RT288X || SOC_RT3883 || SOC_MT7620)
133 + select PHYLIB
134 +
135 +config NET_RALINK_MDIO_RT2880
136 + def_bool NET_RALINK
137 + depends on (SOC_RT288X || SOC_RT3883)
138 + select NET_RALINK_MDIO
139 +
140 +config NET_RALINK_ESW_RT3052
141 + def_bool NET_RALINK
142 + depends on SOC_RT305X
143 + select PHYLIB
144 + select SWCONFIG
145 +
146 +config NET_RALINK_GSW_MT7620
147 + def_bool NET_RALINK
148 + depends on SOC_MT7620
149 + select NET_RALINK_MDIO
150 + select PHYLIB
151 + select SWCONFIG
152 +endif
153 Index: linux-3.10.13/drivers/net/ethernet/ralink/Makefile
154 ===================================================================
155 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
156 +++ linux-3.10.13/drivers/net/ethernet/ralink/Makefile 2013-10-08 17:26:47.064172635 +0200
157 @@ -0,0 +1,18 @@
158 +#
159 +# Makefile for the Ralink SoCs built-in ethernet macs
160 +#
161 +
162 +ralink-eth-y += ralink_soc_eth.o
163 +
164 +ralink-eth-$(CONFIG_NET_RALINK_MDIO) += mdio.o
165 +ralink-eth-$(CONFIG_NET_RALINK_MDIO_RT2880) += mdio_rt2880.o
166 +
167 +ralink-eth-$(CONFIG_NET_RALINK_ESW_RT3052) += esw_rt3052.o
168 +ralink-eth-$(CONFIG_NET_RALINK_GSW_MT7620) += gsw_mt7620a.o mt7530.o
169 +
170 +ralink-eth-$(CONFIG_SOC_RT288X) += soc_rt2880.o
171 +ralink-eth-$(CONFIG_SOC_RT305X) += soc_rt305x.o
172 +ralink-eth-$(CONFIG_SOC_RT3883) += soc_rt3883.o
173 +ralink-eth-$(CONFIG_SOC_MT7620) += soc_mt7620.o
174 +
175 +obj-$(CONFIG_NET_RALINK) += ralink-eth.o
176 Index: linux-3.10.13/drivers/net/ethernet/ralink/esw_rt3052.c
177 ===================================================================
178 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
179 +++ linux-3.10.13/drivers/net/ethernet/ralink/esw_rt3052.c 2013-10-08 17:26:47.068172664 +0200
180 @@ -0,0 +1,1463 @@
181 +/*
182 + * This program is free software; you can redistribute it and/or modify
183 + * it under the terms of the GNU General Public License as published by
184 + * the Free Software Foundation; version 2 of the License
185 + *
186 + * This program is distributed in the hope that it will be useful,
187 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
188 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
189 + * GNU General Public License for more details.
190 + *
191 + * You should have received a copy of the GNU General Public License
192 + * along with this program; if not, write to the Free Software
193 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
194 + *
195 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
196 + */
197 +
198 +#include <linux/module.h>
199 +#include <linux/kernel.h>
200 +#include <linux/types.h>
201 +#include <linux/dma-mapping.h>
202 +#include <linux/init.h>
203 +#include <linux/skbuff.h>
204 +#include <linux/etherdevice.h>
205 +#include <linux/ethtool.h>
206 +#include <linux/platform_device.h>
207 +#include <linux/of_device.h>
208 +#include <linux/clk.h>
209 +#include <linux/of_net.h>
210 +#include <linux/of_mdio.h>
211 +
212 +#include <asm/mach-ralink/ralink_regs.h>
213 +
214 +#include "ralink_soc_eth.h"
215 +
216 +#include <linux/ioport.h>
217 +#include <linux/switch.h>
218 +#include <linux/mii.h>
219 +
220 +#include <ralink_regs.h>
221 +#include <asm/mach-ralink/rt305x.h>
222 +#include <asm/mach-ralink/rt305x_esw_platform.h>
223 +
224 +/*
225 + * HW limitations for this switch:
226 + * - No large frame support (PKT_MAX_LEN at most 1536)
227 + * - Can't have untagged vlan and tagged vlan on one port at the same time,
228 + * though this might be possible using the undocumented PPE.
229 + */
230 +
231 +#define RT305X_ESW_REG_ISR 0x00
232 +#define RT305X_ESW_REG_IMR 0x04
233 +#define RT305X_ESW_REG_FCT0 0x08
234 +#define RT305X_ESW_REG_PFC1 0x14
235 +#define RT305X_ESW_REG_ATS 0x24
236 +#define RT305X_ESW_REG_ATS0 0x28
237 +#define RT305X_ESW_REG_ATS1 0x2c
238 +#define RT305X_ESW_REG_ATS2 0x30
239 +#define RT305X_ESW_REG_PVIDC(_n) (0x40 + 4 * (_n))
240 +#define RT305X_ESW_REG_VLANI(_n) (0x50 + 4 * (_n))
241 +#define RT305X_ESW_REG_VMSC(_n) (0x70 + 4 * (_n))
242 +#define RT305X_ESW_REG_POA 0x80
243 +#define RT305X_ESW_REG_FPA 0x84
244 +#define RT305X_ESW_REG_SOCPC 0x8c
245 +#define RT305X_ESW_REG_POC0 0x90
246 +#define RT305X_ESW_REG_POC1 0x94
247 +#define RT305X_ESW_REG_POC2 0x98
248 +#define RT305X_ESW_REG_SGC 0x9c
249 +#define RT305X_ESW_REG_STRT 0xa0
250 +#define RT305X_ESW_REG_PCR0 0xc0
251 +#define RT305X_ESW_REG_PCR1 0xc4
252 +#define RT305X_ESW_REG_FPA2 0xc8
253 +#define RT305X_ESW_REG_FCT2 0xcc
254 +#define RT305X_ESW_REG_SGC2 0xe4
255 +#define RT305X_ESW_REG_P0LED 0xa4
256 +#define RT305X_ESW_REG_P1LED 0xa8
257 +#define RT305X_ESW_REG_P2LED 0xac
258 +#define RT305X_ESW_REG_P3LED 0xb0
259 +#define RT305X_ESW_REG_P4LED 0xb4
260 +#define RT305X_ESW_REG_PXPC(_x) (0xe8 + (4 * _x))
261 +#define RT305X_ESW_REG_P1PC 0xec
262 +#define RT305X_ESW_REG_P2PC 0xf0
263 +#define RT305X_ESW_REG_P3PC 0xf4
264 +#define RT305X_ESW_REG_P4PC 0xf8
265 +#define RT305X_ESW_REG_P5PC 0xfc
266 +
267 +#define RT305X_ESW_LED_LINK 0
268 +#define RT305X_ESW_LED_100M 1
269 +#define RT305X_ESW_LED_DUPLEX 2
270 +#define RT305X_ESW_LED_ACTIVITY 3
271 +#define RT305X_ESW_LED_COLLISION 4
272 +#define RT305X_ESW_LED_LINKACT 5
273 +#define RT305X_ESW_LED_DUPLCOLL 6
274 +#define RT305X_ESW_LED_10MACT 7
275 +#define RT305X_ESW_LED_100MACT 8
276 +/* Additional led states not in datasheet: */
277 +#define RT305X_ESW_LED_BLINK 10
278 +#define RT305X_ESW_LED_ON 12
279 +
280 +#define RT305X_ESW_LINK_S 25
281 +#define RT305X_ESW_DUPLEX_S 9
282 +#define RT305X_ESW_SPD_S 0
283 +
284 +#define RT305X_ESW_PCR0_WT_NWAY_DATA_S 16
285 +#define RT305X_ESW_PCR0_WT_PHY_CMD BIT(13)
286 +#define RT305X_ESW_PCR0_CPU_PHY_REG_S 8
287 +
288 +#define RT305X_ESW_PCR1_WT_DONE BIT(0)
289 +
290 +#define RT305X_ESW_ATS_TIMEOUT (5 * HZ)
291 +#define RT305X_ESW_PHY_TIMEOUT (5 * HZ)
292 +
293 +#define RT305X_ESW_PVIDC_PVID_M 0xfff
294 +#define RT305X_ESW_PVIDC_PVID_S 12
295 +
296 +#define RT305X_ESW_VLANI_VID_M 0xfff
297 +#define RT305X_ESW_VLANI_VID_S 12
298 +
299 +#define RT305X_ESW_VMSC_MSC_M 0xff
300 +#define RT305X_ESW_VMSC_MSC_S 8
301 +
302 +#define RT305X_ESW_SOCPC_DISUN2CPU_S 0
303 +#define RT305X_ESW_SOCPC_DISMC2CPU_S 8
304 +#define RT305X_ESW_SOCPC_DISBC2CPU_S 16
305 +#define RT305X_ESW_SOCPC_CRC_PADDING BIT(25)
306 +
307 +#define RT305X_ESW_POC0_EN_BP_S 0
308 +#define RT305X_ESW_POC0_EN_FC_S 8
309 +#define RT305X_ESW_POC0_DIS_RMC2CPU_S 16
310 +#define RT305X_ESW_POC0_DIS_PORT_M 0x7f
311 +#define RT305X_ESW_POC0_DIS_PORT_S 23
312 +
313 +#define RT305X_ESW_POC2_UNTAG_EN_M 0xff
314 +#define RT305X_ESW_POC2_UNTAG_EN_S 0
315 +#define RT305X_ESW_POC2_ENAGING_S 8
316 +#define RT305X_ESW_POC2_DIS_UC_PAUSE_S 16
317 +
318 +#define RT305X_ESW_SGC2_DOUBLE_TAG_M 0x7f
319 +#define RT305X_ESW_SGC2_DOUBLE_TAG_S 0
320 +#define RT305X_ESW_SGC2_LAN_PMAP_M 0x3f
321 +#define RT305X_ESW_SGC2_LAN_PMAP_S 24
322 +
323 +#define RT305X_ESW_PFC1_EN_VLAN_M 0xff
324 +#define RT305X_ESW_PFC1_EN_VLAN_S 16
325 +#define RT305X_ESW_PFC1_EN_TOS_S 24
326 +
327 +#define RT305X_ESW_VLAN_NONE 0xfff
328 +
329 +#define RT305X_ESW_GSC_BC_STROM_MASK 0x3
330 +#define RT305X_ESW_GSC_BC_STROM_SHIFT 4
331 +
332 +#define RT305X_ESW_GSC_LED_FREQ_MASK 0x3
333 +#define RT305X_ESW_GSC_LED_FREQ_SHIFT 23
334 +
335 +#define RT305X_ESW_POA_LINK_MASK 0x1f
336 +#define RT305X_ESW_POA_LINK_SHIFT 25
337 +
338 +#define RT305X_ESW_PORT_ST_CHG BIT(26)
339 +#define RT305X_ESW_PORT0 0
340 +#define RT305X_ESW_PORT1 1
341 +#define RT305X_ESW_PORT2 2
342 +#define RT305X_ESW_PORT3 3
343 +#define RT305X_ESW_PORT4 4
344 +#define RT305X_ESW_PORT5 5
345 +#define RT305X_ESW_PORT6 6
346 +
347 +#define RT305X_ESW_PORTS_NONE 0
348 +
349 +#define RT305X_ESW_PMAP_LLLLLL 0x3f
350 +#define RT305X_ESW_PMAP_LLLLWL 0x2f
351 +#define RT305X_ESW_PMAP_WLLLLL 0x3e
352 +
353 +#define RT305X_ESW_PORTS_INTERNAL \
354 + (BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT1) | \
355 + BIT(RT305X_ESW_PORT2) | BIT(RT305X_ESW_PORT3) | \
356 + BIT(RT305X_ESW_PORT4))
357 +
358 +#define RT305X_ESW_PORTS_NOCPU \
359 + (RT305X_ESW_PORTS_INTERNAL | BIT(RT305X_ESW_PORT5))
360 +
361 +#define RT305X_ESW_PORTS_CPU BIT(RT305X_ESW_PORT6)
362 +
363 +#define RT305X_ESW_PORTS_ALL \
364 + (RT305X_ESW_PORTS_NOCPU | RT305X_ESW_PORTS_CPU)
365 +
366 +#define RT305X_ESW_NUM_VLANS 16
367 +#define RT305X_ESW_NUM_VIDS 4096
368 +#define RT305X_ESW_NUM_PORTS 7
369 +#define RT305X_ESW_NUM_LANWAN 6
370 +#define RT305X_ESW_NUM_LEDS 5
371 +
372 +#define RT5350_ESW_REG_PXTPC(_x) (0x150 + (4 * _x))
373 +#define RT5350_EWS_REG_LED_POLARITY 0x168
374 +#define RT5350_RESET_EPHY BIT(24)
375 +#define SYSC_REG_RESET_CTRL 0x34
376 +
377 +enum {
378 + /* Global attributes. */
379 + RT305X_ESW_ATTR_ENABLE_VLAN,
380 + RT305X_ESW_ATTR_ALT_VLAN_DISABLE,
381 + RT305X_ESW_ATTR_BC_STATUS,
382 + RT305X_ESW_ATTR_LED_FREQ,
383 + /* Port attributes. */
384 + RT305X_ESW_ATTR_PORT_DISABLE,
385 + RT305X_ESW_ATTR_PORT_DOUBLETAG,
386 + RT305X_ESW_ATTR_PORT_UNTAG,
387 + RT305X_ESW_ATTR_PORT_LED,
388 + RT305X_ESW_ATTR_PORT_LAN,
389 + RT305X_ESW_ATTR_PORT_RECV_BAD,
390 + RT305X_ESW_ATTR_PORT_RECV_GOOD,
391 + RT5350_ESW_ATTR_PORT_TR_BAD,
392 + RT5350_ESW_ATTR_PORT_TR_GOOD,
393 +};
394 +
395 +struct esw_port {
396 + bool disable;
397 + bool doubletag;
398 + bool untag;
399 + u8 led;
400 + u16 pvid;
401 +};
402 +
403 +struct esw_vlan {
404 + u8 ports;
405 + u16 vid;
406 +};
407 +
408 +struct rt305x_esw {
409 + struct device *dev;
410 + void __iomem *base;
411 + int irq;
412 + const struct rt305x_esw_platform_data *pdata;
413 + /* Protects against concurrent register rmw operations. */
414 + spinlock_t reg_rw_lock;
415 +
416 + unsigned char port_map;
417 + unsigned int reg_initval_fct2;
418 + unsigned int reg_initval_fpa2;
419 + unsigned int reg_led_polarity;
420 +
421 +
422 + struct switch_dev swdev;
423 + bool global_vlan_enable;
424 + bool alt_vlan_disable;
425 + int bc_storm_protect;
426 + int led_frequency;
427 + struct esw_vlan vlans[RT305X_ESW_NUM_VLANS];
428 + struct esw_port ports[RT305X_ESW_NUM_PORTS];
429 +
430 +};
431 +
432 +static inline void esw_w32(struct rt305x_esw *esw, u32 val, unsigned reg)
433 +{
434 + __raw_writel(val, esw->base + reg);
435 +}
436 +
437 +static inline u32 esw_r32(struct rt305x_esw *esw, unsigned reg)
438 +{
439 + return __raw_readl(esw->base + reg);
440 +}
441 +
442 +static inline void esw_rmw_raw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
443 + unsigned long val)
444 +{
445 + unsigned long t;
446 +
447 + t = __raw_readl(esw->base + reg) & ~mask;
448 + __raw_writel(t | val, esw->base + reg);
449 +}
450 +
451 +static void esw_rmw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
452 + unsigned long val)
453 +{
454 + unsigned long flags;
455 +
456 + spin_lock_irqsave(&esw->reg_rw_lock, flags);
457 + esw_rmw_raw(esw, reg, mask, val);
458 + spin_unlock_irqrestore(&esw->reg_rw_lock, flags);
459 +}
460 +
461 +static u32 rt305x_mii_write(struct rt305x_esw *esw, u32 phy_addr, u32 phy_register,
462 + u32 write_data)
463 +{
464 + unsigned long t_start = jiffies;
465 + int ret = 0;
466 +
467 + while (1) {
468 + if (!(esw_r32(esw, RT305X_ESW_REG_PCR1) &
469 + RT305X_ESW_PCR1_WT_DONE))
470 + break;
471 + if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
472 + ret = 1;
473 + goto out;
474 + }
475 + }
476 +
477 + write_data &= 0xffff;
478 + esw_w32(esw,
479 + (write_data << RT305X_ESW_PCR0_WT_NWAY_DATA_S) |
480 + (phy_register << RT305X_ESW_PCR0_CPU_PHY_REG_S) |
481 + (phy_addr) | RT305X_ESW_PCR0_WT_PHY_CMD,
482 + RT305X_ESW_REG_PCR0);
483 +
484 + t_start = jiffies;
485 + while (1) {
486 + if (esw_r32(esw, RT305X_ESW_REG_PCR1) &
487 + RT305X_ESW_PCR1_WT_DONE)
488 + break;
489 +
490 + if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
491 + ret = 1;
492 + break;
493 + }
494 + }
495 +out:
496 + if (ret)
497 + printk(KERN_ERR "ramips_eth: MDIO timeout\n");
498 + return ret;
499 +}
500 +
501 +static unsigned esw_get_vlan_id(struct rt305x_esw *esw, unsigned vlan)
502 +{
503 + unsigned s;
504 + unsigned val;
505 +
506 + s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
507 + val = esw_r32(esw, RT305X_ESW_REG_VLANI(vlan / 2));
508 + val = (val >> s) & RT305X_ESW_VLANI_VID_M;
509 +
510 + return val;
511 +}
512 +
513 +static void esw_set_vlan_id(struct rt305x_esw *esw, unsigned vlan, unsigned vid)
514 +{
515 + unsigned s;
516 +
517 + s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
518 + esw_rmw(esw,
519 + RT305X_ESW_REG_VLANI(vlan / 2),
520 + RT305X_ESW_VLANI_VID_M << s,
521 + (vid & RT305X_ESW_VLANI_VID_M) << s);
522 +}
523 +
524 +static unsigned esw_get_pvid(struct rt305x_esw *esw, unsigned port)
525 +{
526 + unsigned s, val;
527 +
528 + s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
529 + val = esw_r32(esw, RT305X_ESW_REG_PVIDC(port / 2));
530 + return (val >> s) & RT305X_ESW_PVIDC_PVID_M;
531 +}
532 +
533 +static void esw_set_pvid(struct rt305x_esw *esw, unsigned port, unsigned pvid)
534 +{
535 + unsigned s;
536 +
537 + s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
538 + esw_rmw(esw,
539 + RT305X_ESW_REG_PVIDC(port / 2),
540 + RT305X_ESW_PVIDC_PVID_M << s,
541 + (pvid & RT305X_ESW_PVIDC_PVID_M) << s);
542 +}
543 +
544 +static unsigned esw_get_vmsc(struct rt305x_esw *esw, unsigned vlan)
545 +{
546 + unsigned s, val;
547 +
548 + s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
549 + val = esw_r32(esw, RT305X_ESW_REG_VMSC(vlan / 4));
550 + val = (val >> s) & RT305X_ESW_VMSC_MSC_M;
551 +
552 + return val;
553 +}
554 +
555 +static void esw_set_vmsc(struct rt305x_esw *esw, unsigned vlan, unsigned msc)
556 +{
557 + unsigned s;
558 +
559 + s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
560 + esw_rmw(esw,
561 + RT305X_ESW_REG_VMSC(vlan / 4),
562 + RT305X_ESW_VMSC_MSC_M << s,
563 + (msc & RT305X_ESW_VMSC_MSC_M) << s);
564 +}
565 +
566 +static unsigned esw_get_port_disable(struct rt305x_esw *esw)
567 +{
568 + unsigned reg;
569 + reg = esw_r32(esw, RT305X_ESW_REG_POC0);
570 + return (reg >> RT305X_ESW_POC0_DIS_PORT_S) &
571 + RT305X_ESW_POC0_DIS_PORT_M;
572 +}
573 +
574 +static void esw_set_port_disable(struct rt305x_esw *esw, unsigned disable_mask)
575 +{
576 + unsigned old_mask;
577 + unsigned enable_mask;
578 + unsigned changed;
579 + int i;
580 +
581 + old_mask = esw_get_port_disable(esw);
582 + changed = old_mask ^ disable_mask;
583 + enable_mask = old_mask & disable_mask;
584 +
585 + /* enable before writing to MII */
586 + esw_rmw(esw, RT305X_ESW_REG_POC0,
587 + (RT305X_ESW_POC0_DIS_PORT_M <<
588 + RT305X_ESW_POC0_DIS_PORT_S),
589 + enable_mask << RT305X_ESW_POC0_DIS_PORT_S);
590 +
591 + for (i = 0; i < RT305X_ESW_NUM_LEDS; i++) {
592 + if (!(changed & (1 << i)))
593 + continue;
594 + if (disable_mask & (1 << i)) {
595 + /* disable */
596 + rt305x_mii_write(esw, i, MII_BMCR,
597 + BMCR_PDOWN);
598 + } else {
599 + /* enable */
600 + rt305x_mii_write(esw, i, MII_BMCR,
601 + BMCR_FULLDPLX |
602 + BMCR_ANENABLE |
603 + BMCR_ANRESTART |
604 + BMCR_SPEED100);
605 + }
606 + }
607 +
608 + /* disable after writing to MII */
609 + esw_rmw(esw, RT305X_ESW_REG_POC0,
610 + (RT305X_ESW_POC0_DIS_PORT_M <<
611 + RT305X_ESW_POC0_DIS_PORT_S),
612 + disable_mask << RT305X_ESW_POC0_DIS_PORT_S);
613 +}
614 +
615 +static void esw_set_gsc(struct rt305x_esw *esw)
616 +{
617 + esw_rmw(esw, RT305X_ESW_REG_SGC,
618 + RT305X_ESW_GSC_BC_STROM_MASK << RT305X_ESW_GSC_BC_STROM_SHIFT,
619 + esw->bc_storm_protect << RT305X_ESW_GSC_BC_STROM_SHIFT);
620 + esw_rmw(esw, RT305X_ESW_REG_SGC,
621 + RT305X_ESW_GSC_LED_FREQ_MASK << RT305X_ESW_GSC_LED_FREQ_SHIFT,
622 + esw->led_frequency << RT305X_ESW_GSC_LED_FREQ_SHIFT);
623 +}
624 +
625 +static int esw_apply_config(struct switch_dev *dev);
626 +
627 +static void esw_hw_init(struct rt305x_esw *esw)
628 +{
629 + int i;
630 + u8 port_disable = 0;
631 + u8 port_map = RT305X_ESW_PMAP_LLLLLL;
632 +
633 + /* vodoo from original driver */
634 + esw_w32(esw, 0xC8A07850, RT305X_ESW_REG_FCT0);
635 + esw_w32(esw, 0x00000000, RT305X_ESW_REG_SGC2);
636 + /* Port priority 1 for all ports, vlan enabled. */
637 + esw_w32(esw, 0x00005555 |
638 + (RT305X_ESW_PORTS_ALL << RT305X_ESW_PFC1_EN_VLAN_S),
639 + RT305X_ESW_REG_PFC1);
640 +
641 + /* Enable Back Pressure, and Flow Control */
642 + esw_w32(esw,
643 + ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_BP_S) |
644 + (RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_FC_S)),
645 + RT305X_ESW_REG_POC0);
646 +
647 + /* Enable Aging, and VLAN TAG removal */
648 + esw_w32(esw,
649 + ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC2_ENAGING_S) |
650 + (RT305X_ESW_PORTS_NOCPU << RT305X_ESW_POC2_UNTAG_EN_S)),
651 + RT305X_ESW_REG_POC2);
652 +
653 + if (esw->reg_initval_fct2)
654 + esw_w32(esw, esw->reg_initval_fct2, RT305X_ESW_REG_FCT2);
655 + else
656 + esw_w32(esw, esw->pdata->reg_initval_fct2, RT305X_ESW_REG_FCT2);
657 +
658 + /*
659 + * 300s aging timer, max packet len 1536, broadcast storm prevention
660 + * disabled, disable collision abort, mac xor48 hash, 10 packet back
661 + * pressure jam, GMII disable was_transmit, back pressure disabled,
662 + * 30ms led flash, unmatched IGMP as broadcast, rmc tb fault to all
663 + * ports.
664 + */
665 + esw_w32(esw, 0x0008a301, RT305X_ESW_REG_SGC);
666 +
667 + /* Setup SoC Port control register */
668 + esw_w32(esw,
669 + (RT305X_ESW_SOCPC_CRC_PADDING |
670 + (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISUN2CPU_S) |
671 + (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISMC2CPU_S) |
672 + (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISBC2CPU_S)),
673 + RT305X_ESW_REG_SOCPC);
674 +
675 + if (esw->reg_initval_fpa2)
676 + esw_w32(esw, esw->reg_initval_fpa2, RT305X_ESW_REG_FPA2);
677 + else
678 + esw_w32(esw, esw->pdata->reg_initval_fpa2, RT305X_ESW_REG_FPA2);
679 + esw_w32(esw, 0x00000000, RT305X_ESW_REG_FPA);
680 +
681 + /* Force Link/Activity on ports */
682 + esw_w32(esw, 0x00000005, RT305X_ESW_REG_P0LED);
683 + esw_w32(esw, 0x00000005, RT305X_ESW_REG_P1LED);
684 + esw_w32(esw, 0x00000005, RT305X_ESW_REG_P2LED);
685 + esw_w32(esw, 0x00000005, RT305X_ESW_REG_P3LED);
686 + esw_w32(esw, 0x00000005, RT305X_ESW_REG_P4LED);
687 +
688 + /* Copy disabled port configuration from bootloader setup */
689 + port_disable = esw_get_port_disable(esw);
690 + for (i = 0; i < 6; i++)
691 + esw->ports[i].disable = (port_disable & (1 << i)) != 0;
692 +
693 + if (soc_is_rt3352()) {
694 + /* reset EPHY */
695 + u32 val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
696 + rt_sysc_w32(val | RT5350_RESET_EPHY, SYSC_REG_RESET_CTRL);
697 + rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
698 +
699 + rt305x_mii_write(esw, 0, 31, 0x8000);
700 + for (i = 0; i < 5; i++) {
701 + if (esw->ports[i].disable) {
702 + rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
703 + } else {
704 + rt305x_mii_write(esw, i, MII_BMCR,
705 + BMCR_FULLDPLX |
706 + BMCR_ANENABLE |
707 + BMCR_SPEED100);
708 + }
709 + /* TX10 waveform coefficient LSB=0 disable PHY */
710 + rt305x_mii_write(esw, i, 26, 0x1601);
711 + /* TX100/TX10 AD/DA current bias */
712 + rt305x_mii_write(esw, i, 29, 0x7016);
713 + /* TX100 slew rate control */
714 + rt305x_mii_write(esw, i, 30, 0x0038);
715 + }
716 +
717 + /* select global register */
718 + rt305x_mii_write(esw, 0, 31, 0x0);
719 + /* enlarge agcsel threshold 3 and threshold 2 */
720 + rt305x_mii_write(esw, 0, 1, 0x4a40);
721 + /* enlarge agcsel threshold 5 and threshold 4 */
722 + rt305x_mii_write(esw, 0, 2, 0x6254);
723 + /* enlarge agcsel threshold */
724 + rt305x_mii_write(esw, 0, 3, 0xa17f);
725 + rt305x_mii_write(esw, 0,12, 0x7eaa);
726 + /* longer TP_IDL tail length */
727 + rt305x_mii_write(esw, 0, 14, 0x65);
728 + /* increased squelch pulse count threshold. */
729 + rt305x_mii_write(esw, 0, 16, 0x0684);
730 + /* set TX10 signal amplitude threshold to minimum */
731 + rt305x_mii_write(esw, 0, 17, 0x0fe0);
732 + /* set squelch amplitude to higher threshold */
733 + rt305x_mii_write(esw, 0, 18, 0x40ba);
734 + /* tune TP_IDL tail and head waveform, enable power down slew rate control */
735 + rt305x_mii_write(esw, 0, 22, 0x253f);
736 + /* set PLL/Receive bias current are calibrated */
737 + rt305x_mii_write(esw, 0, 27, 0x2fda);
738 + /* change PLL/Receive bias current to internal(RT3350) */
739 + rt305x_mii_write(esw, 0, 28, 0xc410);
740 + /* change PLL bias current to internal(RT3052_MP3) */
741 + rt305x_mii_write(esw, 0, 29, 0x598b);
742 + /* select local register */
743 + rt305x_mii_write(esw, 0, 31, 0x8000);
744 + } else if (soc_is_rt5350()) {
745 + /* reset EPHY */
746 + u32 val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
747 + rt_sysc_w32(val | RT5350_RESET_EPHY, SYSC_REG_RESET_CTRL);
748 + rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
749 +
750 + /* set the led polarity */
751 + esw_w32(esw, esw->reg_led_polarity & 0x1F, RT5350_EWS_REG_LED_POLARITY);
752 +
753 + /* local registers */
754 + rt305x_mii_write(esw, 0, 31, 0x8000);
755 + for (i = 0; i < 5; i++) {
756 + if (esw->ports[i].disable) {
757 + rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
758 + } else {
759 + rt305x_mii_write(esw, i, MII_BMCR,
760 + BMCR_FULLDPLX |
761 + BMCR_ANENABLE |
762 + BMCR_SPEED100);
763 + }
764 + /* TX10 waveform coefficient LSB=0 disable PHY */
765 + rt305x_mii_write(esw, i, 26, 0x1601);
766 + /* TX100/TX10 AD/DA current bias */
767 + rt305x_mii_write(esw, i, 29, 0x7015);
768 + /* TX100 slew rate control */
769 + rt305x_mii_write(esw, i, 30, 0x0038);
770 + }
771 +
772 + /* global registers */
773 + rt305x_mii_write(esw, 0, 31, 0x0);
774 + /* enlarge agcsel threshold 3 and threshold 2 */
775 + rt305x_mii_write(esw, 0, 1, 0x4a40);
776 + /* enlarge agcsel threshold 5 and threshold 4 */
777 + rt305x_mii_write(esw, 0, 2, 0x6254);
778 + /* enlarge agcsel threshold 6 */
779 + rt305x_mii_write(esw, 0, 3, 0xa17f);
780 + rt305x_mii_write(esw, 0, 12, 0x7eaa);
781 + /* longer TP_IDL tail length */
782 + rt305x_mii_write(esw, 0, 14, 0x65);
783 + /* increased squelch pulse count threshold. */
784 + rt305x_mii_write(esw, 0, 16, 0x0684);
785 + /* set TX10 signal amplitude threshold to minimum */
786 + rt305x_mii_write(esw, 0, 17, 0x0fe0);
787 + /* set squelch amplitude to higher threshold */
788 + rt305x_mii_write(esw, 0, 18, 0x40ba);
789 + /* tune TP_IDL tail and head waveform, enable power down slew rate control */
790 + rt305x_mii_write(esw, 0, 22, 0x253f);
791 + /* set PLL/Receive bias current are calibrated */
792 + rt305x_mii_write(esw, 0, 27, 0x2fda);
793 + /* change PLL/Receive bias current to internal(RT3350) */
794 + rt305x_mii_write(esw, 0, 28, 0xc410);
795 + /* change PLL bias current to internal(RT3052_MP3) */
796 + rt305x_mii_write(esw, 0, 29, 0x598b);
797 + /* select local register */
798 + rt305x_mii_write(esw, 0, 31, 0x8000);
799 + } else {
800 + rt305x_mii_write(esw, 0, 31, 0x8000);
801 + for (i = 0; i < 5; i++) {
802 + if (esw->ports[i].disable) {
803 + rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
804 + } else {
805 + rt305x_mii_write(esw, i, MII_BMCR,
806 + BMCR_FULLDPLX |
807 + BMCR_ANENABLE |
808 + BMCR_SPEED100);
809 + }
810 + /* TX10 waveform coefficient */
811 + rt305x_mii_write(esw, i, 26, 0x1601);
812 + /* TX100/TX10 AD/DA current bias */
813 + rt305x_mii_write(esw, i, 29, 0x7058);
814 + /* TX100 slew rate control */
815 + rt305x_mii_write(esw, i, 30, 0x0018);
816 + }
817 +
818 + /* PHY IOT */
819 + /* select global register */
820 + rt305x_mii_write(esw, 0, 31, 0x0);
821 + /* tune TP_IDL tail and head waveform */
822 + rt305x_mii_write(esw, 0, 22, 0x052f);
823 + /* set TX10 signal amplitude threshold to minimum */
824 + rt305x_mii_write(esw, 0, 17, 0x0fe0);
825 + /* set squelch amplitude to higher threshold */
826 + rt305x_mii_write(esw, 0, 18, 0x40ba);
827 + /* longer TP_IDL tail length */
828 + rt305x_mii_write(esw, 0, 14, 0x65);
829 + /* select local register */
830 + rt305x_mii_write(esw, 0, 31, 0x8000);
831 + }
832 +
833 + if (esw->port_map)
834 + port_map = esw->port_map;
835 + else
836 + port_map = RT305X_ESW_PMAP_LLLLLL;
837 +
838 + /*
839 + * Unused HW feature, but still nice to be consistent here...
840 + * This is also exported to userspace ('lan' attribute) so it's
841 + * conveniently usable to decide which ports go into the wan vlan by
842 + * default.
843 + */
844 + esw_rmw(esw, RT305X_ESW_REG_SGC2,
845 + RT305X_ESW_SGC2_LAN_PMAP_M << RT305X_ESW_SGC2_LAN_PMAP_S,
846 + port_map << RT305X_ESW_SGC2_LAN_PMAP_S);
847 +
848 + /* make the switch leds blink */
849 + for (i = 0; i < RT305X_ESW_NUM_LEDS; i++)
850 + esw->ports[i].led = 0x05;
851 +
852 + /* Apply the empty config. */
853 + esw_apply_config(&esw->swdev);
854 +
855 + /* Only unmask the port change interrupt */
856 + esw_w32(esw, ~RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_IMR);
857 +}
858 +
859 +static irqreturn_t esw_interrupt(int irq, void *_esw)
860 +{
861 + struct rt305x_esw *esw = (struct rt305x_esw *) _esw;
862 + u32 status;
863 +
864 + status = esw_r32(esw, RT305X_ESW_REG_ISR);
865 + if (status & RT305X_ESW_PORT_ST_CHG) {
866 + u32 link = esw_r32(esw, RT305X_ESW_REG_POA);
867 + link >>= RT305X_ESW_POA_LINK_SHIFT;
868 + link &= RT305X_ESW_POA_LINK_MASK;
869 + dev_info(esw->dev, "link changed 0x%02X\n", link);
870 + }
871 + esw_w32(esw, status, RT305X_ESW_REG_ISR);
872 +
873 + return IRQ_HANDLED;
874 +}
875 +
876 +static int esw_apply_config(struct switch_dev *dev)
877 +{
878 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
879 + int i;
880 + u8 disable = 0;
881 + u8 doubletag = 0;
882 + u8 en_vlan = 0;
883 + u8 untag = 0;
884 +
885 + for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
886 + u32 vid, vmsc;
887 + if (esw->global_vlan_enable) {
888 + vid = esw->vlans[i].vid;
889 + vmsc = esw->vlans[i].ports;
890 + } else {
891 + vid = RT305X_ESW_VLAN_NONE;
892 + vmsc = RT305X_ESW_PORTS_NONE;
893 + }
894 + esw_set_vlan_id(esw, i, vid);
895 + esw_set_vmsc(esw, i, vmsc);
896 + }
897 +
898 + for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {
899 + u32 pvid;
900 + disable |= esw->ports[i].disable << i;
901 + if (esw->global_vlan_enable) {
902 + doubletag |= esw->ports[i].doubletag << i;
903 + en_vlan |= 1 << i;
904 + untag |= esw->ports[i].untag << i;
905 + pvid = esw->ports[i].pvid;
906 + } else {
907 + int x = esw->alt_vlan_disable ? 0 : 1;
908 + doubletag |= x << i;
909 + en_vlan |= x << i;
910 + untag |= x << i;
911 + pvid = 0;
912 + }
913 + esw_set_pvid(esw, i, pvid);
914 + if (i < RT305X_ESW_NUM_LEDS)
915 + esw_w32(esw, esw->ports[i].led,
916 + RT305X_ESW_REG_P0LED + 4*i);
917 + }
918 +
919 + esw_set_gsc(esw);
920 + esw_set_port_disable(esw, disable);
921 + esw_rmw(esw, RT305X_ESW_REG_SGC2,
922 + (RT305X_ESW_SGC2_DOUBLE_TAG_M <<
923 + RT305X_ESW_SGC2_DOUBLE_TAG_S),
924 + doubletag << RT305X_ESW_SGC2_DOUBLE_TAG_S);
925 + esw_rmw(esw, RT305X_ESW_REG_PFC1,
926 + RT305X_ESW_PFC1_EN_VLAN_M << RT305X_ESW_PFC1_EN_VLAN_S,
927 + en_vlan << RT305X_ESW_PFC1_EN_VLAN_S);
928 + esw_rmw(esw, RT305X_ESW_REG_POC2,
929 + RT305X_ESW_POC2_UNTAG_EN_M << RT305X_ESW_POC2_UNTAG_EN_S,
930 + untag << RT305X_ESW_POC2_UNTAG_EN_S);
931 +
932 + if (!esw->global_vlan_enable) {
933 + /*
934 + * Still need to put all ports into vlan 0 or they'll be
935 + * isolated.
936 + * NOTE: vlan 0 is special, no vlan tag is prepended
937 + */
938 + esw_set_vlan_id(esw, 0, 0);
939 + esw_set_vmsc(esw, 0, RT305X_ESW_PORTS_ALL);
940 + }
941 +
942 + return 0;
943 +}
944 +
945 +static int esw_reset_switch(struct switch_dev *dev)
946 +{
947 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
948 +
949 + esw->global_vlan_enable = 0;
950 + memset(esw->ports, 0, sizeof(esw->ports));
951 + memset(esw->vlans, 0, sizeof(esw->vlans));
952 + esw_hw_init(esw);
953 +
954 + return 0;
955 +}
956 +
957 +static int esw_get_vlan_enable(struct switch_dev *dev,
958 + const struct switch_attr *attr,
959 + struct switch_val *val)
960 +{
961 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
962 +
963 + val->value.i = esw->global_vlan_enable;
964 +
965 + return 0;
966 +}
967 +
968 +static int esw_set_vlan_enable(struct switch_dev *dev,
969 + const struct switch_attr *attr,
970 + struct switch_val *val)
971 +{
972 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
973 +
974 + esw->global_vlan_enable = val->value.i != 0;
975 +
976 + return 0;
977 +}
978 +
979 +static int esw_get_alt_vlan_disable(struct switch_dev *dev,
980 + const struct switch_attr *attr,
981 + struct switch_val *val)
982 +{
983 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
984 +
985 + val->value.i = esw->alt_vlan_disable;
986 +
987 + return 0;
988 +}
989 +
990 +static int esw_set_alt_vlan_disable(struct switch_dev *dev,
991 + const struct switch_attr *attr,
992 + struct switch_val *val)
993 +{
994 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
995 +
996 + esw->alt_vlan_disable = val->value.i != 0;
997 +
998 + return 0;
999 +}
1000 +
1001 +static int
1002 +rt305x_esw_set_bc_status(struct switch_dev *dev,
1003 + const struct switch_attr *attr,
1004 + struct switch_val *val)
1005 +{
1006 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1007 +
1008 + esw->bc_storm_protect = val->value.i & RT305X_ESW_GSC_BC_STROM_MASK;
1009 +
1010 + return 0;
1011 +}
1012 +
1013 +static int
1014 +rt305x_esw_get_bc_status(struct switch_dev *dev,
1015 + const struct switch_attr *attr,
1016 + struct switch_val *val)
1017 +{
1018 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1019 +
1020 + val->value.i = esw->bc_storm_protect;
1021 +
1022 + return 0;
1023 +}
1024 +
1025 +static int
1026 +rt305x_esw_set_led_freq(struct switch_dev *dev,
1027 + const struct switch_attr *attr,
1028 + struct switch_val *val)
1029 +{
1030 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1031 +
1032 + esw->led_frequency = val->value.i & RT305X_ESW_GSC_LED_FREQ_MASK;
1033 +
1034 + return 0;
1035 +}
1036 +
1037 +static int
1038 +rt305x_esw_get_led_freq(struct switch_dev *dev,
1039 + const struct switch_attr *attr,
1040 + struct switch_val *val)
1041 +{
1042 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1043 +
1044 + val->value.i = esw->led_frequency;
1045 +
1046 + return 0;
1047 +}
1048 +
1049 +static int esw_get_port_link(struct switch_dev *dev,
1050 + int port,
1051 + struct switch_port_link *link)
1052 +{
1053 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1054 + u32 speed, poa;
1055 +
1056 + if (port < 0 || port >= RT305X_ESW_NUM_PORTS)
1057 + return -EINVAL;
1058 +
1059 + poa = esw_r32(esw, RT305X_ESW_REG_POA) >> port;
1060 +
1061 + link->link = (poa >> RT305X_ESW_LINK_S) & 1;
1062 + link->duplex = (poa >> RT305X_ESW_DUPLEX_S) & 1;
1063 + if (port < RT305X_ESW_NUM_LEDS) {
1064 + speed = (poa >> RT305X_ESW_SPD_S) & 1;
1065 + } else {
1066 + if (port == RT305X_ESW_NUM_PORTS - 1)
1067 + poa >>= 1;
1068 + speed = (poa >> RT305X_ESW_SPD_S) & 3;
1069 + }
1070 + switch (speed) {
1071 + case 0:
1072 + link->speed = SWITCH_PORT_SPEED_10;
1073 + break;
1074 + case 1:
1075 + link->speed = SWITCH_PORT_SPEED_100;
1076 + break;
1077 + case 2:
1078 + case 3: /* forced gige speed can be 2 or 3 */
1079 + link->speed = SWITCH_PORT_SPEED_1000;
1080 + break;
1081 + default:
1082 + link->speed = SWITCH_PORT_SPEED_UNKNOWN;
1083 + break;
1084 + }
1085 +
1086 + return 0;
1087 +}
1088 +
1089 +static int esw_get_port_bool(struct switch_dev *dev,
1090 + const struct switch_attr *attr,
1091 + struct switch_val *val)
1092 +{
1093 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1094 + int idx = val->port_vlan;
1095 + u32 x, reg, shift;
1096 +
1097 + if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS)
1098 + return -EINVAL;
1099 +
1100 + switch (attr->id) {
1101 + case RT305X_ESW_ATTR_PORT_DISABLE:
1102 + reg = RT305X_ESW_REG_POC0;
1103 + shift = RT305X_ESW_POC0_DIS_PORT_S;
1104 + break;
1105 + case RT305X_ESW_ATTR_PORT_DOUBLETAG:
1106 + reg = RT305X_ESW_REG_SGC2;
1107 + shift = RT305X_ESW_SGC2_DOUBLE_TAG_S;
1108 + break;
1109 + case RT305X_ESW_ATTR_PORT_UNTAG:
1110 + reg = RT305X_ESW_REG_POC2;
1111 + shift = RT305X_ESW_POC2_UNTAG_EN_S;
1112 + break;
1113 + case RT305X_ESW_ATTR_PORT_LAN:
1114 + reg = RT305X_ESW_REG_SGC2;
1115 + shift = RT305X_ESW_SGC2_LAN_PMAP_S;
1116 + if (idx >= RT305X_ESW_NUM_LANWAN)
1117 + return -EINVAL;
1118 + break;
1119 + default:
1120 + return -EINVAL;
1121 + }
1122 +
1123 + x = esw_r32(esw, reg);
1124 + val->value.i = (x >> (idx + shift)) & 1;
1125 +
1126 + return 0;
1127 +}
1128 +
1129 +static int esw_set_port_bool(struct switch_dev *dev,
1130 + const struct switch_attr *attr,
1131 + struct switch_val *val)
1132 +{
1133 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1134 + int idx = val->port_vlan;
1135 +
1136 + if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS ||
1137 + val->value.i < 0 || val->value.i > 1)
1138 + return -EINVAL;
1139 +
1140 + switch (attr->id) {
1141 + case RT305X_ESW_ATTR_PORT_DISABLE:
1142 + esw->ports[idx].disable = val->value.i;
1143 + break;
1144 + case RT305X_ESW_ATTR_PORT_DOUBLETAG:
1145 + esw->ports[idx].doubletag = val->value.i;
1146 + break;
1147 + case RT305X_ESW_ATTR_PORT_UNTAG:
1148 + esw->ports[idx].untag = val->value.i;
1149 + break;
1150 + default:
1151 + return -EINVAL;
1152 + }
1153 +
1154 + return 0;
1155 +}
1156 +
1157 +static int esw_get_port_recv_badgood(struct switch_dev *dev,
1158 + const struct switch_attr *attr,
1159 + struct switch_val *val)
1160 +{
1161 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1162 + int idx = val->port_vlan;
1163 + int shift = attr->id == RT305X_ESW_ATTR_PORT_RECV_GOOD ? 0 : 16;
1164 + u32 reg;
1165 +
1166 + if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN)
1167 + return -EINVAL;
1168 + reg = esw_r32(esw, RT305X_ESW_REG_PXPC(idx));
1169 + val->value.i = (reg >> shift) & 0xffff;
1170 +
1171 + return 0;
1172 +}
1173 +
1174 +static int
1175 +esw_get_port_tr_badgood(struct switch_dev *dev,
1176 + const struct switch_attr *attr,
1177 + struct switch_val *val)
1178 +{
1179 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1180 +
1181 + int idx = val->port_vlan;
1182 + int shift = attr->id == RT5350_ESW_ATTR_PORT_TR_GOOD ? 0 : 16;
1183 + u32 reg;
1184 +
1185 + if (!soc_is_rt5350())
1186 + return -EINVAL;
1187 +
1188 + if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN)
1189 + return -EINVAL;
1190 +
1191 + reg = esw_r32(esw, RT5350_ESW_REG_PXTPC(idx));
1192 + val->value.i = (reg >> shift) & 0xffff;
1193 +
1194 + return 0;
1195 +}
1196 +
1197 +static int esw_get_port_led(struct switch_dev *dev,
1198 + const struct switch_attr *attr,
1199 + struct switch_val *val)
1200 +{
1201 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1202 + int idx = val->port_vlan;
1203 +
1204 + if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS ||
1205 + idx >= RT305X_ESW_NUM_LEDS)
1206 + return -EINVAL;
1207 +
1208 + val->value.i = esw_r32(esw, RT305X_ESW_REG_P0LED + 4*idx);
1209 +
1210 + return 0;
1211 +}
1212 +
1213 +static int esw_set_port_led(struct switch_dev *dev,
1214 + const struct switch_attr *attr,
1215 + struct switch_val *val)
1216 +{
1217 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1218 + int idx = val->port_vlan;
1219 +
1220 + if (idx < 0 || idx >= RT305X_ESW_NUM_LEDS)
1221 + return -EINVAL;
1222 +
1223 + esw->ports[idx].led = val->value.i;
1224 +
1225 + return 0;
1226 +}
1227 +
1228 +static int esw_get_port_pvid(struct switch_dev *dev, int port, int *val)
1229 +{
1230 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1231 +
1232 + if (port >= RT305X_ESW_NUM_PORTS)
1233 + return -EINVAL;
1234 +
1235 + *val = esw_get_pvid(esw, port);
1236 +
1237 + return 0;
1238 +}
1239 +
1240 +static int esw_set_port_pvid(struct switch_dev *dev, int port, int val)
1241 +{
1242 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1243 +
1244 + if (port >= RT305X_ESW_NUM_PORTS)
1245 + return -EINVAL;
1246 +
1247 + esw->ports[port].pvid = val;
1248 +
1249 + return 0;
1250 +}
1251 +
1252 +static int esw_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
1253 +{
1254 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1255 + u32 vmsc, poc2;
1256 + int vlan_idx = -1;
1257 + int i;
1258 +
1259 + val->len = 0;
1260 +
1261 + if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS)
1262 + return -EINVAL;
1263 +
1264 + /* valid vlan? */
1265 + for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
1266 + if (esw_get_vlan_id(esw, i) == val->port_vlan &&
1267 + esw_get_vmsc(esw, i) != RT305X_ESW_PORTS_NONE) {
1268 + vlan_idx = i;
1269 + break;
1270 + }
1271 + }
1272 +
1273 + if (vlan_idx == -1)
1274 + return -EINVAL;
1275 +
1276 + vmsc = esw_get_vmsc(esw, vlan_idx);
1277 + poc2 = esw_r32(esw, RT305X_ESW_REG_POC2);
1278 +
1279 + for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {
1280 + struct switch_port *p;
1281 + int port_mask = 1 << i;
1282 +
1283 + if (!(vmsc & port_mask))
1284 + continue;
1285 +
1286 + p = &val->value.ports[val->len++];
1287 + p->id = i;
1288 + if (poc2 & (port_mask << RT305X_ESW_POC2_UNTAG_EN_S))
1289 + p->flags = 0;
1290 + else
1291 + p->flags = 1 << SWITCH_PORT_FLAG_TAGGED;
1292 + }
1293 +
1294 + return 0;
1295 +}
1296 +
1297 +static int esw_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)
1298 +{
1299 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1300 + int ports;
1301 + int vlan_idx = -1;
1302 + int i;
1303 +
1304 + if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS ||
1305 + val->len > RT305X_ESW_NUM_PORTS)
1306 + return -EINVAL;
1307 +
1308 + /* one of the already defined vlans? */
1309 + for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
1310 + if (esw->vlans[i].vid == val->port_vlan &&
1311 + esw->vlans[i].ports != RT305X_ESW_PORTS_NONE) {
1312 + vlan_idx = i;
1313 + break;
1314 + }
1315 + }
1316 +
1317 + /* select a free slot */
1318 + for (i = 0; vlan_idx == -1 && i < RT305X_ESW_NUM_VLANS; i++) {
1319 + if (esw->vlans[i].ports == RT305X_ESW_PORTS_NONE)
1320 + vlan_idx = i;
1321 + }
1322 +
1323 + /* bail if all slots are in use */
1324 + if (vlan_idx == -1)
1325 + return -EINVAL;
1326 +
1327 + ports = RT305X_ESW_PORTS_NONE;
1328 + for (i = 0; i < val->len; i++) {
1329 + struct switch_port *p = &val->value.ports[i];
1330 + int port_mask = 1 << p->id;
1331 + bool untagged = !(p->flags & (1 << SWITCH_PORT_FLAG_TAGGED));
1332 +
1333 + if (p->id >= RT305X_ESW_NUM_PORTS)
1334 + return -EINVAL;
1335 +
1336 + ports |= port_mask;
1337 + esw->ports[p->id].untag = untagged;
1338 + }
1339 + esw->vlans[vlan_idx].ports = ports;
1340 + if (ports == RT305X_ESW_PORTS_NONE)
1341 + esw->vlans[vlan_idx].vid = RT305X_ESW_VLAN_NONE;
1342 + else
1343 + esw->vlans[vlan_idx].vid = val->port_vlan;
1344 +
1345 + return 0;
1346 +}
1347 +
1348 +static const struct switch_attr esw_global[] = {
1349 + {
1350 + .type = SWITCH_TYPE_INT,
1351 + .name = "enable_vlan",
1352 + .description = "VLAN mode (1:enabled)",
1353 + .max = 1,
1354 + .id = RT305X_ESW_ATTR_ENABLE_VLAN,
1355 + .get = esw_get_vlan_enable,
1356 + .set = esw_set_vlan_enable,
1357 + },
1358 + {
1359 + .type = SWITCH_TYPE_INT,
1360 + .name = "alternate_vlan_disable",
1361 + .description = "Use en_vlan instead of doubletag to disable"
1362 + " VLAN mode",
1363 + .max = 1,
1364 + .id = RT305X_ESW_ATTR_ALT_VLAN_DISABLE,
1365 + .get = esw_get_alt_vlan_disable,
1366 + .set = esw_set_alt_vlan_disable,
1367 + },
1368 + {
1369 + .type = SWITCH_TYPE_INT,
1370 + .name = "bc_storm_protect",
1371 + .description = "Global broadcast storm protection (0:Disable, 1:64 blocks, 2:96 blocks, 3:128 blocks)",
1372 + .max = 3,
1373 + .id = RT305X_ESW_ATTR_BC_STATUS,
1374 + .get = rt305x_esw_get_bc_status,
1375 + .set = rt305x_esw_set_bc_status,
1376 + },
1377 + {
1378 + .type = SWITCH_TYPE_INT,
1379 + .name = "led_frequency",
1380 + .description = "LED Flash frequency (0:30mS, 1:60mS, 2:240mS, 3:480mS)",
1381 + .max = 3,
1382 + .id = RT305X_ESW_ATTR_LED_FREQ,
1383 + .get = rt305x_esw_get_led_freq,
1384 + .set = rt305x_esw_set_led_freq,
1385 + }
1386 +};
1387 +
1388 +static const struct switch_attr esw_port[] = {
1389 + {
1390 + .type = SWITCH_TYPE_INT,
1391 + .name = "disable",
1392 + .description = "Port state (1:disabled)",
1393 + .max = 1,
1394 + .id = RT305X_ESW_ATTR_PORT_DISABLE,
1395 + .get = esw_get_port_bool,
1396 + .set = esw_set_port_bool,
1397 + },
1398 + {
1399 + .type = SWITCH_TYPE_INT,
1400 + .name = "doubletag",
1401 + .description = "Double tagging for incoming vlan packets "
1402 + "(1:enabled)",
1403 + .max = 1,
1404 + .id = RT305X_ESW_ATTR_PORT_DOUBLETAG,
1405 + .get = esw_get_port_bool,
1406 + .set = esw_set_port_bool,
1407 + },
1408 + {
1409 + .type = SWITCH_TYPE_INT,
1410 + .name = "untag",
1411 + .description = "Untag (1:strip outgoing vlan tag)",
1412 + .max = 1,
1413 + .id = RT305X_ESW_ATTR_PORT_UNTAG,
1414 + .get = esw_get_port_bool,
1415 + .set = esw_set_port_bool,
1416 + },
1417 + {
1418 + .type = SWITCH_TYPE_INT,
1419 + .name = "led",
1420 + .description = "LED mode (0:link, 1:100m, 2:duplex, 3:activity,"
1421 + " 4:collision, 5:linkact, 6:duplcoll, 7:10mact,"
1422 + " 8:100mact, 10:blink, 11:off, 12:on)",
1423 + .max = 15,
1424 + .id = RT305X_ESW_ATTR_PORT_LED,
1425 + .get = esw_get_port_led,
1426 + .set = esw_set_port_led,
1427 + },
1428 + {
1429 + .type = SWITCH_TYPE_INT,
1430 + .name = "lan",
1431 + .description = "HW port group (0:wan, 1:lan)",
1432 + .max = 1,
1433 + .id = RT305X_ESW_ATTR_PORT_LAN,
1434 + .get = esw_get_port_bool,
1435 + },
1436 + {
1437 + .type = SWITCH_TYPE_INT,
1438 + .name = "recv_bad",
1439 + .description = "Receive bad packet counter",
1440 + .id = RT305X_ESW_ATTR_PORT_RECV_BAD,
1441 + .get = esw_get_port_recv_badgood,
1442 + },
1443 + {
1444 + .type = SWITCH_TYPE_INT,
1445 + .name = "recv_good",
1446 + .description = "Receive good packet counter",
1447 + .id = RT305X_ESW_ATTR_PORT_RECV_GOOD,
1448 + .get = esw_get_port_recv_badgood,
1449 + },
1450 + {
1451 + .type = SWITCH_TYPE_INT,
1452 + .name = "tr_bad",
1453 +
1454 + .description = "Transmit bad packet counter. rt5350 only",
1455 + .id = RT5350_ESW_ATTR_PORT_TR_BAD,
1456 + .get = esw_get_port_tr_badgood,
1457 + },
1458 + {
1459 + .type = SWITCH_TYPE_INT,
1460 + .name = "tr_good",
1461 +
1462 + .description = "Transmit good packet counter. rt5350 only",
1463 + .id = RT5350_ESW_ATTR_PORT_TR_GOOD,
1464 + .get = esw_get_port_tr_badgood,
1465 + },
1466 +};
1467 +
1468 +static const struct switch_attr esw_vlan[] = {
1469 +};
1470 +
1471 +static const struct switch_dev_ops esw_ops = {
1472 + .attr_global = {
1473 + .attr = esw_global,
1474 + .n_attr = ARRAY_SIZE(esw_global),
1475 + },
1476 + .attr_port = {
1477 + .attr = esw_port,
1478 + .n_attr = ARRAY_SIZE(esw_port),
1479 + },
1480 + .attr_vlan = {
1481 + .attr = esw_vlan,
1482 + .n_attr = ARRAY_SIZE(esw_vlan),
1483 + },
1484 + .get_vlan_ports = esw_get_vlan_ports,
1485 + .set_vlan_ports = esw_set_vlan_ports,
1486 + .get_port_pvid = esw_get_port_pvid,
1487 + .set_port_pvid = esw_set_port_pvid,
1488 + .get_port_link = esw_get_port_link,
1489 + .apply_config = esw_apply_config,
1490 + .reset_switch = esw_reset_switch,
1491 +};
1492 +
1493 +static struct rt305x_esw_platform_data rt3050_esw_data = {
1494 + /* All ports are LAN ports. */
1495 + .vlan_config = RT305X_ESW_VLAN_CONFIG_NONE,
1496 + .reg_initval_fct2 = 0x00d6500c,
1497 + /*
1498 + * ext phy base addr 31, enable port 5 polling, rx/tx clock skew 1,
1499 + * turbo mii off, rgmi 3.3v off
1500 + * port5: disabled
1501 + * port6: enabled, gige, full-duplex, rx/tx-flow-control
1502 + */
1503 + .reg_initval_fpa2 = 0x3f502b28,
1504 +};
1505 +
1506 +static const struct of_device_id ralink_esw_match[] = {
1507 + { .compatible = "ralink,rt3050-esw", .data = &rt3050_esw_data },
1508 + {},
1509 +};
1510 +MODULE_DEVICE_TABLE(of, ralink_esw_match);
1511 +
1512 +static int esw_probe(struct platform_device *pdev)
1513 +{
1514 + struct device_node *np = pdev->dev.of_node;
1515 + const struct rt305x_esw_platform_data *pdata;
1516 + const __be32 *port_map, *reg_init;
1517 + struct rt305x_esw *esw;
1518 + struct switch_dev *swdev;
1519 + struct resource *res, *irq;
1520 + int err;
1521 +
1522 + pdata = pdev->dev.platform_data;
1523 + if (!pdata) {
1524 + const struct of_device_id *match;
1525 + match = of_match_device(ralink_esw_match, &pdev->dev);
1526 + if (match)
1527 + pdata = (struct rt305x_esw_platform_data *) match->data;
1528 + }
1529 + if (!pdata)
1530 + return -EINVAL;
1531 +
1532 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1533 + if (!res) {
1534 + dev_err(&pdev->dev, "no memory resource found\n");
1535 + return -ENOMEM;
1536 + }
1537 +
1538 + irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1539 + if (!irq) {
1540 + dev_err(&pdev->dev, "no irq resource found\n");
1541 + return -ENOMEM;
1542 + }
1543 +
1544 + esw = kzalloc(sizeof(struct rt305x_esw), GFP_KERNEL);
1545 + if (!esw) {
1546 + dev_err(&pdev->dev, "no memory for private data\n");
1547 + return -ENOMEM;
1548 + }
1549 +
1550 + esw->dev = &pdev->dev;
1551 + esw->irq = irq->start;
1552 + esw->base = ioremap(res->start, resource_size(res));
1553 + if (!esw->base) {
1554 + dev_err(&pdev->dev, "ioremap failed\n");
1555 + err = -ENOMEM;
1556 + goto free_esw;
1557 + }
1558 +
1559 + port_map = of_get_property(np, "ralink,portmap", NULL);
1560 + if (port_map)
1561 + esw->port_map = be32_to_cpu(*port_map);
1562 +
1563 + reg_init = of_get_property(np, "ralink,fct2", NULL);
1564 + if (reg_init)
1565 + esw->reg_initval_fct2 = be32_to_cpu(*reg_init);
1566 +
1567 + reg_init = of_get_property(np, "ralink,fpa2", NULL);
1568 + if (reg_init)
1569 + esw->reg_initval_fpa2 = be32_to_cpu(*reg_init);
1570 +
1571 + reg_init = of_get_property(np, "ralink,led_polarity", NULL);
1572 + if (reg_init)
1573 + esw->reg_led_polarity = be32_to_cpu(*reg_init);
1574 +
1575 + swdev = &esw->swdev;
1576 + swdev->of_node = pdev->dev.of_node;
1577 + swdev->name = "rt305x-esw";
1578 + swdev->alias = "rt305x";
1579 + swdev->cpu_port = RT305X_ESW_PORT6;
1580 + swdev->ports = RT305X_ESW_NUM_PORTS;
1581 + swdev->vlans = RT305X_ESW_NUM_VIDS;
1582 + swdev->ops = &esw_ops;
1583 +
1584 + err = register_switch(swdev, NULL);
1585 + if (err < 0) {
1586 + dev_err(&pdev->dev, "register_switch failed\n");
1587 + goto unmap_base;
1588 + }
1589 +
1590 + platform_set_drvdata(pdev, esw);
1591 +
1592 + esw->pdata = pdata;
1593 + spin_lock_init(&esw->reg_rw_lock);
1594 +
1595 + esw_hw_init(esw);
1596 +
1597 + esw_w32(esw, RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_ISR);
1598 + esw_w32(esw, ~RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_IMR);
1599 + request_irq(esw->irq, esw_interrupt, 0, "esw", esw);
1600 +
1601 + return 0;
1602 +
1603 +unmap_base:
1604 + iounmap(esw->base);
1605 +free_esw:
1606 + kfree(esw);
1607 + return err;
1608 +}
1609 +
1610 +static int esw_remove(struct platform_device *pdev)
1611 +{
1612 + struct rt305x_esw *esw;
1613 +
1614 + esw = platform_get_drvdata(pdev);
1615 + if (esw) {
1616 + unregister_switch(&esw->swdev);
1617 + platform_set_drvdata(pdev, NULL);
1618 + iounmap(esw->base);
1619 + kfree(esw);
1620 + }
1621 +
1622 + return 0;
1623 +}
1624 +
1625 +static struct platform_driver esw_driver = {
1626 + .probe = esw_probe,
1627 + .remove = esw_remove,
1628 + .driver = {
1629 + .name = "rt305x-esw",
1630 + .owner = THIS_MODULE,
1631 + .of_match_table = ralink_esw_match,
1632 + },
1633 +};
1634 +
1635 +int __init rtesw_init(void)
1636 +{
1637 + return platform_driver_register(&esw_driver);
1638 +}
1639 +
1640 +void rtesw_exit(void)
1641 +{
1642 + platform_driver_unregister(&esw_driver);
1643 +}
1644 Index: linux-3.10.13/drivers/net/ethernet/ralink/esw_rt3052.h
1645 ===================================================================
1646 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
1647 +++ linux-3.10.13/drivers/net/ethernet/ralink/esw_rt3052.h 2013-10-08 17:26:47.068172664 +0200
1648 @@ -0,0 +1,32 @@
1649 +/*
1650 + * This program is free software; you can redistribute it and/or modify
1651 + * it under the terms of the GNU General Public License as published by
1652 + * the Free Software Foundation; version 2 of the License
1653 + *
1654 + * This program is distributed in the hope that it will be useful,
1655 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1656 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1657 + * GNU General Public License for more details.
1658 + *
1659 + * You should have received a copy of the GNU General Public License
1660 + * along with this program; if not, write to the Free Software
1661 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
1662 + *
1663 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
1664 + */
1665 +
1666 +#ifndef _RALINK_ESW_RT3052_H__
1667 +#define _RALINK_ESW_RT3052_H__
1668 +
1669 +#ifdef CONFIG_NET_RALINK_ESW_RT3052
1670 +
1671 +int __init rtesw_init(void);
1672 +void rtesw_exit(void);
1673 +
1674 +#else
1675 +
1676 +static inline int __init rtesw_init(void) { return 0; }
1677 +static inline void rtesw_exit(void) { }
1678 +
1679 +#endif
1680 +#endif
1681 Index: linux-3.10.13/drivers/net/ethernet/ralink/gsw_mt7620a.c
1682 ===================================================================
1683 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
1684 +++ linux-3.10.13/drivers/net/ethernet/ralink/gsw_mt7620a.c 2013-10-08 17:26:47.068172664 +0200
1685 @@ -0,0 +1,566 @@
1686 +/*
1687 + * This program is free software; you can redistribute it and/or modify
1688 + * it under the terms of the GNU General Public License as published by
1689 + * the Free Software Foundation; version 2 of the License
1690 + *
1691 + * This program is distributed in the hope that it will be useful,
1692 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1693 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1694 + * GNU General Public License for more details.
1695 + *
1696 + * You should have received a copy of the GNU General Public License
1697 + * along with this program; if not, write to the Free Software
1698 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
1699 + *
1700 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
1701 + */
1702 +
1703 +#include <linux/module.h>
1704 +#include <linux/kernel.h>
1705 +#include <linux/types.h>
1706 +#include <linux/dma-mapping.h>
1707 +#include <linux/init.h>
1708 +#include <linux/skbuff.h>
1709 +#include <linux/etherdevice.h>
1710 +#include <linux/ethtool.h>
1711 +#include <linux/platform_device.h>
1712 +#include <linux/of_device.h>
1713 +#include <linux/clk.h>
1714 +#include <linux/of_net.h>
1715 +#include <linux/of_mdio.h>
1716 +#include <linux/of_irq.h>
1717 +#include <linux/of_address.h>
1718 +#include <linux/switch.h>
1719 +
1720 +#include <asm/mach-ralink/ralink_regs.h>
1721 +
1722 +#include "ralink_soc_eth.h"
1723 +
1724 +#include <linux/ioport.h>
1725 +#include <linux/switch.h>
1726 +#include <linux/mii.h>
1727 +
1728 +#include <ralink_regs.h>
1729 +#include <asm/mach-ralink/mt7620.h>
1730 +
1731 +#include "ralink_soc_eth.h"
1732 +#include "gsw_mt7620a.h"
1733 +#include "mt7530.h"
1734 +#include "mdio.h"
1735 +
1736 +#define GSW_REG_PHY_TIMEOUT (5 * HZ)
1737 +
1738 +#define MT7620A_GSW_REG_PIAC 0x7004
1739 +
1740 +#define GSW_NUM_VLANS 16
1741 +#define GSW_NUM_VIDS 4096
1742 +#define GSW_NUM_PORTS 7
1743 +#define GSW_PORT6 6
1744 +
1745 +#define GSW_MDIO_ACCESS BIT(31)
1746 +#define GSW_MDIO_READ BIT(19)
1747 +#define GSW_MDIO_WRITE BIT(18)
1748 +#define GSW_MDIO_START BIT(16)
1749 +#define GSW_MDIO_ADDR_SHIFT 20
1750 +#define GSW_MDIO_REG_SHIFT 25
1751 +
1752 +#define GSW_REG_PORT_PMCR(x) (0x3000 + (x * 0x100))
1753 +#define GSW_REG_PORT_STATUS(x) (0x3008 + (x * 0x100))
1754 +#define GSW_REG_SMACCR0 0x3fE4
1755 +#define GSW_REG_SMACCR1 0x3fE8
1756 +#define GSW_REG_CKGCR 0x3ff0
1757 +
1758 +#define GSW_REG_IMR 0x7008
1759 +#define GSW_REG_ISR 0x700c
1760 +
1761 +#define SYSC_REG_CFG1 0x14
1762 +
1763 +#define PORT_IRQ_ST_CHG 0x7f
1764 +
1765 +#define SYSCFG1 0x14
1766 +
1767 +#define ESW_PHY_POLLING 0x7000
1768 +
1769 +#define PMCR_IPG BIT(18)
1770 +#define PMCR_MAC_MODE BIT(16)
1771 +#define PMCR_FORCE BIT(15)
1772 +#define PMCR_TX_EN BIT(14)
1773 +#define PMCR_RX_EN BIT(13)
1774 +#define PMCR_BACKOFF BIT(9)
1775 +#define PMCR_BACKPRES BIT(8)
1776 +#define PMCR_RX_FC BIT(5)
1777 +#define PMCR_TX_FC BIT(4)
1778 +#define PMCR_SPEED(_x) (_x << 2)
1779 +#define PMCR_DUPLEX BIT(1)
1780 +#define PMCR_LINK BIT(0)
1781 +
1782 +#define PHY_AN_EN BIT(31)
1783 +#define PHY_PRE_EN BIT(30)
1784 +#define PMY_MDC_CONF(_x) ((_x & 0x3f) << 24)
1785 +
1786 +enum {
1787 + /* Global attributes. */
1788 + GSW_ATTR_ENABLE_VLAN,
1789 + /* Port attributes. */
1790 + GSW_ATTR_PORT_UNTAG,
1791 +};
1792 +
1793 +enum {
1794 + PORT4_EPHY = 0,
1795 + PORT4_EXT,
1796 +};
1797 +
1798 +struct mt7620_gsw {
1799 + struct device *dev;
1800 + void __iomem *base;
1801 + int irq;
1802 + int port4;
1803 + long unsigned int autopoll;
1804 +};
1805 +
1806 +static inline void gsw_w32(struct mt7620_gsw *gsw, u32 val, unsigned reg)
1807 +{
1808 + iowrite32(val, gsw->base + reg);
1809 +}
1810 +
1811 +static inline u32 gsw_r32(struct mt7620_gsw *gsw, unsigned reg)
1812 +{
1813 + return ioread32(gsw->base + reg);
1814 +}
1815 +
1816 +static int mt7620_mii_busy_wait(struct mt7620_gsw *gsw)
1817 +{
1818 + unsigned long t_start = jiffies;
1819 +
1820 + while (1) {
1821 + if (!(gsw_r32(gsw, MT7620A_GSW_REG_PIAC) & GSW_MDIO_ACCESS))
1822 + return 0;
1823 + if (time_after(jiffies, t_start + GSW_REG_PHY_TIMEOUT)) {
1824 + break;
1825 + }
1826 + }
1827 +
1828 + printk(KERN_ERR "mdio: MDIO timeout\n");
1829 + return -1;
1830 +}
1831 +
1832 +static u32 _mt7620_mii_write(struct mt7620_gsw *gsw, u32 phy_addr, u32 phy_register,
1833 + u32 write_data)
1834 +{
1835 + if (mt7620_mii_busy_wait(gsw))
1836 + return -1;
1837 +
1838 + write_data &= 0xffff;
1839 +
1840 + gsw_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_WRITE |
1841 + (phy_register << GSW_MDIO_REG_SHIFT) |
1842 + (phy_addr << GSW_MDIO_ADDR_SHIFT) | write_data,
1843 + MT7620A_GSW_REG_PIAC);
1844 +
1845 + if (mt7620_mii_busy_wait(gsw))
1846 + return -1;
1847 +
1848 + return 0;
1849 +}
1850 +
1851 +static u32 _mt7620_mii_read(struct mt7620_gsw *gsw, int phy_addr, int phy_reg)
1852 +{
1853 + u32 d;
1854 +
1855 + if (mt7620_mii_busy_wait(gsw))
1856 + return 0xffff;
1857 +
1858 + gsw_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_READ |
1859 + (phy_reg << GSW_MDIO_REG_SHIFT) |
1860 + (phy_addr << GSW_MDIO_ADDR_SHIFT),
1861 + MT7620A_GSW_REG_PIAC);
1862 +
1863 + if (mt7620_mii_busy_wait(gsw))
1864 + return 0xffff;
1865 +
1866 + d = gsw_r32(gsw, MT7620A_GSW_REG_PIAC) & 0xffff;
1867 +
1868 + return d;
1869 +}
1870 +
1871 +int mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val)
1872 +{
1873 + struct fe_priv *priv = bus->priv;
1874 + struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
1875 +
1876 + return _mt7620_mii_write(gsw, phy_addr, phy_reg, val);
1877 +}
1878 +
1879 +int mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
1880 +{
1881 + struct fe_priv *priv = bus->priv;
1882 + struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
1883 +
1884 + return _mt7620_mii_read(gsw, phy_addr, phy_reg);
1885 +}
1886 +
1887 +static unsigned char *fe_speed_str(int speed)
1888 +{
1889 + switch (speed) {
1890 + case 2:
1891 + case SPEED_1000:
1892 + return "1000";
1893 + case 1:
1894 + case SPEED_100:
1895 + return "100";
1896 + case 0:
1897 + case SPEED_10:
1898 + return "10";
1899 + }
1900 +
1901 + return "? ";
1902 +}
1903 +
1904 +int mt7620a_has_carrier(struct fe_priv *priv)
1905 +{
1906 + struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
1907 + int i;
1908 +
1909 + for (i = 0; i < GSW_PORT6; i++)
1910 + if (gsw_r32(gsw, GSW_REG_PORT_STATUS(i)) & 0x1)
1911 + return 1;
1912 + return 0;
1913 +}
1914 +
1915 +static void mt7620a_handle_carrier(struct fe_priv *priv)
1916 +{
1917 + if (!priv->phy)
1918 + return;
1919 +
1920 + if (mt7620a_has_carrier(priv))
1921 + netif_carrier_on(priv->netdev);
1922 + else
1923 + netif_carrier_off(priv->netdev);
1924 +}
1925 +
1926 +void mt7620_mdio_link_adjust(struct fe_priv *priv, int port)
1927 +{
1928 + if (priv->link[port])
1929 + netdev_info(priv->netdev, "port %d link up (%sMbps/%s duplex)\n",
1930 + port, fe_speed_str(priv->phy->speed[port]),
1931 + (DUPLEX_FULL == priv->phy->duplex[port]) ? "Full" : "Half");
1932 + else
1933 + netdev_info(priv->netdev, "port %d link down\n", port);
1934 + mt7620a_handle_carrier(priv);
1935 +}
1936 +
1937 +static irqreturn_t gsw_interrupt(int irq, void *_priv)
1938 +{
1939 + struct fe_priv *priv = (struct fe_priv *) _priv;
1940 + struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
1941 + u32 status;
1942 + int i, max = (gsw->port4 == PORT4_EPHY) ? (4) : (3);
1943 +
1944 + status = gsw_r32(gsw, GSW_REG_ISR);
1945 + if (status & PORT_IRQ_ST_CHG)
1946 + for (i = 0; i <= max; i++) {
1947 + u32 status = gsw_r32(gsw, GSW_REG_PORT_STATUS(i));
1948 + int link = status & 0x1;
1949 +
1950 + if (link != priv->link[i]) {
1951 + if (link)
1952 + netdev_info(priv->netdev, "port %d link up (%sMbps/%s duplex)\n",
1953 + i, fe_speed_str((status >> 2) & 3),
1954 + (status & 0x2) ? "Full" : "Half");
1955 + else
1956 + netdev_info(priv->netdev, "port %d link down\n", i);
1957 + }
1958 +
1959 + priv->link[i] = link;
1960 + }
1961 + mt7620a_handle_carrier(priv);
1962 +
1963 + gsw_w32(gsw, status, GSW_REG_ISR);
1964 +
1965 + return IRQ_HANDLED;
1966 +}
1967 +
1968 +static int mt7620_is_bga(void)
1969 +{
1970 + u32 bga = rt_sysc_r32(0x0c);
1971 +
1972 + return (bga >> 16) & 1;
1973 +}
1974 +
1975 +static void gsw_auto_poll(struct mt7620_gsw *gsw)
1976 +{
1977 + int phy;
1978 + int lsb = -1, msb = 0;
1979 +
1980 + for_each_set_bit(phy, &gsw->autopoll, 32) {
1981 + if (lsb < 0)
1982 + lsb = phy;
1983 + msb = phy;
1984 + }
1985 +
1986 + gsw_w32(gsw, PHY_AN_EN | PHY_PRE_EN | PMY_MDC_CONF(5) | (msb << 8) | lsb, ESW_PHY_POLLING);
1987 +}
1988 +
1989 +void mt7620_port_init(struct fe_priv *priv, struct device_node *np)
1990 +{
1991 + struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
1992 + const __be32 *_id = of_get_property(np, "reg", NULL);
1993 + int phy_mode, size, id;
1994 + int shift = 12;
1995 + u32 val, mask = 0;
1996 + int min = (gsw->port4 == PORT4_EPHY) ? (5) : (4);
1997 +
1998 + if (!_id || (be32_to_cpu(*_id) < min) || (be32_to_cpu(*_id) > 5)) {
1999 + if (_id)
2000 + pr_err("%s: invalid port id %d\n", np->name, be32_to_cpu(*_id));
2001 + else
2002 + pr_err("%s: invalid port id\n", np->name);
2003 + return;
2004 + }
2005 +
2006 + id = be32_to_cpu(*_id);
2007 +
2008 + if (id == 4)
2009 + shift = 14;
2010 +
2011 + priv->phy->phy_fixed[id] = of_get_property(np, "ralink,fixed-link", &size);
2012 + if (priv->phy->phy_fixed[id] && (size != (4 * sizeof(*priv->phy->phy_fixed[id])))) {
2013 + pr_err("%s: invalid fixed link property\n", np->name);
2014 + priv->phy->phy_fixed[id] = NULL;
2015 + return;
2016 + }
2017 +
2018 + phy_mode = of_get_phy_mode(np);
2019 + switch (phy_mode) {
2020 + case PHY_INTERFACE_MODE_RGMII:
2021 + mask = 0;
2022 + break;
2023 + case PHY_INTERFACE_MODE_MII:
2024 + mask = 1;
2025 + break;
2026 + case PHY_INTERFACE_MODE_RMII:
2027 + mask = 2;
2028 + break;
2029 + default:
2030 + dev_err(priv->device, "port %d - invalid phy mode\n", id);
2031 + return;
2032 + }
2033 +
2034 + priv->phy->phy_node[id] = of_parse_phandle(np, "phy-handle", 0);
2035 + if (!priv->phy->phy_node[id] && !priv->phy->phy_fixed[id])
2036 + return;
2037 +
2038 + val = rt_sysc_r32(SYSCFG1);
2039 + val &= ~(3 << shift);
2040 + val |= mask << shift;
2041 + rt_sysc_w32(val, SYSCFG1);
2042 +
2043 + if (priv->phy->phy_fixed[id]) {
2044 + const __be32 *link = priv->phy->phy_fixed[id];
2045 + int tx_fc, rx_fc;
2046 + u32 val = 0;
2047 +
2048 + priv->phy->speed[id] = be32_to_cpup(link++);
2049 + tx_fc = be32_to_cpup(link++);
2050 + rx_fc = be32_to_cpup(link++);
2051 + priv->phy->duplex[id] = be32_to_cpup(link++);
2052 + priv->link[id] = 1;
2053 +
2054 + switch (priv->phy->speed[id]) {
2055 + case SPEED_10:
2056 + val = 0;
2057 + break;
2058 + case SPEED_100:
2059 + val = 1;
2060 + break;
2061 + case SPEED_1000:
2062 + val = 2;
2063 + break;
2064 + default:
2065 + dev_err(priv->device, "invalid link speed: %d\n", priv->phy->speed[id]);
2066 + priv->phy->phy_fixed[id] = 0;
2067 + return;
2068 + }
2069 + val = PMCR_SPEED(val);
2070 + val |= PMCR_LINK | PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
2071 + PMCR_TX_EN | PMCR_FORCE | PMCR_MAC_MODE | PMCR_IPG;
2072 + if (tx_fc)
2073 + val |= PMCR_TX_FC;
2074 + if (rx_fc)
2075 + val |= PMCR_RX_FC;
2076 + if (priv->phy->duplex[id])
2077 + val |= PMCR_DUPLEX;
2078 + gsw_w32(gsw, val, GSW_REG_PORT_PMCR(id));
2079 + dev_info(priv->device, "using fixed link parameters\n");
2080 + return;
2081 + }
2082 +
2083 + if (priv->phy->phy_node[id] && priv->mii_bus->phy_map[id]) {
2084 + u32 val = PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
2085 + PMCR_TX_EN | PMCR_MAC_MODE | PMCR_IPG;
2086 +
2087 + gsw_w32(gsw, val, GSW_REG_PORT_PMCR(id));
2088 + fe_connect_phy_node(priv, priv->phy->phy_node[id]);
2089 + gsw->autopoll |= BIT(id);
2090 + gsw_auto_poll(gsw);
2091 + return;
2092 + }
2093 +}
2094 +
2095 +static void gsw_hw_init(struct mt7620_gsw *gsw)
2096 +{
2097 + u32 is_BGA = mt7620_is_bga();
2098 +
2099 + rt_sysc_w32(rt_sysc_r32(SYSC_REG_CFG1) | BIT(8), SYSC_REG_CFG1);
2100 + gsw_w32(gsw, gsw_r32(gsw, GSW_REG_CKGCR) & ~(0x3 << 4), GSW_REG_CKGCR);
2101 +
2102 + /*correct PHY setting L3.0 BGA*/
2103 + _mt7620_mii_write(gsw, 1, 31, 0x4000); //global, page 4
2104 +
2105 + _mt7620_mii_write(gsw, 1, 17, 0x7444);
2106 + if (is_BGA)
2107 + _mt7620_mii_write(gsw, 1, 19, 0x0114);
2108 + else
2109 + _mt7620_mii_write(gsw, 1, 19, 0x0117);
2110 +
2111 + _mt7620_mii_write(gsw, 1, 22, 0x10cf);
2112 + _mt7620_mii_write(gsw, 1, 25, 0x6212);
2113 + _mt7620_mii_write(gsw, 1, 26, 0x0777);
2114 + _mt7620_mii_write(gsw, 1, 29, 0x4000);
2115 + _mt7620_mii_write(gsw, 1, 28, 0xc077);
2116 + _mt7620_mii_write(gsw, 1, 24, 0x0000);
2117 +
2118 + _mt7620_mii_write(gsw, 1, 31, 0x3000); //global, page 3
2119 + _mt7620_mii_write(gsw, 1, 17, 0x4838);
2120 +
2121 + _mt7620_mii_write(gsw, 1, 31, 0x2000); //global, page 2
2122 + if (is_BGA) {
2123 + _mt7620_mii_write(gsw, 1, 21, 0x0515);
2124 + _mt7620_mii_write(gsw, 1, 22, 0x0053);
2125 + _mt7620_mii_write(gsw, 1, 23, 0x00bf);
2126 + _mt7620_mii_write(gsw, 1, 24, 0x0aaf);
2127 + _mt7620_mii_write(gsw, 1, 25, 0x0fad);
2128 + _mt7620_mii_write(gsw, 1, 26, 0x0fc1);
2129 + } else {
2130 + _mt7620_mii_write(gsw, 1, 21, 0x0517);
2131 + _mt7620_mii_write(gsw, 1, 22, 0x0fd2);
2132 + _mt7620_mii_write(gsw, 1, 23, 0x00bf);
2133 + _mt7620_mii_write(gsw, 1, 24, 0x0aab);
2134 + _mt7620_mii_write(gsw, 1, 25, 0x00ae);
2135 + _mt7620_mii_write(gsw, 1, 26, 0x0fff);
2136 + }
2137 + _mt7620_mii_write(gsw, 1, 31, 0x1000); //global, page 1
2138 + _mt7620_mii_write(gsw, 1, 17, 0xe7f8);
2139 +
2140 + _mt7620_mii_write(gsw, 1, 31, 0x8000); //local, page 0
2141 + _mt7620_mii_write(gsw, 0, 30, 0xa000);
2142 + _mt7620_mii_write(gsw, 1, 30, 0xa000);
2143 + _mt7620_mii_write(gsw, 2, 30, 0xa000);
2144 + _mt7620_mii_write(gsw, 3, 30, 0xa000);
2145 +
2146 + _mt7620_mii_write(gsw, 0, 4, 0x05e1);
2147 + _mt7620_mii_write(gsw, 1, 4, 0x05e1);
2148 + _mt7620_mii_write(gsw, 2, 4, 0x05e1);
2149 + _mt7620_mii_write(gsw, 3, 4, 0x05e1);
2150 + _mt7620_mii_write(gsw, 1, 31, 0xa000); //local, page 2
2151 + _mt7620_mii_write(gsw, 0, 16, 0x1111);
2152 + _mt7620_mii_write(gsw, 1, 16, 0x1010);
2153 + _mt7620_mii_write(gsw, 2, 16, 0x1515);
2154 + _mt7620_mii_write(gsw, 3, 16, 0x0f0f);
2155 +
2156 + /* CPU Port6 Force Link 1G, FC ON */
2157 + gsw_w32(gsw, 0x5e33b, GSW_REG_PORT_PMCR(6));
2158 + /* Set Port6 CPU Port */
2159 + gsw_w32(gsw, 0x7f7f7fe0, 0x0010);
2160 +
2161 + /* setup port 4 */
2162 + if (gsw->port4 == PORT4_EPHY) {
2163 + u32 val = rt_sysc_r32(SYSCFG1);
2164 + val |= 3 << 14;
2165 + rt_sysc_w32(val, SYSCFG1);
2166 + _mt7620_mii_write(gsw, 4, 30, 0xa000);
2167 + _mt7620_mii_write(gsw, 4, 4, 0x05e1);
2168 + _mt7620_mii_write(gsw, 4, 16, 0x1313);
2169 + pr_info("gsw: setting port4 to ephy mode\n");
2170 + }
2171 +}
2172 +
2173 +void mt7620_set_mac(struct fe_priv *priv, unsigned char *mac)
2174 +{
2175 + struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
2176 + unsigned long flags;
2177 +
2178 + spin_lock_irqsave(&priv->page_lock, flags);
2179 + gsw_w32(gsw, (mac[0] << 8) | mac[1], GSW_REG_SMACCR1);
2180 + gsw_w32(gsw, (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
2181 + GSW_REG_SMACCR0);
2182 + spin_unlock_irqrestore(&priv->page_lock, flags);
2183 +}
2184 +
2185 +static struct of_device_id gsw_match[] = {
2186 + { .compatible = "ralink,mt7620a-gsw" },
2187 + {}
2188 +};
2189 +
2190 +int mt7620_gsw_config(struct fe_priv *priv)
2191 +{
2192 + struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
2193 +
2194 + /* is the mt7530 internal or external */
2195 + if ((_mt7620_mii_read(gsw, 0x1f, 2) == 1) && (_mt7620_mii_read(gsw, 0x1f, 3) == 0xbeef))
2196 + mt7530_probe(priv->device, NULL, priv->mii_bus);
2197 + else
2198 + mt7530_probe(priv->device, gsw->base, NULL);
2199 +
2200 + return 0;
2201 +}
2202 +
2203 +int mt7620_gsw_probe(struct fe_priv *priv)
2204 +{
2205 + struct mt7620_gsw *gsw;
2206 + struct device_node *np;
2207 + const char *port4 = NULL;
2208 +
2209 + np = of_find_matching_node(NULL, gsw_match);
2210 + if (!np) {
2211 + dev_err(priv->device, "no gsw node found\n");
2212 + return -EINVAL;
2213 + }
2214 + np = of_node_get(np);
2215 +
2216 + gsw = devm_kzalloc(priv->device, sizeof(struct mt7620_gsw), GFP_KERNEL);
2217 + if (!gsw) {
2218 + dev_err(priv->device, "no gsw memory for private data\n");
2219 + return -ENOMEM;
2220 + }
2221 +
2222 + gsw->irq = irq_of_parse_and_map(np, 0);
2223 + if (!gsw->irq) {
2224 + dev_err(priv->device, "no gsw irq resource found\n");
2225 + return -ENOMEM;
2226 + }
2227 +
2228 + gsw->base = of_iomap(np, 0);
2229 + if (!gsw->base) {
2230 + dev_err(priv->device, "gsw ioremap failed\n");
2231 + return -ENOMEM;
2232 + }
2233 +
2234 + gsw->dev = priv->device;
2235 + priv->soc->swpriv = gsw;
2236 +
2237 + of_property_read_string(np, "ralink,port4", &port4);
2238 + if (port4 && !strcmp(port4, "ephy"))
2239 + gsw->port4 = PORT4_EPHY;
2240 + else if (port4 && !strcmp(port4, "gmac"))
2241 + gsw->port4 = PORT4_EXT;
2242 + else
2243 + WARN_ON(port4);
2244 +
2245 + gsw_hw_init(gsw);
2246 +
2247 + gsw_w32(gsw, ~PORT_IRQ_ST_CHG, GSW_REG_IMR);
2248 + request_irq(gsw->irq, gsw_interrupt, 0, "gsw", priv);
2249 +
2250 + return 0;
2251 +}
2252 Index: linux-3.10.13/drivers/net/ethernet/ralink/gsw_mt7620a.h
2253 ===================================================================
2254 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
2255 +++ linux-3.10.13/drivers/net/ethernet/ralink/gsw_mt7620a.h 2013-10-08 17:26:47.068172664 +0200
2256 @@ -0,0 +1,30 @@
2257 +/*
2258 + * This program is free software; you can redistribute it and/or modify
2259 + * it under the terms of the GNU General Public License as published by
2260 + * the Free Software Foundation; version 2 of the License
2261 + *
2262 + * This program is distributed in the hope that it will be useful,
2263 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2264 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2265 + * GNU General Public License for more details.
2266 + *
2267 + * You should have received a copy of the GNU General Public License
2268 + * along with this program; if not, write to the Free Software
2269 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
2270 + *
2271 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
2272 + */
2273 +
2274 +#ifndef _RALINK_GSW_MT7620_H__
2275 +#define _RALINK_GSW_MT7620_H__
2276 +
2277 +extern int mt7620_gsw_config(struct fe_priv *priv);
2278 +extern int mt7620_gsw_probe(struct fe_priv *priv);
2279 +extern void mt7620_set_mac(struct fe_priv *priv, unsigned char *mac);
2280 +extern int mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
2281 +extern int mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg);
2282 +extern void mt7620_mdio_link_adjust(struct fe_priv *priv, int port);
2283 +extern void mt7620_port_init(struct fe_priv *priv, struct device_node *np);
2284 +extern int mt7620a_has_carrier(struct fe_priv *priv);
2285 +
2286 +#endif
2287 Index: linux-3.10.13/drivers/net/ethernet/ralink/mdio.c
2288 ===================================================================
2289 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
2290 +++ linux-3.10.13/drivers/net/ethernet/ralink/mdio.c 2013-10-08 17:26:47.068172664 +0200
2291 @@ -0,0 +1,244 @@
2292 +/*
2293 + * This program is free software; you can redistribute it and/or modify
2294 + * it under the terms of the GNU General Public License as published by
2295 + * the Free Software Foundation; version 2 of the License
2296 + *
2297 + * This program is distributed in the hope that it will be useful,
2298 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2299 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2300 + * GNU General Public License for more details.
2301 + *
2302 + * You should have received a copy of the GNU General Public License
2303 + * along with this program; if not, write to the Free Software
2304 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
2305 + *
2306 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
2307 + */
2308 +
2309 +#include <linux/module.h>
2310 +#include <linux/kernel.h>
2311 +#include <linux/types.h>
2312 +#include <linux/dma-mapping.h>
2313 +#include <linux/init.h>
2314 +#include <linux/skbuff.h>
2315 +#include <linux/etherdevice.h>
2316 +#include <linux/ethtool.h>
2317 +#include <linux/platform_device.h>
2318 +#include <linux/phy.h>
2319 +#include <linux/of_device.h>
2320 +#include <linux/clk.h>
2321 +#include <linux/of_net.h>
2322 +#include <linux/of_mdio.h>
2323 +
2324 +#include "ralink_soc_eth.h"
2325 +#include "mdio.h"
2326 +
2327 +static int fe_mdio_reset(struct mii_bus *bus)
2328 +{
2329 + /* TODO */
2330 + return 0;
2331 +}
2332 +
2333 +static void fe_phy_link_adjust(struct net_device *dev)
2334 +{
2335 + struct fe_priv *priv = netdev_priv(dev);
2336 + unsigned long flags;
2337 + int i;
2338 +
2339 + spin_lock_irqsave(&priv->phy->lock, flags);
2340 + for (i = 0; i < 8; i++) {
2341 + if (priv->phy->phy_node[i]) {
2342 + struct phy_device *phydev = priv->phy->phy[i];
2343 + int status_change = 0;
2344 +
2345 + if (phydev->link)
2346 + if (priv->phy->duplex[i] != phydev->duplex ||
2347 + priv->phy->speed[i] != phydev->speed)
2348 + status_change = 1;
2349 +
2350 + if (phydev->link != priv->link[i])
2351 + status_change = 1;
2352 +
2353 + switch (phydev->speed) {
2354 + case SPEED_1000:
2355 + case SPEED_100:
2356 + case SPEED_10:
2357 + priv->link[i] = phydev->link;
2358 + priv->phy->duplex[i] = phydev->duplex;
2359 + priv->phy->speed[i] = phydev->speed;
2360 +
2361 + if (status_change && priv->soc->mdio_adjust_link)
2362 + priv->soc->mdio_adjust_link(priv, i);
2363 + break;
2364 + }
2365 + }
2366 + }
2367 +}
2368 +
2369 +int fe_connect_phy_node(struct fe_priv *priv, struct device_node *phy_node)
2370 +{
2371 + const __be32 *_port = NULL;
2372 + struct phy_device *phydev;
2373 + int phy_mode, port;
2374 +
2375 + _port = of_get_property(phy_node, "reg", NULL);
2376 +
2377 + if (!_port || (be32_to_cpu(*_port) >= 0x20)) {
2378 + pr_err("%s: invalid port id\n", phy_node->name);
2379 + return -EINVAL;
2380 + }
2381 + port = be32_to_cpu(*_port);
2382 + phy_mode = of_get_phy_mode(phy_node);
2383 + if (phy_mode < 0) {
2384 + dev_err(priv->device, "incorrect phy-mode %d\n", phy_mode);
2385 + priv->phy->phy_node[port] = NULL;
2386 + return -EINVAL;
2387 + }
2388 +
2389 + phydev = of_phy_connect(priv->netdev, phy_node, fe_phy_link_adjust,
2390 + 0, phy_mode);
2391 + if (IS_ERR(phydev)) {
2392 + dev_err(priv->device, "could not connect to PHY\n");
2393 + priv->phy->phy_node[port] = NULL;
2394 + return PTR_ERR(phydev);
2395 + }
2396 +
2397 + phydev->supported &= PHY_GBIT_FEATURES;
2398 + phydev->advertising = phydev->supported;
2399 + phydev->no_auto_carrier_off = 1;
2400 +
2401 + dev_info(priv->device,
2402 + "connected port %d to PHY at %s [uid=%08x, driver=%s]\n",
2403 + port, dev_name(&phydev->dev), phydev->phy_id,
2404 + phydev->drv->name);
2405 +
2406 + priv->phy->phy[port] = phydev;
2407 + priv->link[port] = 0;
2408 +
2409 + return 0;
2410 +}
2411 +
2412 +static int fe_phy_connect(struct fe_priv *priv)
2413 +{
2414 + return 0;
2415 +}
2416 +
2417 +static void fe_phy_disconnect(struct fe_priv *priv)
2418 +{
2419 + unsigned long flags;
2420 + int i;
2421 +
2422 + for (i = 0; i < 8; i++)
2423 + if (priv->phy->phy_fixed[i]) {
2424 + spin_lock_irqsave(&priv->phy->lock, flags);
2425 + priv->link[i] = 0;
2426 + if (priv->soc->mdio_adjust_link)
2427 + priv->soc->mdio_adjust_link(priv, i);
2428 + spin_unlock_irqrestore(&priv->phy->lock, flags);
2429 + } else if (priv->phy->phy[i]) {
2430 + phy_disconnect(priv->phy->phy[i]);
2431 + }
2432 +}
2433 +
2434 +static void fe_phy_start(struct fe_priv *priv)
2435 +{
2436 + unsigned long flags;
2437 + int i;
2438 +
2439 + for (i = 0; i < 8; i++) {
2440 + if (priv->phy->phy_fixed[i]) {
2441 + spin_lock_irqsave(&priv->phy->lock, flags);
2442 + priv->link[i] = 1;
2443 + if (priv->soc->mdio_adjust_link)
2444 + priv->soc->mdio_adjust_link(priv, i);
2445 + spin_unlock_irqrestore(&priv->phy->lock, flags);
2446 + } else if (priv->phy->phy[i]) {
2447 + phy_start(priv->phy->phy[i]);
2448 + }
2449 + }
2450 +}
2451 +
2452 +static void fe_phy_stop(struct fe_priv *priv)
2453 +{
2454 + unsigned long flags;
2455 + int i;
2456 +
2457 + for (i = 0; i < 8; i++)
2458 + if (priv->phy->phy_fixed[i]) {
2459 + spin_lock_irqsave(&priv->phy->lock, flags);
2460 + priv->link[i] = 0;
2461 + if (priv->soc->mdio_adjust_link)
2462 + priv->soc->mdio_adjust_link(priv, i);
2463 + spin_unlock_irqrestore(&priv->phy->lock, flags);
2464 + } else if (priv->phy->phy[i]) {
2465 + phy_stop(priv->phy->phy[i]);
2466 + }
2467 +}
2468 +
2469 +static struct fe_phy phy_ralink = {
2470 + .connect = fe_phy_connect,
2471 + .disconnect = fe_phy_disconnect,
2472 + .start = fe_phy_start,
2473 + .stop = fe_phy_stop,
2474 +};
2475 +
2476 +int fe_mdio_init(struct fe_priv *priv)
2477 +{
2478 + struct device_node *mii_np;
2479 + int err;
2480 +
2481 + if (!priv->soc->mdio_read || !priv->soc->mdio_write)
2482 + return 0;
2483 +
2484 + spin_lock_init(&phy_ralink.lock);
2485 + priv->phy = &phy_ralink;
2486 +
2487 + mii_np = of_get_child_by_name(priv->device->of_node, "mdio-bus");
2488 + if (!mii_np) {
2489 + dev_err(priv->device, "no %s child node found", "mdio-bus");
2490 + return -ENODEV;
2491 + }
2492 +
2493 + if (!of_device_is_available(mii_np)) {
2494 + err = 0;
2495 + goto err_put_node;
2496 + }
2497 +
2498 + priv->mii_bus = mdiobus_alloc();
2499 + if (priv->mii_bus == NULL) {
2500 + err = -ENOMEM;
2501 + goto err_put_node;
2502 + }
2503 +
2504 + priv->mii_bus->name = "mdio";
2505 + priv->mii_bus->read = priv->soc->mdio_read;
2506 + priv->mii_bus->write = priv->soc->mdio_write;
2507 + priv->mii_bus->reset = fe_mdio_reset;
2508 + priv->mii_bus->irq = priv->mii_irq;
2509 + priv->mii_bus->priv = priv;
2510 + priv->mii_bus->parent = priv->device;
2511 +
2512 + snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s", mii_np->name);
2513 + err = of_mdiobus_register(priv->mii_bus, mii_np);
2514 + if (err)
2515 + goto err_free_bus;
2516 +
2517 + return 0;
2518 +
2519 +err_free_bus:
2520 + kfree(priv->mii_bus);
2521 +err_put_node:
2522 + of_node_put(mii_np);
2523 + priv->mii_bus = NULL;
2524 + return err;
2525 +}
2526 +
2527 +void fe_mdio_cleanup(struct fe_priv *priv)
2528 +{
2529 + if (!priv->mii_bus)
2530 + return;
2531 +
2532 + mdiobus_unregister(priv->mii_bus);
2533 + of_node_put(priv->mii_bus->dev.of_node);
2534 + kfree(priv->mii_bus);
2535 +}
2536 Index: linux-3.10.13/drivers/net/ethernet/ralink/mdio.h
2537 ===================================================================
2538 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
2539 +++ linux-3.10.13/drivers/net/ethernet/ralink/mdio.h 2013-10-08 17:26:47.072172683 +0200
2540 @@ -0,0 +1,29 @@
2541 +/*
2542 + * This program is free software; you can redistribute it and/or modify
2543 + * it under the terms of the GNU General Public License as published by
2544 + * the Free Software Foundation; version 2 of the License
2545 + *
2546 + * This program is distributed in the hope that it will be useful,
2547 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2548 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2549 + * GNU General Public License for more details.
2550 + *
2551 + * You should have received a copy of the GNU General Public License
2552 + * along with this program; if not, write to the Free Software
2553 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
2554 + *
2555 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
2556 + */
2557 +
2558 +#ifndef _RALINK_MDIO_H__
2559 +#define _RALINK_MDIO_H__
2560 +
2561 +#ifdef CONFIG_NET_RALINK_MDIO
2562 +extern int fe_mdio_init(struct fe_priv *priv);
2563 +extern void fe_mdio_cleanup(struct fe_priv *priv);
2564 +extern int fe_connect_phy_node(struct fe_priv *priv, struct device_node *phy_node);
2565 +#else
2566 +static inline int fe_mdio_init(struct fe_priv *priv) { return 0; }
2567 +static inline void fe_mdio_cleanup(struct fe_priv *priv) {}
2568 +#endif
2569 +#endif
2570 Index: linux-3.10.13/drivers/net/ethernet/ralink/mdio_rt2880.c
2571 ===================================================================
2572 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
2573 +++ linux-3.10.13/drivers/net/ethernet/ralink/mdio_rt2880.c 2013-10-08 17:26:47.072172683 +0200
2574 @@ -0,0 +1,232 @@
2575 +/*
2576 + * This program is free software; you can redistribute it and/or modify
2577 + * it under the terms of the GNU General Public License as published by
2578 + * the Free Software Foundation; version 2 of the License
2579 + *
2580 + * This program is distributed in the hope that it will be useful,
2581 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2582 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2583 + * GNU General Public License for more details.
2584 + *
2585 + * You should have received a copy of the GNU General Public License
2586 + * along with this program; if not, write to the Free Software
2587 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
2588 + *
2589 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
2590 + */
2591 +
2592 +#include <linux/module.h>
2593 +#include <linux/kernel.h>
2594 +#include <linux/types.h>
2595 +#include <linux/dma-mapping.h>
2596 +#include <linux/init.h>
2597 +#include <linux/skbuff.h>
2598 +#include <linux/etherdevice.h>
2599 +#include <linux/ethtool.h>
2600 +#include <linux/platform_device.h>
2601 +#include <linux/phy.h>
2602 +#include <linux/of_device.h>
2603 +#include <linux/clk.h>
2604 +#include <linux/of_net.h>
2605 +#include <linux/of_mdio.h>
2606 +
2607 +#include "ralink_soc_eth.h"
2608 +#include "mdio_rt2880.h"
2609 +#include "mdio.h"
2610 +
2611 +#define FE_MDIO_RETRY 1000
2612 +
2613 +static unsigned char *rt2880_speed_str(struct fe_priv *priv)
2614 +{
2615 + switch (priv->phy->speed[0]) {
2616 + case SPEED_1000:
2617 + return "1000";
2618 + case SPEED_100:
2619 + return "100";
2620 + case SPEED_10:
2621 + return "10";
2622 + }
2623 +
2624 + return "?";
2625 +}
2626 +
2627 +void rt2880_mdio_link_adjust(struct fe_priv *priv, int port)
2628 +{
2629 + u32 mdio_cfg;
2630 +
2631 + if (!priv->link[0]) {
2632 + netif_carrier_off(priv->netdev);
2633 + netdev_info(priv->netdev, "link down\n");
2634 + return;
2635 + }
2636 +
2637 + mdio_cfg = FE_MDIO_CFG_TX_CLK_SKEW_200 |
2638 + FE_MDIO_CFG_RX_CLK_SKEW_200 |
2639 + FE_MDIO_CFG_GP1_FRC_EN;
2640 +
2641 + if (priv->phy->duplex[0] == DUPLEX_FULL)
2642 + mdio_cfg |= FE_MDIO_CFG_GP1_DUPLEX;
2643 +
2644 + if (priv->phy->tx_fc[0])
2645 + mdio_cfg |= FE_MDIO_CFG_GP1_FC_TX;
2646 +
2647 + if (priv->phy->rx_fc[0])
2648 + mdio_cfg |= FE_MDIO_CFG_GP1_FC_RX;
2649 +
2650 + switch (priv->phy->speed[0]) {
2651 + case SPEED_10:
2652 + mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_10;
2653 + break;
2654 + case SPEED_100:
2655 + mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_100;
2656 + break;
2657 + case SPEED_1000:
2658 + mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_1000;
2659 + break;
2660 + default:
2661 + BUG();
2662 + }
2663 +
2664 + fe_w32(mdio_cfg, FE_MDIO_CFG);
2665 +
2666 + netif_carrier_on(priv->netdev);
2667 + netdev_info(priv->netdev, "link up (%sMbps/%s duplex)\n",
2668 + rt2880_speed_str(priv),
2669 + (DUPLEX_FULL == priv->phy->duplex[0]) ? "Full" : "Half");
2670 +}
2671 +
2672 +static int rt2880_mdio_wait_ready(struct fe_priv *priv)
2673 +{
2674 + int retries;
2675 +
2676 + retries = FE_MDIO_RETRY;
2677 + while (1) {
2678 + u32 t;
2679 +
2680 + t = fe_r32(FE_MDIO_ACCESS);
2681 + if ((t & (0x1 << 31)) == 0)
2682 + return 0;
2683 +
2684 + if (retries-- == 0)
2685 + break;
2686 +
2687 + udelay(1);
2688 + }
2689 +
2690 + dev_err(priv->device, "MDIO operation timed out\n");
2691 + return -ETIMEDOUT;
2692 +}
2693 +
2694 +int rt2880_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
2695 +{
2696 + struct fe_priv *priv = bus->priv;
2697 + int err;
2698 + u32 t;
2699 +
2700 + err = rt2880_mdio_wait_ready(priv);
2701 + if (err)
2702 + return 0xffff;
2703 +
2704 + t = (phy_addr << 24) | (phy_reg << 16);
2705 + fe_w32(t, FE_MDIO_ACCESS);
2706 + t |= (1 << 31);
2707 + fe_w32(t, FE_MDIO_ACCESS);
2708 +
2709 + err = rt2880_mdio_wait_ready(priv);
2710 + if (err)
2711 + return 0xffff;
2712 +
2713 + pr_info("%s: addr=%04x, reg=%04x, value=%04x\n", __func__,
2714 + phy_addr, phy_reg, fe_r32(FE_MDIO_ACCESS) & 0xffff);
2715 +
2716 + return fe_r32(FE_MDIO_ACCESS) & 0xffff;
2717 +}
2718 +
2719 +int rt2880_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val)
2720 +{
2721 + struct fe_priv *priv = bus->priv;
2722 + int err;
2723 + u32 t;
2724 +
2725 + pr_info("%s: addr=%04x, reg=%04x, value=%04x\n", __func__,
2726 + phy_addr, phy_reg, fe_r32(FE_MDIO_ACCESS) & 0xffff);
2727 +
2728 + err = rt2880_mdio_wait_ready(priv);
2729 + if (err)
2730 + return err;
2731 +
2732 + t = (1 << 30) | (phy_addr << 24) | (phy_reg << 16) | val;
2733 + fe_w32(t, FE_MDIO_ACCESS);
2734 + t |= (1 << 31);
2735 + fe_w32(t, FE_MDIO_ACCESS);
2736 +
2737 + return rt2880_mdio_wait_ready(priv);
2738 +}
2739 +
2740 +void rt2880_port_init(struct fe_priv *priv, struct device_node *np)
2741 +{
2742 + const __be32 *id = of_get_property(np, "reg", NULL);
2743 + const __be32 *link;
2744 + int size;
2745 + int phy_mode;
2746 +
2747 + if (!id || (be32_to_cpu(*id) != 0)) {
2748 + pr_err("%s: invalid port id\n", np->name);
2749 + return;
2750 + }
2751 +
2752 + priv->phy->phy_fixed[0] = of_get_property(np, "ralink,fixed-link", &size);
2753 + if (priv->phy->phy_fixed[0] && (size != (4 * sizeof(*priv->phy->phy_fixed[0])))) {
2754 + pr_err("%s: invalid fixed link property\n", np->name);
2755 + priv->phy->phy_fixed[0] = NULL;
2756 + return;
2757 + }
2758 +
2759 + phy_mode = of_get_phy_mode(np);
2760 + switch (phy_mode) {
2761 + case PHY_INTERFACE_MODE_RGMII:
2762 + break;
2763 + case PHY_INTERFACE_MODE_MII:
2764 + break;
2765 + case PHY_INTERFACE_MODE_RMII:
2766 + break;
2767 + default:
2768 + if (!priv->phy->phy_fixed[0])
2769 + dev_err(priv->device, "port %d - invalid phy mode\n", priv->phy->speed[0]);
2770 + break;
2771 + }
2772 +
2773 + priv->phy->phy_node[0] = of_parse_phandle(np, "phy-handle", 0);
2774 + if (!priv->phy->phy_node[0] && !priv->phy->phy_fixed[0])
2775 + return;
2776 +
2777 + if (priv->phy->phy_fixed[0]) {
2778 + link = priv->phy->phy_fixed[0];
2779 + priv->phy->speed[0] = be32_to_cpup(link++);
2780 + priv->phy->duplex[0] = be32_to_cpup(link++);
2781 + priv->phy->tx_fc[0] = be32_to_cpup(link++);
2782 + priv->phy->rx_fc[0] = be32_to_cpup(link++);
2783 +
2784 + priv->link[0] = 1;
2785 + switch (priv->phy->speed[0]) {
2786 + case SPEED_10:
2787 + break;
2788 + case SPEED_100:
2789 + break;
2790 + case SPEED_1000:
2791 + break;
2792 + default:
2793 + dev_err(priv->device, "invalid link speed: %d\n", priv->phy->speed[0]);
2794 + priv->phy->phy_fixed[0] = 0;
2795 + return;
2796 + }
2797 + dev_info(priv->device, "using fixed link parameters\n");
2798 + rt2880_mdio_link_adjust(priv, 0);
2799 + return;
2800 + }
2801 + if (priv->phy->phy_node[0] && priv->mii_bus->phy_map[0]) {
2802 + fe_connect_phy_node(priv, priv->phy->phy_node[0]);
2803 + }
2804 +
2805 + return;
2806 +}
2807 Index: linux-3.10.13/drivers/net/ethernet/ralink/mdio_rt2880.h
2808 ===================================================================
2809 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
2810 +++ linux-3.10.13/drivers/net/ethernet/ralink/mdio_rt2880.h 2013-10-08 17:26:47.072172683 +0200
2811 @@ -0,0 +1,26 @@
2812 +/*
2813 + * This program is free software; you can redistribute it and/or modify
2814 + * it under the terms of the GNU General Public License as published by
2815 + * the Free Software Foundation; version 2 of the License
2816 + *
2817 + * This program is distributed in the hope that it will be useful,
2818 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2819 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2820 + * GNU General Public License for more details.
2821 + *
2822 + * You should have received a copy of the GNU General Public License
2823 + * along with this program; if not, write to the Free Software
2824 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
2825 + *
2826 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
2827 + */
2828 +
2829 +#ifndef _RALINK_MDIO_RT2880_H__
2830 +#define _RALINK_MDIO_RT2880_H__
2831 +
2832 +void rt2880_mdio_link_adjust(struct fe_priv *priv, int port);
2833 +int rt2880_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg);
2834 +int rt2880_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
2835 +void rt2880_port_init(struct fe_priv *priv, struct device_node *np);
2836 +
2837 +#endif
2838 Index: linux-3.10.13/drivers/net/ethernet/ralink/ralink_soc_eth.c
2839 ===================================================================
2840 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
2841 +++ linux-3.10.13/drivers/net/ethernet/ralink/ralink_soc_eth.c 2013-10-08 17:26:47.072172683 +0200
2842 @@ -0,0 +1,738 @@
2843 +/*
2844 + * This program is free software; you can redistribute it and/or modify
2845 + * it under the terms of the GNU General Public License as published by
2846 + * the Free Software Foundation; version 2 of the License
2847 + *
2848 + * This program is distributed in the hope that it will be useful,
2849 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2850 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2851 + * GNU General Public License for more details.
2852 + *
2853 + * You should have received a copy of the GNU General Public License
2854 + * along with this program; if not, write to the Free Software
2855 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
2856 + *
2857 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
2858 + */
2859 +
2860 +#include <linux/module.h>
2861 +#include <linux/kernel.h>
2862 +#include <linux/types.h>
2863 +#include <linux/dma-mapping.h>
2864 +#include <linux/init.h>
2865 +#include <linux/skbuff.h>
2866 +#include <linux/etherdevice.h>
2867 +#include <linux/ethtool.h>
2868 +#include <linux/platform_device.h>
2869 +#include <linux/of_device.h>
2870 +#include <linux/clk.h>
2871 +#include <linux/of_net.h>
2872 +#include <linux/of_mdio.h>
2873 +#include <linux/if_vlan.h>
2874 +
2875 +#include <asm/mach-ralink/ralink_regs.h>
2876 +
2877 +#include "ralink_soc_eth.h"
2878 +#include "esw_rt3052.h"
2879 +#include "mdio.h"
2880 +
2881 +#define TX_TIMEOUT (20 * HZ / 100)
2882 +#define MAX_RX_LENGTH 1536
2883 +
2884 +static const u32 fe_reg_table_default[FE_REG_COUNT] = {
2885 + [FE_REG_PDMA_GLO_CFG] = FE_PDMA_GLO_CFG,
2886 + [FE_REG_PDMA_RST_CFG] = FE_PDMA_RST_CFG,
2887 + [FE_REG_DLY_INT_CFG] = FE_DLY_INT_CFG,
2888 + [FE_REG_TX_BASE_PTR0] = FE_TX_BASE_PTR0,
2889 + [FE_REG_TX_MAX_CNT0] = FE_TX_MAX_CNT0,
2890 + [FE_REG_TX_CTX_IDX0] = FE_TX_CTX_IDX0,
2891 + [FE_REG_RX_BASE_PTR0] = FE_RX_BASE_PTR0,
2892 + [FE_REG_RX_MAX_CNT0] = FE_RX_MAX_CNT0,
2893 + [FE_REG_RX_CALC_IDX0] = FE_RX_CALC_IDX0,
2894 + [FE_REG_FE_INT_ENABLE] = FE_FE_INT_ENABLE,
2895 + [FE_REG_FE_INT_STATUS] = FE_FE_INT_STATUS,
2896 +};
2897 +
2898 +static const u32 *fe_reg_table = fe_reg_table_default;
2899 +
2900 +static void __iomem *fe_base = 0;
2901 +
2902 +void fe_w32(u32 val, unsigned reg)
2903 +{
2904 + __raw_writel(val, fe_base + reg);
2905 +}
2906 +
2907 +u32 fe_r32(unsigned reg)
2908 +{
2909 + return __raw_readl(fe_base + reg);
2910 +}
2911 +
2912 +static inline void fe_reg_w32(u32 val, enum fe_reg reg)
2913 +{
2914 + fe_w32(val, fe_reg_table[reg]);
2915 +}
2916 +
2917 +static inline u32 fe_reg_r32(enum fe_reg reg)
2918 +{
2919 + return fe_r32(fe_reg_table[reg]);
2920 +}
2921 +
2922 +static inline void fe_int_disable(u32 mask)
2923 +{
2924 + fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) & ~mask,
2925 + FE_REG_FE_INT_ENABLE);
2926 + /* flush write */
2927 + fe_reg_r32(FE_REG_FE_INT_ENABLE);
2928 +}
2929 +
2930 +static inline void fe_int_enable(u32 mask)
2931 +{
2932 + fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) | mask,
2933 + FE_REG_FE_INT_ENABLE);
2934 + /* flush write */
2935 + fe_reg_r32(FE_REG_FE_INT_ENABLE);
2936 +}
2937 +
2938 +static inline void fe_hw_set_macaddr(struct fe_priv *priv, unsigned char *mac)
2939 +{
2940 + unsigned long flags;
2941 +
2942 + spin_lock_irqsave(&priv->page_lock, flags);
2943 + fe_w32((mac[0] << 8) | mac[1], FE_GDMA1_MAC_ADRH);
2944 + fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
2945 + FE_GDMA1_MAC_ADRL);
2946 + spin_unlock_irqrestore(&priv->page_lock, flags);
2947 +}
2948 +
2949 +static int fe_set_mac_address(struct net_device *dev, void *p)
2950 +{
2951 + int ret = eth_mac_addr(dev, p);
2952 +
2953 + if (!ret) {
2954 + struct fe_priv *priv = netdev_priv(dev);
2955 +
2956 + if (priv->soc->set_mac)
2957 + priv->soc->set_mac(priv, dev->dev_addr);
2958 + else
2959 + fe_hw_set_macaddr(priv, p);
2960 + }
2961 +
2962 + return ret;
2963 +}
2964 +
2965 +static struct sk_buff* fe_alloc_skb(struct fe_priv *priv)
2966 +{
2967 + struct sk_buff *skb;
2968 +
2969 + skb = netdev_alloc_skb(priv->netdev, MAX_RX_LENGTH + NET_IP_ALIGN);
2970 + if (!skb)
2971 + return NULL;
2972 +
2973 + skb_reserve(skb, NET_IP_ALIGN);
2974 +
2975 + return skb;
2976 +}
2977 +
2978 +static int fe_alloc_rx(struct fe_priv *priv)
2979 +{
2980 + int size = NUM_DMA_DESC * sizeof(struct fe_rx_dma);
2981 + int i;
2982 +
2983 + priv->rx_dma = dma_alloc_coherent(&priv->netdev->dev, size,
2984 + &priv->rx_phys, GFP_ATOMIC);
2985 + if (!priv->rx_dma)
2986 + return -ENOMEM;
2987 +
2988 + memset(priv->rx_dma, 0, size);
2989 +
2990 + for (i = 0; i < NUM_DMA_DESC; i++) {
2991 + priv->rx_skb[i] = fe_alloc_skb(priv);
2992 + if (!priv->rx_skb[i])
2993 + return -ENOMEM;
2994 + }
2995 +
2996 + for (i = 0; i < NUM_DMA_DESC; i++) {
2997 + dma_addr_t dma_addr = dma_map_single(&priv->netdev->dev,
2998 + priv->rx_skb[i]->data,
2999 + MAX_RX_LENGTH,
3000 + DMA_FROM_DEVICE);
3001 + priv->rx_dma[i].rxd1 = (unsigned int) dma_addr;
3002 +
3003 + if (priv->soc->rx_dma)
3004 + priv->soc->rx_dma(priv, i, MAX_RX_LENGTH);
3005 + else
3006 + priv->rx_dma[i].rxd2 = RX_DMA_LSO;
3007 + }
3008 + wmb();
3009 +
3010 + fe_reg_w32(priv->rx_phys, FE_REG_RX_BASE_PTR0);
3011 + fe_reg_w32(NUM_DMA_DESC, FE_REG_RX_MAX_CNT0);
3012 + fe_reg_w32((NUM_DMA_DESC - 1), FE_REG_RX_CALC_IDX0);
3013 + fe_reg_w32(FE_PST_DRX_IDX0, FE_REG_PDMA_RST_CFG);
3014 +
3015 + return 0;
3016 +}
3017 +
3018 +static int fe_alloc_tx(struct fe_priv *priv)
3019 +{
3020 + int size = NUM_DMA_DESC * sizeof(struct fe_tx_dma);
3021 + int i;
3022 +
3023 + priv->tx_free_idx = 0;
3024 +
3025 + priv->tx_dma = dma_alloc_coherent(&priv->netdev->dev, size,
3026 + &priv->tx_phys, GFP_ATOMIC);
3027 + if (!priv->tx_dma)
3028 + return -ENOMEM;
3029 +
3030 + memset(priv->tx_dma, 0, size);
3031 +
3032 + for (i = 0; i < NUM_DMA_DESC; i++) {
3033 + if (priv->soc->tx_dma) {
3034 + priv->soc->tx_dma(priv, i, 0);
3035 + continue;
3036 + }
3037 +
3038 + priv->tx_dma[i].txd2 = TX_DMA_LSO | TX_DMA_DONE;
3039 + priv->tx_dma[i].txd4 = TX_DMA_QN(3) | TX_DMA_PN(1);
3040 + }
3041 +
3042 + fe_reg_w32(priv->tx_phys, FE_REG_TX_BASE_PTR0);
3043 + fe_reg_w32(NUM_DMA_DESC, FE_REG_TX_MAX_CNT0);
3044 + fe_reg_w32(0, FE_REG_TX_CTX_IDX0);
3045 + fe_reg_w32(FE_PST_DTX_IDX0, FE_REG_PDMA_RST_CFG);
3046 +
3047 + return 0;
3048 +}
3049 +
3050 +static void fe_free_dma(struct fe_priv *priv)
3051 +{
3052 + int i;
3053 +
3054 + for (i = 0; i < NUM_DMA_DESC; i++) {
3055 + if (priv->rx_skb[i]) {
3056 + dma_unmap_single(&priv->netdev->dev, priv->rx_dma[i].rxd1,
3057 + MAX_RX_LENGTH, DMA_FROM_DEVICE);
3058 + dev_kfree_skb_any(priv->rx_skb[i]);
3059 + priv->rx_skb[i] = NULL;
3060 + }
3061 +
3062 + if (priv->tx_skb[i]) {
3063 + dev_kfree_skb_any(priv->tx_skb[i]);
3064 + priv->tx_skb[i] = NULL;
3065 + }
3066 + }
3067 +
3068 + if (priv->rx_dma) {
3069 + int size = NUM_DMA_DESC * sizeof(struct fe_rx_dma);
3070 + dma_free_coherent(&priv->netdev->dev, size, priv->rx_dma,
3071 + priv->rx_phys);
3072 + }
3073 +
3074 + if (priv->tx_dma) {
3075 + int size = NUM_DMA_DESC * sizeof(struct fe_tx_dma);
3076 + dma_free_coherent(&priv->netdev->dev, size, priv->tx_dma,
3077 + priv->tx_phys);
3078 + }
3079 +
3080 + netdev_reset_queue(priv->netdev);
3081 +}
3082 +
3083 +static int fe_start_xmit(struct sk_buff *skb, struct net_device *dev)
3084 +{
3085 + struct fe_priv *priv = netdev_priv(dev);
3086 + dma_addr_t mapped_addr;
3087 + u32 tx_next;
3088 + u32 tx;
3089 +
3090 + if (priv->soc->min_pkt_len) {
3091 + if (skb->len < priv->soc->min_pkt_len) {
3092 + if (skb_padto(skb, priv->soc->min_pkt_len)) {
3093 + printk(KERN_ERR
3094 + "fe_eth: skb_padto failed\n");
3095 + kfree_skb(skb);
3096 + return 0;
3097 + }
3098 + skb_put(skb, priv->soc->min_pkt_len - skb->len);
3099 + }
3100 + }
3101 +
3102 + dev->trans_start = jiffies;
3103 + mapped_addr = dma_map_single(&priv->netdev->dev, skb->data,
3104 + skb->len, DMA_TO_DEVICE);
3105 +
3106 + spin_lock(&priv->page_lock);
3107 +
3108 + tx = fe_reg_r32(FE_REG_TX_CTX_IDX0);
3109 + tx_next = (tx + 1) % NUM_DMA_DESC;
3110 +
3111 + if ((priv->tx_skb[tx]) || (priv->tx_skb[tx_next]) ||
3112 + !(priv->tx_dma[tx].txd2 & TX_DMA_DONE) ||
3113 + !(priv->tx_dma[tx_next].txd2 & TX_DMA_DONE))
3114 + {
3115 + spin_unlock(&priv->page_lock);
3116 + dev->stats.tx_dropped++;
3117 + kfree_skb(skb);
3118 +
3119 + return NETDEV_TX_OK;
3120 + }
3121 +
3122 + priv->tx_skb[tx] = skb;
3123 + priv->tx_dma[tx].txd1 = (unsigned int) mapped_addr;
3124 + wmb();
3125 + if (priv->soc->tx_dma)
3126 + priv->soc->tx_dma(priv, tx, skb->len);
3127 + else
3128 + priv->tx_dma[tx].txd2 = TX_DMA_LSO | TX_DMA_PLEN0(skb->len);
3129 +
3130 + if (skb->ip_summed == CHECKSUM_PARTIAL)
3131 + priv->tx_dma[tx].txd4 |= TX_DMA_CHKSUM;
3132 + else
3133 + priv->tx_dma[tx].txd4 &= ~TX_DMA_CHKSUM;
3134 +
3135 + priv->tx_dma[tx].txd4 &= ~0x80;
3136 +
3137 + dev->stats.tx_packets++;
3138 + dev->stats.tx_bytes += skb->len;
3139 +
3140 + fe_reg_w32(tx_next, FE_REG_TX_CTX_IDX0);
3141 + netdev_sent_queue(dev, skb->len);
3142 +
3143 + spin_unlock(&priv->page_lock);
3144 +
3145 + return NETDEV_TX_OK;
3146 +}
3147 +
3148 +static int fe_poll_rx(struct napi_struct *napi, int budget)
3149 +{
3150 + struct fe_priv *priv = container_of(napi, struct fe_priv, rx_napi);
3151 + int idx = fe_reg_r32(FE_REG_RX_CALC_IDX0);
3152 + int complete = 0;
3153 + int rx = 0;
3154 +
3155 + while ((rx < budget) && !complete) {
3156 + idx = (idx + 1) % NUM_DMA_DESC;
3157 +
3158 + if (priv->rx_dma[idx].rxd2 & RX_DMA_DONE) {
3159 + struct sk_buff *new_skb = fe_alloc_skb(priv);
3160 +
3161 + if (new_skb) {
3162 + int pktlen = RX_DMA_PLEN0(priv->rx_dma[idx].rxd2);
3163 + dma_addr_t dma_addr;
3164 +
3165 + dma_unmap_single(&priv->netdev->dev, priv->rx_dma[idx].rxd1,
3166 + MAX_RX_LENGTH, DMA_FROM_DEVICE);
3167 +
3168 + skb_put(priv->rx_skb[idx], pktlen);
3169 + priv->rx_skb[idx]->dev = priv->netdev;
3170 + priv->rx_skb[idx]->protocol = eth_type_trans(priv->rx_skb[idx], priv->netdev);
3171 + if (priv->rx_dma[idx].rxd4 & priv->soc->checksum_bit)
3172 + priv->rx_skb[idx]->ip_summed = CHECKSUM_UNNECESSARY;
3173 + else
3174 + priv->rx_skb[idx]->ip_summed = CHECKSUM_NONE;
3175 + priv->netdev->stats.rx_packets++;
3176 + priv->netdev->stats.rx_bytes += pktlen;
3177 + netif_receive_skb(priv->rx_skb[idx]);
3178 +
3179 + priv->rx_skb[idx] = new_skb;
3180 +
3181 + dma_addr = dma_map_single(&priv->netdev->dev,
3182 + new_skb->data,
3183 + MAX_RX_LENGTH,
3184 + DMA_FROM_DEVICE);
3185 + priv->rx_dma[idx].rxd1 = (unsigned int) dma_addr;
3186 + wmb();
3187 + } else {
3188 + priv->netdev->stats.rx_dropped++;
3189 + }
3190 +
3191 + if (priv->soc->rx_dma)
3192 + priv->soc->rx_dma(priv, idx, MAX_RX_LENGTH);
3193 + else
3194 + priv->rx_dma[idx].rxd2 = RX_DMA_LSO;
3195 + fe_reg_w32(idx, FE_REG_RX_CALC_IDX0);
3196 +
3197 + rx++;
3198 + } else {
3199 + complete = 1;
3200 + }
3201 + }
3202 +
3203 + if (complete) {
3204 + napi_complete(&priv->rx_napi);
3205 + fe_int_enable(priv->soc->rx_dly_int);
3206 + }
3207 +
3208 + return rx;
3209 +}
3210 +
3211 +static void fe_tx_housekeeping(unsigned long ptr)
3212 +{
3213 + struct net_device *dev = (struct net_device*)ptr;
3214 + struct fe_priv *priv = netdev_priv(dev);
3215 + unsigned int bytes_compl = 0;
3216 + unsigned int pkts_compl = 0;
3217 +
3218 + spin_lock(&priv->page_lock);
3219 + while (1) {
3220 + struct fe_tx_dma *txd;
3221 +
3222 + txd = &priv->tx_dma[priv->tx_free_idx];
3223 +
3224 + if (!(txd->txd2 & TX_DMA_DONE) || !(priv->tx_skb[priv->tx_free_idx]))
3225 + break;
3226 +
3227 + bytes_compl += priv->tx_skb[priv->tx_free_idx]->len;
3228 + pkts_compl++;
3229 +
3230 + dev_kfree_skb_irq(priv->tx_skb[priv->tx_free_idx]);
3231 + priv->tx_skb[priv->tx_free_idx] = NULL;
3232 + priv->tx_free_idx++;
3233 + if (priv->tx_free_idx >= NUM_DMA_DESC)
3234 + priv->tx_free_idx = 0;
3235 + }
3236 +
3237 + netdev_completed_queue(priv->netdev, pkts_compl, bytes_compl);
3238 + spin_unlock(&priv->page_lock);
3239 +
3240 + fe_int_enable(priv->soc->tx_dly_int);
3241 +}
3242 +
3243 +static void fe_tx_timeout(struct net_device *dev)
3244 +{
3245 + struct fe_priv *priv = netdev_priv(dev);
3246 +
3247 + tasklet_schedule(&priv->tx_tasklet);
3248 + priv->netdev->stats.tx_errors++;
3249 + netdev_err(dev, "transmit timed out, waking up the queue\n");
3250 + netif_wake_queue(dev);
3251 +}
3252 +
3253 +static irqreturn_t fe_handle_irq(int irq, void *dev)
3254 +{
3255 + struct fe_priv *priv = netdev_priv(dev);
3256 + unsigned int status;
3257 + unsigned int mask;
3258 +
3259 + status = fe_reg_r32(FE_REG_FE_INT_STATUS);
3260 + mask = fe_reg_r32(FE_REG_FE_INT_ENABLE);
3261 +
3262 + if (!(status & mask))
3263 + return IRQ_NONE;
3264 +
3265 + if (status & priv->soc->rx_dly_int) {
3266 + fe_int_disable(priv->soc->rx_dly_int);
3267 + napi_schedule(&priv->rx_napi);
3268 + }
3269 +
3270 + if (status & priv->soc->tx_dly_int) {
3271 + fe_int_disable(priv->soc->tx_dly_int);
3272 + tasklet_schedule(&priv->tx_tasklet);
3273 + }
3274 +
3275 + fe_reg_w32(status, FE_REG_FE_INT_STATUS);
3276 +
3277 + return IRQ_HANDLED;
3278 +}
3279 +
3280 +static int fe_hw_init(struct net_device *dev)
3281 +{
3282 + struct fe_priv *priv = netdev_priv(dev);
3283 + int err;
3284 +
3285 + err = devm_request_irq(priv->device, dev->irq, fe_handle_irq, 0,
3286 + dev_name(priv->device), dev);
3287 + if (err)
3288 + return err;
3289 +
3290 + err = fe_alloc_rx(priv);
3291 + if (!err)
3292 + err = fe_alloc_tx(priv);
3293 + if (err)
3294 + return err;
3295 +
3296 + if (priv->soc->set_mac)
3297 + priv->soc->set_mac(priv, dev->dev_addr);
3298 + else
3299 + fe_hw_set_macaddr(priv, dev->dev_addr);
3300 +
3301 + fe_reg_w32(FE_DELAY_INIT, FE_REG_DLY_INT_CFG);
3302 +
3303 + fe_int_disable(priv->soc->tx_dly_int | priv->soc->rx_dly_int);
3304 +
3305 + tasklet_init(&priv->tx_tasklet, fe_tx_housekeeping, (unsigned long)dev);
3306 +
3307 + if (priv->soc->fwd_config) {
3308 + priv->soc->fwd_config(priv);
3309 + } else {
3310 + unsigned long sysclk = priv->sysclk;
3311 +
3312 + if (!sysclk) {
3313 + netdev_err(dev, "unable to get clock\n");
3314 + return -EINVAL;
3315 + }
3316 +
3317 + sysclk /= FE_US_CYC_CNT_DIVISOR;
3318 + sysclk <<= FE_US_CYC_CNT_SHIFT;
3319 +
3320 + fe_w32((fe_r32(FE_FE_GLO_CFG) &
3321 + ~(FE_US_CYC_CNT_MASK << FE_US_CYC_CNT_SHIFT)) | sysclk,
3322 + FE_FE_GLO_CFG);
3323 +
3324 + fe_w32(fe_r32(FE_GDMA1_FWD_CFG) & ~0xffff, FE_GDMA1_FWD_CFG);
3325 + fe_w32(fe_r32(FE_GDMA1_FWD_CFG) | (FE_GDM1_ICS_EN | FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
3326 + FE_GDMA1_FWD_CFG);
3327 + fe_w32(fe_r32(FE_CDMA_CSG_CFG) | (FE_ICS_GEN_EN | FE_TCS_GEN_EN | FE_UCS_GEN_EN),
3328 + FE_CDMA_CSG_CFG);
3329 + fe_w32(FE_PSE_FQFC_CFG_INIT, FE_PSE_FQ_CFG);
3330 + }
3331 +
3332 + fe_w32(1, FE_FE_RST_GL);
3333 + fe_w32(0, FE_FE_RST_GL);
3334 +
3335 + return 0;
3336 +}
3337 +
3338 +static int fe_open(struct net_device *dev)
3339 +{
3340 + struct fe_priv *priv = netdev_priv(dev);
3341 + unsigned long flags;
3342 + u32 val;
3343 +
3344 + spin_lock_irqsave(&priv->page_lock, flags);
3345 + napi_enable(&priv->rx_napi);
3346 +
3347 + val = FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN;
3348 + val |= priv->soc->pdma_glo_cfg;
3349 + fe_reg_w32(val, FE_REG_PDMA_GLO_CFG);
3350 +
3351 + spin_unlock_irqrestore(&priv->page_lock, flags);
3352 +
3353 + if (priv->phy)
3354 + priv->phy->start(priv);
3355 +
3356 + if (priv->soc->has_carrier && priv->soc->has_carrier(priv))
3357 + netif_carrier_on(dev);
3358 +
3359 + netif_start_queue(dev);
3360 + fe_int_enable(priv->soc->tx_dly_int | priv->soc->rx_dly_int);
3361 +
3362 + return 0;
3363 +}
3364 +
3365 +static int fe_stop(struct net_device *dev)
3366 +{
3367 + struct fe_priv *priv = netdev_priv(dev);
3368 + unsigned long flags;
3369 +
3370 + fe_int_disable(priv->soc->tx_dly_int | priv->soc->rx_dly_int);
3371 +
3372 + netif_stop_queue(dev);
3373 +
3374 + if (priv->phy)
3375 + priv->phy->stop(priv);
3376 +
3377 + spin_lock_irqsave(&priv->page_lock, flags);
3378 + napi_disable(&priv->rx_napi);
3379 +
3380 + fe_reg_w32(fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
3381 + ~(FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN),
3382 + FE_REG_PDMA_GLO_CFG);
3383 + spin_unlock_irqrestore(&priv->page_lock, flags);
3384 +
3385 + return 0;
3386 +}
3387 +
3388 +static int __init fe_init(struct net_device *dev)
3389 +{
3390 + struct fe_priv *priv = netdev_priv(dev);
3391 + struct device_node *port;
3392 + int err;
3393 +
3394 + BUG_ON(!priv->soc->reset_fe);
3395 + priv->soc->reset_fe();
3396 +
3397 + if (priv->soc->switch_init)
3398 + priv->soc->switch_init(priv);
3399 +
3400 + net_srandom(jiffies);
3401 + memcpy(dev->dev_addr, priv->soc->mac, ETH_ALEN);
3402 + of_get_mac_address_mtd(priv->device->of_node, dev->dev_addr);
3403 +
3404 + err = fe_mdio_init(priv);
3405 + if (err)
3406 + return err;
3407 +
3408 + if (priv->phy) {
3409 + err = priv->phy->connect(priv);
3410 + if (err)
3411 + goto err_mdio_cleanup;
3412 + }
3413 +
3414 + if (priv->soc->port_init)
3415 + for_each_child_of_node(priv->device->of_node, port)
3416 + if (of_device_is_compatible(port, "ralink,eth-port") && of_device_is_available(port))
3417 + priv->soc->port_init(priv, port);
3418 +
3419 + err = fe_hw_init(dev);
3420 + if (err)
3421 + goto err_phy_disconnect;
3422 +
3423 + if (priv->soc->switch_config)
3424 + priv->soc->switch_config(priv);
3425 +
3426 + return 0;
3427 +
3428 +err_phy_disconnect:
3429 + if (priv->phy)
3430 + priv->phy->disconnect(priv);
3431 +err_mdio_cleanup:
3432 + fe_mdio_cleanup(priv);
3433 +
3434 + return err;
3435 +}
3436 +
3437 +static void fe_uninit(struct net_device *dev)
3438 +{
3439 + struct fe_priv *priv = netdev_priv(dev);
3440 +
3441 + tasklet_kill(&priv->tx_tasklet);
3442 +
3443 + if (priv->phy)
3444 + priv->phy->disconnect(priv);
3445 + fe_mdio_cleanup(priv);
3446 +
3447 + fe_reg_w32(0, FE_REG_FE_INT_ENABLE);
3448 + free_irq(dev->irq, dev);
3449 +
3450 + fe_free_dma(priv);
3451 +}
3452 +
3453 +static const struct net_device_ops fe_netdev_ops = {
3454 + .ndo_init = fe_init,
3455 + .ndo_uninit = fe_uninit,
3456 + .ndo_open = fe_open,
3457 + .ndo_stop = fe_stop,
3458 + .ndo_start_xmit = fe_start_xmit,
3459 + .ndo_tx_timeout = fe_tx_timeout,
3460 + .ndo_set_mac_address = fe_set_mac_address,
3461 + .ndo_change_mtu = eth_change_mtu,
3462 + .ndo_validate_addr = eth_validate_addr,
3463 +};
3464 +
3465 +static int fe_probe(struct platform_device *pdev)
3466 +{
3467 + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3468 + const struct of_device_id *match;
3469 + struct fe_soc_data *soc = NULL;
3470 + struct net_device *netdev;
3471 + struct fe_priv *priv;
3472 + struct clk *sysclk;
3473 + int err;
3474 +
3475 + match = of_match_device(of_fe_match, &pdev->dev);
3476 + soc = (struct fe_soc_data *) match->data;
3477 + if (soc->reg_table)
3478 + fe_reg_table = soc->reg_table;
3479 +
3480 + fe_base = devm_request_and_ioremap(&pdev->dev, res);
3481 + if (!fe_base)
3482 + return -ENOMEM;
3483 +
3484 + netdev = alloc_etherdev(sizeof(struct fe_priv));
3485 + if (!netdev) {
3486 + dev_err(&pdev->dev, "alloc_etherdev failed\n");
3487 + return -ENOMEM;
3488 + }
3489 +
3490 + strcpy(netdev->name, "eth%d");
3491 + netdev->netdev_ops = &fe_netdev_ops;
3492 + netdev->base_addr = (unsigned long) fe_base;
3493 + netdev->watchdog_timeo = TX_TIMEOUT;
3494 + netdev->features |= NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
3495 +
3496 + netdev->irq = platform_get_irq(pdev, 0);
3497 + if (netdev->irq < 0) {
3498 + dev_err(&pdev->dev, "no IRQ resource found\n");
3499 + kfree(netdev);
3500 + return -ENXIO;
3501 + }
3502 +
3503 + priv = netdev_priv(netdev);
3504 + memset(priv, 0, sizeof(struct fe_priv));
3505 + spin_lock_init(&priv->page_lock);
3506 +
3507 + sysclk = devm_clk_get(&pdev->dev, NULL);
3508 + if (!IS_ERR(sysclk))
3509 + priv->sysclk = clk_get_rate(sysclk);
3510 +
3511 + priv->netdev = netdev;
3512 + priv->device = &pdev->dev;
3513 + priv->soc = soc;
3514 +
3515 + err = register_netdev(netdev);
3516 + if (err) {
3517 + dev_err(&pdev->dev, "error bringing up device\n");
3518 + kfree(netdev);
3519 + return err;
3520 + }
3521 + netif_napi_add(netdev, &priv->rx_napi, fe_poll_rx, 32);
3522 +
3523 + platform_set_drvdata(pdev, netdev);
3524 +
3525 + netdev_info(netdev, "done loading\n");
3526 +
3527 + return 0;
3528 +}
3529 +
3530 +static int fe_remove(struct platform_device *pdev)
3531 +{
3532 + struct net_device *dev = platform_get_drvdata(pdev);
3533 + struct fe_priv *priv = netdev_priv(dev);
3534 +
3535 + netif_stop_queue(dev);
3536 + netif_napi_del(&priv->rx_napi);
3537 +
3538 + unregister_netdev(dev);
3539 + free_netdev(dev);
3540 +
3541 + return 0;
3542 +}
3543 +
3544 +static struct platform_driver fe_driver = {
3545 + .probe = fe_probe,
3546 + .remove = fe_remove,
3547 + .driver = {
3548 + .name = "ralink_soc_eth",
3549 + .owner = THIS_MODULE,
3550 + .of_match_table = of_fe_match,
3551 + },
3552 +};
3553 +
3554 +static int __init init_rtfe(void)
3555 +{
3556 + int ret;
3557 +
3558 + ret = rtesw_init();
3559 + if (ret)
3560 + return ret;
3561 +
3562 + ret = platform_driver_register(&fe_driver);
3563 + if (ret)
3564 + rtesw_exit();
3565 +
3566 + return ret;
3567 +}
3568 +
3569 +static void __exit exit_rtfe(void)
3570 +{
3571 + platform_driver_unregister(&fe_driver);
3572 + rtesw_exit();
3573 +}
3574 +
3575 +module_init(init_rtfe);
3576 +module_exit(exit_rtfe);
3577 +
3578 +MODULE_LICENSE("GPL");
3579 +MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
3580 +MODULE_DESCRIPTION("Ethernet driver for Ralink SoC");
3581 Index: linux-3.10.13/drivers/net/ethernet/ralink/ralink_soc_eth.h
3582 ===================================================================
3583 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
3584 +++ linux-3.10.13/drivers/net/ethernet/ralink/ralink_soc_eth.h 2013-10-08 17:26:47.076172688 +0200
3585 @@ -0,0 +1,375 @@
3586 +/*
3587 + * This program is free software; you can redistribute it and/or modify
3588 + * it under the terms of the GNU General Public License as published by
3589 + * the Free Software Foundation; version 2 of the License
3590 + *
3591 + * This program is distributed in the hope that it will be useful,
3592 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3593 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3594 + * GNU General Public License for more details.
3595 + *
3596 + * You should have received a copy of the GNU General Public License
3597 + * along with this program; if not, write to the Free Software
3598 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
3599 + *
3600 + * based on Ralink SDK3.3
3601 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
3602 + */
3603 +
3604 +#ifndef FE_ETH_H
3605 +#define FE_ETH_H
3606 +
3607 +#include <linux/mii.h>
3608 +#include <linux/interrupt.h>
3609 +#include <linux/netdevice.h>
3610 +#include <linux/dma-mapping.h>
3611 +#include <linux/phy.h>
3612 +
3613 +
3614 +enum fe_reg {
3615 + FE_REG_PDMA_GLO_CFG = 0,
3616 + FE_REG_PDMA_RST_CFG,
3617 + FE_REG_DLY_INT_CFG,
3618 + FE_REG_TX_BASE_PTR0,
3619 + FE_REG_TX_MAX_CNT0,
3620 + FE_REG_TX_CTX_IDX0,
3621 + FE_REG_RX_BASE_PTR0,
3622 + FE_REG_RX_MAX_CNT0,
3623 + FE_REG_RX_CALC_IDX0,
3624 + FE_REG_FE_INT_ENABLE,
3625 + FE_REG_FE_INT_STATUS,
3626 + FE_REG_FE_DMA_VID_BASE,
3627 + FE_REG_COUNT
3628 +};
3629 +
3630 +#define NUM_DMA_DESC 0x100
3631 +
3632 +#define FE_DELAY_EN_INT 0x80
3633 +#define FE_DELAY_MAX_INT 0x04
3634 +#define FE_DELAY_MAX_TOUT 0x04
3635 +#define FE_DELAY_CHAN (((FE_DELAY_EN_INT | FE_DELAY_MAX_INT) << 8) | FE_DELAY_MAX_TOUT)
3636 +#define FE_DELAY_INIT ((FE_DELAY_CHAN << 16) | FE_DELAY_CHAN)
3637 +#define FE_PSE_FQFC_CFG_INIT 0x80504000
3638 +
3639 +/* interrupt bits */
3640 +#define FE_CNT_PPE_AF BIT(31)
3641 +#define FE_CNT_GDM_AF BIT(29)
3642 +#define FE_PSE_P2_FC BIT(26)
3643 +#define FE_PSE_BUF_DROP BIT(24)
3644 +#define FE_GDM_OTHER_DROP BIT(23)
3645 +#define FE_PSE_P1_FC BIT(22)
3646 +#define FE_PSE_P0_FC BIT(21)
3647 +#define FE_PSE_FQ_EMPTY BIT(20)
3648 +#define FE_GE1_STA_CHG BIT(18)
3649 +#define FE_TX_COHERENT BIT(17)
3650 +#define FE_RX_COHERENT BIT(16)
3651 +#define FE_TX_DONE_INT3 BIT(11)
3652 +#define FE_TX_DONE_INT2 BIT(10)
3653 +#define FE_TX_DONE_INT1 BIT(9)
3654 +#define FE_TX_DONE_INT0 BIT(8)
3655 +#define FE_RX_DONE_INT0 BIT(2)
3656 +#define FE_TX_DLY_INT BIT(1)
3657 +#define FE_RX_DLY_INT BIT(0)
3658 +
3659 +#define RT5350_RX_DLY_INT BIT(30)
3660 +#define RT5350_TX_DLY_INT BIT(28)
3661 +
3662 +/* registers */
3663 +#define FE_FE_OFFSET 0x0000
3664 +#define FE_GDMA_OFFSET 0x0020
3665 +#define FE_PSE_OFFSET 0x0040
3666 +#define FE_GDMA2_OFFSET 0x0060
3667 +#define FE_CDMA_OFFSET 0x0080
3668 +#define FE_DMA_VID0 0x00a8
3669 +#define FE_PDMA_OFFSET 0x0100
3670 +#define FE_PPE_OFFSET 0x0200
3671 +#define FE_CMTABLE_OFFSET 0x0400
3672 +#define FE_POLICYTABLE_OFFSET 0x1000
3673 +
3674 +#define RT5350_PDMA_OFFSET 0x0800
3675 +#define RT5350_SDM_OFFSET 0x0c00
3676 +
3677 +#define FE_MDIO_ACCESS (FE_FE_OFFSET + 0x00)
3678 +#define FE_MDIO_CFG (FE_FE_OFFSET + 0x04)
3679 +#define FE_FE_GLO_CFG (FE_FE_OFFSET + 0x08)
3680 +#define FE_FE_RST_GL (FE_FE_OFFSET + 0x0C)
3681 +#define FE_FE_INT_STATUS (FE_FE_OFFSET + 0x10)
3682 +#define FE_FE_INT_ENABLE (FE_FE_OFFSET + 0x14)
3683 +#define FE_MDIO_CFG2 (FE_FE_OFFSET + 0x18)
3684 +#define FE_FOC_TS_T (FE_FE_OFFSET + 0x1C)
3685 +
3686 +#define FE_GDMA1_FWD_CFG (FE_GDMA_OFFSET + 0x00)
3687 +#define FE_GDMA1_SCH_CFG (FE_GDMA_OFFSET + 0x04)
3688 +#define FE_GDMA1_SHPR_CFG (FE_GDMA_OFFSET + 0x08)
3689 +#define FE_GDMA1_MAC_ADRL (FE_GDMA_OFFSET + 0x0C)
3690 +#define FE_GDMA1_MAC_ADRH (FE_GDMA_OFFSET + 0x10)
3691 +
3692 +#define FE_GDMA2_FWD_CFG (FE_GDMA2_OFFSET + 0x00)
3693 +#define FE_GDMA2_SCH_CFG (FE_GDMA2_OFFSET + 0x04)
3694 +#define FE_GDMA2_SHPR_CFG (FE_GDMA2_OFFSET + 0x08)
3695 +#define FE_GDMA2_MAC_ADRL (FE_GDMA2_OFFSET + 0x0C)
3696 +#define FE_GDMA2_MAC_ADRH (FE_GDMA2_OFFSET + 0x10)
3697 +
3698 +#define FE_PSE_FQ_CFG (FE_PSE_OFFSET + 0x00)
3699 +#define FE_CDMA_FC_CFG (FE_PSE_OFFSET + 0x04)
3700 +#define FE_GDMA1_FC_CFG (FE_PSE_OFFSET + 0x08)
3701 +#define FE_GDMA2_FC_CFG (FE_PSE_OFFSET + 0x0C)
3702 +
3703 +#define FE_CDMA_CSG_CFG (FE_CDMA_OFFSET + 0x00)
3704 +#define FE_CDMA_SCH_CFG (FE_CDMA_OFFSET + 0x04)
3705 +
3706 +#define MT7620A_GDMA_OFFSET 0x0600
3707 +#define MT7620A_GDMA1_FWD_CFG (MT7620A_GDMA_OFFSET + 0x00)
3708 +#define MT7620A_FE_GDMA1_SCH_CFG (MT7620A_GDMA_OFFSET + 0x04)
3709 +#define MT7620A_FE_GDMA1_SHPR_CFG (MT7620A_GDMA_OFFSET + 0x08)
3710 +#define MT7620A_FE_GDMA1_MAC_ADRL (MT7620A_GDMA_OFFSET + 0x0C)
3711 +#define MT7620A_FE_GDMA1_MAC_ADRH (MT7620A_GDMA_OFFSET + 0x10)
3712 +
3713 +#define RT5350_TX_BASE_PTR0 (RT5350_PDMA_OFFSET + 0x00)
3714 +#define RT5350_TX_MAX_CNT0 (RT5350_PDMA_OFFSET + 0x04)
3715 +#define RT5350_TX_CTX_IDX0 (RT5350_PDMA_OFFSET + 0x08)
3716 +#define RT5350_TX_DTX_IDX0 (RT5350_PDMA_OFFSET + 0x0C)
3717 +#define RT5350_TX_BASE_PTR1 (RT5350_PDMA_OFFSET + 0x10)
3718 +#define RT5350_TX_MAX_CNT1 (RT5350_PDMA_OFFSET + 0x14)
3719 +#define RT5350_TX_CTX_IDX1 (RT5350_PDMA_OFFSET + 0x18)
3720 +#define RT5350_TX_DTX_IDX1 (RT5350_PDMA_OFFSET + 0x1C)
3721 +#define RT5350_TX_BASE_PTR2 (RT5350_PDMA_OFFSET + 0x20)
3722 +#define RT5350_TX_MAX_CNT2 (RT5350_PDMA_OFFSET + 0x24)
3723 +#define RT5350_TX_CTX_IDX2 (RT5350_PDMA_OFFSET + 0x28)
3724 +#define RT5350_TX_DTX_IDX2 (RT5350_PDMA_OFFSET + 0x2C)
3725 +#define RT5350_TX_BASE_PTR3 (RT5350_PDMA_OFFSET + 0x30)
3726 +#define RT5350_TX_MAX_CNT3 (RT5350_PDMA_OFFSET + 0x34)
3727 +#define RT5350_TX_CTX_IDX3 (RT5350_PDMA_OFFSET + 0x38)
3728 +#define RT5350_TX_DTX_IDX3 (RT5350_PDMA_OFFSET + 0x3C)
3729 +#define RT5350_RX_BASE_PTR0 (RT5350_PDMA_OFFSET + 0x100)
3730 +#define RT5350_RX_MAX_CNT0 (RT5350_PDMA_OFFSET + 0x104)
3731 +#define RT5350_RX_CALC_IDX0 (RT5350_PDMA_OFFSET + 0x108)
3732 +#define RT5350_RX_DRX_IDX0 (RT5350_PDMA_OFFSET + 0x10C)
3733 +#define RT5350_RX_BASE_PTR1 (RT5350_PDMA_OFFSET + 0x110)
3734 +#define RT5350_RX_MAX_CNT1 (RT5350_PDMA_OFFSET + 0x114)
3735 +#define RT5350_RX_CALC_IDX1 (RT5350_PDMA_OFFSET + 0x118)
3736 +#define RT5350_RX_DRX_IDX1 (RT5350_PDMA_OFFSET + 0x11C)
3737 +#define RT5350_PDMA_GLO_CFG (RT5350_PDMA_OFFSET + 0x204)
3738 +#define RT5350_PDMA_RST_CFG (RT5350_PDMA_OFFSET + 0x208)
3739 +#define RT5350_DLY_INT_CFG (RT5350_PDMA_OFFSET + 0x20c)
3740 +#define RT5350_FE_INT_STATUS (RT5350_PDMA_OFFSET + 0x220)
3741 +#define RT5350_FE_INT_ENABLE (RT5350_PDMA_OFFSET + 0x228)
3742 +#define RT5350_PDMA_SCH_CFG (RT5350_PDMA_OFFSET + 0x280)
3743 +
3744 +#define FE_PDMA_GLO_CFG (FE_PDMA_OFFSET + 0x00)
3745 +#define FE_PDMA_RST_CFG (FE_PDMA_OFFSET + 0x04)
3746 +#define FE_PDMA_SCH_CFG (FE_PDMA_OFFSET + 0x08)
3747 +#define FE_DLY_INT_CFG (FE_PDMA_OFFSET + 0x0C)
3748 +#define FE_TX_BASE_PTR0 (FE_PDMA_OFFSET + 0x10)
3749 +#define FE_TX_MAX_CNT0 (FE_PDMA_OFFSET + 0x14)
3750 +#define FE_TX_CTX_IDX0 (FE_PDMA_OFFSET + 0x18)
3751 +#define FE_TX_DTX_IDX0 (FE_PDMA_OFFSET + 0x1C)
3752 +#define FE_TX_BASE_PTR1 (FE_PDMA_OFFSET + 0x20)
3753 +#define FE_TX_MAX_CNT1 (FE_PDMA_OFFSET + 0x24)
3754 +#define FE_TX_CTX_IDX1 (FE_PDMA_OFFSET + 0x28)
3755 +#define FE_TX_DTX_IDX1 (FE_PDMA_OFFSET + 0x2C)
3756 +#define FE_RX_BASE_PTR0 (FE_PDMA_OFFSET + 0x30)
3757 +#define FE_RX_MAX_CNT0 (FE_PDMA_OFFSET + 0x34)
3758 +#define FE_RX_CALC_IDX0 (FE_PDMA_OFFSET + 0x38)
3759 +#define FE_RX_DRX_IDX0 (FE_PDMA_OFFSET + 0x3C)
3760 +#define FE_TX_BASE_PTR2 (FE_PDMA_OFFSET + 0x40)
3761 +#define FE_TX_MAX_CNT2 (FE_PDMA_OFFSET + 0x44)
3762 +#define FE_TX_CTX_IDX2 (FE_PDMA_OFFSET + 0x48)
3763 +#define FE_TX_DTX_IDX2 (FE_PDMA_OFFSET + 0x4C)
3764 +#define FE_TX_BASE_PTR3 (FE_PDMA_OFFSET + 0x50)
3765 +#define FE_TX_MAX_CNT3 (FE_PDMA_OFFSET + 0x54)
3766 +#define FE_TX_CTX_IDX3 (FE_PDMA_OFFSET + 0x58)
3767 +#define FE_TX_DTX_IDX3 (FE_PDMA_OFFSET + 0x5C)
3768 +#define FE_RX_BASE_PTR1 (FE_PDMA_OFFSET + 0x60)
3769 +#define FE_RX_MAX_CNT1 (FE_PDMA_OFFSET + 0x64)
3770 +#define FE_RX_CALC_IDX1 (FE_PDMA_OFFSET + 0x68)
3771 +#define FE_RX_DRX_IDX1 (FE_PDMA_OFFSET + 0x6C)
3772 +
3773 +#define RT5350_SDM_CFG (RT5350_SDM_OFFSET + 0x00) //Switch DMA configuration
3774 +#define RT5350_SDM_RRING (RT5350_SDM_OFFSET + 0x04) //Switch DMA Rx Ring
3775 +#define RT5350_SDM_TRING (RT5350_SDM_OFFSET + 0x08) //Switch DMA Tx Ring
3776 +#define RT5350_SDM_MAC_ADRL (RT5350_SDM_OFFSET + 0x0C) //Switch MAC address LSB
3777 +#define RT5350_SDM_MAC_ADRH (RT5350_SDM_OFFSET + 0x10) //Switch MAC Address MSB
3778 +#define RT5350_SDM_TPCNT (RT5350_SDM_OFFSET + 0x100) //Switch DMA Tx packet count
3779 +#define RT5350_SDM_TBCNT (RT5350_SDM_OFFSET + 0x104) //Switch DMA Tx byte count
3780 +#define RT5350_SDM_RPCNT (RT5350_SDM_OFFSET + 0x108) //Switch DMA rx packet count
3781 +#define RT5350_SDM_RBCNT (RT5350_SDM_OFFSET + 0x10C) //Switch DMA rx byte count
3782 +#define RT5350_SDM_CS_ERR (RT5350_SDM_OFFSET + 0x110) //Switch DMA rx checksum error count
3783 +
3784 +#define RT5350_SDM_ICS_EN BIT(16)
3785 +#define RT5350_SDM_TCS_EN BIT(17)
3786 +#define RT5350_SDM_UCS_EN BIT(18)
3787 +
3788 +
3789 +/* MDIO_CFG register bits */
3790 +#define FE_MDIO_CFG_AUTO_POLL_EN BIT(29)
3791 +#define FE_MDIO_CFG_GP1_BP_EN BIT(16)
3792 +#define FE_MDIO_CFG_GP1_FRC_EN BIT(15)
3793 +#define FE_MDIO_CFG_GP1_SPEED_10 (0 << 13)
3794 +#define FE_MDIO_CFG_GP1_SPEED_100 (1 << 13)
3795 +#define FE_MDIO_CFG_GP1_SPEED_1000 (2 << 13)
3796 +#define FE_MDIO_CFG_GP1_DUPLEX BIT(12)
3797 +#define FE_MDIO_CFG_GP1_FC_TX BIT(11)
3798 +#define FE_MDIO_CFG_GP1_FC_RX BIT(10)
3799 +#define FE_MDIO_CFG_GP1_LNK_DWN BIT(9)
3800 +#define FE_MDIO_CFG_GP1_AN_FAIL BIT(8)
3801 +#define FE_MDIO_CFG_MDC_CLK_DIV_1 (0 << 6)
3802 +#define FE_MDIO_CFG_MDC_CLK_DIV_2 (1 << 6)
3803 +#define FE_MDIO_CFG_MDC_CLK_DIV_4 (2 << 6)
3804 +#define FE_MDIO_CFG_MDC_CLK_DIV_8 (3 << 6)
3805 +#define FE_MDIO_CFG_TURBO_MII_FREQ BIT(5)
3806 +#define FE_MDIO_CFG_TURBO_MII_MODE BIT(4)
3807 +#define FE_MDIO_CFG_RX_CLK_SKEW_0 (0 << 2)
3808 +#define FE_MDIO_CFG_RX_CLK_SKEW_200 (1 << 2)
3809 +#define FE_MDIO_CFG_RX_CLK_SKEW_400 (2 << 2)
3810 +#define FE_MDIO_CFG_RX_CLK_SKEW_INV (3 << 2)
3811 +#define FE_MDIO_CFG_TX_CLK_SKEW_0 0
3812 +#define FE_MDIO_CFG_TX_CLK_SKEW_200 1
3813 +#define FE_MDIO_CFG_TX_CLK_SKEW_400 2
3814 +#define FE_MDIO_CFG_TX_CLK_SKEW_INV 3
3815 +
3816 +/* uni-cast port */
3817 +#define FE_GDM1_ICS_EN BIT(22)
3818 +#define FE_GDM1_TCS_EN BIT(21)
3819 +#define FE_GDM1_UCS_EN BIT(20)
3820 +#define FE_GDM1_JMB_EN BIT(19)
3821 +#define FE_GDM1_STRPCRC BIT(16)
3822 +#define FE_GDM1_UFRC_P_CPU (0 << 12)
3823 +#define FE_GDM1_UFRC_P_GDMA1 (1 << 12)
3824 +#define FE_GDM1_UFRC_P_PPE (6 << 12)
3825 +
3826 +/* checksums */
3827 +#define FE_ICS_GEN_EN BIT(2)
3828 +#define FE_UCS_GEN_EN BIT(1)
3829 +#define FE_TCS_GEN_EN BIT(0)
3830 +
3831 +/* dma ring */
3832 +#define FE_PST_DRX_IDX0 BIT(16)
3833 +#define FE_PST_DTX_IDX3 BIT(3)
3834 +#define FE_PST_DTX_IDX2 BIT(2)
3835 +#define FE_PST_DTX_IDX1 BIT(1)
3836 +#define FE_PST_DTX_IDX0 BIT(0)
3837 +
3838 +#define FE_TX_WB_DDONE BIT(6)
3839 +#define FE_RX_DMA_BUSY BIT(3)
3840 +#define FE_TX_DMA_BUSY BIT(1)
3841 +#define FE_RX_DMA_EN BIT(2)
3842 +#define FE_TX_DMA_EN BIT(0)
3843 +
3844 +#define FE_PDMA_SIZE_4DWORDS (0 << 4)
3845 +#define FE_PDMA_SIZE_8DWORDS (1 << 4)
3846 +#define FE_PDMA_SIZE_16DWORDS (2 << 4)
3847 +
3848 +#define FE_US_CYC_CNT_MASK 0xff
3849 +#define FE_US_CYC_CNT_SHIFT 0x8
3850 +#define FE_US_CYC_CNT_DIVISOR 1000000
3851 +
3852 +#define RX_DMA_PLEN0(_x) (((_x) >> 16) & 0x3fff)
3853 +#define RX_DMA_LSO BIT(30)
3854 +#define RX_DMA_DONE BIT(31)
3855 +#define RX_DMA_L4VALID BIT(30)
3856 +
3857 +struct fe_rx_dma {
3858 + unsigned int rxd1;
3859 + unsigned int rxd2;
3860 + unsigned int rxd3;
3861 + unsigned int rxd4;
3862 +} __packed __aligned(4);
3863 +
3864 +#define TX_DMA_PLEN0_MASK ((0x3fff) << 16)
3865 +#define TX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16)
3866 +#define TX_DMA_LSO BIT(30)
3867 +#define TX_DMA_DONE BIT(31)
3868 +#define TX_DMA_QN(_x) ((_x) << 16)
3869 +#define TX_DMA_PN(_x) ((_x) << 24)
3870 +#define TX_DMA_QN_MASK TX_DMA_QN(0x7)
3871 +#define TX_DMA_PN_MASK TX_DMA_PN(0x7)
3872 +#define TX_DMA_CHKSUM (0x7 << 29)
3873 +
3874 +struct fe_tx_dma {
3875 + unsigned int txd1;
3876 + unsigned int txd2;
3877 + unsigned int txd3;
3878 + unsigned int txd4;
3879 +} __packed __aligned(4);
3880 +
3881 +struct fe_priv;
3882 +
3883 +struct fe_phy {
3884 + struct phy_device *phy[8];
3885 + struct device_node *phy_node[8];
3886 + const __be32 *phy_fixed[8];
3887 + int duplex[8];
3888 + int speed[8];
3889 + int tx_fc[8];
3890 + int rx_fc[8];
3891 + spinlock_t lock;
3892 +
3893 + int (*connect)(struct fe_priv *priv);
3894 + void (*disconnect)(struct fe_priv *priv);
3895 + void (*start)(struct fe_priv *priv);
3896 + void (*stop)(struct fe_priv *priv);
3897 +};
3898 +
3899 +struct fe_soc_data
3900 +{
3901 + unsigned char mac[6];
3902 + const u32 *reg_table;
3903 +
3904 + void (*reset_fe)(void);
3905 + void (*set_mac)(struct fe_priv *priv, unsigned char *mac);
3906 + void (*fwd_config)(struct fe_priv *priv);
3907 + void (*tx_dma)(struct fe_priv *priv, int idx, int len);
3908 + void (*rx_dma)(struct fe_priv *priv, int idx, int len);
3909 + int (*switch_init)(struct fe_priv *priv);
3910 + int (*switch_config)(struct fe_priv *priv);
3911 + void (*port_init)(struct fe_priv *priv, struct device_node *port);
3912 + int (*has_carrier)(struct fe_priv *priv);
3913 + int (*mdio_init)(struct fe_priv *priv);
3914 + void (*mdio_cleanup)(struct fe_priv *priv);
3915 + int (*mdio_write)(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
3916 + int (*mdio_read)(struct mii_bus *bus, int phy_addr, int phy_reg);
3917 + void (*mdio_adjust_link)(struct fe_priv *priv, int port);
3918 +
3919 + void *swpriv;
3920 + u32 pdma_glo_cfg;
3921 + u32 rx_dly_int;
3922 + u32 tx_dly_int;
3923 + u32 checksum_bit;
3924 +
3925 + int min_pkt_len;
3926 +};
3927 +
3928 +struct fe_priv
3929 +{
3930 + spinlock_t page_lock;
3931 +
3932 + struct fe_soc_data *soc;
3933 + struct net_device *netdev;
3934 + struct device *device;
3935 + unsigned long sysclk;
3936 +
3937 + struct fe_rx_dma *rx_dma;
3938 + struct napi_struct rx_napi;
3939 + struct sk_buff *rx_skb[NUM_DMA_DESC];
3940 + dma_addr_t rx_phys;
3941 +
3942 + struct fe_tx_dma *tx_dma;
3943 + struct tasklet_struct tx_tasklet;
3944 + struct sk_buff *tx_skb[NUM_DMA_DESC];
3945 + dma_addr_t tx_phys;
3946 + unsigned int tx_free_idx;
3947 +
3948 + struct fe_phy *phy;
3949 + struct mii_bus *mii_bus;
3950 + int mii_irq[PHY_MAX_ADDR];
3951 +
3952 + int link[8];
3953 +};
3954 +
3955 +extern const struct of_device_id of_fe_match[];
3956 +
3957 +void fe_w32(u32 val, unsigned reg);
3958 +u32 fe_r32(unsigned reg);
3959 +
3960 +#endif /* FE_ETH_H */
3961 Index: linux-3.10.13/drivers/net/ethernet/ralink/soc_mt7620.c
3962 ===================================================================
3963 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
3964 +++ linux-3.10.13/drivers/net/ethernet/ralink/soc_mt7620.c 2013-10-08 17:26:47.076172688 +0200
3965 @@ -0,0 +1,112 @@
3966 +/*
3967 + * This program is free software; you can redistribute it and/or modify
3968 + * it under the terms of the GNU General Public License as published by
3969 + * the Free Software Foundation; version 2 of the License
3970 + *
3971 + * This program is distributed in the hope that it will be useful,
3972 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3973 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3974 + * GNU General Public License for more details.
3975 + *
3976 + * You should have received a copy of the GNU General Public License
3977 + * along with this program; if not, write to the Free Software
3978 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
3979 + *
3980 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
3981 + */
3982 +
3983 +#include <linux/module.h>
3984 +#include <linux/platform_device.h>
3985 +
3986 +#include <asm/mach-ralink/ralink_regs.h>
3987 +
3988 +#include "ralink_soc_eth.h"
3989 +#include "gsw_mt7620a.h"
3990 +
3991 +#define MT7620A_CDMA_CSG_CFG 0x400
3992 +#define MT7620_DMA_VID (MT7620A_CDMA_CSG_CFG | 0x30)
3993 +#define MT7620A_DMA_2B_OFFSET BIT(31)
3994 +#define MT7620A_RESET_FE BIT(21)
3995 +#define MT7620A_RESET_ESW BIT(23)
3996 +#define MT7620_L4_VALID BIT(23)
3997 +
3998 +#define SYSC_REG_RESET_CTRL 0x34
3999 +#define MAX_RX_LENGTH 1536
4000 +
4001 +#define CDMA_ICS_EN BIT(2)
4002 +#define CDMA_UCS_EN BIT(1)
4003 +#define CDMA_TCS_EN BIT(0)
4004 +
4005 +#define GDMA_ICS_EN BIT(22)
4006 +#define GDMA_TCS_EN BIT(21)
4007 +#define GDMA_UCS_EN BIT(20)
4008 +
4009 +static const u32 rt5350_reg_table[FE_REG_COUNT] = {
4010 + [FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
4011 + [FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
4012 + [FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
4013 + [FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
4014 + [FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
4015 + [FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
4016 + [FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
4017 + [FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
4018 + [FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
4019 + [FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
4020 + [FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
4021 + [FE_REG_FE_DMA_VID_BASE] = MT7620_DMA_VID,
4022 +};
4023 +
4024 +static void mt7620_fe_reset(void)
4025 +{
4026 + rt_sysc_w32(MT7620A_RESET_FE | MT7620A_RESET_ESW, SYSC_REG_RESET_CTRL);
4027 + rt_sysc_w32(0, SYSC_REG_RESET_CTRL);
4028 +}
4029 +
4030 +static void mt7620_fwd_config(struct fe_priv *priv)
4031 +{
4032 + fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~7, MT7620A_GDMA1_FWD_CFG);
4033 + fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) | (GDMA_ICS_EN | GDMA_TCS_EN | GDMA_UCS_EN), MT7620A_GDMA1_FWD_CFG);
4034 + fe_w32(fe_r32(MT7620A_CDMA_CSG_CFG) | (CDMA_ICS_EN | CDMA_UCS_EN | CDMA_TCS_EN), MT7620A_CDMA_CSG_CFG);
4035 +}
4036 +
4037 +static void mt7620_tx_dma(struct fe_priv *priv, int idx, int len)
4038 +{
4039 + if (len)
4040 + priv->tx_dma[idx].txd2 = TX_DMA_LSO | TX_DMA_PLEN0(len);
4041 + else
4042 + priv->tx_dma[idx].txd2 = TX_DMA_LSO | TX_DMA_DONE;
4043 +}
4044 +
4045 +static void mt7620_rx_dma(struct fe_priv *priv, int idx, int len)
4046 +{
4047 + priv->rx_dma[idx].rxd2 = RX_DMA_PLEN0(len);
4048 +}
4049 +
4050 +static struct fe_soc_data mt7620_data = {
4051 + .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
4052 + .reset_fe = mt7620_fe_reset,
4053 + .set_mac = mt7620_set_mac,
4054 + .fwd_config = mt7620_fwd_config,
4055 + .tx_dma = mt7620_tx_dma,
4056 + .rx_dma = mt7620_rx_dma,
4057 + .switch_init = mt7620_gsw_probe,
4058 + .switch_config = mt7620_gsw_config,
4059 + .port_init = mt7620_port_init,
4060 + .min_pkt_len = 0,
4061 + .reg_table = rt5350_reg_table,
4062 + .pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS | MT7620A_DMA_2B_OFFSET,
4063 + .rx_dly_int = RT5350_RX_DLY_INT,
4064 + .tx_dly_int = RT5350_TX_DLY_INT,
4065 + .checksum_bit = MT7620_L4_VALID,
4066 + .has_carrier = mt7620a_has_carrier,
4067 + .mdio_read = mt7620_mdio_read,
4068 + .mdio_write = mt7620_mdio_write,
4069 + .mdio_adjust_link = mt7620_mdio_link_adjust,
4070 +};
4071 +
4072 +const struct of_device_id of_fe_match[] = {
4073 + { .compatible = "ralink,mt7620a-eth", .data = &mt7620_data },
4074 + {},
4075 +};
4076 +
4077 +MODULE_DEVICE_TABLE(of, of_fe_match);
4078 Index: linux-3.10.13/drivers/net/ethernet/ralink/soc_rt2880.c
4079 ===================================================================
4080 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
4081 +++ linux-3.10.13/drivers/net/ethernet/ralink/soc_rt2880.c 2013-10-08 17:26:47.076172688 +0200
4082 @@ -0,0 +1,51 @@
4083 +/*
4084 + * This program is free software; you can redistribute it and/or modify
4085 + * it under the terms of the GNU General Public License as published by
4086 + * the Free Software Foundation; version 2 of the License
4087 + *
4088 + * This program is distributed in the hope that it will be useful,
4089 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4090 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4091 + * GNU General Public License for more details.
4092 + *
4093 + * You should have received a copy of the GNU General Public License
4094 + * along with this program; if not, write to the Free Software
4095 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
4096 + *
4097 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
4098 + */
4099 +
4100 +#include <linux/module.h>
4101 +
4102 +#include <asm/mach-ralink/ralink_regs.h>
4103 +
4104 +#include "ralink_soc_eth.h"
4105 +#include "mdio_rt2880.h"
4106 +
4107 +#define SYSC_REG_RESET_CTRL 0x034
4108 +#define RT2880_RESET_FE BIT(18)
4109 +
4110 +void rt2880_fe_reset(void)
4111 +{
4112 + rt_sysc_w32(RT2880_RESET_FE, SYSC_REG_RESET_CTRL);
4113 +}
4114 +
4115 +struct fe_soc_data rt2880_data = {
4116 + .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
4117 + .reset_fe = rt2880_fe_reset,
4118 + .min_pkt_len = 64,
4119 + .pdma_glo_cfg = FE_PDMA_SIZE_4DWORDS,
4120 + .checksum_bit = RX_DMA_L4VALID,
4121 + .rx_dly_int = FE_RX_DLY_INT,
4122 + .tx_dly_int = FE_TX_DLY_INT,
4123 + .mdio_read = rt2880_mdio_read,
4124 + .mdio_write = rt2880_mdio_write,
4125 + .mdio_adjust_link = rt2880_mdio_link_adjust,
4126 +};
4127 +
4128 +const struct of_device_id of_fe_match[] = {
4129 + { .compatible = "ralink,rt2880-eth", .data = &rt2880_data },
4130 + {},
4131 +};
4132 +
4133 +MODULE_DEVICE_TABLE(of, of_fe_match);
4134 Index: linux-3.10.13/drivers/net/ethernet/ralink/soc_rt305x.c
4135 ===================================================================
4136 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
4137 +++ linux-3.10.13/drivers/net/ethernet/ralink/soc_rt305x.c 2013-10-08 17:26:47.076172688 +0200
4138 @@ -0,0 +1,113 @@
4139 +/*
4140 + * This program is free software; you can redistribute it and/or modify
4141 + * it under the terms of the GNU General Public License as published by
4142 + * the Free Software Foundation; version 2 of the License
4143 + *
4144 + * This program is distributed in the hope that it will be useful,
4145 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4146 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4147 + * GNU General Public License for more details.
4148 + *
4149 + * You should have received a copy of the GNU General Public License
4150 + * along with this program; if not, write to the Free Software
4151 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
4152 + *
4153 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
4154 + */
4155 +
4156 +#include <linux/module.h>
4157 +
4158 +#include <asm/mach-ralink/ralink_regs.h>
4159 +
4160 +#include "ralink_soc_eth.h"
4161 +
4162 +#define RT305X_RESET_FE BIT(21)
4163 +#define RT305X_RESET_ESW BIT(23)
4164 +#define SYSC_REG_RESET_CTRL 0x034
4165 +
4166 +static const u32 rt5350_reg_table[FE_REG_COUNT] = {
4167 + [FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
4168 + [FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
4169 + [FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
4170 + [FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
4171 + [FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
4172 + [FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
4173 + [FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
4174 + [FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
4175 + [FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
4176 + [FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
4177 + [FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
4178 + [FE_REG_FE_DMA_VID_BASE] = 0,
4179 +};
4180 +
4181 +static void rt305x_fe_reset(void)
4182 +{
4183 + rt_sysc_w32(RT305X_RESET_FE, SYSC_REG_RESET_CTRL);
4184 + rt_sysc_w32(0, SYSC_REG_RESET_CTRL);
4185 +}
4186 +
4187 +static void rt5350_set_mac(struct fe_priv *priv, unsigned char *mac)
4188 +{
4189 + unsigned long flags;
4190 +
4191 + spin_lock_irqsave(&priv->page_lock, flags);
4192 + fe_w32((mac[0] << 8) | mac[1], RT5350_SDM_MAC_ADRH);
4193 + fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
4194 + RT5350_SDM_MAC_ADRL);
4195 + spin_unlock_irqrestore(&priv->page_lock, flags);
4196 +}
4197 +
4198 +static void rt5350_fwd_config(struct fe_priv *priv)
4199 +{
4200 + unsigned long sysclk = priv->sysclk;
4201 +
4202 + if (sysclk) {
4203 + sysclk /= FE_US_CYC_CNT_DIVISOR;
4204 + sysclk <<= FE_US_CYC_CNT_SHIFT;
4205 +
4206 + fe_w32((fe_r32(FE_FE_GLO_CFG) &
4207 + ~(FE_US_CYC_CNT_MASK << FE_US_CYC_CNT_SHIFT)) | sysclk,
4208 + FE_FE_GLO_CFG);
4209 + }
4210 +
4211 + fe_w32(fe_r32(RT5350_SDM_CFG) & ~0xffff, RT5350_SDM_CFG);
4212 + fe_w32(fe_r32(RT5350_SDM_CFG) | RT5350_SDM_ICS_EN | RT5350_SDM_TCS_EN | RT5350_SDM_UCS_EN,
4213 + RT5350_SDM_CFG);
4214 +}
4215 +
4216 +static void rt5350_fe_reset(void)
4217 +{
4218 + rt_sysc_w32(RT305X_RESET_FE | RT305X_RESET_ESW, SYSC_REG_RESET_CTRL);
4219 + rt_sysc_w32(0, SYSC_REG_RESET_CTRL);
4220 +}
4221 +
4222 +static struct fe_soc_data rt3050_data = {
4223 + .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
4224 + .reset_fe = rt305x_fe_reset,
4225 + .min_pkt_len = 64,
4226 + .pdma_glo_cfg = FE_PDMA_SIZE_4DWORDS,
4227 + .checksum_bit = RX_DMA_L4VALID,
4228 + .rx_dly_int = FE_RX_DLY_INT,
4229 + .tx_dly_int = FE_TX_DLY_INT,
4230 +};
4231 +
4232 +static struct fe_soc_data rt5350_data = {
4233 + .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
4234 + .reg_table = rt5350_reg_table,
4235 + .reset_fe = rt5350_fe_reset,
4236 + .set_mac = rt5350_set_mac,
4237 + .fwd_config = rt5350_fwd_config,
4238 + .min_pkt_len = 64,
4239 + .pdma_glo_cfg = FE_PDMA_SIZE_4DWORDS,
4240 + .checksum_bit = RX_DMA_L4VALID,
4241 + .rx_dly_int = RT5350_RX_DLY_INT,
4242 + .tx_dly_int = RT5350_TX_DLY_INT,
4243 +};
4244 +
4245 +const struct of_device_id of_fe_match[] = {
4246 + { .compatible = "ralink,rt3050-eth", .data = &rt3050_data },
4247 + { .compatible = "ralink,rt5350-eth", .data = &rt5350_data },
4248 + {},
4249 +};
4250 +
4251 +MODULE_DEVICE_TABLE(of, of_fe_match);
4252 Index: linux-3.10.13/drivers/net/ethernet/ralink/soc_rt3883.c
4253 ===================================================================
4254 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
4255 +++ linux-3.10.13/drivers/net/ethernet/ralink/soc_rt3883.c 2013-10-08 17:26:47.076172688 +0200
4256 @@ -0,0 +1,60 @@
4257 +/*
4258 + * This program is free software; you can redistribute it and/or modify
4259 + * it under the terms of the GNU General Public License as published by
4260 + * the Free Software Foundation; version 2 of the License
4261 + *
4262 + * This program is distributed in the hope that it will be useful,
4263 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4264 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4265 + * GNU General Public License for more details.
4266 + *
4267 + * You should have received a copy of the GNU General Public License
4268 + * along with this program; if not, write to the Free Software
4269 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
4270 + *
4271 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
4272 + */
4273 +
4274 +#include <linux/module.h>
4275 +
4276 +#include <asm/mach-ralink/ralink_regs.h>
4277 +
4278 +#include "ralink_soc_eth.h"
4279 +#include "mdio_rt2880.h"
4280 +
4281 +#define RT3883_SYSC_REG_RSTCTRL 0x34
4282 +#define RT3883_RSTCTRL_FE BIT(21)
4283 +
4284 +static void rt3883_fe_reset(void)
4285 +{
4286 + u32 t;
4287 +
4288 + t = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
4289 + t |= RT3883_RSTCTRL_FE;
4290 + rt_sysc_w32(t , RT3883_SYSC_REG_RSTCTRL);
4291 +
4292 + t &= ~RT3883_RSTCTRL_FE;
4293 + rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL);
4294 +}
4295 +
4296 +static struct fe_soc_data rt3883_data = {
4297 + .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
4298 + .reset_fe = rt3883_fe_reset,
4299 + .min_pkt_len = 64,
4300 + .pdma_glo_cfg = FE_PDMA_SIZE_4DWORDS,
4301 + .rx_dly_int = FE_RX_DLY_INT,
4302 + .tx_dly_int = FE_TX_DLY_INT,
4303 + .checksum_bit = RX_DMA_L4VALID,
4304 + .mdio_read = rt2880_mdio_read,
4305 + .mdio_write = rt2880_mdio_write,
4306 + .mdio_adjust_link = rt2880_mdio_link_adjust,
4307 + .port_init = rt2880_port_init,
4308 +};
4309 +
4310 +const struct of_device_id of_fe_match[] = {
4311 + { .compatible = "ralink,rt3883-eth", .data = &rt3883_data },
4312 + {},
4313 +};
4314 +
4315 +MODULE_DEVICE_TABLE(of, of_fe_match);
4316 +
4317 Index: linux-3.10.13/drivers/net/ethernet/ralink/mt7530.c
4318 ===================================================================
4319 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
4320 +++ linux-3.10.13/drivers/net/ethernet/ralink/mt7530.c 2013-10-08 17:29:27.020179572 +0200
4321 @@ -0,0 +1,456 @@
4322 +/*
4323 + * This program is free software; you can redistribute it and/or
4324 + * modify it under the terms of the GNU General Public License
4325 + * as published by the Free Software Foundation; either version 2
4326 + * of the License, or (at your option) any later version.
4327 + *
4328 + * This program is distributed in the hope that it will be useful,
4329 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4330 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4331 + * GNU General Public License for more details.
4332 + *
4333 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
4334 + */
4335 +
4336 +#include <linux/if.h>
4337 +#include <linux/module.h>
4338 +#include <linux/init.h>
4339 +#include <linux/list.h>
4340 +#include <linux/if_ether.h>
4341 +#include <linux/skbuff.h>
4342 +#include <linux/netdevice.h>
4343 +#include <linux/netlink.h>
4344 +#include <linux/bitops.h>
4345 +#include <net/genetlink.h>
4346 +#include <linux/switch.h>
4347 +#include <linux/delay.h>
4348 +#include <linux/phy.h>
4349 +#include <linux/netdevice.h>
4350 +#include <linux/etherdevice.h>
4351 +#include <linux/lockdep.h>
4352 +#include <linux/workqueue.h>
4353 +#include <linux/of_device.h>
4354 +
4355 +#include "mt7530.h"
4356 +
4357 +#define MT7530_CPU_PORT 6
4358 +#define MT7530_NUM_PORTS 7
4359 +#define MT7530_NUM_VLANS 16
4360 +#define MT7530_NUM_VIDS 16
4361 +
4362 +#define REG_ESW_VLAN_VTCR 0x90
4363 +#define REG_ESW_VLAN_VAWD1 0x94
4364 +#define REG_ESW_VLAN_VAWD2 0x98
4365 +
4366 +enum {
4367 + /* Global attributes. */
4368 + MT7530_ATTR_ENABLE_VLAN,
4369 +};
4370 +
4371 +struct mt7530_port {
4372 + u16 pvid;
4373 +};
4374 +
4375 +struct mt7530_vlan {
4376 + u8 ports;
4377 +};
4378 +
4379 +struct mt7530_priv {
4380 + void __iomem *base;
4381 + struct mii_bus *bus;
4382 + struct switch_dev swdev;
4383 +
4384 + bool global_vlan_enable;
4385 + struct mt7530_vlan vlans[MT7530_NUM_VLANS];
4386 + struct mt7530_port ports[MT7530_NUM_PORTS];
4387 +};
4388 +
4389 +struct mt7530_mapping {
4390 + char *name;
4391 + u8 pvids[6];
4392 + u8 vlans[8];
4393 +} mt7530_defaults[] = {
4394 + {
4395 + .name = "llllw",
4396 + .pvids = { 1, 1, 1, 1, 2, 1 },
4397 + .vlans = { 0, 0x4f, 0x50 },
4398 + }, {
4399 + .name = "wllll",
4400 + .pvids = { 2, 1, 1, 1, 1, 1 },
4401 + .vlans = { 0, 0x5e, 0x41 },
4402 + },
4403 +};
4404 +
4405 +struct mt7530_mapping*
4406 +mt7530_find_mapping(struct device_node *np)
4407 +{
4408 + const char *map;
4409 + int i;
4410 +
4411 + if (of_property_read_string(np, "ralink,port-map", &map))
4412 + return NULL;
4413 +
4414 + for (i = 0; i < ARRAY_SIZE(mt7530_defaults); i++)
4415 + if (!strcmp(map, mt7530_defaults[i].name))
4416 + return &mt7530_defaults[i];
4417 +
4418 + return NULL;
4419 +}
4420 +
4421 +static void
4422 +mt7530_apply_mapping(struct mt7530_priv *mt7530, struct mt7530_mapping *map)
4423 +{
4424 + int i = 0;
4425 +
4426 + mt7530->global_vlan_enable = 1;
4427 +
4428 + for (i = 0; i < 6; i++)
4429 + mt7530->ports[i].pvid = map->pvids[i];
4430 + for (i = 0; i < 8; i++)
4431 + mt7530->vlans[i].ports = map->vlans[i];
4432 +}
4433 +
4434 +static int
4435 +mt7530_reset_switch(struct switch_dev *dev)
4436 +{
4437 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
4438 +
4439 + memset(priv->ports, 0, sizeof(priv->ports));
4440 + memset(priv->vlans, 0, sizeof(priv->vlans));
4441 +
4442 + return 0;
4443 +}
4444 +
4445 +static int
4446 +mt7530_get_vlan_enable(struct switch_dev *dev,
4447 + const struct switch_attr *attr,
4448 + struct switch_val *val)
4449 +{
4450 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
4451 +
4452 + val->value.i = priv->global_vlan_enable;
4453 +
4454 + return 0;
4455 +}
4456 +
4457 +static int
4458 +mt7530_set_vlan_enable(struct switch_dev *dev,
4459 + const struct switch_attr *attr,
4460 + struct switch_val *val)
4461 +{
4462 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
4463 +
4464 + priv->global_vlan_enable = val->value.i != 0;
4465 +
4466 + return 0;
4467 +}
4468 +
4469 +static u32
4470 +mt7530_r32(struct mt7530_priv *priv, u32 reg)
4471 +{
4472 + if (priv->bus) {
4473 + u16 high, low;
4474 +
4475 + mdiobus_write(priv->bus, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
4476 + low = mdiobus_read(priv->bus, 0x1f, (reg >> 2) & 0xf);
4477 + high = mdiobus_read(priv->bus, 0x1f, 0x10);
4478 +
4479 + return (high << 16) | (low & 0xffff);
4480 + }
4481 +
4482 + return ioread32(priv->base + reg);
4483 +}
4484 +
4485 +static void
4486 +mt7530_w32(struct mt7530_priv *priv, u32 reg, u32 val)
4487 +{
4488 + if (priv->bus) {
4489 + mdiobus_write(priv->bus, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
4490 + mdiobus_write(priv->bus, 0x1f, (reg >> 2) & 0xf, val & 0xffff);
4491 + mdiobus_write(priv->bus, 0x1f, 0x10, val >> 16);
4492 + return;
4493 + }
4494 +
4495 + iowrite32(val, priv->base + reg);
4496 +}
4497 +
4498 +static void
4499 +mt7530_vtcr(struct mt7530_priv *priv, u32 cmd, u32 val)
4500 +{
4501 + int i;
4502 +
4503 + mt7530_w32(priv, REG_ESW_VLAN_VTCR, BIT(31) | (cmd << 12) | val);
4504 +
4505 + for (i = 0; i < 20; i++) {
4506 + u32 val = mt7530_r32(priv, REG_ESW_VLAN_VTCR);
4507 +
4508 + if ((val & BIT(31)) == 0)
4509 + break;
4510 +
4511 + udelay(1000);
4512 + }
4513 + if (i == 20)
4514 + printk("mt7530: vtcr timeout\n");
4515 +}
4516 +
4517 +static int
4518 +mt7530_get_port_pvid(struct switch_dev *dev, int port, int *val)
4519 +{
4520 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
4521 +
4522 + if (port >= MT7530_NUM_PORTS)
4523 + return -EINVAL;
4524 +
4525 + *val = mt7530_r32(priv, 0x2014 + (0x100 * port));
4526 + *val &= 0xff;
4527 +
4528 + return 0;
4529 +}
4530 +
4531 +static int
4532 +mt7530_set_port_pvid(struct switch_dev *dev, int port, int pvid)
4533 +{
4534 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
4535 +
4536 + if (port >= MT7530_NUM_PORTS)
4537 + return -1;
4538 +
4539 + priv->ports[port].pvid = pvid;
4540 +
4541 + return 0;
4542 +}
4543 +
4544 +static int
4545 +mt7530_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
4546 +{
4547 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
4548 + u32 member;
4549 + int i;
4550 +
4551 + val->len = 0;
4552 +
4553 + if (val->port_vlan < 0 || val->port_vlan >= MT7530_NUM_VIDS)
4554 + return -EINVAL;
4555 +
4556 + mt7530_vtcr(priv, 0, val->port_vlan);
4557 + member = mt7530_r32(priv, REG_ESW_VLAN_VAWD1);
4558 + member >>= 16;
4559 + member &= 0xff;
4560 +
4561 + for (i = 0; i < MT7530_NUM_PORTS; i++) {
4562 + struct switch_port *p;
4563 + if (!(member & BIT(i)))
4564 + continue;
4565 +
4566 + p = &val->value.ports[val->len++];
4567 + p->id = i;
4568 + p->flags = 0;
4569 + }
4570 +
4571 + return 0;
4572 +}
4573 +
4574 +static int
4575 +mt7530_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)
4576 +{
4577 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
4578 + int ports = 0;
4579 + int i;
4580 +
4581 + if (val->port_vlan < 0 || val->port_vlan >= MT7530_NUM_VIDS ||
4582 + val->len > MT7530_NUM_PORTS)
4583 + return -EINVAL;
4584 +
4585 + for (i = 0; i < val->len; i++) {
4586 + struct switch_port *p = &val->value.ports[i];
4587 +
4588 + if (p->id >= MT7530_NUM_PORTS)
4589 + return -EINVAL;
4590 +
4591 + ports |= BIT(p->id);
4592 + }
4593 + priv->vlans[val->port_vlan].ports = ports;
4594 +
4595 + return 0;
4596 +}
4597 +
4598 +static int
4599 +mt7530_apply_config(struct switch_dev *dev)
4600 +{
4601 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
4602 + int i;
4603 +
4604 + if (!priv->global_vlan_enable) {
4605 + mt7530_w32(priv, 0x2004, 0xff000);
4606 + mt7530_w32(priv, 0x2104, 0xff000);
4607 + mt7530_w32(priv, 0x2204, 0xff000);
4608 + mt7530_w32(priv, 0x2304, 0xff000);
4609 + mt7530_w32(priv, 0x2404, 0xff000);
4610 + mt7530_w32(priv, 0x2504, 0xff000);
4611 + mt7530_w32(priv, 0x2604, 0xff000);
4612 + mt7530_w32(priv, 0x2010, 0x810000c);
4613 + mt7530_w32(priv, 0x2110, 0x810000c);
4614 + mt7530_w32(priv, 0x2210, 0x810000c);
4615 + mt7530_w32(priv, 0x2310, 0x810000c);
4616 + mt7530_w32(priv, 0x2410, 0x810000c);
4617 + mt7530_w32(priv, 0x2510, 0x810000c);
4618 + mt7530_w32(priv, 0x2610, 0x810000c);
4619 + return 0;
4620 + }
4621 +
4622 + // LAN/WAN ports as security mode
4623 + mt7530_w32(priv, 0x2004, 0xff0003);
4624 + mt7530_w32(priv, 0x2104, 0xff0003);
4625 + mt7530_w32(priv, 0x2204, 0xff0003);
4626 + mt7530_w32(priv, 0x2304, 0xff0003);
4627 + mt7530_w32(priv, 0x2404, 0xff0003);
4628 + mt7530_w32(priv, 0x2504, 0xff0003);
4629 + // LAN/WAN ports as transparent port
4630 + mt7530_w32(priv, 0x2010, 0x810000c0);
4631 + mt7530_w32(priv, 0x2110, 0x810000c0);
4632 + mt7530_w32(priv, 0x2210, 0x810000c0);
4633 + mt7530_w32(priv, 0x2310, 0x810000c0);
4634 + mt7530_w32(priv, 0x2410, 0x810000c0);
4635 + mt7530_w32(priv, 0x2510, 0x810000c0);
4636 + // set CPU/P7 port as user port
4637 + mt7530_w32(priv, 0x2610, 0x81000000);
4638 + mt7530_w32(priv, 0x2710, 0x81000000);
4639 +
4640 + mt7530_w32(priv, 0x2604, 0x20ff0003);
4641 + mt7530_w32(priv, 0x2704, 0x20ff0003);
4642 + mt7530_w32(priv, 0x2610, 0x81000000);
4643 +
4644 + for (i = 0; i < MT7530_NUM_VLANS; i++) {
4645 + u8 ports = priv->vlans[i].ports;
4646 +
4647 + if (ports)
4648 + mt7530_w32(priv, REG_ESW_VLAN_VAWD1, BIT(30) | (ports << 16) | BIT(0));
4649 + else
4650 + mt7530_w32(priv, REG_ESW_VLAN_VAWD1, 0);
4651 +
4652 + mt7530_vtcr(priv, 1, i);
4653 + }
4654 +
4655 + for (i = 0; i < MT7530_NUM_PORTS; i++)
4656 + mt7530_w32(priv, 0x2014 + (0x100 * i), 0x10000 | priv->ports[i].pvid);
4657 +
4658 + return 0;
4659 +}
4660 +
4661 +static int
4662 +mt7530_get_port_link(struct switch_dev *dev, int port,
4663 + struct switch_port_link *link)
4664 +{
4665 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
4666 + u32 speed, pmsr;
4667 +
4668 + if (port < 0 || port >= MT7530_NUM_PORTS)
4669 + return -EINVAL;
4670 +
4671 + pmsr = mt7530_r32(priv, 0x3008 + (0x100 * port));
4672 +
4673 + link->link = pmsr & 1;
4674 + link->duplex = (pmsr >> 1) & 1;
4675 + speed = (pmsr >> 2) & 3;
4676 +
4677 + switch (speed) {
4678 + case 0:
4679 + link->speed = SWITCH_PORT_SPEED_10;
4680 + break;
4681 + case 1:
4682 + link->speed = SWITCH_PORT_SPEED_100;
4683 + break;
4684 + case 2:
4685 + case 3: /* forced gige speed can be 2 or 3 */
4686 + link->speed = SWITCH_PORT_SPEED_1000;
4687 + break;
4688 + default:
4689 + link->speed = SWITCH_PORT_SPEED_UNKNOWN;
4690 + break;
4691 + }
4692 +
4693 + return 0;
4694 +}
4695 +
4696 +static const struct switch_attr mt7530_global[] = {
4697 + {
4698 + .type = SWITCH_TYPE_INT,
4699 + .name = "enable_vlan",
4700 + .description = "VLAN mode (1:enabled)",
4701 + .max = 1,
4702 + .id = MT7530_ATTR_ENABLE_VLAN,
4703 + .get = mt7530_get_vlan_enable,
4704 + .set = mt7530_set_vlan_enable,
4705 + },
4706 +};
4707 +
4708 +static const struct switch_attr mt7530_port[] = {
4709 +};
4710 +
4711 +static const struct switch_attr mt7530_vlan[] = {
4712 +};
4713 +
4714 +static const struct switch_dev_ops mt7530_ops = {
4715 + .attr_global = {
4716 + .attr = mt7530_global,
4717 + .n_attr = ARRAY_SIZE(mt7530_global),
4718 + },
4719 + .attr_port = {
4720 + .attr = mt7530_port,
4721 + .n_attr = ARRAY_SIZE(mt7530_port),
4722 + },
4723 + .attr_vlan = {
4724 + .attr = mt7530_vlan,
4725 + .n_attr = ARRAY_SIZE(mt7530_vlan),
4726 + },
4727 + .get_vlan_ports = mt7530_get_vlan_ports,
4728 + .set_vlan_ports = mt7530_set_vlan_ports,
4729 + .get_port_pvid = mt7530_get_port_pvid,
4730 + .set_port_pvid = mt7530_set_port_pvid,
4731 + .get_port_link = mt7530_get_port_link,
4732 + .apply_config = mt7530_apply_config,
4733 + .reset_switch = mt7530_reset_switch,
4734 +};
4735 +
4736 +int
4737 +mt7530_probe(struct device *dev, void __iomem *base, struct mii_bus *bus)
4738 +{
4739 + struct switch_dev *swdev;
4740 + struct mt7530_priv *mt7530;
4741 + struct mt7530_mapping *map;
4742 + int ret;
4743 +
4744 + if (bus && bus->phy_map[0x1f]->phy_id != 0x1beef)
4745 + return 0;
4746 +
4747 + mt7530 = devm_kzalloc(dev, sizeof(struct mt7530_priv), GFP_KERNEL);
4748 + if (!mt7530)
4749 + return -ENOMEM;
4750 +
4751 + mt7530->base = base;
4752 + mt7530->bus = bus;
4753 + mt7530->global_vlan_enable = 1;
4754 +
4755 + swdev = &mt7530->swdev;
4756 + swdev->name = "mt7530";
4757 + swdev->alias = "mt7530";
4758 + swdev->cpu_port = MT7530_CPU_PORT;
4759 + swdev->ports = MT7530_NUM_PORTS;
4760 + swdev->vlans = MT7530_NUM_VLANS;
4761 + swdev->ops = &mt7530_ops;
4762 +
4763 + ret = register_switch(swdev, NULL);
4764 + if (ret) {
4765 + dev_err(dev, "failed to register mt7530\n");
4766 + return ret;
4767 + }
4768 +
4769 + dev_info(dev, "loaded mt7530 driver\n");
4770 +
4771 + map = mt7530_find_mapping(dev->of_node);
4772 + if (map)
4773 + mt7530_apply_mapping(mt7530, map);
4774 + mt7530_apply_config(swdev);
4775 +
4776 + return 0;
4777 +}
4778 Index: linux-3.10.13/drivers/net/ethernet/ralink/mt7530.h
4779 ===================================================================
4780 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
4781 +++ linux-3.10.13/drivers/net/ethernet/ralink/mt7530.h 2013-10-08 17:29:59.596180829 +0200
4782 @@ -0,0 +1,20 @@
4783 +/*
4784 + * This program is free software; you can redistribute it and/or
4785 + * modify it under the terms of the GNU General Public License
4786 + * as published by the Free Software Foundation; either version 2
4787 + * of the License, or (at your option) any later version.
4788 + *
4789 + * This program is distributed in the hope that it will be useful,
4790 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4791 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4792 + * GNU General Public License for more details.
4793 + *
4794 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
4795 + */
4796 +
4797 +#ifndef _MT7530_H__
4798 +#define _MT7530_H__
4799 +
4800 +int mt7530_probe(struct device *dev, void __iomem *base, struct mii_bus *bus);
4801 +
4802 +#endif
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