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[openwrt/openwrt.git] / target / linux / ramips / patches-3.10 / 0122-pinmux.patch
1 From d59fe652e3674e98caa688b4ddc9308007267adc Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Mon, 19 Aug 2013 13:49:52 +0200
4 Subject: [PATCH] pinctrl: ralink; add pinctrl driver
5
6 Signed-off-by: John Crispin <blogic@openwrt.org>
7 ---
8 arch/mips/Kconfig | 2 +
9 arch/mips/ralink/common.h | 21 +--
10 arch/mips/ralink/dts/mt7620a.dtsi | 7 +
11 drivers/pinctrl/Kconfig | 5 +
12 drivers/pinctrl/Makefile | 1 +
13 drivers/pinctrl/pinctrl-rt2880.c | 368 +++++++++++++++++++++++++++++++++++++
14 6 files changed, 385 insertions(+), 19 deletions(-)
15 create mode 100644 drivers/pinctrl/pinctrl-rt2880.c
16
17 --- a/arch/mips/Kconfig
18 +++ b/arch/mips/Kconfig
19 @@ -446,6 +446,8 @@ config RALINK
20 select HAVE_MACH_CLKDEV
21 select CLKDEV_LOOKUP
22 select ARCH_REQUIRE_GPIOLIB
23 + select PINCTRL
24 + select PINCTRL_RT2880
25
26 config SGI_IP22
27 bool "SGI IP22 (Indy/Indigo2)"
28 --- a/drivers/pinctrl/Kconfig
29 +++ b/drivers/pinctrl/Kconfig
30 @@ -114,6 +114,11 @@ config PINCTRL_LANTIQ
31 select PINMUX
32 select PINCONF
33
34 +config PINCTRL_RT2880
35 + bool
36 + depends on RALINK
37 + select PINMUX
38 +
39 config PINCTRL_FALCON
40 bool
41 depends on SOC_FALCON
42 --- a/drivers/pinctrl/Makefile
43 +++ b/drivers/pinctrl/Makefile
44 @@ -45,6 +45,7 @@ obj-$(CONFIG_PINCTRL_EXYNOS5440) += pinc
45 obj-$(CONFIG_PINCTRL_S3C64XX) += pinctrl-s3c64xx.o
46 obj-$(CONFIG_PINCTRL_XWAY) += pinctrl-xway.o
47 obj-$(CONFIG_PINCTRL_LANTIQ) += pinctrl-lantiq.o
48 +obj-$(CONFIG_PINCTRL_RT2880) += pinctrl-rt2880.o
49
50 obj-$(CONFIG_PLAT_ORION) += mvebu/
51 obj-$(CONFIG_ARCH_SHMOBILE) += sh-pfc/
52 --- /dev/null
53 +++ b/drivers/pinctrl/pinctrl-rt2880.c
54 @@ -0,0 +1,456 @@
55 +/*
56 + * linux/drivers/pinctrl/pinctrl-rt2880.c
57 + *
58 + * This program is free software; you can redistribute it and/or modify
59 + * it under the terms of the GNU General Public License version 2 as
60 + * publishhed by the Free Software Foundation.
61 + *
62 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
63 + */
64 +
65 +#include <linux/module.h>
66 +#include <linux/device.h>
67 +#include <linux/io.h>
68 +#include <linux/platform_device.h>
69 +#include <linux/slab.h>
70 +#include <linux/of.h>
71 +#include <linux/pinctrl/pinctrl.h>
72 +#include <linux/pinctrl/pinconf.h>
73 +#include <linux/pinctrl/pinmux.h>
74 +#include <linux/pinctrl/consumer.h>
75 +#include <linux/pinctrl/machine.h>
76 +
77 +#include <asm/mach-ralink/ralink_regs.h>
78 +#include <asm/mach-ralink/pinmux.h>
79 +#include <asm/mach-ralink/mt7620.h>
80 +
81 +#include "core.h"
82 +
83 +#define SYSC_REG_GPIO_MODE 0x60
84 +
85 +struct rt2880_priv {
86 + struct device *dev;
87 +
88 + struct pinctrl_pin_desc *pads;
89 + struct pinctrl_desc *desc;
90 +
91 + struct rt2880_pmx_func **func;
92 + int func_count;
93 +
94 + struct rt2880_pmx_group *groups;
95 + const char **group_names;
96 + int group_count;
97 +
98 + uint8_t *gpio;
99 + int max_pins;
100 +};
101 +
102 +struct rt2880_pmx_group *rt2880_pinmux_data = NULL;
103 +
104 +static int rt2880_get_group_count(struct pinctrl_dev *pctrldev)
105 +{
106 + struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
107 +
108 + return p->group_count;
109 +}
110 +
111 +static const char *rt2880_get_group_name(struct pinctrl_dev *pctrldev,
112 + unsigned group)
113 +{
114 + struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
115 +
116 + if (group >= p->group_count)
117 + return NULL;
118 +
119 + return p->group_names[group];
120 +}
121 +
122 +static int rt2880_get_group_pins(struct pinctrl_dev *pctrldev,
123 + unsigned group,
124 + const unsigned **pins,
125 + unsigned *num_pins)
126 +{
127 + struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
128 +
129 + if (group >= p->group_count)
130 + return -EINVAL;
131 +
132 + *pins = p->groups[group].func[0].pins;
133 + *num_pins = p->groups[group].func[0].pin_count;
134 +
135 + return 0;
136 +}
137 +
138 +static void rt2880_pinctrl_dt_free_map(struct pinctrl_dev *pctrldev,
139 + struct pinctrl_map *map, unsigned num_maps)
140 +{
141 + int i;
142 +
143 + for (i = 0; i < num_maps; i++)
144 + if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN ||
145 + map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
146 + kfree(map[i].data.configs.configs);
147 + kfree(map);
148 +}
149 +
150 +static void rt2880_pinctrl_pin_dbg_show(struct pinctrl_dev *pctrldev,
151 + struct seq_file *s,
152 + unsigned offset)
153 +{
154 + seq_printf(s, "ralink pio");
155 +}
156 +
157 +static void rt2880_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctrldev,
158 + struct device_node *np,
159 + struct pinctrl_map **map)
160 +{
161 + const char *function;
162 + int func = of_property_read_string(np, "ralink,function", &function);
163 + int grps = of_property_count_strings(np, "ralink,group");
164 + int i;
165 +
166 + if (func || !grps)
167 + return;
168 +
169 + for (i = 0; i < grps; i++) {
170 + const char *group;
171 +
172 + of_property_read_string_index(np, "ralink,group", i, &group);
173 +
174 + (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
175 + (*map)->name = function;
176 + (*map)->data.mux.group = group;
177 + (*map)->data.mux.function = function;
178 + (*map)++;
179 + }
180 +}
181 +
182 +static int rt2880_pinctrl_dt_node_to_map(struct pinctrl_dev *pctrldev,
183 + struct device_node *np_config,
184 + struct pinctrl_map **map,
185 + unsigned *num_maps)
186 +{
187 + int max_maps = 0;
188 + struct pinctrl_map *tmp;
189 + struct device_node *np;
190 +
191 + for_each_child_of_node(np_config, np) {
192 + int ret = of_property_count_strings(np, "ralink,group");
193 +
194 + if (ret >= 0)
195 + max_maps += ret;
196 + }
197 +
198 + if (!max_maps)
199 + return max_maps;
200 +
201 + *map = kzalloc(max_maps * sizeof(struct pinctrl_map), GFP_KERNEL);
202 + if (!*map)
203 + return -ENOMEM;
204 +
205 + tmp = *map;
206 +
207 + for_each_child_of_node(np_config, np)
208 + rt2880_pinctrl_dt_subnode_to_map(pctrldev, np, &tmp);
209 + *num_maps = max_maps;
210 +
211 + return 0;
212 +}
213 +
214 +static const struct pinctrl_ops rt2880_pctrl_ops = {
215 + .get_groups_count = rt2880_get_group_count,
216 + .get_group_name = rt2880_get_group_name,
217 + .get_group_pins = rt2880_get_group_pins,
218 + .pin_dbg_show = rt2880_pinctrl_pin_dbg_show,
219 + .dt_node_to_map = rt2880_pinctrl_dt_node_to_map,
220 + .dt_free_map = rt2880_pinctrl_dt_free_map,
221 +};
222 +
223 +static int rt2880_pmx_func_count(struct pinctrl_dev *pctrldev)
224 +{
225 + struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
226 +
227 + return p->func_count;
228 +}
229 +
230 +static const char *rt2880_pmx_func_name(struct pinctrl_dev *pctrldev,
231 + unsigned func)
232 +{
233 + struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
234 +
235 + return p->func[func]->name;
236 +}
237 +
238 +static int rt2880_pmx_group_get_groups(struct pinctrl_dev *pctrldev,
239 + unsigned func,
240 + const char * const **groups,
241 + unsigned * const num_groups)
242 +{
243 + struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
244 +
245 + if (p->func[func]->group_count == 1)
246 + *groups = &p->group_names[p->func[func]->groups[0]];
247 + else
248 + *groups = p->group_names;
249 +
250 + *num_groups = p->func[func]->group_count;
251 +
252 + return 0;
253 +}
254 +
255 +static int rt2880_pmx_group_enable(struct pinctrl_dev *pctrldev,
256 + unsigned func,
257 + unsigned group)
258 +{
259 + struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
260 + u32 mode = 0;
261 +
262 + /* dont allow double use */
263 + if (p->groups[group].enabled) {
264 + dev_err(p->dev, "%s is already enabled\n", p->groups[group].name);
265 + return -EBUSY;
266 + }
267 +
268 + p->groups[group].enabled = 1;
269 + p->func[func]->enabled = 1;
270 +
271 + mode = rt_sysc_r32(SYSC_REG_GPIO_MODE);
272 + mode &= ~(p->groups[group].mask << p->groups[group].shift);
273 +
274 + /* function 0 is gpio and needs special handling */
275 + if (func == 0) {
276 + int i;
277 +
278 + mode |= p->groups[group].mask << p->groups[group].shift;
279 + /* mark the pins as gpio */
280 + for (i = 0; i < p->groups[group].func[0].pin_count; i++)
281 + p->gpio[p->groups[group].func[0].pins[i]] = 1;
282 + } else {
283 + mode |= p->func[func]->value << p->groups[group].shift;
284 + }
285 + rt_sysc_w32(mode, SYSC_REG_GPIO_MODE);
286 +
287 + return 0;
288 +}
289 +
290 +static int rt2880_pmx_group_gpio_request_enable(struct pinctrl_dev *pctrldev,
291 + struct pinctrl_gpio_range *range,
292 + unsigned pin)
293 +{
294 + struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
295 +
296 + if (!p->gpio[pin]) {
297 + dev_err(p->dev, "pin %d is not set to gpio mux\n", pin);
298 + return -EINVAL;
299 + }
300 +
301 + return 0;
302 +}
303 +
304 +static const struct pinmux_ops rt2880_pmx_group_ops = {
305 + .get_functions_count = rt2880_pmx_func_count,
306 + .get_function_name = rt2880_pmx_func_name,
307 + .get_function_groups = rt2880_pmx_group_get_groups,
308 + .enable = rt2880_pmx_group_enable,
309 + .gpio_request_enable = rt2880_pmx_group_gpio_request_enable,
310 +};
311 +
312 +static struct pinctrl_desc rt2880_pctrl_desc = {
313 + .owner = THIS_MODULE,
314 + .name = "rt2880-pinmux",
315 + .pctlops = &rt2880_pctrl_ops,
316 + .pmxops = &rt2880_pmx_group_ops,
317 +};
318 +
319 +static struct rt2880_pmx_func gpio_func = {
320 + .name = "gpio",
321 +};
322 +
323 +static int rt2880_pinmux_index(struct rt2880_priv *p)
324 +{
325 + struct rt2880_pmx_func **f;
326 + struct rt2880_pmx_group *mux = p->groups;
327 + int i, j, c = 0;
328 +
329 + /* count the mux functions */
330 + while (mux->name) {
331 + p->group_count++;
332 + mux++;
333 + }
334 +
335 + /* allocate the group names array needed by the gpio function */
336 + p->group_names = devm_kzalloc(p->dev, sizeof(char *) * p->group_count, GFP_KERNEL);
337 + if (!p->group_names)
338 + return -1;
339 +
340 + for (i = 0; i < p->group_count; i++) {
341 + p->group_names[i] = p->groups[i].name;
342 + p->func_count += p->groups[i].func_count;
343 + }
344 +
345 + /* we have a dummy function[0] for gpio */
346 + p->func_count++;
347 +
348 + /* allocate our function and group mapping index buffers */
349 + f = p->func = devm_kzalloc(p->dev, sizeof(struct rt2880_pmx_func) * p->func_count, GFP_KERNEL);
350 + gpio_func.groups = devm_kzalloc(p->dev, sizeof(int) * p->group_count, GFP_KERNEL);
351 + if (!f || !gpio_func.groups)
352 + return -1;
353 +
354 + /* add a backpointer to the function so it knows its group */
355 + gpio_func.group_count = p->group_count;
356 + for (i = 0; i < gpio_func.group_count; i++)
357 + gpio_func.groups[i] = i;
358 +
359 + f[c] = &gpio_func;
360 + c++;
361 +
362 + /* add remaining functions */
363 + for (i = 0; i < p->group_count; i++) {
364 + for (j = 0; j < p->groups[i].func_count; j++) {
365 + int k;
366 +
367 + f[c] = &p->groups[i].func[j];
368 + f[c]->groups = devm_kzalloc(p->dev, sizeof(int), GFP_KERNEL);
369 + f[c]->groups[0] = i;
370 + f[c]->group_count = 1;
371 + c++;
372 + }
373 + }
374 + return 0;
375 +}
376 +
377 +static int rt2880_pinmux_pins(struct rt2880_priv *p)
378 +{
379 + int i, j;
380 +
381 + /* loop over the functions and initialize the pins array. also work out the highest pin used */
382 + for (i = 0; i < p->func_count; i++) {
383 + int pin;
384 +
385 + if (!p->func[i]->pin_count)
386 + continue;
387 +
388 + p->func[i]->pins = devm_kzalloc(p->dev, sizeof(int) * p->func[i]->pin_count, GFP_KERNEL);
389 + for (j = 0; j < p->func[i]->pin_count; j++)
390 + p->func[i]->pins[j] = p->func[i]->pin_first + j;
391 +
392 + pin = p->func[i]->pin_first + p->func[i]->pin_count;
393 + if (pin > p->max_pins)
394 + p->max_pins = pin;
395 + }
396 +
397 + /* the buffer that tells us which pins are gpio */
398 + p->gpio = devm_kzalloc(p->dev,sizeof(uint8_t) * p->max_pins,
399 + GFP_KERNEL);
400 + /* the pads needed to tell pinctrl about our pins */
401 + p->pads = devm_kzalloc(p->dev,
402 + sizeof(struct pinctrl_pin_desc) * p->max_pins,
403 + GFP_KERNEL);
404 + if (!p->pads || !p->gpio ) {
405 + dev_err(p->dev, "Failed to allocate gpio data\n");
406 + return -ENOMEM;
407 + }
408 +
409 + /* pin 0 is always a gpio */
410 + p->gpio[0] = 1;
411 +
412 + /* set the pads */
413 + for (i = 0; i < p->max_pins; i++) {
414 + /* strlen("ioXY") + 1 = 5 */
415 + char *name = devm_kzalloc(p->dev, 5, GFP_KERNEL);
416 +
417 + if (!name) {
418 + dev_err(p->dev, "Failed to allocate pad name\n");
419 + return -ENOMEM;
420 + }
421 + snprintf(name, 5, "io%d", i);
422 + p->pads[i].number = i;
423 + p->pads[i].name = name;
424 + }
425 + p->desc->pins = p->pads;
426 + p->desc->npins = p->max_pins;
427 +
428 + return 0;
429 +}
430 +
431 +static int rt2880_pinmux_probe(struct platform_device *pdev)
432 +{
433 + struct rt2880_priv *p;
434 + struct pinctrl_dev *dev;
435 + struct device_node *np;
436 +
437 + if (!rt2880_pinmux_data)
438 + return -ENOSYS;
439 +
440 + /* setup the private data */
441 + p = devm_kzalloc(&pdev->dev, sizeof(struct rt2880_priv), GFP_KERNEL);
442 + if (!p)
443 + return -ENOMEM;
444 +
445 + p->dev = &pdev->dev;
446 + p->desc = &rt2880_pctrl_desc;
447 + p->groups = rt2880_pinmux_data;
448 + platform_set_drvdata(pdev, p);
449 +
450 + /* init the device */
451 + if (rt2880_pinmux_index(p)) {
452 + dev_err(&pdev->dev, "failed to load index\n");
453 + return -EINVAL;
454 + }
455 + if (rt2880_pinmux_pins(p)) {
456 + dev_err(&pdev->dev, "failed to load pins\n");
457 + return -EINVAL;
458 + }
459 + dev = pinctrl_register(p->desc, &pdev->dev, p);
460 + if (IS_ERR(dev))
461 + return PTR_ERR(dev);
462 +
463 + /* finalize by adding gpio ranges for enables gpio controllers */
464 + for_each_compatible_node(np, NULL, "ralink,rt2880-gpio") {
465 + const __be32 *ngpio, *gpiobase;
466 + struct pinctrl_gpio_range *range;
467 + char *name;
468 +
469 + if (!of_device_is_available(np))
470 + continue;
471 +
472 + ngpio = of_get_property(np, "ralink,num-gpios", NULL);
473 + gpiobase = of_get_property(np, "ralink,gpio-base", NULL);
474 + if (!ngpio || !gpiobase) {
475 + dev_err(&pdev->dev, "failed to load chip info\n");
476 + return -EINVAL;
477 + }
478 +
479 + range = devm_kzalloc(p->dev, sizeof(struct pinctrl_gpio_range) + 4, GFP_KERNEL);
480 + range->name = name = (char *) &range[1];
481 + sprintf(name, "pio");
482 + range->npins = __be32_to_cpu(*ngpio);
483 + range->base = __be32_to_cpu(*gpiobase);
484 + pinctrl_add_gpio_range(dev, range);
485 + }
486 +
487 + return 0;
488 +}
489 +
490 +static const struct of_device_id rt2880_pinmux_match[] = {
491 + { .compatible = "ralink,rt2880-pinmux" },
492 + {},
493 +};
494 +MODULE_DEVICE_TABLE(of, rt2880_pinmux_match);
495 +
496 +static struct platform_driver rt2880_pinmux_driver = {
497 + .probe = rt2880_pinmux_probe,
498 + .driver = {
499 + .name = "rt2880-pinmux",
500 + .owner = THIS_MODULE,
501 + .of_match_table = rt2880_pinmux_match,
502 + },
503 +};
504 +
505 +int __init rt2880_pinmux_init(void)
506 +{
507 + return platform_driver_register(&rt2880_pinmux_driver);
508 +}
509 +
510 +core_initcall_sync(rt2880_pinmux_init);
511 --- /dev/null
512 +++ b/arch/mips/include/asm/mach-ralink/pinmux.h
513 @@ -0,0 +1,47 @@
514 +/*
515 + * This program is free software; you can redistribute it and/or modify
516 + * it under the terms of the GNU General Public License version 2 as
517 + * publishhed by the Free Software Foundation.
518 + *
519 + * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
520 + */
521 +
522 +#ifndef _RT288X_PINMUX_H__
523 +#define _RT288X_PINMUX_H__
524 +
525 +#define FUNC(name, value, pin_first, pin_count) { name, value, pin_first, pin_count }
526 +#define GRP(_name, _func, _mask, _shift) \
527 + { .name = _name, .mask = _mask, .shift = _shift, \
528 + .func = _func, \
529 + .func_count = ARRAY_SIZE(_func) }
530 +
531 +struct rt2880_pmx_group;
532 +
533 +struct rt2880_pmx_func {
534 + const char *name;
535 + const char value;
536 +
537 + int pin_first;
538 + int pin_count;
539 + int *pins;
540 +
541 + int *groups;
542 + int group_count;
543 +
544 + int enabled;
545 +};
546 +
547 +struct rt2880_pmx_group {
548 + const char *name;
549 + int enabled;
550 +
551 + const u32 shift;
552 + const char mask;
553 +
554 + struct rt2880_pmx_func *func;
555 + int func_count;
556 +};
557 +
558 +extern struct rt2880_pmx_group *rt2880_pinmux_data;
559 +
560 +#endif
561 --- a/arch/mips/ralink/mt7620.c
562 +++ b/arch/mips/ralink/mt7620.c
563 @@ -17,6 +17,7 @@
564 #include <asm/mipsregs.h>
565 #include <asm/mach-ralink/ralink_regs.h>
566 #include <asm/mach-ralink/mt7620.h>
567 +#include <asm/mach-ralink/pinmux.h>
568
569 #include "common.h"
570
571 @@ -48,118 +49,40 @@ static int dram_type;
572 /* the pll dividers */
573 static u32 mt7620_clk_divider[] = { 2, 3, 4, 8 };
574
575 -static struct ralink_pinmux_grp mode_mux[] = {
576 - {
577 - .name = "i2c",
578 - .mask = MT7620_GPIO_MODE_I2C,
579 - .gpio_first = 1,
580 - .gpio_last = 2,
581 - }, {
582 - .name = "spi",
583 - .mask = MT7620_GPIO_MODE_SPI,
584 - .gpio_first = 3,
585 - .gpio_last = 6,
586 - }, {
587 - .name = "uartlite",
588 - .mask = MT7620_GPIO_MODE_UART1,
589 - .gpio_first = 15,
590 - .gpio_last = 16,
591 - }, {
592 - .name = "wdt",
593 - .mask = MT7620_GPIO_MODE_WDT,
594 - .gpio_first = 17,
595 - .gpio_last = 17,
596 - }, {
597 - .name = "mdio",
598 - .mask = MT7620_GPIO_MODE_MDIO,
599 - .gpio_first = 22,
600 - .gpio_last = 23,
601 - }, {
602 - .name = "rgmii1",
603 - .mask = MT7620_GPIO_MODE_RGMII1,
604 - .gpio_first = 24,
605 - .gpio_last = 35,
606 - }, {
607 - .name = "spi refclk",
608 - .mask = MT7620_GPIO_MODE_SPI_REF_CLK,
609 - .gpio_first = 37,
610 - .gpio_last = 39,
611 - }, {
612 - .name = "jtag",
613 - .mask = MT7620_GPIO_MODE_JTAG,
614 - .gpio_first = 40,
615 - .gpio_last = 44,
616 - }, {
617 - /* shared lines with jtag */
618 - .name = "ephy",
619 - .mask = MT7620_GPIO_MODE_EPHY,
620 - .gpio_first = 40,
621 - .gpio_last = 44,
622 - }, {
623 - .name = "nand",
624 - .mask = MT7620_GPIO_MODE_JTAG,
625 - .gpio_first = 45,
626 - .gpio_last = 59,
627 - }, {
628 - .name = "rgmii2",
629 - .mask = MT7620_GPIO_MODE_RGMII2,
630 - .gpio_first = 60,
631 - .gpio_last = 71,
632 - }, {
633 - .name = "wled",
634 - .mask = MT7620_GPIO_MODE_WLED,
635 - .gpio_first = 72,
636 - .gpio_last = 72,
637 - }, {0}
638 +static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 1, 1, 2) };
639 +static struct rt2880_pmx_func spi_grp[] = { FUNC("spi", 1, 3, 4) };
640 +static struct rt2880_pmx_func uartf_grp[] = {
641 + FUNC("uartf", MT7620_GPIO_MODE_UARTF, 7, 8),
642 + FUNC("pcm uartf", MT7620_GPIO_MODE_PCM_UARTF, 7, 8),
643 + FUNC("pcm i2s", MT7620_GPIO_MODE_PCM_I2S, 7, 8),
644 + FUNC("i2s uartf", MT7620_GPIO_MODE_I2S_UARTF, 7, 8),
645 + FUNC("pcm gpio", MT7620_GPIO_MODE_PCM_GPIO, 11, 4),
646 + FUNC("gpio uartf", MT7620_GPIO_MODE_GPIO_UARTF, 7, 4),
647 + FUNC("gpio i2s", MT7620_GPIO_MODE_GPIO_I2S, 7, 4),
648 };
649 -
650 -static struct ralink_pinmux_grp uart_mux[] = {
651 - {
652 - .name = "uartf",
653 - .mask = MT7620_GPIO_MODE_UARTF,
654 - .gpio_first = 7,
655 - .gpio_last = 14,
656 - }, {
657 - .name = "pcm uartf",
658 - .mask = MT7620_GPIO_MODE_PCM_UARTF,
659 - .gpio_first = 7,
660 - .gpio_last = 14,
661 - }, {
662 - .name = "pcm i2s",
663 - .mask = MT7620_GPIO_MODE_PCM_I2S,
664 - .gpio_first = 7,
665 - .gpio_last = 14,
666 - }, {
667 - .name = "i2s uartf",
668 - .mask = MT7620_GPIO_MODE_I2S_UARTF,
669 - .gpio_first = 7,
670 - .gpio_last = 14,
671 - }, {
672 - .name = "pcm gpio",
673 - .mask = MT7620_GPIO_MODE_PCM_GPIO,
674 - .gpio_first = 11,
675 - .gpio_last = 14,
676 - }, {
677 - .name = "gpio uartf",
678 - .mask = MT7620_GPIO_MODE_GPIO_UARTF,
679 - .gpio_first = 7,
680 - .gpio_last = 10,
681 - }, {
682 - .name = "gpio i2s",
683 - .mask = MT7620_GPIO_MODE_GPIO_I2S,
684 - .gpio_first = 7,
685 - .gpio_last = 10,
686 - }, {
687 - .name = "gpio",
688 - .mask = MT7620_GPIO_MODE_GPIO,
689 - }, {0}
690 -};
691 -
692 -struct ralink_pinmux rt_gpio_pinmux = {
693 - .mode = mode_mux,
694 - .uart = uart_mux,
695 - .uart_shift = MT7620_GPIO_MODE_UART0_SHIFT,
696 - .uart_mask = MT7620_GPIO_MODE_UART0_MASK,
697 +static struct rt2880_pmx_func uartlite_grp[] = { FUNC("uartlite", 1, 15, 2) };
698 +static struct rt2880_pmx_func wdt_grp[] = { FUNC("wdt", 1, 17, 1) };
699 +static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 1, 22, 2) };
700 +static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 1, 24, 12) };
701 +static struct rt2880_pmx_func refclk_grp[] = { FUNC("spi refclk", 1, 37, 3) };
702 +static struct rt2880_pmx_func ephy_grp[] = { FUNC("ephy", 1, 40, 5) };
703 +static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 1, 60, 12) };
704 +static struct rt2880_pmx_func wled_grp[] = { FUNC("wled", 1, 72, 1) };
705 +
706 +static struct rt2880_pmx_group mt7620a_pinmux_data[] = {
707 + GRP("i2c", i2c_grp, 1, MT7620_GPIO_MODE_I2C),
708 + GRP("spi", spi_grp, 1, MT7620_GPIO_MODE_SPI),
709 + GRP("uartlite", uartlite_grp, 1, MT7620_GPIO_MODE_UART1),
710 + GRP("wdt", wdt_grp, 1, MT7620_GPIO_MODE_WDT),
711 + GRP("mdio", mdio_grp, 1, MT7620_GPIO_MODE_MDIO),
712 + GRP("rgmii1", rgmii1_grp, 1, MT7620_GPIO_MODE_RGMII1),
713 + GRP("spi refclk", refclk_grp, 1, MT7620_GPIO_MODE_SPI_REF_CLK),
714 + GRP("rgmii2", rgmii2_grp, 1, MT7620_GPIO_MODE_RGMII2),
715 + GRP("ephy", ephy_grp, 1, MT7620_GPIO_MODE_EPHY),
716 + GRP("wled", wled_grp, 1, MT7620_GPIO_MODE_WLED),
717 + GRP("uartf", uartf_grp, MT7620_GPIO_MODE_UART0_MASK,
718 + MT7620_GPIO_MODE_UART0_SHIFT),
719 + { 0 }
720 };
721
722 void __init ralink_clk_init(void)
723 @@ -281,4 +204,6 @@ void prom_soc_init(struct ralink_soc_inf
724 (pmu0 & PMU_SW_SET) ? ("sw") : ("hw"));
725 pr_info("Digital PMU set to %s control\n",
726 (pmu1 & DIG_SW_SEL) ? ("sw") : ("hw"));
727 +
728 + rt2880_pinmux_data = mt7620a_pinmux_data;
729 }
730 --- a/arch/mips/ralink/rt305x.c
731 +++ b/arch/mips/ralink/rt305x.c
732 @@ -17,90 +17,71 @@
733 #include <asm/mipsregs.h>
734 #include <asm/mach-ralink/ralink_regs.h>
735 #include <asm/mach-ralink/rt305x.h>
736 +#include <asm/mach-ralink/pinmux.h>
737
738 #include "common.h"
739
740 enum rt305x_soc_type rt305x_soc;
741
742 -static struct ralink_pinmux_grp mode_mux[] = {
743 - {
744 - .name = "i2c",
745 - .mask = RT305X_GPIO_MODE_I2C,
746 - .gpio_first = RT305X_GPIO_I2C_SD,
747 - .gpio_last = RT305X_GPIO_I2C_SCLK,
748 - }, {
749 - .name = "spi",
750 - .mask = RT305X_GPIO_MODE_SPI,
751 - .gpio_first = RT305X_GPIO_SPI_EN,
752 - .gpio_last = RT305X_GPIO_SPI_CLK,
753 - }, {
754 - .name = "uartlite",
755 - .mask = RT305X_GPIO_MODE_UART1,
756 - .gpio_first = RT305X_GPIO_UART1_TXD,
757 - .gpio_last = RT305X_GPIO_UART1_RXD,
758 - }, {
759 - .name = "jtag",
760 - .mask = RT305X_GPIO_MODE_JTAG,
761 - .gpio_first = RT305X_GPIO_JTAG_TDO,
762 - .gpio_last = RT305X_GPIO_JTAG_TDI,
763 - }, {
764 - .name = "mdio",
765 - .mask = RT305X_GPIO_MODE_MDIO,
766 - .gpio_first = RT305X_GPIO_MDIO_MDC,
767 - .gpio_last = RT305X_GPIO_MDIO_MDIO,
768 - }, {
769 - .name = "sdram",
770 - .mask = RT305X_GPIO_MODE_SDRAM,
771 - .gpio_first = RT305X_GPIO_SDRAM_MD16,
772 - .gpio_last = RT305X_GPIO_SDRAM_MD31,
773 - }, {
774 - .name = "rgmii",
775 - .mask = RT305X_GPIO_MODE_RGMII,
776 - .gpio_first = RT305X_GPIO_GE0_TXD0,
777 - .gpio_last = RT305X_GPIO_GE0_RXCLK,
778 - }, {0}
779 +static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) };
780 +static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
781 +static struct rt2880_pmx_func uartf_func[] = {
782 + FUNC("uartf", RT305X_GPIO_MODE_UARTF, 7, 8),
783 + FUNC("pcm uartf", RT305X_GPIO_MODE_PCM_UARTF, 7, 8),
784 + FUNC("pcm i2s", RT305X_GPIO_MODE_PCM_I2S, 7, 8),
785 + FUNC("i2s uartf", RT305X_GPIO_MODE_I2S_UARTF, 7, 8),
786 + FUNC("pcm gpio", RT305X_GPIO_MODE_PCM_GPIO, 11, 4),
787 + FUNC("gpio uartf", RT305X_GPIO_MODE_GPIO_UARTF, 7, 4),
788 + FUNC("gpio i2s", RT305X_GPIO_MODE_GPIO_I2S, 7, 4),
789 +};
790 +static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) };
791 +static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 25) };
792 +static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
793 +static struct rt2880_pmx_func rt5350_led_func[] = { FUNC("led", 0, 22, 5) };
794 +static struct rt2880_pmx_func sdram_func[] = { FUNC("sdram", 0, 24, 16) };
795 +static struct rt2880_pmx_func rt3352_rgmii_func[] = { FUNC("rgmii", 0, 24, 12) };
796 +static struct rt2880_pmx_func rgmii_func[] = { FUNC("rgmii", 0, 40, 12) };
797 +static struct rt2880_pmx_func rt3352_lna_func[] = { FUNC("lna", 0, 36, 2) };
798 +static struct rt2880_pmx_func rt3352_pa_func[] = { FUNC("pa", 0, 38, 2) };
799 +static struct rt2880_pmx_func rt3352_led_func[] = { FUNC("led", 0, 40, 5) };
800 +
801 +static struct rt2880_pmx_group rt3050_pinmux_data[] = {
802 + GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
803 + GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
804 + GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
805 + RT305X_GPIO_MODE_UART0_SHIFT),
806 + GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1),
807 + GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG),
808 + GRP("mdio", mdio_func, 1, RT305X_GPIO_MODE_MDIO),
809 + GRP("rgmii", rgmii_func, 1, RT305X_GPIO_MODE_RGMII),
810 + GRP("sdram", sdram_func, 1, RT305X_GPIO_MODE_SDRAM),
811 + { 0 }
812 +};
813 +
814 +static struct rt2880_pmx_group rt3352_pinmux_data[] = {
815 + GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
816 + GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
817 + GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
818 + RT305X_GPIO_MODE_UART0_SHIFT),
819 + GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1),
820 + GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG),
821 + GRP("mdio", mdio_func, 1, RT305X_GPIO_MODE_MDIO),
822 + GRP("rgmii", rt3352_rgmii_func, 1, RT305X_GPIO_MODE_RGMII),
823 + GRP("lna", rt3352_lna_func, 1, RT3352_GPIO_MODE_LNA),
824 + GRP("pa", rt3352_pa_func, 1, RT3352_GPIO_MODE_PA),
825 + GRP("led", rt3352_led_func, 1, RT5350_GPIO_MODE_PHY_LED),
826 + { 0 }
827 };
828
829 -static struct ralink_pinmux_grp uart_mux[] = {
830 - {
831 - .name = "uartf",
832 - .mask = RT305X_GPIO_MODE_UARTF,
833 - .gpio_first = RT305X_GPIO_7,
834 - .gpio_last = RT305X_GPIO_14,
835 - }, {
836 - .name = "pcm uartf",
837 - .mask = RT305X_GPIO_MODE_PCM_UARTF,
838 - .gpio_first = RT305X_GPIO_7,
839 - .gpio_last = RT305X_GPIO_14,
840 - }, {
841 - .name = "pcm i2s",
842 - .mask = RT305X_GPIO_MODE_PCM_I2S,
843 - .gpio_first = RT305X_GPIO_7,
844 - .gpio_last = RT305X_GPIO_14,
845 - }, {
846 - .name = "i2s uartf",
847 - .mask = RT305X_GPIO_MODE_I2S_UARTF,
848 - .gpio_first = RT305X_GPIO_7,
849 - .gpio_last = RT305X_GPIO_14,
850 - }, {
851 - .name = "pcm gpio",
852 - .mask = RT305X_GPIO_MODE_PCM_GPIO,
853 - .gpio_first = RT305X_GPIO_10,
854 - .gpio_last = RT305X_GPIO_14,
855 - }, {
856 - .name = "gpio uartf",
857 - .mask = RT305X_GPIO_MODE_GPIO_UARTF,
858 - .gpio_first = RT305X_GPIO_7,
859 - .gpio_last = RT305X_GPIO_10,
860 - }, {
861 - .name = "gpio i2s",
862 - .mask = RT305X_GPIO_MODE_GPIO_I2S,
863 - .gpio_first = RT305X_GPIO_7,
864 - .gpio_last = RT305X_GPIO_10,
865 - }, {
866 - .name = "gpio",
867 - .mask = RT305X_GPIO_MODE_GPIO,
868 - }, {0}
869 +static struct rt2880_pmx_group rt5350_pinmux_data[] = {
870 + GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
871 + GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
872 + GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
873 + RT305X_GPIO_MODE_UART0_SHIFT),
874 + GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1),
875 + GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG),
876 + GRP("led", rt5350_led_func, 1, RT5350_GPIO_MODE_PHY_LED),
877 + { 0 }
878 };
879
880 static void rt305x_wdt_reset(void)
881 @@ -114,14 +95,6 @@ static void rt305x_wdt_reset(void)
882 rt_sysc_w32(t, SYSC_REG_SYSTEM_CONFIG);
883 }
884
885 -struct ralink_pinmux rt_gpio_pinmux = {
886 - .mode = mode_mux,
887 - .uart = uart_mux,
888 - .uart_shift = RT305X_GPIO_MODE_UART0_SHIFT,
889 - .uart_mask = RT305X_GPIO_MODE_UART0_MASK,
890 - .wdt_reset = rt305x_wdt_reset,
891 -};
892 -
893 static unsigned long rt5350_get_mem_size(void)
894 {
895 void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE);
896 @@ -291,11 +264,14 @@ void prom_soc_init(struct ralink_soc_inf
897 soc_info->mem_base = RT305X_SDRAM_BASE;
898 if (soc_is_rt5350()) {
899 soc_info->mem_size = rt5350_get_mem_size();
900 + rt2880_pinmux_data = rt5350_pinmux_data;
901 } else if (soc_is_rt305x() || soc_is_rt3350()) {
902 soc_info->mem_size_min = RT305X_MEM_SIZE_MIN;
903 soc_info->mem_size_max = RT305X_MEM_SIZE_MAX;
904 + rt2880_pinmux_data = rt3050_pinmux_data;
905 } else if (soc_is_rt3352()) {
906 soc_info->mem_size_min = RT3352_MEM_SIZE_MIN;
907 soc_info->mem_size_max = RT3352_MEM_SIZE_MAX;
908 + rt2880_pinmux_data = rt3352_pinmux_data;
909 }
910 }
911 --- a/arch/mips/include/asm/mach-ralink/rt305x.h
912 +++ b/arch/mips/include/asm/mach-ralink/rt305x.h
913 @@ -125,24 +125,28 @@ static inline int soc_is_rt5350(void)
914 #define RT305X_GPIO_GE0_TXD0 40
915 #define RT305X_GPIO_GE0_RXCLK 51
916
917 -#define RT305X_GPIO_MODE_I2C BIT(0)
918 -#define RT305X_GPIO_MODE_SPI BIT(1)
919 #define RT305X_GPIO_MODE_UART0_SHIFT 2
920 #define RT305X_GPIO_MODE_UART0_MASK 0x7
921 #define RT305X_GPIO_MODE_UART0(x) ((x) << RT305X_GPIO_MODE_UART0_SHIFT)
922 -#define RT305X_GPIO_MODE_UARTF 0x0
923 -#define RT305X_GPIO_MODE_PCM_UARTF 0x1
924 -#define RT305X_GPIO_MODE_PCM_I2S 0x2
925 -#define RT305X_GPIO_MODE_I2S_UARTF 0x3
926 -#define RT305X_GPIO_MODE_PCM_GPIO 0x4
927 -#define RT305X_GPIO_MODE_GPIO_UARTF 0x5
928 -#define RT305X_GPIO_MODE_GPIO_I2S 0x6
929 -#define RT305X_GPIO_MODE_GPIO 0x7
930 -#define RT305X_GPIO_MODE_UART1 BIT(5)
931 -#define RT305X_GPIO_MODE_JTAG BIT(6)
932 -#define RT305X_GPIO_MODE_MDIO BIT(7)
933 -#define RT305X_GPIO_MODE_SDRAM BIT(8)
934 -#define RT305X_GPIO_MODE_RGMII BIT(9)
935 +#define RT305X_GPIO_MODE_UARTF 0
936 +#define RT305X_GPIO_MODE_PCM_UARTF 1
937 +#define RT305X_GPIO_MODE_PCM_I2S 2
938 +#define RT305X_GPIO_MODE_I2S_UARTF 3
939 +#define RT305X_GPIO_MODE_PCM_GPIO 4
940 +#define RT305X_GPIO_MODE_GPIO_UARTF 5
941 +#define RT305X_GPIO_MODE_GPIO_I2S 6
942 +#define RT305X_GPIO_MODE_GPIO 7
943 +
944 +#define RT305X_GPIO_MODE_I2C 0
945 +#define RT305X_GPIO_MODE_SPI 1
946 +#define RT305X_GPIO_MODE_UART1 5
947 +#define RT305X_GPIO_MODE_JTAG 6
948 +#define RT305X_GPIO_MODE_MDIO 7
949 +#define RT305X_GPIO_MODE_SDRAM 8
950 +#define RT305X_GPIO_MODE_RGMII 9
951 +#define RT5350_GPIO_MODE_PHY_LED 14
952 +#define RT3352_GPIO_MODE_LNA 18
953 +#define RT3352_GPIO_MODE_PA 20
954
955 #define RT3352_SYSC_REG_SYSCFG0 0x010
956 #define RT3352_SYSC_REG_SYSCFG1 0x014
957 --- a/arch/mips/include/asm/mach-ralink/mt7620.h
958 +++ b/arch/mips/include/asm/mach-ralink/mt7620.h
959 @@ -59,7 +59,6 @@
960 #define MT7620_DDR2_SIZE_MIN 32
961 #define MT7620_DDR2_SIZE_MAX 256
962
963 -#define MT7620_GPIO_MODE_I2C BIT(0)
964 #define MT7620_GPIO_MODE_UART0_SHIFT 2
965 #define MT7620_GPIO_MODE_UART0_MASK 0x7
966 #define MT7620_GPIO_MODE_UART0(x) ((x) << MT7620_GPIO_MODE_UART0_SHIFT)
967 @@ -71,15 +70,17 @@
968 #define MT7620_GPIO_MODE_GPIO_UARTF 0x5
969 #define MT7620_GPIO_MODE_GPIO_I2S 0x6
970 #define MT7620_GPIO_MODE_GPIO 0x7
971 -#define MT7620_GPIO_MODE_UART1 BIT(5)
972 -#define MT7620_GPIO_MODE_MDIO BIT(8)
973 -#define MT7620_GPIO_MODE_RGMII1 BIT(9)
974 -#define MT7620_GPIO_MODE_RGMII2 BIT(10)
975 -#define MT7620_GPIO_MODE_SPI BIT(11)
976 -#define MT7620_GPIO_MODE_SPI_REF_CLK BIT(12)
977 -#define MT7620_GPIO_MODE_WLED BIT(13)
978 -#define MT7620_GPIO_MODE_JTAG BIT(15)
979 -#define MT7620_GPIO_MODE_EPHY BIT(15)
980 -#define MT7620_GPIO_MODE_WDT BIT(22)
981 +
982 +#define MT7620_GPIO_MODE_I2C 0
983 +#define MT7620_GPIO_MODE_UART1 5
984 +#define MT7620_GPIO_MODE_MDIO 8
985 +#define MT7620_GPIO_MODE_RGMII1 9
986 +#define MT7620_GPIO_MODE_RGMII2 10
987 +#define MT7620_GPIO_MODE_SPI 11
988 +#define MT7620_GPIO_MODE_SPI_REF_CLK 12
989 +#define MT7620_GPIO_MODE_WLED 13
990 +#define MT7620_GPIO_MODE_JTAG 15
991 +#define MT7620_GPIO_MODE_EPHY 15
992 +#define MT7620_GPIO_MODE_WDT 22
993
994 #endif
995 --- a/arch/mips/include/asm/mach-ralink/rt3883.h
996 +++ b/arch/mips/include/asm/mach-ralink/rt3883.h
997 @@ -112,8 +112,6 @@
998 #define RT3883_CLKCFG1_PCI_CLK_EN BIT(19)
999 #define RT3883_CLKCFG1_UPHY0_CLK_EN BIT(18)
1000
1001 -#define RT3883_GPIO_MODE_I2C BIT(0)
1002 -#define RT3883_GPIO_MODE_SPI BIT(1)
1003 #define RT3883_GPIO_MODE_UART0_SHIFT 2
1004 #define RT3883_GPIO_MODE_UART0_MASK 0x7
1005 #define RT3883_GPIO_MODE_UART0(x) ((x) << RT3883_GPIO_MODE_UART0_SHIFT)
1006 @@ -125,11 +123,15 @@
1007 #define RT3883_GPIO_MODE_GPIO_UARTF 0x5
1008 #define RT3883_GPIO_MODE_GPIO_I2S 0x6
1009 #define RT3883_GPIO_MODE_GPIO 0x7
1010 -#define RT3883_GPIO_MODE_UART1 BIT(5)
1011 -#define RT3883_GPIO_MODE_JTAG BIT(6)
1012 -#define RT3883_GPIO_MODE_MDIO BIT(7)
1013 -#define RT3883_GPIO_MODE_GE1 BIT(9)
1014 -#define RT3883_GPIO_MODE_GE2 BIT(10)
1015 +
1016 +#define RT3883_GPIO_MODE_I2C 0
1017 +#define RT3883_GPIO_MODE_SPI 1
1018 +#define RT3883_GPIO_MODE_UART1 5
1019 +#define RT3883_GPIO_MODE_JTAG 6
1020 +#define RT3883_GPIO_MODE_MDIO 7
1021 +#define RT3883_GPIO_MODE_GE1 9
1022 +#define RT3883_GPIO_MODE_GE2 10
1023 +
1024 #define RT3883_GPIO_MODE_PCI_SHIFT 11
1025 #define RT3883_GPIO_MODE_PCI_MASK 0x7
1026 #define RT3883_GPIO_MODE_PCI (RT3883_GPIO_MODE_PCI_MASK << RT3883_GPIO_MODE_PCI_SHIFT)
1027 --- a/arch/mips/ralink/common.h
1028 +++ b/arch/mips/ralink/common.h
1029 @@ -11,25 +11,6 @@
1030
1031 #define RAMIPS_SYS_TYPE_LEN 32
1032
1033 -struct ralink_pinmux_grp {
1034 - const char *name;
1035 - u32 mask;
1036 - int gpio_first;
1037 - int gpio_last;
1038 -};
1039 -
1040 -struct ralink_pinmux {
1041 - struct ralink_pinmux_grp *mode;
1042 - struct ralink_pinmux_grp *uart;
1043 - int uart_shift;
1044 - u32 uart_mask;
1045 - void (*wdt_reset)(void);
1046 - struct ralink_pinmux_grp *pci;
1047 - int pci_shift;
1048 - u32 pci_mask;
1049 -};
1050 -extern struct ralink_pinmux rt_gpio_pinmux;
1051 -
1052 struct ralink_soc_info {
1053 unsigned char sys_type[RAMIPS_SYS_TYPE_LEN];
1054 unsigned char *compatible;
1055 --- a/arch/mips/ralink/rt3883.c
1056 +++ b/arch/mips/ralink/rt3883.c
1057 @@ -17,132 +17,50 @@
1058 #include <asm/mipsregs.h>
1059 #include <asm/mach-ralink/ralink_regs.h>
1060 #include <asm/mach-ralink/rt3883.h>
1061 +#include <asm/mach-ralink/pinmux.h>
1062
1063 #include "common.h"
1064
1065 -static struct ralink_pinmux_grp mode_mux[] = {
1066 - {
1067 - .name = "i2c",
1068 - .mask = RT3883_GPIO_MODE_I2C,
1069 - .gpio_first = RT3883_GPIO_I2C_SD,
1070 - .gpio_last = RT3883_GPIO_I2C_SCLK,
1071 - }, {
1072 - .name = "spi",
1073 - .mask = RT3883_GPIO_MODE_SPI,
1074 - .gpio_first = RT3883_GPIO_SPI_CS0,
1075 - .gpio_last = RT3883_GPIO_SPI_MISO,
1076 - }, {
1077 - .name = "uartlite",
1078 - .mask = RT3883_GPIO_MODE_UART1,
1079 - .gpio_first = RT3883_GPIO_UART1_TXD,
1080 - .gpio_last = RT3883_GPIO_UART1_RXD,
1081 - }, {
1082 - .name = "jtag",
1083 - .mask = RT3883_GPIO_MODE_JTAG,
1084 - .gpio_first = RT3883_GPIO_JTAG_TDO,
1085 - .gpio_last = RT3883_GPIO_JTAG_TCLK,
1086 - }, {
1087 - .name = "mdio",
1088 - .mask = RT3883_GPIO_MODE_MDIO,
1089 - .gpio_first = RT3883_GPIO_MDIO_MDC,
1090 - .gpio_last = RT3883_GPIO_MDIO_MDIO,
1091 - }, {
1092 - .name = "ge1",
1093 - .mask = RT3883_GPIO_MODE_GE1,
1094 - .gpio_first = RT3883_GPIO_GE1_TXD0,
1095 - .gpio_last = RT3883_GPIO_GE1_RXCLK,
1096 - }, {
1097 - .name = "ge2",
1098 - .mask = RT3883_GPIO_MODE_GE2,
1099 - .gpio_first = RT3883_GPIO_GE2_TXD0,
1100 - .gpio_last = RT3883_GPIO_GE2_RXCLK,
1101 - }, {
1102 - .name = "pci",
1103 - .mask = RT3883_GPIO_MODE_PCI,
1104 - .gpio_first = RT3883_GPIO_PCI_AD0,
1105 - .gpio_last = RT3883_GPIO_PCI_AD31,
1106 - }, {
1107 - .name = "lna a",
1108 - .mask = RT3883_GPIO_MODE_LNA_A,
1109 - .gpio_first = RT3883_GPIO_LNA_PE_A0,
1110 - .gpio_last = RT3883_GPIO_LNA_PE_A2,
1111 - }, {
1112 - .name = "lna g",
1113 - .mask = RT3883_GPIO_MODE_LNA_G,
1114 - .gpio_first = RT3883_GPIO_LNA_PE_G0,
1115 - .gpio_last = RT3883_GPIO_LNA_PE_G2,
1116 - }, {0}
1117 +static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) };
1118 +static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
1119 +static struct rt2880_pmx_func uartf_func[] = {
1120 + FUNC("uartf", RT3883_GPIO_MODE_UARTF, 7, 8),
1121 + FUNC("pcm uartf", RT3883_GPIO_MODE_PCM_UARTF, 7, 8),
1122 + FUNC("pcm i2s", RT3883_GPIO_MODE_PCM_I2S, 7, 8),
1123 + FUNC("i2s uartf", RT3883_GPIO_MODE_I2S_UARTF, 7, 8),
1124 + FUNC("pcm gpio", RT3883_GPIO_MODE_PCM_GPIO, 11, 4),
1125 + FUNC("gpio uartf", RT3883_GPIO_MODE_GPIO_UARTF, 7, 4),
1126 + FUNC("gpio i2s", RT3883_GPIO_MODE_GPIO_I2S, 7, 4),
1127 };
1128 -
1129 -static struct ralink_pinmux_grp uart_mux[] = {
1130 - {
1131 - .name = "uartf",
1132 - .mask = RT3883_GPIO_MODE_UARTF,
1133 - .gpio_first = RT3883_GPIO_7,
1134 - .gpio_last = RT3883_GPIO_14,
1135 - }, {
1136 - .name = "pcm uartf",
1137 - .mask = RT3883_GPIO_MODE_PCM_UARTF,
1138 - .gpio_first = RT3883_GPIO_7,
1139 - .gpio_last = RT3883_GPIO_14,
1140 - }, {
1141 - .name = "pcm i2s",
1142 - .mask = RT3883_GPIO_MODE_PCM_I2S,
1143 - .gpio_first = RT3883_GPIO_7,
1144 - .gpio_last = RT3883_GPIO_14,
1145 - }, {
1146 - .name = "i2s uartf",
1147 - .mask = RT3883_GPIO_MODE_I2S_UARTF,
1148 - .gpio_first = RT3883_GPIO_7,
1149 - .gpio_last = RT3883_GPIO_14,
1150 - }, {
1151 - .name = "pcm gpio",
1152 - .mask = RT3883_GPIO_MODE_PCM_GPIO,
1153 - .gpio_first = RT3883_GPIO_11,
1154 - .gpio_last = RT3883_GPIO_14,
1155 - }, {
1156 - .name = "gpio uartf",
1157 - .mask = RT3883_GPIO_MODE_GPIO_UARTF,
1158 - .gpio_first = RT3883_GPIO_7,
1159 - .gpio_last = RT3883_GPIO_10,
1160 - }, {
1161 - .name = "gpio i2s",
1162 - .mask = RT3883_GPIO_MODE_GPIO_I2S,
1163 - .gpio_first = RT3883_GPIO_7,
1164 - .gpio_last = RT3883_GPIO_10,
1165 - }, {
1166 - .name = "gpio",
1167 - .mask = RT3883_GPIO_MODE_GPIO,
1168 - }, {0}
1169 +static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) };
1170 +static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 25) };
1171 +static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
1172 +static struct rt2880_pmx_func lna_a_func[] = { FUNC("lna a", 0, 32, 3) };
1173 +static struct rt2880_pmx_func lna_g_func[] = { FUNC("lna a", 0, 35, 3) };
1174 +static struct rt2880_pmx_func pci_func[] = {
1175 + FUNC("pci-dev", 0, 40, 32),
1176 + FUNC("pci-host2", 1, 40, 32),
1177 + FUNC("pci-host1", 2, 40, 32),
1178 + FUNC("pci-fnc", 3, 40, 32)
1179 };
1180 +static struct rt2880_pmx_func ge1_func[] = { FUNC("ge1", 0, 72, 12) };
1181 +static struct rt2880_pmx_func ge2_func[] = { FUNC("ge1", 0, 84, 12) };
1182
1183 -static struct ralink_pinmux_grp pci_mux[] = {
1184 - {
1185 - .name = "pci-dev",
1186 - .mask = 0,
1187 - .gpio_first = RT3883_GPIO_PCI_AD0,
1188 - .gpio_last = RT3883_GPIO_PCI_AD31,
1189 - }, {
1190 - .name = "pci-host2",
1191 - .mask = 1,
1192 - .gpio_first = RT3883_GPIO_PCI_AD0,
1193 - .gpio_last = RT3883_GPIO_PCI_AD31,
1194 - }, {
1195 - .name = "pci-host1",
1196 - .mask = 2,
1197 - .gpio_first = RT3883_GPIO_PCI_AD0,
1198 - .gpio_last = RT3883_GPIO_PCI_AD31,
1199 - }, {
1200 - .name = "pci-fnc",
1201 - .mask = 3,
1202 - .gpio_first = RT3883_GPIO_PCI_AD0,
1203 - .gpio_last = RT3883_GPIO_PCI_AD31,
1204 - }, {
1205 - .name = "pci-gpio",
1206 - .mask = 7,
1207 - .gpio_first = RT3883_GPIO_PCI_AD0,
1208 - .gpio_last = RT3883_GPIO_PCI_AD31,
1209 - }, {0}
1210 +static struct rt2880_pmx_group rt3883_pinmux_data[] = {
1211 + GRP("i2c", i2c_func, 1, RT3883_GPIO_MODE_I2C),
1212 + GRP("spi", spi_func, 1, RT3883_GPIO_MODE_SPI),
1213 + GRP("uartf", uartf_func, RT3883_GPIO_MODE_UART0_MASK,
1214 + RT3883_GPIO_MODE_UART0_SHIFT),
1215 + GRP("uartlite", uartlite_func, 1, RT3883_GPIO_MODE_UART1),
1216 + GRP("jtag", jtag_func, 1, RT3883_GPIO_MODE_JTAG),
1217 + GRP("mdio", mdio_func, 1, RT3883_GPIO_MODE_MDIO),
1218 + GRP("lna a", lna_a_func, 1, RT3883_GPIO_MODE_LNA_A),
1219 + GRP("lna g", lna_g_func, 1, RT3883_GPIO_MODE_LNA_G),
1220 + GRP("pci", pci_func, RT3883_GPIO_MODE_PCI_MASK,
1221 + RT3883_GPIO_MODE_PCI_SHIFT),
1222 + GRP("ge1", ge1_func, 1, RT3883_GPIO_MODE_GE1),
1223 + GRP("ge2", ge2_func, 1, RT3883_GPIO_MODE_GE2),
1224 + { 0 }
1225 };
1226
1227 static void rt3883_wdt_reset(void)
1228 @@ -155,17 +73,6 @@ static void rt3883_wdt_reset(void)
1229 rt_sysc_w32(t, RT3883_SYSC_REG_SYSCFG1);
1230 }
1231
1232 -struct ralink_pinmux rt_gpio_pinmux = {
1233 - .mode = mode_mux,
1234 - .uart = uart_mux,
1235 - .uart_shift = RT3883_GPIO_MODE_UART0_SHIFT,
1236 - .uart_mask = RT3883_GPIO_MODE_UART0_MASK,
1237 - .wdt_reset = rt3883_wdt_reset,
1238 - .pci = pci_mux,
1239 - .pci_shift = RT3883_GPIO_MODE_PCI_SHIFT,
1240 - .pci_mask = RT3883_GPIO_MODE_PCI_MASK,
1241 -};
1242 -
1243 void __init ralink_clk_init(void)
1244 {
1245 unsigned long cpu_rate, sys_rate;
1246 @@ -243,4 +150,6 @@ void prom_soc_init(struct ralink_soc_inf
1247 soc_info->mem_base = RT3883_SDRAM_BASE;
1248 soc_info->mem_size_min = RT3883_MEM_SIZE_MIN;
1249 soc_info->mem_size_max = RT3883_MEM_SIZE_MAX;
1250 +
1251 + rt2880_pinmux_data = rt3883_pinmux_data;
1252 }
OpenWrt Source Repository