target/linux/ramips/patches-3.10/0210-MIPS-ralink-add-MT7621-pcie-driver.patch

   1 From 6541090161342ef11cf319a7471aeb6769e20c2c Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Sun, 16 Mar 2014 05:22:39 +0000
   4 Subject: [PATCH 210/215] MIPS: ralink: add MT7621 pcie driver
   5
   6 Signed-off-by: John Crispin <blogic@openwrt.org>
   7 ---
   8  arch/mips/pci/Makefile     |    1 +
   9  arch/mips/pci/pci-mt7621.c |  797 ++++++++++++++++++++++++++++++++++++++++++++
  10  2 files changed, 798 insertions(+)
  11  create mode 100644 arch/mips/pci/pci-mt7621.c
  12
  13 --- a/arch/mips/pci/Makefile
  14 +++ b/arch/mips/pci/Makefile
  15 @@ -42,6 +42,7 @@ obj-$(CONFIG_SNI_RM)          += fixup-sni.o ops
  16  obj-$(CONFIG_LANTIQ)           += fixup-lantiq.o
  17  obj-$(CONFIG_PCI_LANTIQ)       += pci-lantiq.o ops-lantiq.o
  18  obj-$(CONFIG_SOC_MT7620)       += pci-mt7620a.o
  19 +obj-$(CONFIG_SOC_MT7621)       += pci-mt7621.o
  20  obj-$(CONFIG_SOC_RT2880)       += pci-rt2880.o
  21  obj-$(CONFIG_SOC_RT3883)       += pci-rt3883.o
  22  obj-$(CONFIG_TANBAC_TB0219)    += fixup-tb0219.o
  23 --- /dev/null
  24 +++ b/arch/mips/pci/pci-mt7621.c
  25 @@ -0,0 +1,797 @@
  26 +/**************************************************************************
  27 + *
  28 + *  BRIEF MODULE DESCRIPTION
  29 + *     PCI init for Ralink RT2880 solution
  30 + *
  31 + *  Copyright 2007 Ralink Inc. (bruce_chang@ralinktech.com.tw)
  32 + *
  33 + *  This program is free software; you can redistribute  it and/or modify it
  34 + *  under  the terms of  the GNU General  Public License as published by the
  35 + *  Free Software Foundation;  either version 2 of the  License, or (at your
  36 + *  option) any later version.
  37 + *
  38 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  39 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  40 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  41 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  42 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  43 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  44 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  45 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  46 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  47 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  48 + *
  49 + *  You should have received a copy of the  GNU General Public License along
  50 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
  51 + *  675 Mass Ave, Cambridge, MA 02139, USA.
  52 + *
  53 + *
  54 + **************************************************************************
  55 + * May 2007 Bruce Chang
  56 + * Initial Release
  57 + *
  58 + * May 2009 Bruce Chang
  59 + * support RT2880/RT3883 PCIe
  60 + *
  61 + * May 2011 Bruce Chang
  62 + * support RT6855/MT7620 PCIe
  63 + *
  64 + **************************************************************************
  65 + */
  66 +
  67 +#include <linux/types.h>
  68 +#include <linux/pci.h>
  69 +#include <linux/kernel.h>
  70 +#include <linux/slab.h>
  71 +#include <linux/version.h>
  72 +#include <asm/pci.h>
  73 +#include <asm/io.h>
  74 +//#include <asm/mach-ralink/eureka_ep430.h>
  75 +#include <linux/init.h>
  76 +#include <linux/mod_devicetable.h>
  77 +#include <linux/delay.h>
  78 +//#include <asm/rt2880/surfboardint.h>
  79 +
  80 +#include <ralink_regs.h>
  81 +
  82 +extern void pcie_phy_init(void);
  83 +extern void chk_phy_pll(void);
  84 +
  85 +/*
  86 + * These functions and structures provide the BIOS scan and mapping of the PCI
  87 + * devices.
  88 + */
  89 +
  90 +#define CONFIG_PCIE_PORT0
  91 +#define CONFIG_PCIE_PORT1
  92 +#define CONFIG_PCIE_PORT2
  93 +#define RALINK_PCIE0_CLK_EN             (1<<24)
  94 +#define RALINK_PCIE1_CLK_EN             (1<<25)
  95 +#define RALINK_PCIE2_CLK_EN             (1<<26)
  96 +
  97 +#define RALINK_PCI_CONFIG_ADDR                         0x20
  98 +#define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG     0x24
  99 +#define SURFBOARDINT_PCIE0       12      /* PCIE0 */
 100 +#define RALINK_INT_PCIE0         SURFBOARDINT_PCIE0
 101 +#define RALINK_INT_PCIE1         SURFBOARDINT_PCIE1
 102 +#define RALINK_INT_PCIE2         SURFBOARDINT_PCIE2
 103 +#define SURFBOARDINT_PCIE1       32     /* PCIE1 */
 104 +#define SURFBOARDINT_PCIE2       33     /* PCIE2 */
 105 +#define RALINK_PCI_MEMBASE              *(volatile u32 *)(RALINK_PCI_BASE + 0x0028)
 106 +#define RALINK_PCI_IOBASE               *(volatile u32 *)(RALINK_PCI_BASE + 0x002C)
 107 +#define RALINK_PCIE0_RST                (1<<24)
 108 +#define RALINK_PCIE1_RST                (1<<25)
 109 +#define RALINK_PCIE2_RST                (1<<26)
 110 +#define RALINK_SYSCTL_BASE              0xBE000000
 111 +
 112 +#define RALINK_PCI_PCICFG_ADDR          *(volatile u32 *)(RALINK_PCI_BASE + 0x0000)
 113 +#define RALINK_PCI_PCIMSK_ADDR          *(volatile u32 *)(RALINK_PCI_BASE + 0x000C)
 114 +#define RALINK_PCI_BASE                 0xBE140000
 115 +
 116 +#define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000)
 117 +#define RT6855_PCIE0_OFFSET     0x2000
 118 +#define RT6855_PCIE1_OFFSET     0x3000
 119 +#define RT6855_PCIE2_OFFSET     0x4000
 120 +
 121 +#define RALINK_PCI0_BAR0SETUP_ADDR      *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0010)
 122 +#define RALINK_PCI0_IMBASEBAR0_ADDR     *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0018)
 123 +#define RALINK_PCI0_ID                  *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0030)
 124 +#define RALINK_PCI0_CLASS               *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0034)
 125 +#define RALINK_PCI0_SUBID               *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0038)
 126 +#define RALINK_PCI0_STATUS              *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0050)
 127 +#define RALINK_PCI0_DERR                *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0060)
 128 +#define RALINK_PCI0_ECRC                *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0064)
 129 +
 130 +#define RALINK_PCI1_BAR0SETUP_ADDR      *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0010)
 131 +#define RALINK_PCI1_IMBASEBAR0_ADDR     *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0018)
 132 +#define RALINK_PCI1_ID                  *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0030)
 133 +#define RALINK_PCI1_CLASS               *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0034)
 134 +#define RALINK_PCI1_SUBID               *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0038)
 135 +#define RALINK_PCI1_STATUS              *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0050)
 136 +#define RALINK_PCI1_DERR                *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0060)
 137 +#define RALINK_PCI1_ECRC                *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0064)
 138 +
 139 +#define RALINK_PCI2_BAR0SETUP_ADDR      *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0010)
 140 +#define RALINK_PCI2_IMBASEBAR0_ADDR     *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0018)
 141 +#define RALINK_PCI2_ID                  *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0030)
 142 +#define RALINK_PCI2_CLASS               *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0034)
 143 +#define RALINK_PCI2_SUBID               *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0038)
 144 +#define RALINK_PCI2_STATUS              *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0050)
 145 +#define RALINK_PCI2_DERR                *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0060)
 146 +#define RALINK_PCI2_ECRC                *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0064)
 147 +
 148 +#define RALINK_PCIEPHY_P0P1_CTL_OFFSET  (RALINK_PCI_BASE + 0x9000)
 149 +#define RALINK_PCIEPHY_P2_CTL_OFFSET    (RALINK_PCI_BASE + 0xA000)
 150 +
 151 +
 152 +#define MV_WRITE(ofs, data)  \
 153 +        *(volatile u32 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le32(data)
 154 +#define MV_READ(ofs, data)   \
 155 +               *(data) = le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
 156 +#define MV_READ_DATA(ofs)    \
 157 +                       le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
 158 +
 159 +#define MV_WRITE_16(ofs, data)  \
 160 +        *(volatile u16 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le16(data)
 161 +#define MV_READ_16(ofs, data)   \
 162 +               *(data) = le16_to_cpu(*(volatile u16 *)(RALINK_PCI_BASE+(ofs)))
 163 +
 164 +#define MV_WRITE_8(ofs, data)  \
 165 +        *(volatile u8 *)(RALINK_PCI_BASE+(ofs)) = data
 166 +#define MV_READ_8(ofs, data)   \
 167 +               *(data) = *(volatile u8 *)(RALINK_PCI_BASE+(ofs))
 168 +
 169 +
 170 +
 171 +#define RALINK_PCI_MM_MAP_BASE 0x60000000
 172 +#define RALINK_PCI_IO_MAP_BASE 0x1e160000
 173 +
 174 +#define RALINK_SYSTEM_CONTROL_BASE     0xbe000000
 175 +#define GPIO_PERST
 176 +#define ASSERT_SYSRST_PCIE(val)                do {    \
 177 +                                               if (*(unsigned int *)(0xbe00000c) == 0x00030101)        \
 178 +                                                       RALINK_RSTCTRL |= val;  \
 179 +                                               else    \
 180 +                                                       RALINK_RSTCTRL &= ~val; \
 181 +                                       } while(0)
 182 +#define DEASSERT_SYSRST_PCIE(val)      do {    \
 183 +                                               if (*(unsigned int *)(0xbe00000c) == 0x00030101)        \
 184 +                                                       RALINK_RSTCTRL &= ~val; \
 185 +                                               else    \
 186 +                                                       RALINK_RSTCTRL |= val;  \
 187 +                                       } while(0)
 188 +#define RALINK_SYSCFG1                 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x14)
 189 +#define RALINK_CLKCFG1                 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x30)
 190 +#define RALINK_RSTCTRL                 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x34)
 191 +#define RALINK_GPIOMODE                        *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x60)
 192 +#define RALINK_PCIE_CLK_GEN            *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x7c)
 193 +#define RALINK_PCIE_CLK_GEN1           *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x80)
 194 +#define PPLL_CFG1                      *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x9c)
 195 +#define PPLL_DRV                       *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0xa0)
 196 +//RALINK_SYSCFG1 bit
 197 +#define RALINK_PCI_HOST_MODE_EN                (1<<7)
 198 +#define RALINK_PCIE_RC_MODE_EN         (1<<8)
 199 +//RALINK_RSTCTRL bit
 200 +#define RALINK_PCIE_RST                        (1<<23)
 201 +#define RALINK_PCI_RST                 (1<<24)
 202 +//RALINK_CLKCFG1 bit
 203 +#define RALINK_PCI_CLK_EN              (1<<19)
 204 +#define RALINK_PCIE_CLK_EN             (1<<21)
 205 +//RALINK_GPIOMODE bit
 206 +#define PCI_SLOTx2                     (1<<11)
 207 +#define PCI_SLOTx1                     (2<<11)
 208 +//MTK PCIE PLL bit
 209 +#define PDRV_SW_SET                    (1<<31)
 210 +#define LC_CKDRVPD_                    (1<<19)
 211 +
 212 +#define MEMORY_BASE 0x0
 213 +int pcie_link_status = 0;
 214 +
 215 +void __inline__ read_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned long reg, unsigned long *val);
 216 +void __inline__ write_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned long reg, unsigned long val);
 217 +
 218 +#define PCI_ACCESS_READ_1  0
 219 +#define PCI_ACCESS_READ_2  1
 220 +#define PCI_ACCESS_READ_4  2
 221 +#define PCI_ACCESS_WRITE_1 3
 222 +#define PCI_ACCESS_WRITE_2 4
 223 +#define PCI_ACCESS_WRITE_4 5
 224 +
 225 +static int config_access(unsigned char access_type, struct pci_bus *bus,
 226 +                       unsigned int devfn, unsigned int where, u32 * data)
 227 +{
 228 +       unsigned int slot = PCI_SLOT(devfn);
 229 +       u8 func = PCI_FUNC(devfn);
 230 +       uint32_t address_reg, data_reg;
 231 +       unsigned int address;
 232 +
 233 +       address_reg = RALINK_PCI_CONFIG_ADDR;
 234 +       data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
 235 +
 236 +       address = (((where&0xF00)>>8)<<24) |(bus->number << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000;
 237 +       MV_WRITE(address_reg, address);
 238 +
 239 +       switch(access_type) {
 240 +       case PCI_ACCESS_WRITE_1:
 241 +               MV_WRITE_8(data_reg+(where&0x3), *data);
 242 +               break;
 243 +       case PCI_ACCESS_WRITE_2:
 244 +               MV_WRITE_16(data_reg+(where&0x3), *data);
 245 +               break;
 246 +       case PCI_ACCESS_WRITE_4:
 247 +               MV_WRITE(data_reg, *data);
 248 +               break;
 249 +       case PCI_ACCESS_READ_1:
 250 +               MV_READ_8( data_reg+(where&0x3), data);
 251 +               break;
 252 +       case PCI_ACCESS_READ_2:
 253 +               MV_READ_16(data_reg+(where&0x3), data);
 254 +               break;
 255 +       case PCI_ACCESS_READ_4:
 256 +               MV_READ(data_reg, data);
 257 +               break;
 258 +       default:
 259 +               printk("no specify access type\n");
 260 +               break;
 261 +       }
 262 +       return 0;
 263 +}
 264 +
 265 +static int
 266 +read_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 * val)
 267 +{
 268 +       return config_access(PCI_ACCESS_READ_1, bus, devfn, (unsigned int)where, (u32 *)val);
 269 +}
 270 +
 271 +static int
 272 +read_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 * val)
 273 +{
 274 +       return config_access(PCI_ACCESS_READ_2, bus, devfn, (unsigned int)where, (u32 *)val);
 275 +}
 276 +
 277 +static int
 278 +read_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 * val)
 279 +{
 280 +       return config_access(PCI_ACCESS_READ_4, bus, devfn, (unsigned int)where, (u32 *)val);
 281 +}
 282 +
 283 +static int
 284 +write_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 val)
 285 +{
 286 +       if (config_access(PCI_ACCESS_WRITE_1, bus, devfn, (unsigned int)where, (u32 *)&val))
 287 +               return -1;
 288 +
 289 +       return PCIBIOS_SUCCESSFUL;
 290 +}
 291 +
 292 +static int
 293 +write_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 val)
 294 +{
 295 +       if (config_access(PCI_ACCESS_WRITE_2, bus, devfn, where, (u32 *)&val))
 296 +               return -1;
 297 +
 298 +       return PCIBIOS_SUCCESSFUL;
 299 +}
 300 +
 301 +static int
 302 +write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 val)
 303 +{
 304 +       if (config_access(PCI_ACCESS_WRITE_4, bus, devfn, where, &val))
 305 +               return -1;
 306 +
 307 +       return PCIBIOS_SUCCESSFUL;
 308 +}
 309 +
 310 +
 311 +static int
 312 +pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val)
 313 +{
 314 +       switch (size) {
 315 +       case 1:
 316 +               return read_config_byte(bus, devfn, where, (u8 *) val);
 317 +       case 2:
 318 +               return read_config_word(bus, devfn, where, (u16 *) val);
 319 +       default:
 320 +               return read_config_dword(bus, devfn, where, val);
 321 +       }
 322 +}
 323 +
 324 +static int
 325 +pci_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
 326 +{
 327 +       switch (size) {
 328 +       case 1:
 329 +               return write_config_byte(bus, devfn, where, (u8) val);
 330 +       case 2:
 331 +               return write_config_word(bus, devfn, where, (u16) val);
 332 +       default:
 333 +               return write_config_dword(bus, devfn, where, val);
 334 +       }
 335 +}
 336 +
 337 +struct pci_ops rt2880_pci_ops= {
 338 +       .read           =  pci_config_read,
 339 +       .write          = pci_config_write,
 340 +};
 341 +
 342 +static struct resource rt2880_res_pci_mem1 = {
 343 +       .name           = "PCI MEM1",
 344 +       .start          = RALINK_PCI_MM_MAP_BASE,
 345 +       .end            = (u32)((RALINK_PCI_MM_MAP_BASE + (unsigned char *)0x0fffffff)),
 346 +       .flags          = IORESOURCE_MEM,
 347 +};
 348 +static struct resource rt2880_res_pci_io1 = {
 349 +       .name           = "PCI I/O1",
 350 +       .start          = RALINK_PCI_IO_MAP_BASE,
 351 +       .end            = (u32)((RALINK_PCI_IO_MAP_BASE + (unsigned char *)0x0ffff)),
 352 +       .flags          = IORESOURCE_IO,
 353 +};
 354 +
 355 +struct pci_controller rt2880_controller = {
 356 +       .pci_ops        = &rt2880_pci_ops,
 357 +       .mem_resource   = &rt2880_res_pci_mem1,
 358 +       .io_resource    = &rt2880_res_pci_io1,
 359 +       .mem_offset     = 0x00000000UL,
 360 +       .io_offset      = 0x00000000UL,
 361 +       .io_map_base    = 0xa0000000,
 362 +};
 363 +
 364 +void __inline__
 365 +read_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned long reg, unsigned long *val)
 366 +{
 367 +       unsigned int address_reg, data_reg, address;
 368 +
 369 +       address_reg = RALINK_PCI_CONFIG_ADDR;
 370 +        data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
 371 +       address = (((reg & 0xF00)>>8)<<24) | (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 0x80000000 ;
 372 +        MV_WRITE(address_reg, address);
 373 +        MV_READ(data_reg, val);
 374 +       return;
 375 +}
 376 +
 377 +void __inline__
 378 +write_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned long reg, unsigned long val)
 379 +{
 380 +       unsigned int address_reg, data_reg, address;
 381 +
 382 +       address_reg = RALINK_PCI_CONFIG_ADDR;
 383 +       data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
 384 +       address = (((reg & 0xF00)>>8)<<24) | (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 0x80000000 ;
 385 +       MV_WRITE(address_reg, address);
 386 +       MV_WRITE(data_reg, val);
 387 +       return;
 388 +}
 389 +
 390 +
 391 +int __init
 392 +pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 393 +{
 394 +       u16 cmd;
 395 +       u32 val;
 396 +       int irq = 0;
 397 +
 398 +       if ((dev->bus->number == 0) && (slot == 0)) {
 399 +               write_config(0, 0, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
 400 +               read_config(0, 0, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
 401 +               printk("BAR0 at slot 0 = %x\n", val);
 402 +               printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
 403 +       } else if((dev->bus->number == 0) && (slot == 0x1)) {
 404 +               write_config(0, 1, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
 405 +               read_config(0, 1, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
 406 +               printk("BAR0 at slot 1 = %x\n", val);
 407 +               printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
 408 +       } else if((dev->bus->number == 0) && (slot == 0x2)) {
 409 +               write_config(0, 2, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
 410 +               read_config(0, 2, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
 411 +               printk("BAR0 at slot 2 = %x\n", val);
 412 +               printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
 413 +       } else if ((dev->bus->number == 1) && (slot == 0x0)) {
 414 +               switch (pcie_link_status) {
 415 +               case 2:
 416 +               case 6:
 417 +                       irq = RALINK_INT_PCIE1;
 418 +                       break;
 419 +               case 4:
 420 +                       irq = RALINK_INT_PCIE2;
 421 +                       break;
 422 +               default:
 423 +                       irq = RALINK_INT_PCIE0;
 424 +               }
 425 +               printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
 426 +       } else if ((dev->bus->number == 2) && (slot == 0x0)) {
 427 +               switch (pcie_link_status) {
 428 +               case 5:
 429 +               case 6:
 430 +                       irq = RALINK_INT_PCIE2;
 431 +                       break;
 432 +               default:
 433 +                       irq = RALINK_INT_PCIE1;
 434 +               }
 435 +               printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
 436 +       } else if ((dev->bus->number == 2) && (slot == 0x1)) {
 437 +               switch (pcie_link_status) {
 438 +               case 5:
 439 +               case 6:
 440 +                       irq = RALINK_INT_PCIE2;
 441 +                       break;
 442 +               default:
 443 +                       irq = RALINK_INT_PCIE1;
 444 +               }
 445 +               printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
 446 +       } else if ((dev->bus->number ==3) && (slot == 0x0)) {
 447 +               irq = RALINK_INT_PCIE2;
 448 +               printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
 449 +       } else if ((dev->bus->number ==3) && (slot == 0x1)) {
 450 +               irq = RALINK_INT_PCIE2;
 451 +               printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
 452 +       } else if ((dev->bus->number ==3) && (slot == 0x2)) {
 453 +               irq = RALINK_INT_PCIE2;
 454 +               printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
 455 +       } else {
 456 +               printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
 457 +               return 0;
 458 +       }
 459 +
 460 +       pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14);  //configure cache line size 0x14
 461 +       pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xFF);  //configure latency timer 0x10
 462 +       pci_read_config_word(dev, PCI_COMMAND, &cmd);
 463 +       cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
 464 +       pci_write_config_word(dev, PCI_COMMAND, cmd);
 465 +       pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
 466 +       return irq;
 467 +}
 468 +
 469 +void
 470 +set_pcie_phy(u32 *addr, int start_b, int bits, int val)
 471 +{
 472 +//     printk("0x%p:", addr);
 473 +//     printk(" %x", *addr);
 474 +       *(unsigned int *)(addr) &= ~(((1<<bits) - 1)<<start_b);
 475 +       *(unsigned int *)(addr) |= val << start_b;
 476 +//     printk(" -> %x\n", *addr);
 477 +}
 478 +
 479 +void
 480 +bypass_pipe_rst(void)
 481 +{
 482 +#if defined (CONFIG_PCIE_PORT0)
 483 +       /* PCIe Port 0 */
 484 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c), 12, 1, 0x01);     // rg_pe1_pipe_rst_b
 485 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c),  4, 1, 0x01);     // rg_pe1_pipe_cmd_frc[4]
 486 +#endif
 487 +#if defined (CONFIG_PCIE_PORT1)
 488 +       /* PCIe Port 1 */
 489 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c), 12, 1, 0x01);     // rg_pe1_pipe_rst_b
 490 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c),  4, 1, 0x01);     // rg_pe1_pipe_cmd_frc[4]
 491 +#endif
 492 +#if defined (CONFIG_PCIE_PORT2)
 493 +       /* PCIe Port 2 */
 494 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c), 12, 1, 0x01);       // rg_pe1_pipe_rst_b
 495 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c),  4, 1, 0x01);       // rg_pe1_pipe_cmd_frc[4]
 496 +#endif
 497 +}
 498 +
 499 +void
 500 +set_phy_for_ssc(void)
 501 +{
 502 +       unsigned long reg = (*(volatile u32 *)(RALINK_SYSCTL_BASE + 0x10));
 503 +
 504 +       reg = (reg >> 6) & 0x7;
 505 +#if defined (CONFIG_PCIE_PORT0) || defined (CONFIG_PCIE_PORT1)
 506 +       /* Set PCIe Port0 & Port1 PHY to disable SSC */
 507 +       /* Debug Xtal Type */
 508 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400),  8, 1, 0x01);     // rg_pe1_frc_h_xtal_type
 509 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400),  9, 2, 0x00);     // rg_pe1_h_xtal_type
 510 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000),  4, 1, 0x01);     // rg_pe1_frc_phy_en               //Force Port 0 enable control
 511 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100),  4, 1, 0x01);     // rg_pe1_frc_phy_en               //Force Port 1 enable control
 512 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000),  5, 1, 0x00);     // rg_pe1_phy_en                   //Port 0 disable
 513 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100),  5, 1, 0x00);     // rg_pe1_phy_en                   //Port 1 disable
 514 +       if(reg <= 5 && reg >= 3) {      // 40MHz Xtal
 515 +               set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),  6, 2, 0x01);     // RG_PE1_H_PLL_PREDIV             //Pre-divider ratio (for host mode)
 516 +               printk("***** Xtal 40MHz *****\n");
 517 +       } else {                        // 25MHz | 20MHz Xtal
 518 +               set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),  6, 2, 0x00);     // RG_PE1_H_PLL_PREDIV             //Pre-divider ratio (for host mode)
 519 +               if (reg >= 6) {
 520 +                       printk("***** Xtal 25MHz *****\n");
 521 +                       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4bc),  4, 2, 0x01);     // RG_PE1_H_PLL_FBKSEL             //Feedback clock select
 522 +                       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x49c),  0,31, 0x18000000);       // RG_PE1_H_LCDDS_PCW_NCPO         //DDS NCPO PCW (for host mode)
 523 +                       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a4),  0,16, 0x18d);    // RG_PE1_H_LCDDS_SSC_PRD          //DDS SSC dither period control
 524 +                       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8),  0,12, 0x4a);     // RG_PE1_H_LCDDS_SSC_DELTA        //DDS SSC dither amplitude control
 525 +                       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8), 16,12, 0x4a);     // RG_PE1_H_LCDDS_SSC_DELTA1       //DDS SSC dither amplitude control for initial
 526 +               } else {
 527 +                       printk("***** Xtal 20MHz *****\n");
 528 +               }
 529 +       }
 530 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a0),  5, 1, 0x01);     // RG_PE1_LCDDS_CLK_PH_INV         //DDS clock inversion
 531 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 22, 2, 0x02);     // RG_PE1_H_PLL_BC
 532 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 18, 4, 0x06);     // RG_PE1_H_PLL_BP
 533 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 12, 4, 0x02);     // RG_PE1_H_PLL_IR
 534 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),  8, 4, 0x01);     // RG_PE1_H_PLL_IC
 535 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4ac), 16, 3, 0x00);     // RG_PE1_H_PLL_BR
 536 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),  1, 3, 0x02);     // RG_PE1_PLL_DIVEN
 537 +       if(reg <= 5 && reg >= 3) {      // 40MHz Xtal
 538 +               set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414),  6, 2, 0x01);     // rg_pe1_mstckdiv              //value of da_pe1_mstckdiv when force mode enable
 539 +               set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414),  5, 1, 0x01);     // rg_pe1_frc_mstckdiv          //force mode enable of da_pe1_mstckdiv
 540 +       }
 541 +       /* Enable PHY and disable force mode */
 542 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000),  5, 1, 0x01);     // rg_pe1_phy_en                   //Port 0 enable
 543 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100),  5, 1, 0x01);     // rg_pe1_phy_en                   //Port 1 enable
 544 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000),  4, 1, 0x00);     // rg_pe1_frc_phy_en               //Force Port 0 disable control
 545 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100),  4, 1, 0x00);     // rg_pe1_frc_phy_en               //Force Port 1 disable control
 546 +#endif
 547 +#if defined (CONFIG_PCIE_PORT2)
 548 +       /* Set PCIe Port2 PHY to disable SSC */
 549 +       /* Debug Xtal Type */
 550 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400),  8, 1, 0x01);       // rg_pe1_frc_h_xtal_type
 551 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400),  9, 2, 0x00);       // rg_pe1_h_xtal_type
 552 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000),  4, 1, 0x01);       // rg_pe1_frc_phy_en               //Force Port 0 enable control
 553 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000),  5, 1, 0x00);       // rg_pe1_phy_en                   //Port 0 disable
 554 +       if(reg <= 5 && reg >= 3) {      // 40MHz Xtal
 555 +               set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490),  6, 2, 0x01);       // RG_PE1_H_PLL_PREDIV             //Pre-divider ratio (for host mode)
 556 +       } else {                        // 25MHz | 20MHz Xtal
 557 +               set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490),  6, 2, 0x00);       // RG_PE1_H_PLL_PREDIV             //Pre-divider ratio (for host mode)
 558 +               if (reg >= 6) {         // 25MHz Xtal
 559 +                       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4bc),  4, 2, 0x01);       // RG_PE1_H_PLL_FBKSEL             //Feedback clock select
 560 +                       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x49c),  0,31, 0x18000000); // RG_PE1_H_LCDDS_PCW_NCPO         //DDS NCPO PCW (for host mode)
 561 +                       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a4),  0,16, 0x18d);      // RG_PE1_H_LCDDS_SSC_PRD          //DDS SSC dither period control
 562 +                       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8),  0,12, 0x4a);       // RG_PE1_H_LCDDS_SSC_DELTA        //DDS SSC dither amplitude control
 563 +                       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8), 16,12, 0x4a);       // RG_PE1_H_LCDDS_SSC_DELTA1       //DDS SSC dither amplitude control for initial
 564 +               }
 565 +       }
 566 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a0),  5, 1, 0x01);       // RG_PE1_LCDDS_CLK_PH_INV         //DDS clock inversion
 567 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 22, 2, 0x02);       // RG_PE1_H_PLL_BC
 568 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 18, 4, 0x06);       // RG_PE1_H_PLL_BP
 569 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 12, 4, 0x02);       // RG_PE1_H_PLL_IR
 570 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490),  8, 4, 0x01);       // RG_PE1_H_PLL_IC
 571 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4ac), 16, 3, 0x00);       // RG_PE1_H_PLL_BR
 572 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490),  1, 3, 0x02);       // RG_PE1_PLL_DIVEN
 573 +       if(reg <= 5 && reg >= 3) {      // 40MHz Xtal
 574 +               set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414),  6, 2, 0x01);       // rg_pe1_mstckdiv              //value of da_pe1_mstckdiv when force mode enable
 575 +               set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414),  5, 1, 0x01);       // rg_pe1_frc_mstckdiv          //force mode enable of da_pe1_mstckdiv
 576 +       }
 577 +       /* Enable PHY and disable force mode */
 578 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000),  5, 1, 0x01);       // rg_pe1_phy_en                   //Port 0 enable
 579 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000),  4, 1, 0x00);       // rg_pe1_frc_phy_en               //Force Port 0 disable control
 580 +#endif
 581 +}
 582 +
 583 +int init_rt2880pci(void)
 584 +{
 585 +       unsigned long val = 0;
 586 +       iomem_resource.start = 0;
 587 +       iomem_resource.end= ~0;
 588 +       ioport_resource.start= 0;
 589 +       ioport_resource.end = ~0;
 590 +
 591 +#if defined (CONFIG_PCIE_PORT0)
 592 +       val = RALINK_PCIE0_RST;
 593 +#endif
 594 +#if defined (CONFIG_PCIE_PORT1)
 595 +       val |= RALINK_PCIE1_RST;
 596 +#endif
 597 +#if defined (CONFIG_PCIE_PORT2)
 598 +       val |= RALINK_PCIE2_RST;
 599 +#endif
 600 +       DEASSERT_SYSRST_PCIE(val);
 601 +       printk("release PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
 602 +
 603 +       bypass_pipe_rst();
 604 +       set_phy_for_ssc();
 605 +       ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST | RALINK_PCIE1_RST | RALINK_PCIE2_RST);
 606 +       printk("pull PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
 607 +#if defined GPIO_PERST /* add GPIO control instead of PERST_N */ /*chhung*/
 608 +       *(unsigned int *)(0xbe000060) &= ~(0x3<<10 | 0x3<<3);
 609 +       *(unsigned int *)(0xbe000060) |= 0x1<<10 | 0x1<<3;
 610 +       mdelay(100);
 611 +       *(unsigned int *)(0xbe000600) |= 0x1<<19 | 0x1<<8 | 0x1<<7; // use GPIO19/GPIO8/GPIO7 (PERST_N/UART_RXD3/UART_TXD3)
 612 +       mdelay(100);
 613 +       *(unsigned int *)(0xbe000620) &= ~(0x1<<19 | 0x1<<8 | 0x1<<7);          // clear DATA
 614 +
 615 +       mdelay(100);
 616 +#else
 617 +       *(unsigned int *)(0xbe000060) &= ~0x00000c00;
 618 +#endif
 619 +#if defined (CONFIG_PCIE_PORT0)
 620 +       val = RALINK_PCIE0_RST;
 621 +#endif
 622 +#if defined (CONFIG_PCIE_PORT1)
 623 +       val |= RALINK_PCIE1_RST;
 624 +#endif
 625 +#if defined (CONFIG_PCIE_PORT2)
 626 +       val |= RALINK_PCIE2_RST;
 627 +#endif
 628 +       DEASSERT_SYSRST_PCIE(val);
 629 +       printk("release PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
 630 +#if defined (CONFIG_PCIE_PORT0)
 631 +       read_config(0, 0, 0, 0x70c, &val);
 632 +       val &= ~(0xff)<<8;
 633 +       val |= 0x50<<8;
 634 +       write_config(0, 0, 0, 0x70c, val);
 635 +#endif
 636 +#if defined (CONFIG_PCIE_PORT1)
 637 +       read_config(0, 1, 0, 0x70c, &val);
 638 +       val &= ~(0xff)<<8;
 639 +       val |= 0x50<<8;
 640 +       write_config(0, 1, 0, 0x70c, val);
 641 +#endif
 642 +#if defined (CONFIG_PCIE_PORT2)
 643 +       read_config(0, 2, 0, 0x70c, &val);
 644 +       val &= ~(0xff)<<8;
 645 +       val |= 0x50<<8;
 646 +       write_config(0, 2, 0, 0x70c, val);
 647 +#endif
 648 +
 649 +#if defined (CONFIG_PCIE_PORT0)
 650 +       read_config(0, 0, 0, 0x70c, &val);
 651 +       printk("Port 0 N_FTS = %x\n", (unsigned int)val);
 652 +#endif
 653 +#if defined (CONFIG_PCIE_PORT1)
 654 +       read_config(0, 1, 0, 0x70c, &val);
 655 +       printk("Port 1 N_FTS = %x\n", (unsigned int)val);
 656 +#endif
 657 +#if defined (CONFIG_PCIE_PORT2)
 658 +       read_config(0, 2, 0, 0x70c, &val);
 659 +       printk("Port 2 N_FTS = %x\n", (unsigned int)val);
 660 +#endif
 661 +
 662 +       RALINK_RSTCTRL = (RALINK_RSTCTRL | RALINK_PCIE_RST);
 663 +       RALINK_SYSCFG1 &= ~(0x30);
 664 +       RALINK_SYSCFG1 |= (2<<4);
 665 +       RALINK_PCIE_CLK_GEN &= 0x7fffffff;
 666 +       RALINK_PCIE_CLK_GEN1 &= 0x80ffffff;
 667 +       RALINK_PCIE_CLK_GEN1 |= 0xa << 24;
 668 +       RALINK_PCIE_CLK_GEN |= 0x80000000;
 669 +       mdelay(50);
 670 +       RALINK_RSTCTRL = (RALINK_RSTCTRL & ~RALINK_PCIE_RST);
 671 +
 672 +
 673 +#if defined GPIO_PERST /* add GPIO control instead of PERST_N */  /*chhung*/
 674 +       *(unsigned int *)(0xbe000620) |= 0x1<<19 | 0x1<<8 | 0x1<<7;             // set DATA
 675 +       mdelay(100);
 676 +#else
 677 +       RALINK_PCI_PCICFG_ADDR &= ~(1<<1); //de-assert PERST
 678 +#endif
 679 +       mdelay(500);
 680 +
 681 +
 682 +       mdelay(500);
 683 +#if defined (CONFIG_PCIE_PORT0)
 684 +       if(( RALINK_PCI0_STATUS & 0x1) == 0)
 685 +       {
 686 +               printk("PCIE0 no card, disable it(RST&CLK)\n");
 687 +               ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST);
 688 +               RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE0_CLK_EN);
 689 +               pcie_link_status &= ~(1<<0);
 690 +       } else {
 691 +               pcie_link_status |= 1<<0;
 692 +               RALINK_PCI_PCIMSK_ADDR |= (1<<20); // enable pcie1 interrupt
 693 +       }
 694 +#endif
 695 +#if defined (CONFIG_PCIE_PORT1)
 696 +       if(( RALINK_PCI1_STATUS & 0x1) == 0)
 697 +       {
 698 +               printk("PCIE1 no card, disable it(RST&CLK)\n");
 699 +               ASSERT_SYSRST_PCIE(RALINK_PCIE1_RST);
 700 +               RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE1_CLK_EN);
 701 +               pcie_link_status &= ~(1<<1);
 702 +       } else {
 703 +               pcie_link_status |= 1<<1;
 704 +               RALINK_PCI_PCIMSK_ADDR |= (1<<21); // enable pcie1 interrupt
 705 +       }
 706 +#endif
 707 +#if defined (CONFIG_PCIE_PORT2)
 708 +       if (( RALINK_PCI2_STATUS & 0x1) == 0) {
 709 +               printk("PCIE2 no card, disable it(RST&CLK)\n");
 710 +               ASSERT_SYSRST_PCIE(RALINK_PCIE2_RST);
 711 +               RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE2_CLK_EN);
 712 +               pcie_link_status &= ~(1<<2);
 713 +       } else {
 714 +               pcie_link_status |= 1<<2;
 715 +               RALINK_PCI_PCIMSK_ADDR |= (1<<22); // enable pcie2 interrupt
 716 +       }
 717 +#endif
 718 +       if (pcie_link_status == 0)
 719 +               return 0;
 720 +
 721 +/*
 722 +pcie(2/1/0) link status        pcie2_num       pcie1_num       pcie0_num
 723 +3'b000                 x               x               x
 724 +3'b001                 x               x               0
 725 +3'b010                 x               0               x
 726 +3'b011                 x               1               0
 727 +3'b100                 0               x               x
 728 +3'b101                 1               x               0
 729 +3'b110                 1               0               x
 730 +3'b111                 2               1               0
 731 +*/
 732 +       switch(pcie_link_status) {
 733 +       case 2:
 734 +               RALINK_PCI_PCICFG_ADDR &= ~0x00ff0000;
 735 +               RALINK_PCI_PCICFG_ADDR |= 0x1 << 16;    //port0
 736 +               RALINK_PCI_PCICFG_ADDR |= 0x0 << 20;    //port1
 737 +               break;
 738 +       case 4:
 739 +               RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000;
 740 +               RALINK_PCI_PCICFG_ADDR |= 0x1 << 16;    //port0
 741 +               RALINK_PCI_PCICFG_ADDR |= 0x2 << 20;    //port1
 742 +               RALINK_PCI_PCICFG_ADDR |= 0x0 << 24;    //port2
 743 +               break;
 744 +       case 5:
 745 +               RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000;
 746 +               RALINK_PCI_PCICFG_ADDR |= 0x0 << 16;    //port0
 747 +               RALINK_PCI_PCICFG_ADDR |= 0x2 << 20;    //port1
 748 +               RALINK_PCI_PCICFG_ADDR |= 0x1 << 24;    //port2
 749 +               break;
 750 +       case 6:
 751 +               RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000;
 752 +               RALINK_PCI_PCICFG_ADDR |= 0x2 << 16;    //port0
 753 +               RALINK_PCI_PCICFG_ADDR |= 0x0 << 20;    //port1
 754 +               RALINK_PCI_PCICFG_ADDR |= 0x1 << 24;    //port2
 755 +               break;
 756 +       }
 757 +       printk(" -> %x\n", RALINK_PCI_PCICFG_ADDR);
 758 +       //printk(" RALINK_PCI_ARBCTL = %x\n", RALINK_PCI_ARBCTL);
 759 +
 760 +/*
 761 +       ioport_resource.start = rt2880_res_pci_io1.start;
 762 +       ioport_resource.end = rt2880_res_pci_io1.end;
 763 +*/
 764 +
 765 +       RALINK_PCI_MEMBASE = 0xffffffff; //RALINK_PCI_MM_MAP_BASE;
 766 +       RALINK_PCI_IOBASE = RALINK_PCI_IO_MAP_BASE;
 767 +
 768 +#if defined (CONFIG_PCIE_PORT0)
 769 +       //PCIe0
 770 +       if((pcie_link_status & 0x1) != 0) {
 771 +               RALINK_PCI0_BAR0SETUP_ADDR = 0x7FFF0001;        //open 7FFF:2G; ENABLE
 772 +               RALINK_PCI0_IMBASEBAR0_ADDR = MEMORY_BASE;
 773 +               RALINK_PCI0_CLASS = 0x06040001;
 774 +               printk("PCIE0 enabled\n");
 775 +       }
 776 +#endif
 777 +#if defined (CONFIG_PCIE_PORT1)
 778 +       //PCIe1
 779 +       if ((pcie_link_status & 0x2) != 0) {
 780 +               RALINK_PCI1_BAR0SETUP_ADDR = 0x7FFF0001;        //open 7FFF:2G; ENABLE
 781 +               RALINK_PCI1_IMBASEBAR0_ADDR = MEMORY_BASE;
 782 +               RALINK_PCI1_CLASS = 0x06040001;
 783 +               printk("PCIE1 enabled\n");
 784 +       }
 785 +#endif
 786 +#if defined (CONFIG_PCIE_PORT2)
 787 +       //PCIe2
 788 +       if ((pcie_link_status & 0x4) != 0) {
 789 +               RALINK_PCI2_BAR0SETUP_ADDR = 0x7FFF0001;        //open 7FFF:2G; ENABLE
 790 +               RALINK_PCI2_IMBASEBAR0_ADDR = MEMORY_BASE;
 791 +               RALINK_PCI2_CLASS = 0x06040001;
 792 +               printk("PCIE2 enabled\n");
 793 +       }
 794 +#endif
 795 +
 796 +
 797 +       switch(pcie_link_status) {
 798 +       case 7:
 799 +               read_config(0, 2, 0, 0x4, &val);
 800 +               write_config(0, 2, 0, 0x4, val|0x4);
 801 +               // write_config(0, 1, 0, 0x4, val|0x7);
 802 +       case 3:
 803 +       case 5:
 804 +       case 6:
 805 +               read_config(0, 1, 0, 0x4, &val);
 806 +               write_config(0, 1, 0, 0x4, val|0x4);
 807 +               // write_config(0, 1, 0, 0x4, val|0x7);
 808 +       default:
 809 +               read_config(0, 0, 0, 0x4, &val);
 810 +               write_config(0, 0, 0, 0x4, val|0x4); //bus master enable
 811 +               // write_config(0, 0, 0, 0x4, val|0x7); //bus master enable
 812 +       }
 813 +       register_pci_controller(&rt2880_controller);
 814 +       return 0;
 815 +
 816 +}
 817 +arch_initcall(init_rt2880pci);
 818 +
 819 +int pcibios_plat_dev_init(struct pci_dev *dev)
 820 +{
 821 +       return 0;
 822 +}