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ramips: basic support for Planex MZK-750DHP
[openwrt/openwrt.git] / target / linux / ramips / patches-3.10 / 0214-usb-add-mt7621-xhci-support.patch
1 From b823088d8782e02cc39c7eb4d834396b83dabe49 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Mon, 27 Jan 2014 13:11:01 +0000
4 Subject: [PATCH 214/215] usb: add mt7621 xhci support
5
6 Signed-off-by: John Crispin <blogic@openwrt.org>
7 ---
8 drivers/usb/core/hub.c | 2 +-
9 drivers/usb/core/port.c | 3 +-
10 drivers/usb/host/Kconfig | 6 +-
11 drivers/usb/host/Makefile | 10 +-
12 drivers/usb/host/mtk-phy-7621.c | 445 +++++
13 drivers/usb/host/mtk-phy-7621.h | 2871 +++++++++++++++++++++++++++++++++
14 drivers/usb/host/mtk-phy-ahb.c | 58 +
15 drivers/usb/host/mtk-phy.c | 102 ++
16 drivers/usb/host/mtk-phy.h | 179 ++
17 drivers/usb/host/pci-quirks.h | 2 +-
18 drivers/usb/host/xhci-dbg.c | 3 +
19 drivers/usb/host/xhci-mem.c | 11 +
20 drivers/usb/host/xhci-mtk-power.c | 115 ++
21 drivers/usb/host/xhci-mtk-power.h | 13 +
22 drivers/usb/host/xhci-mtk-scheduler.c | 608 +++++++
23 drivers/usb/host/xhci-mtk-scheduler.h | 77 +
24 drivers/usb/host/xhci-mtk.c | 265 +++
25 drivers/usb/host/xhci-mtk.h | 120 ++
26 drivers/usb/host/xhci-plat.c | 19 +
27 drivers/usb/host/xhci-ring.c | 109 +-
28 drivers/usb/host/xhci.c | 201 ++-
29 drivers/usb/host/xhci.h | 23 +-
30 22 files changed, 5229 insertions(+), 13 deletions(-)
31 create mode 100644 drivers/usb/host/mtk-phy-7621.c
32 create mode 100644 drivers/usb/host/mtk-phy-7621.h
33 create mode 100644 drivers/usb/host/mtk-phy-ahb.c
34 create mode 100644 drivers/usb/host/mtk-phy.c
35 create mode 100644 drivers/usb/host/mtk-phy.h
36 create mode 100644 drivers/usb/host/xhci-mtk-power.c
37 create mode 100644 drivers/usb/host/xhci-mtk-power.h
38 create mode 100644 drivers/usb/host/xhci-mtk-scheduler.c
39 create mode 100644 drivers/usb/host/xhci-mtk-scheduler.h
40 create mode 100644 drivers/usb/host/xhci-mtk.c
41 create mode 100644 drivers/usb/host/xhci-mtk.h
42
43 Index: linux-3.10.44/drivers/usb/core/hub.c
44 ===================================================================
45 --- linux-3.10.44.orig/drivers/usb/core/hub.c 2014-06-16 21:43:06.000000000 +0100
46 +++ linux-3.10.44/drivers/usb/core/hub.c 2014-07-02 11:20:15.817675027 +0100
47 @@ -1254,7 +1254,7 @@
48 if (type != HUB_SUSPEND) {
49 /* Disconnect all the children */
50 for (i = 0; i < hdev->maxchild; ++i) {
51 - if (hub->ports[i]->child)
52 + if (hub->ports[i] && hub->ports[i]->child)
53 usb_disconnect(&hub->ports[i]->child);
54 }
55 }
56 Index: linux-3.10.44/drivers/usb/core/port.c
57 ===================================================================
58 --- linux-3.10.44.orig/drivers/usb/core/port.c 2014-06-16 21:43:06.000000000 +0100
59 +++ linux-3.10.44/drivers/usb/core/port.c 2014-07-02 11:20:15.817675027 +0100
60 @@ -193,6 +193,7 @@
61 void usb_hub_remove_port_device(struct usb_hub *hub,
62 int port1)
63 {
64 - device_unregister(&hub->ports[port1 - 1]->dev);
65 + if (hub->ports[port1 - 1])
66 + device_unregister(&hub->ports[port1 - 1]->dev);
67 }
68
69 Index: linux-3.10.44/drivers/usb/host/Kconfig
70 ===================================================================
71 --- linux-3.10.44.orig/drivers/usb/host/Kconfig 2014-06-16 21:43:06.000000000 +0100
72 +++ linux-3.10.44/drivers/usb/host/Kconfig 2014-07-02 11:27:17.469659353 +0100
73 @@ -28,7 +28,13 @@
74 if USB_XHCI_HCD
75
76 config USB_XHCI_PLATFORM
77 - tristate
78 + bool "xHCI platform"
79 + depends on SOC_MT7621
80 +
81 +config USB_MT7621_XHCI_PLATFORM
82 + bool "MTK MT7621 xHCI"
83 + depends on USB_XHCI_PLATFORM
84 + depends on SOC_MT7621
85
86 config USB_XHCI_HCD_DEBUGGING
87 bool "Debugging for the xHCI host controller"
88 Index: linux-3.10.44/drivers/usb/host/Makefile
89 ===================================================================
90 --- linux-3.10.44.orig/drivers/usb/host/Makefile 2014-06-16 21:43:06.000000000 +0100
91 +++ linux-3.10.44/drivers/usb/host/Makefile 2014-07-02 11:20:15.817675027 +0100
92 @@ -13,15 +13,23 @@
93
94 xhci-hcd-y := xhci.o xhci-mem.o
95 xhci-hcd-y += xhci-ring.o xhci-hub.o xhci-dbg.o
96 +ifndef CONFIG_USB_MT7621_XHCI_PLATFORM
97 xhci-hcd-$(CONFIG_PCI) += xhci-pci.o
98 +endif
99 +
100 +ifdef CONFIG_USB_MT7621_XHCI_PLATFORM
101 +xhci-hcd-y += mtk-phy.o xhci-mtk-scheduler.o xhci-mtk-power.o xhci-mtk.o mtk-phy-7621.o mtk-phy-ahb.o
102 +endif
103
104 ifneq ($(CONFIG_USB_XHCI_PLATFORM), )
105 - xhci-hcd-y += xhci-plat.o
106 +xhci-hcd-y += xhci-plat.o
107 endif
108
109 obj-$(CONFIG_USB_WHCI_HCD) += whci/
110
111 +ifndef CONFIG_USB_MT7621_XHCI_PLATFORM
112 obj-$(CONFIG_PCI) += pci-quirks.o
113 +endif
114
115 obj-$(CONFIG_USB_EHCI_HCD) += ehci-hcd.o
116 obj-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o
117 Index: linux-3.10.44/drivers/usb/host/mtk-phy-7621.c
118 ===================================================================
119 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
120 +++ linux-3.10.44/drivers/usb/host/mtk-phy-7621.c 2014-07-02 11:20:15.817675027 +0100
121 @@ -0,0 +1,445 @@
122 +#include "mtk-phy.h"
123 +
124 +#ifdef CONFIG_PROJECT_7621
125 +#include "mtk-phy-7621.h"
126 +
127 +//not used on SoC
128 +PHY_INT32 phy_init(struct u3phy_info *info){
129 + return PHY_TRUE;
130 +}
131 +
132 +//not used on SoC
133 +PHY_INT32 phy_change_pipe_phase(struct u3phy_info *info, PHY_INT32 phy_drv, PHY_INT32 pipe_phase){
134 + return PHY_TRUE;
135 +}
136 +
137 +//--------------------------------------------------------
138 +// Function : fgEyeScanHelper_CheckPtInRegion()
139 +// Description : Check if the test point is in a rectangle region.
140 +// If it is in the rectangle, also check if this point
141 +// is on the multiple of deltaX and deltaY.
142 +// Parameter : strucScanRegion * prEye - the region
143 +// BYTE bX
144 +// BYTE bY
145 +// Return : BYTE - TRUE : This point needs to be tested
146 +// FALSE: This point will be omitted
147 +// Note : First check within the rectangle.
148 +// Secondly, use modulous to check if the point will be tested.
149 +//--------------------------------------------------------
150 +static PHY_INT8 fgEyeScanHelper_CheckPtInRegion(struct strucScanRegion * prEye, PHY_INT8 bX, PHY_INT8 bY)
151 +{
152 + PHY_INT8 fgValid = true;
153 +
154 +
155 + /// Be careful, the axis origin is on the TOP-LEFT corner.
156 + /// Therefore the top-left point has the minimum X and Y
157 + /// Botton-right point is the maximum X and Y
158 + if ( (prEye->bX_tl <= bX) && (bX <= prEye->bX_br)
159 + && (prEye->bY_tl <= bY) && (bY <= prEye->bX_br))
160 + {
161 + // With the region, now check whether or not the input test point is
162 + // on the multiples of X and Y
163 + // Do not have to worry about negative value, because we have already
164 + // check the input bX, and bY is within the region.
165 + if ( ((bX - prEye->bX_tl) % (prEye->bDeltaX))
166 + || ((bY - prEye->bY_tl) % (prEye->bDeltaY)) )
167 + {
168 + // if the division will have remainder, that means
169 + // the input test point is on the multiples of X and Y
170 + fgValid = false;
171 + }
172 + else
173 + {
174 + }
175 + }
176 + else
177 + {
178 +
179 + fgValid = false;
180 + }
181 + return fgValid;
182 +}
183 +
184 +//--------------------------------------------------------
185 +// Function : EyeScanHelper_RunTest()
186 +// Description : Enable the test, and wait til it is completed
187 +// Parameter : None
188 +// Return : None
189 +// Note : None
190 +//--------------------------------------------------------
191 +static void EyeScanHelper_RunTest(struct u3phy_info *info)
192 +{
193 + DRV_UDELAY(100);
194 + // Disable the test
195 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
196 + , RG_SSUSB_EQ_EYE_CNT_EN_OFST, RG_SSUSB_EQ_EYE_CNT_EN, 0); //RG_SSUSB_RX_EYE_CNT_EN = 0
197 + DRV_UDELAY(100);
198 + // Run the test
199 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
200 + , RG_SSUSB_EQ_EYE_CNT_EN_OFST, RG_SSUSB_EQ_EYE_CNT_EN, 1); //RG_SSUSB_RX_EYE_CNT_EN = 1
201 + DRV_UDELAY(100);
202 + // Wait til it's done
203 + //RGS_SSUSB_RX_EYE_CNT_RDY
204 + while(!U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->phya_rx_mon5)
205 + , RGS_SSUSB_EQ_EYE_CNT_RDY_OFST, RGS_SSUSB_EQ_EYE_CNT_RDY));
206 +}
207 +
208 +//--------------------------------------------------------
209 +// Function : fgEyeScanHelper_CalNextPoint()
210 +// Description : Calcualte the test point for the measurement
211 +// Parameter : None
212 +// Return : BOOL - TRUE : the next point is within the
213 +// boundaryof HW limit
214 +// FALSE: the next point is out of the HW limit
215 +// Note : The next point is obtained by calculating
216 +// from the bottom left of the region rectangle
217 +// and then scanning up until it reaches the upper
218 +// limit. At this time, the x will increment, and
219 +// start scanning downwards until the y hits the
220 +// zero.
221 +//--------------------------------------------------------
222 +static PHY_INT8 fgEyeScanHelper_CalNextPoint(void)
223 +{
224 + if ( ((_bYcurr == MAX_Y) && (_eScanDir == SCAN_DN))
225 + || ((_bYcurr == MIN_Y) && (_eScanDir == SCAN_UP))
226 + )
227 + {
228 + /// Reaches the limit of Y axis
229 + /// Increment X
230 + _bXcurr++;
231 + _fgXChged = true;
232 + _eScanDir = (_eScanDir == SCAN_UP) ? SCAN_DN : SCAN_UP;
233 +
234 + if (_bXcurr > MAX_X)
235 + {
236 + return false;
237 + }
238 + }
239 + else
240 + {
241 + _bYcurr = (_eScanDir == SCAN_DN) ? _bYcurr + 1 : _bYcurr - 1;
242 + _fgXChged = false;
243 + }
244 + return PHY_TRUE;
245 +}
246 +
247 +PHY_INT32 eyescan_init(struct u3phy_info *info){
248 + //initial PHY setting
249 + U3PhyWriteField32(((PHY_UINT32)&info->u3phya_regs->rega)
250 + , RG_SSUSB_CDR_EPEN_OFST, RG_SSUSB_CDR_EPEN, 1);
251 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->phyd_mix3)
252 + , RG_SSUSB_FORCE_CDR_PI_PWD_OFST, RG_SSUSB_FORCE_CDR_PI_PWD, 1);
253 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
254 + , RG_SSUSB_RX_PI_CAL_EN_SEL_OFST, RG_SSUSB_RX_PI_CAL_EN_SEL, 1); //RG_SSUSB_RX_PI_CAL_MANUAL_SEL = 1
255 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
256 + , RG_SSUSB_RX_PI_CAL_EN_OFST, RG_SSUSB_RX_PI_CAL_EN, 1); //RG_SSUSB_RX_PI_CAL_MANUAL_EN = 1
257 + return PHY_TRUE;
258 +}
259 +
260 +PHY_INT32 phy_eyescan(struct u3phy_info *info, PHY_INT32 x_t1, PHY_INT32 y_t1, PHY_INT32 x_br, PHY_INT32 y_br, PHY_INT32 delta_x, PHY_INT32 delta_y
261 + , PHY_INT32 eye_cnt, PHY_INT32 num_cnt, PHY_INT32 PI_cal_en, PHY_INT32 num_ignore_cnt){
262 + PHY_INT32 cOfst = 0;
263 + PHY_UINT8 bIdxX = 0;
264 + PHY_UINT8 bIdxY = 0;
265 + //PHY_INT8 bCnt = 0;
266 + PHY_UINT8 bIdxCycCnt = 0;
267 + PHY_INT8 fgValid;
268 + PHY_INT8 cX;
269 + PHY_INT8 cY;
270 + PHY_UINT8 bExtendCnt;
271 + PHY_INT8 isContinue;
272 + //PHY_INT8 isBreak;
273 + PHY_UINT32 wErr0 = 0, wErr1 = 0;
274 + //PHY_UINT32 temp;
275 +
276 + PHY_UINT32 pwErrCnt0[CYCLE_COUNT_MAX][ERRCNT_MAX][ERRCNT_MAX];
277 + PHY_UINT32 pwErrCnt1[CYCLE_COUNT_MAX][ERRCNT_MAX][ERRCNT_MAX];
278 +
279 + _rEye1.bX_tl = x_t1;
280 + _rEye1.bY_tl = y_t1;
281 + _rEye1.bX_br = x_br;
282 + _rEye1.bY_br = y_br;
283 + _rEye1.bDeltaX = delta_x;
284 + _rEye1.bDeltaY = delta_y;
285 +
286 + _rEye2.bX_tl = x_t1;
287 + _rEye2.bY_tl = y_t1;
288 + _rEye2.bX_br = x_br;
289 + _rEye2.bY_br = y_br;
290 + _rEye2.bDeltaX = delta_x;
291 + _rEye2.bDeltaY = delta_y;
292 +
293 + _rTestCycle.wEyeCnt = eye_cnt;
294 + _rTestCycle.bNumOfEyeCnt = num_cnt;
295 + _rTestCycle.bNumOfIgnoreCnt = num_ignore_cnt;
296 + _rTestCycle.bPICalEn = PI_cal_en;
297 +
298 + _bXcurr = 0;
299 + _bYcurr = 0;
300 + _eScanDir = SCAN_DN;
301 + _fgXChged = false;
302 +
303 + printk("x_t1: %x, y_t1: %x, x_br: %x, y_br: %x, delta_x: %x, delta_y: %x, \
304 + eye_cnt: %x, num_cnt: %x, PI_cal_en: %x, num_ignore_cnt: %x\n", \
305 + x_t1, y_t1, x_br, y_br, delta_x, delta_y, eye_cnt, num_cnt, PI_cal_en, num_ignore_cnt);
306 +
307 + //force SIGDET to OFF
308 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
309 + , RG_SSUSB_RX_SIGDET_EN_SEL_OFST, RG_SSUSB_RX_SIGDET_EN_SEL, 1); //RG_SSUSB_RX_SIGDET_SEL = 1
310 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
311 + , RG_SSUSB_RX_SIGDET_EN_OFST, RG_SSUSB_RX_SIGDET_EN, 0); //RG_SSUSB_RX_SIGDET_EN = 0
312 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye1)
313 + , RG_SSUSB_EQ_SIGDET_OFST, RG_SSUSB_EQ_SIGDET, 0); //RG_SSUSB_RX_SIGDET = 0
314 +
315 + // RX_TRI_DET_EN to Disable
316 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq3)
317 + , RG_SSUSB_EQ_TRI_DET_EN_OFST, RG_SSUSB_EQ_TRI_DET_EN, 0); //RG_SSUSB_RX_TRI_DET_EN = 0
318 +
319 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
320 + , RG_SSUSB_EQ_EYE_MON_EN_OFST, RG_SSUSB_EQ_EYE_MON_EN, 1); //RG_SSUSB_EYE_MON_EN = 1
321 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
322 + , RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET, 0); //RG_SSUSB_RX_EYE_XOFFSET = 0
323 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
324 + , RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y, 0); //RG_SSUSB_RX_EYE0_Y = 0
325 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
326 + , RG_SSUSB_EQ_EYE1_Y_OFST, RG_SSUSB_EQ_EYE1_Y, 0); //RG_SSUSB_RX_EYE1_Y = 0
327 +
328 +
329 + if (PI_cal_en){
330 + // PI Calibration
331 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
332 + , RG_SSUSB_RX_PI_CAL_EN_SEL_OFST, RG_SSUSB_RX_PI_CAL_EN_SEL, 1); //RG_SSUSB_RX_PI_CAL_MANUAL_SEL = 1
333 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
334 + , RG_SSUSB_RX_PI_CAL_EN_OFST, RG_SSUSB_RX_PI_CAL_EN, 0); //RG_SSUSB_RX_PI_CAL_MANUAL_EN = 0
335 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
336 + , RG_SSUSB_RX_PI_CAL_EN_OFST, RG_SSUSB_RX_PI_CAL_EN, 1); //RG_SSUSB_RX_PI_CAL_MANUAL_EN = 1
337 +
338 + DRV_UDELAY(20);
339 +
340 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
341 + , RG_SSUSB_RX_PI_CAL_EN_OFST, RG_SSUSB_RX_PI_CAL_EN, 0); //RG_SSUSB_RX_PI_CAL_MANUAL_EN = 0
342 + _bPIResult = U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->phya_rx_mon5)
343 + , RGS_SSUSB_EQ_PILPO_OFST, RGS_SSUSB_EQ_PILPO); //read RGS_SSUSB_RX_PILPO
344 +
345 + printk(KERN_ERR "PI result: %d\n", _bPIResult);
346 + }
347 + // Read Initial DAC
348 + // Set CYCLE
349 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye3)
350 + ,RG_SSUSB_EQ_EYE_CNT_OFST, RG_SSUSB_EQ_EYE_CNT, eye_cnt); //RG_SSUSB_RX_EYE_CNT
351 +
352 + // Eye Monitor Feature
353 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye1)
354 + , RG_SSUSB_EQ_EYE_MASK_OFST, RG_SSUSB_EQ_EYE_MASK, 0x3ff); //RG_SSUSB_RX_EYE_MASK = 0x3ff
355 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
356 + , RG_SSUSB_EQ_EYE_MON_EN_OFST, RG_SSUSB_EQ_EYE_MON_EN, 1); //RG_SSUSB_EYE_MON_EN = 1
357 +
358 + // Move X,Y to the top-left corner
359 + for (cOfst = 0; cOfst >= -64; cOfst--)
360 + {
361 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
362 + ,RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET, cOfst); //RG_SSUSB_RX_EYE_XOFFSET
363 + }
364 + for (cOfst = 0; cOfst < 64; cOfst++)
365 + {
366 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
367 + , RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y, cOfst); //RG_SSUSB_RX_EYE0_Y
368 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
369 + , RG_SSUSB_EQ_EYE1_Y_OFST, RG_SSUSB_EQ_EYE1_Y, cOfst); //RG_SSUSB_RX_EYE1_Y
370 + }
371 + //ClearErrorResult
372 + for(bIdxCycCnt = 0; bIdxCycCnt < CYCLE_COUNT_MAX; bIdxCycCnt++){
373 + for(bIdxX = 0; bIdxX < ERRCNT_MAX; bIdxX++)
374 + {
375 + for(bIdxY = 0; bIdxY < ERRCNT_MAX; bIdxY++){
376 + pwErrCnt0[bIdxCycCnt][bIdxX][bIdxY] = 0;
377 + pwErrCnt1[bIdxCycCnt][bIdxX][bIdxY] = 0;
378 + }
379 + }
380 + }
381 + isContinue = true;
382 + while(isContinue){
383 + //printk(KERN_ERR "_bXcurr: %d, _bYcurr: %d\n", _bXcurr, _bYcurr);
384 + // The point is within the boundary, then let's check if it is within
385 + // the testing region.
386 + // The point is only test-able if one of the eye region
387 + // includes this point.
388 + fgValid = fgEyeScanHelper_CheckPtInRegion(&_rEye1, _bXcurr, _bYcurr)
389 + || fgEyeScanHelper_CheckPtInRegion(&_rEye2, _bXcurr, _bYcurr);
390 + // Translate bX and bY to 2's complement from where the origin was on the
391 + // top left corner.
392 + // 0x40 and 0x3F needs a bit of thinking!!!! >"<
393 + cX = (_bXcurr ^ 0x40);
394 + cY = (_bYcurr ^ 0x3F);
395 +
396 + // Set X if necessary
397 + if (_fgXChged == true)
398 + {
399 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
400 + , RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET, cX); //RG_SSUSB_RX_EYE_XOFFSET
401 + }
402 + // Set Y
403 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
404 + , RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y, cY); //RG_SSUSB_RX_EYE0_Y
405 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
406 + , RG_SSUSB_EQ_EYE1_Y_OFST, RG_SSUSB_EQ_EYE1_Y, cY); //RG_SSUSB_RX_EYE1_Y
407 +
408 + /// Test this point!
409 + if (fgValid){
410 + for (bExtendCnt = 0; bExtendCnt < num_ignore_cnt; bExtendCnt++)
411 + {
412 + //run test
413 + EyeScanHelper_RunTest(info);
414 + }
415 + for (bExtendCnt = 0; bExtendCnt < num_cnt; bExtendCnt++)
416 + {
417 + EyeScanHelper_RunTest(info);
418 + wErr0 = U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->phya_rx_mon3)
419 + , RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_0_OFST, RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_0);
420 + wErr1 = U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->phya_rx_mon4)
421 + , RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_1_OFST, RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_1);
422 +
423 + pwErrCnt0[bExtendCnt][_bXcurr][_bYcurr] = wErr0;
424 + pwErrCnt1[bExtendCnt][_bXcurr][_bYcurr] = wErr1;
425 +
426 + //EyeScanHelper_GetResult(&_rRes.pwErrCnt0[bCnt], &_rRes.pwErrCnt1[bCnt]);
427 +// printk(KERN_ERR "cnt[%d] cur_x,y [0x%x][0x%x], cX,cY [0x%x][0x%x], ErrCnt[%d][%d]\n"
428 +// , bExtendCnt, _bXcurr, _bYcurr, cX, cY, pwErrCnt0[bExtendCnt][_bXcurr][_bYcurr], pwErrCnt1[bExtendCnt][_bXcurr][_bYcurr]);
429 + }
430 + //printk(KERN_ERR "cur_x,y [0x%x][0x%x], cX,cY [0x%x][0x%x], ErrCnt[%d][%d]\n", _bXcurr, _bYcurr, cX, cY, pwErrCnt0[0][_bXcurr][_bYcurr], pwErrCnt1[0][_bXcurr][_bYcurr]);
431 + }
432 + else{
433 +
434 + }
435 + if (fgEyeScanHelper_CalNextPoint() == false){
436 +#if 0
437 + printk(KERN_ERR "Xcurr [0x%x] Ycurr [0x%x]\n", _bXcurr, _bYcurr);
438 + printk(KERN_ERR "XcurrREG [0x%x] YcurrREG [0x%x]\n", cX, cY);
439 +#endif
440 + printk(KERN_ERR "end of eye scan\n");
441 + isContinue = false;
442 + }
443 + }
444 + printk(KERN_ERR "CurX [0x%x] CurY [0x%x]\n"
445 + , U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0), RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET)
446 + , U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0), RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y));
447 +
448 + // Move X,Y to the top-left corner
449 + for (cOfst = 63; cOfst >= 0; cOfst--)
450 + {
451 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
452 + , RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET, cOfst); //RG_SSUSB_RX_EYE_XOFFSET
453 + }
454 + for (cOfst = 63; cOfst >= 0; cOfst--)
455 + {
456 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
457 + , RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y, cOfst);
458 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
459 + , RG_SSUSB_EQ_EYE1_Y_OFST, RG_SSUSB_EQ_EYE1_Y, cOfst);
460 +
461 + }
462 + printk(KERN_ERR "CurX [0x%x] CurY [0x%x]\n"
463 + , U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0), RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET)
464 + , U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0), RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y));
465 +
466 + printk(KERN_ERR "PI result: %d\n", _bPIResult);
467 + printk(KERN_ERR "pwErrCnt0 addr: 0x%x\n", (PHY_UINT32)pwErrCnt0);
468 + printk(KERN_ERR "pwErrCnt1 addr: 0x%x\n", (PHY_UINT32)pwErrCnt1);
469 +
470 + return PHY_TRUE;
471 +}
472 +
473 +//not used on SoC
474 +PHY_INT32 u2_save_cur_en(struct u3phy_info *info){
475 + return PHY_TRUE;
476 +}
477 +
478 +//not used on SoC
479 +PHY_INT32 u2_save_cur_re(struct u3phy_info *info){
480 + return PHY_TRUE;
481 +}
482 +
483 +PHY_INT32 u2_slew_rate_calibration(struct u3phy_info *info){
484 + PHY_INT32 i=0;
485 + //PHY_INT32 j=0;
486 + //PHY_INT8 u1SrCalVal = 0;
487 + //PHY_INT8 u1Reg_addr_HSTX_SRCAL_EN;
488 + PHY_INT32 fgRet = 0;
489 + PHY_INT32 u4FmOut = 0;
490 + PHY_INT32 u4Tmp = 0;
491 + //PHY_INT32 temp;
492 +
493 + // => RG_USB20_HSTX_SRCAL_EN = 1
494 + // enable HS TX SR calibration
495 + U3PhyWriteField32(((PHY_UINT32)&info->u2phy_regs->u2phyacr0)
496 + , RG_USB20_HSTX_SRCAL_EN_OFST, RG_USB20_HSTX_SRCAL_EN, 0x1);
497 + DRV_MSLEEP(1);
498 +
499 + // => RG_FRCK_EN = 1
500 + // Enable free run clock
501 + U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmmonr1)
502 + , RG_FRCK_EN_OFST, RG_FRCK_EN, 1);
503 +
504 + // MT6290 HS signal quality patch
505 + // => RG_CYCLECNT = 400
506 + // Setting cyclecnt =400
507 + U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmcr0)
508 + , RG_CYCLECNT_OFST, RG_CYCLECNT, 0x400);
509 +
510 + // => RG_FREQDET_EN = 1
511 + // Enable frequency meter
512 + U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmcr0)
513 + , RG_FREQDET_EN_OFST, RG_FREQDET_EN, 0x1);
514 +
515 + // wait for FM detection done, set 10ms timeout
516 + for(i=0; i<10; i++){
517 + // => u4FmOut = USB_FM_OUT
518 + // read FM_OUT
519 + u4FmOut = U3PhyReadReg32(((PHY_UINT32)&info->sifslv_fm_regs->fmmonr0));
520 + printk("FM_OUT value: u4FmOut = %d(0x%08X)\n", u4FmOut, u4FmOut);
521 +
522 + // check if FM detection done
523 + if (u4FmOut != 0)
524 + {
525 + fgRet = 0;
526 + printk("FM detection done! loop = %d\n", i);
527 +
528 + break;
529 + }
530 +
531 + fgRet = 1;
532 + DRV_MSLEEP(1);
533 + }
534 + // => RG_FREQDET_EN = 0
535 + // disable frequency meter
536 + U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmcr0)
537 + , RG_FREQDET_EN_OFST, RG_FREQDET_EN, 0);
538 +
539 + // => RG_FRCK_EN = 0
540 + // disable free run clock
541 + U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmmonr1)
542 + , RG_FRCK_EN_OFST, RG_FRCK_EN, 0);
543 +
544 + // => RG_USB20_HSTX_SRCAL_EN = 0
545 + // disable HS TX SR calibration
546 + U3PhyWriteField32(((PHY_UINT32)&info->u2phy_regs->u2phyacr0)
547 + , RG_USB20_HSTX_SRCAL_EN_OFST, RG_USB20_HSTX_SRCAL_EN, 0);
548 + DRV_MSLEEP(1);
549 +
550 + if(u4FmOut == 0){
551 + U3PhyWriteField32(((PHY_UINT32)&info->u2phy_regs->u2phyacr0)
552 + , RG_USB20_HSTX_SRCTRL_OFST, RG_USB20_HSTX_SRCTRL, 0x4);
553 +
554 + fgRet = 1;
555 + }
556 + else{
557 + // set reg = (1024/FM_OUT) * 25 * 0.028 (round to the nearest digits)
558 + u4Tmp = (((1024 * 25 * U2_SR_COEF_7621) / u4FmOut) + 500) / 1000;
559 + printk("SR calibration value u1SrCalVal = %d\n", (PHY_UINT8)u4Tmp);
560 + U3PhyWriteField32(((PHY_UINT32)&info->u2phy_regs->u2phyacr0)
561 + , RG_USB20_HSTX_SRCTRL_OFST, RG_USB20_HSTX_SRCTRL, u4Tmp);
562 + }
563 + return fgRet;
564 +}
565 +
566 +#endif
567 Index: linux-3.10.44/drivers/usb/host/mtk-phy-7621.h
568 ===================================================================
569 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
570 +++ linux-3.10.44/drivers/usb/host/mtk-phy-7621.h 2014-07-02 11:20:15.821675026 +0100
571 @@ -0,0 +1,2871 @@
572 +#ifdef CONFIG_PROJECT_7621
573 +#ifndef __MTK_PHY_7621_H
574 +#define __MTK_PHY_7621_H
575 +
576 +#define U2_SR_COEF_7621 28
577 +
578 +///////////////////////////////////////////////////////////////////////////////
579 +
580 +struct u2phy_reg {
581 + //0x0
582 + PHY_LE32 u2phyac0;
583 + PHY_LE32 u2phyac1;
584 + PHY_LE32 u2phyac2;
585 + PHY_LE32 reserve0;
586 + //0x10
587 + PHY_LE32 u2phyacr0;
588 + PHY_LE32 u2phyacr1;
589 + PHY_LE32 u2phyacr2;
590 + PHY_LE32 u2phyacr3;
591 + //0x20
592 + PHY_LE32 u2phyacr4;
593 + PHY_LE32 u2phyamon0;
594 + PHY_LE32 reserve1[2];
595 + //0x30~0x50
596 + PHY_LE32 reserve2[12];
597 + //0x60
598 + PHY_LE32 u2phydcr0;
599 + PHY_LE32 u2phydcr1;
600 + PHY_LE32 u2phydtm0;
601 + PHY_LE32 u2phydtm1;
602 + //0x70
603 + PHY_LE32 u2phydmon0;
604 + PHY_LE32 u2phydmon1;
605 + PHY_LE32 u2phydmon2;
606 + PHY_LE32 u2phydmon3;
607 + //0x80
608 + PHY_LE32 u2phybc12c;
609 + PHY_LE32 u2phybc12c1;
610 + PHY_LE32 reserve3[2];
611 + //0x90~0xe0
612 + PHY_LE32 reserve4[24];
613 + //0xf0
614 + PHY_LE32 reserve6[3];
615 + PHY_LE32 regfcom;
616 +};
617 +
618 +//U3D_U2PHYAC0
619 +#define RG_USB20_USBPLL_DIVEN (0x7<<28) //30:28
620 +#define RG_USB20_USBPLL_CKCTRL (0x3<<26) //27:26
621 +#define RG_USB20_USBPLL_PREDIV (0x3<<24) //25:24
622 +#define RG_USB20_USBPLL_FORCE_ON (0x1<<23) //23:23
623 +#define RG_USB20_USBPLL_FBDIV (0x7f<<16) //22:16
624 +#define RG_USB20_REF_EN (0x1<<15) //15:15
625 +#define RG_USB20_INTR_EN (0x1<<14) //14:14
626 +#define RG_USB20_BG_TRIM (0xf<<8) //11:8
627 +#define RG_USB20_BG_RBSEL (0x3<<6) //7:6
628 +#define RG_USB20_BG_RASEL (0x3<<4) //5:4
629 +#define RG_USB20_BGR_DIV (0x3<<2) //3:2
630 +#define RG_SIFSLV_CHP_EN (0x1<<1) //1:1
631 +#define RG_SIFSLV_BGR_EN (0x1<<0) //0:0
632 +
633 +//U3D_U2PHYAC1
634 +#define RG_USB20_VRT_VREF_SEL (0x7<<28) //30:28
635 +#define RG_USB20_TERM_VREF_SEL (0x7<<24) //26:24
636 +#define RG_USB20_MPX_SEL (0xff<<16) //23:16
637 +#define RG_USB20_MPX_OUT_SEL (0x3<<12) //13:12
638 +#define RG_USB20_TX_PH_ROT_SEL (0x7<<8) //10:8
639 +#define RG_USB20_USBPLL_ACCEN (0x1<<3) //3:3
640 +#define RG_USB20_USBPLL_LF (0x1<<2) //2:2
641 +#define RG_USB20_USBPLL_BR (0x1<<1) //1:1
642 +#define RG_USB20_USBPLL_BP (0x1<<0) //0:0
643 +
644 +//U3D_U2PHYAC2
645 +#define RG_SIFSLV_MAC_BANDGAP_EN (0x1<<17) //17:17
646 +#define RG_SIFSLV_MAC_CHOPPER_EN (0x1<<16) //16:16
647 +#define RG_USB20_CLKREF_REV (0xff<<0) //7:0
648 +
649 +//U3D_U2PHYACR0
650 +#define RG_USB20_ICUSB_EN (0x1<<24) //24:24
651 +#define RG_USB20_HSTX_SRCAL_EN (0x1<<23) //23:23
652 +#define RG_USB20_HSTX_SRCTRL (0x7<<16) //18:16
653 +#define RG_USB20_LS_CR (0x7<<12) //14:12
654 +#define RG_USB20_FS_CR (0x7<<8) //10:8
655 +#define RG_USB20_LS_SR (0x7<<4) //6:4
656 +#define RG_USB20_FS_SR (0x7<<0) //2:0
657 +
658 +//U3D_U2PHYACR1
659 +#define RG_USB20_INIT_SQ_EN_DG (0x3<<28) //29:28
660 +#define RG_USB20_SQD (0x3<<24) //25:24
661 +#define RG_USB20_HSTX_TMODE_SEL (0x3<<20) //21:20
662 +#define RG_USB20_HSTX_TMODE_EN (0x1<<19) //19:19
663 +#define RG_USB20_PHYD_MONEN (0x1<<18) //18:18
664 +#define RG_USB20_INLPBK_EN (0x1<<17) //17:17
665 +#define RG_USB20_CHIRP_EN (0x1<<16) //16:16
666 +#define RG_USB20_DM_ABIST_SOURCE_EN (0x1<<15) //15:15
667 +#define RG_USB20_DM_ABIST_SELE (0xf<<8) //11:8
668 +#define RG_USB20_DP_ABIST_SOURCE_EN (0x1<<7) //7:7
669 +#define RG_USB20_DP_ABIST_SELE (0xf<<0) //3:0
670 +
671 +//U3D_U2PHYACR2
672 +#define RG_USB20_OTG_ABIST_SELE (0x7<<29) //31:29
673 +#define RG_USB20_OTG_ABIST_EN (0x1<<28) //28:28
674 +#define RG_USB20_OTG_VBUSCMP_EN (0x1<<27) //27:27
675 +#define RG_USB20_OTG_VBUSTH (0x7<<24) //26:24
676 +#define RG_USB20_DISC_FIT_EN (0x1<<22) //22:22
677 +#define RG_USB20_DISCD (0x3<<20) //21:20
678 +#define RG_USB20_DISCTH (0xf<<16) //19:16
679 +#define RG_USB20_SQCAL_EN (0x1<<15) //15:15
680 +#define RG_USB20_SQCAL (0xf<<8) //11:8
681 +#define RG_USB20_SQTH (0xf<<0) //3:0
682 +
683 +//U3D_U2PHYACR3
684 +#define RG_USB20_HSTX_DBIST (0xf<<28) //31:28
685 +#define RG_USB20_HSTX_BIST_EN (0x1<<26) //26:26
686 +#define RG_USB20_HSTX_I_EN_MODE (0x3<<24) //25:24
687 +#define RG_USB20_HSRX_TMODE_EN (0x1<<23) //23:23
688 +#define RG_USB20_HSRX_BIAS_EN_SEL (0x3<<20) //21:20
689 +#define RG_USB20_USB11_TMODE_EN (0x1<<19) //19:19
690 +#define RG_USB20_TMODE_FS_LS_TX_EN (0x1<<18) //18:18
691 +#define RG_USB20_TMODE_FS_LS_RCV_EN (0x1<<17) //17:17
692 +#define RG_USB20_TMODE_FS_LS_MODE (0x1<<16) //16:16
693 +#define RG_USB20_HS_TERM_EN_MODE (0x3<<13) //14:13
694 +#define RG_USB20_PUPD_BIST_EN (0x1<<12) //12:12
695 +#define RG_USB20_EN_PU_DM (0x1<<11) //11:11
696 +#define RG_USB20_EN_PD_DM (0x1<<10) //10:10
697 +#define RG_USB20_EN_PU_DP (0x1<<9) //9:9
698 +#define RG_USB20_EN_PD_DP (0x1<<8) //8:8
699 +#define RG_USB20_PHY_REV (0xff<<0) //7:0
700 +
701 +//U3D_U2PHYACR4
702 +#define RG_USB20_DP_100K_MODE (0x1<<18) //18:18
703 +#define RG_USB20_DM_100K_EN (0x1<<17) //17:17
704 +#define USB20_DP_100K_EN (0x1<<16) //16:16
705 +#define USB20_GPIO_DM_I (0x1<<15) //15:15
706 +#define USB20_GPIO_DP_I (0x1<<14) //14:14
707 +#define USB20_GPIO_DM_OE (0x1<<13) //13:13
708 +#define USB20_GPIO_DP_OE (0x1<<12) //12:12
709 +#define RG_USB20_GPIO_CTL (0x1<<9) //9:9
710 +#define USB20_GPIO_MODE (0x1<<8) //8:8
711 +#define RG_USB20_TX_BIAS_EN (0x1<<5) //5:5
712 +#define RG_USB20_TX_VCMPDN_EN (0x1<<4) //4:4
713 +#define RG_USB20_HS_SQ_EN_MODE (0x3<<2) //3:2
714 +#define RG_USB20_HS_RCV_EN_MODE (0x3<<0) //1:0
715 +
716 +//U3D_U2PHYAMON0
717 +#define RGO_USB20_GPIO_DM_O (0x1<<1) //1:1
718 +#define RGO_USB20_GPIO_DP_O (0x1<<0) //0:0
719 +
720 +//U3D_U2PHYDCR0
721 +#define RG_USB20_CDR_TST (0x3<<30) //31:30
722 +#define RG_USB20_GATED_ENB (0x1<<29) //29:29
723 +#define RG_USB20_TESTMODE (0x3<<26) //27:26
724 +#define RG_USB20_PLL_STABLE (0x1<<25) //25:25
725 +#define RG_USB20_PLL_FORCE_ON (0x1<<24) //24:24
726 +#define RG_USB20_PHYD_RESERVE (0xffff<<8) //23:8
727 +#define RG_USB20_EBTHRLD (0x1<<7) //7:7
728 +#define RG_USB20_EARLY_HSTX_I (0x1<<6) //6:6
729 +#define RG_USB20_TX_TST (0x1<<5) //5:5
730 +#define RG_USB20_NEGEDGE_ENB (0x1<<4) //4:4
731 +#define RG_USB20_CDR_FILT (0xf<<0) //3:0
732 +
733 +//U3D_U2PHYDCR1
734 +#define RG_USB20_PROBE_SEL (0xff<<24) //31:24
735 +#define RG_USB20_DRVVBUS (0x1<<23) //23:23
736 +#define RG_DEBUG_EN (0x1<<22) //22:22
737 +#define RG_USB20_OTG_PROBE (0x3<<20) //21:20
738 +#define RG_USB20_SW_PLLMODE (0x3<<18) //19:18
739 +#define RG_USB20_BERTH (0x3<<16) //17:16
740 +#define RG_USB20_LBMODE (0x3<<13) //14:13
741 +#define RG_USB20_FORCE_TAP (0x1<<12) //12:12
742 +#define RG_USB20_TAPSEL (0xfff<<0) //11:0
743 +
744 +//U3D_U2PHYDTM0
745 +#define RG_UART_MODE (0x3<<30) //31:30
746 +#define FORCE_UART_I (0x1<<29) //29:29
747 +#define FORCE_UART_BIAS_EN (0x1<<28) //28:28
748 +#define FORCE_UART_TX_OE (0x1<<27) //27:27
749 +#define FORCE_UART_EN (0x1<<26) //26:26
750 +#define FORCE_USB_CLKEN (0x1<<25) //25:25
751 +#define FORCE_DRVVBUS (0x1<<24) //24:24
752 +#define FORCE_DATAIN (0x1<<23) //23:23
753 +#define FORCE_TXVALID (0x1<<22) //22:22
754 +#define FORCE_DM_PULLDOWN (0x1<<21) //21:21
755 +#define FORCE_DP_PULLDOWN (0x1<<20) //20:20
756 +#define FORCE_XCVRSEL (0x1<<19) //19:19
757 +#define FORCE_SUSPENDM (0x1<<18) //18:18
758 +#define FORCE_TERMSEL (0x1<<17) //17:17
759 +#define FORCE_OPMODE (0x1<<16) //16:16
760 +#define UTMI_MUXSEL (0x1<<15) //15:15
761 +#define RG_RESET (0x1<<14) //14:14
762 +#define RG_DATAIN (0xf<<10) //13:10
763 +#define RG_TXVALIDH (0x1<<9) //9:9
764 +#define RG_TXVALID (0x1<<8) //8:8
765 +#define RG_DMPULLDOWN (0x1<<7) //7:7
766 +#define RG_DPPULLDOWN (0x1<<6) //6:6
767 +#define RG_XCVRSEL (0x3<<4) //5:4
768 +#define RG_SUSPENDM (0x1<<3) //3:3
769 +#define RG_TERMSEL (0x1<<2) //2:2
770 +#define RG_OPMODE (0x3<<0) //1:0
771 +
772 +//U3D_U2PHYDTM1
773 +#define RG_USB20_PRBS7_EN (0x1<<31) //31:31
774 +#define RG_USB20_PRBS7_BITCNT (0x3f<<24) //29:24
775 +#define RG_USB20_CLK48M_EN (0x1<<23) //23:23
776 +#define RG_USB20_CLK60M_EN (0x1<<22) //22:22
777 +#define RG_UART_I (0x1<<19) //19:19
778 +#define RG_UART_BIAS_EN (0x1<<18) //18:18
779 +#define RG_UART_TX_OE (0x1<<17) //17:17
780 +#define RG_UART_EN (0x1<<16) //16:16
781 +#define FORCE_VBUSVALID (0x1<<13) //13:13
782 +#define FORCE_SESSEND (0x1<<12) //12:12
783 +#define FORCE_BVALID (0x1<<11) //11:11
784 +#define FORCE_AVALID (0x1<<10) //10:10
785 +#define FORCE_IDDIG (0x1<<9) //9:9
786 +#define FORCE_IDPULLUP (0x1<<8) //8:8
787 +#define RG_VBUSVALID (0x1<<5) //5:5
788 +#define RG_SESSEND (0x1<<4) //4:4
789 +#define RG_BVALID (0x1<<3) //3:3
790 +#define RG_AVALID (0x1<<2) //2:2
791 +#define RG_IDDIG (0x1<<1) //1:1
792 +#define RG_IDPULLUP (0x1<<0) //0:0
793 +
794 +//U3D_U2PHYDMON0
795 +#define RG_USB20_PRBS7_BERTH (0xff<<0) //7:0
796 +
797 +//U3D_U2PHYDMON1
798 +#define USB20_UART_O (0x1<<31) //31:31
799 +#define RGO_USB20_LB_PASS (0x1<<30) //30:30
800 +#define RGO_USB20_LB_DONE (0x1<<29) //29:29
801 +#define AD_USB20_BVALID (0x1<<28) //28:28
802 +#define USB20_IDDIG (0x1<<27) //27:27
803 +#define AD_USB20_VBUSVALID (0x1<<26) //26:26
804 +#define AD_USB20_SESSEND (0x1<<25) //25:25
805 +#define AD_USB20_AVALID (0x1<<24) //24:24
806 +#define USB20_LINE_STATE (0x3<<22) //23:22
807 +#define USB20_HST_DISCON (0x1<<21) //21:21
808 +#define USB20_TX_READY (0x1<<20) //20:20
809 +#define USB20_RX_ERROR (0x1<<19) //19:19
810 +#define USB20_RX_ACTIVE (0x1<<18) //18:18
811 +#define USB20_RX_VALIDH (0x1<<17) //17:17
812 +#define USB20_RX_VALID (0x1<<16) //16:16
813 +#define USB20_DATA_OUT (0xffff<<0) //15:0
814 +
815 +//U3D_U2PHYDMON2
816 +#define RGO_TXVALID_CNT (0xff<<24) //31:24
817 +#define RGO_RXACTIVE_CNT (0xff<<16) //23:16
818 +#define RGO_USB20_LB_BERCNT (0xff<<8) //15:8
819 +#define USB20_PROBE_OUT (0xff<<0) //7:0
820 +
821 +//U3D_U2PHYDMON3
822 +#define RGO_USB20_PRBS7_ERRCNT (0xffff<<16) //31:16
823 +#define RGO_USB20_PRBS7_DONE (0x1<<3) //3:3
824 +#define RGO_USB20_PRBS7_LOCK (0x1<<2) //2:2
825 +#define RGO_USB20_PRBS7_PASS (0x1<<1) //1:1
826 +#define RGO_USB20_PRBS7_PASSTH (0x1<<0) //0:0
827 +
828 +//U3D_U2PHYBC12C
829 +#define RG_SIFSLV_CHGDT_DEGLCH_CNT (0xf<<28) //31:28
830 +#define RG_SIFSLV_CHGDT_CTRL_CNT (0xf<<24) //27:24
831 +#define RG_SIFSLV_CHGDT_FORCE_MODE (0x1<<16) //16:16
832 +#define RG_CHGDT_ISRC_LEV (0x3<<14) //15:14
833 +#define RG_CHGDT_VDATSRC (0x1<<13) //13:13
834 +#define RG_CHGDT_BGVREF_SEL (0x7<<10) //12:10
835 +#define RG_CHGDT_RDVREF_SEL (0x3<<8) //9:8
836 +#define RG_CHGDT_ISRC_DP (0x1<<7) //7:7
837 +#define RG_SIFSLV_CHGDT_OPOUT_DM (0x1<<6) //6:6
838 +#define RG_CHGDT_VDAT_DM (0x1<<5) //5:5
839 +#define RG_CHGDT_OPOUT_DP (0x1<<4) //4:4
840 +#define RG_SIFSLV_CHGDT_VDAT_DP (0x1<<3) //3:3
841 +#define RG_SIFSLV_CHGDT_COMP_EN (0x1<<2) //2:2
842 +#define RG_SIFSLV_CHGDT_OPDRV_EN (0x1<<1) //1:1
843 +#define RG_CHGDT_EN (0x1<<0) //0:0
844 +
845 +//U3D_U2PHYBC12C1
846 +#define RG_CHGDT_REV (0xff<<0) //7:0
847 +
848 +//U3D_REGFCOM
849 +#define RG_PAGE (0xff<<24) //31:24
850 +#define I2C_MODE (0x1<<16) //16:16
851 +
852 +
853 +/* OFFSET */
854 +
855 +//U3D_U2PHYAC0
856 +#define RG_USB20_USBPLL_DIVEN_OFST (28)
857 +#define RG_USB20_USBPLL_CKCTRL_OFST (26)
858 +#define RG_USB20_USBPLL_PREDIV_OFST (24)
859 +#define RG_USB20_USBPLL_FORCE_ON_OFST (23)
860 +#define RG_USB20_USBPLL_FBDIV_OFST (16)
861 +#define RG_USB20_REF_EN_OFST (15)
862 +#define RG_USB20_INTR_EN_OFST (14)
863 +#define RG_USB20_BG_TRIM_OFST (8)
864 +#define RG_USB20_BG_RBSEL_OFST (6)
865 +#define RG_USB20_BG_RASEL_OFST (4)
866 +#define RG_USB20_BGR_DIV_OFST (2)
867 +#define RG_SIFSLV_CHP_EN_OFST (1)
868 +#define RG_SIFSLV_BGR_EN_OFST (0)
869 +
870 +//U3D_U2PHYAC1
871 +#define RG_USB20_VRT_VREF_SEL_OFST (28)
872 +#define RG_USB20_TERM_VREF_SEL_OFST (24)
873 +#define RG_USB20_MPX_SEL_OFST (16)
874 +#define RG_USB20_MPX_OUT_SEL_OFST (12)
875 +#define RG_USB20_TX_PH_ROT_SEL_OFST (8)
876 +#define RG_USB20_USBPLL_ACCEN_OFST (3)
877 +#define RG_USB20_USBPLL_LF_OFST (2)
878 +#define RG_USB20_USBPLL_BR_OFST (1)
879 +#define RG_USB20_USBPLL_BP_OFST (0)
880 +
881 +//U3D_U2PHYAC2
882 +#define RG_SIFSLV_MAC_BANDGAP_EN_OFST (17)
883 +#define RG_SIFSLV_MAC_CHOPPER_EN_OFST (16)
884 +#define RG_USB20_CLKREF_REV_OFST (0)
885 +
886 +//U3D_U2PHYACR0
887 +#define RG_USB20_ICUSB_EN_OFST (24)
888 +#define RG_USB20_HSTX_SRCAL_EN_OFST (23)
889 +#define RG_USB20_HSTX_SRCTRL_OFST (16)
890 +#define RG_USB20_LS_CR_OFST (12)
891 +#define RG_USB20_FS_CR_OFST (8)
892 +#define RG_USB20_LS_SR_OFST (4)
893 +#define RG_USB20_FS_SR_OFST (0)
894 +
895 +//U3D_U2PHYACR1
896 +#define RG_USB20_INIT_SQ_EN_DG_OFST (28)
897 +#define RG_USB20_SQD_OFST (24)
898 +#define RG_USB20_HSTX_TMODE_SEL_OFST (20)
899 +#define RG_USB20_HSTX_TMODE_EN_OFST (19)
900 +#define RG_USB20_PHYD_MONEN_OFST (18)
901 +#define RG_USB20_INLPBK_EN_OFST (17)
902 +#define RG_USB20_CHIRP_EN_OFST (16)
903 +#define RG_USB20_DM_ABIST_SOURCE_EN_OFST (15)
904 +#define RG_USB20_DM_ABIST_SELE_OFST (8)
905 +#define RG_USB20_DP_ABIST_SOURCE_EN_OFST (7)
906 +#define RG_USB20_DP_ABIST_SELE_OFST (0)
907 +
908 +//U3D_U2PHYACR2
909 +#define RG_USB20_OTG_ABIST_SELE_OFST (29)
910 +#define RG_USB20_OTG_ABIST_EN_OFST (28)
911 +#define RG_USB20_OTG_VBUSCMP_EN_OFST (27)
912 +#define RG_USB20_OTG_VBUSTH_OFST (24)
913 +#define RG_USB20_DISC_FIT_EN_OFST (22)
914 +#define RG_USB20_DISCD_OFST (20)
915 +#define RG_USB20_DISCTH_OFST (16)
916 +#define RG_USB20_SQCAL_EN_OFST (15)
917 +#define RG_USB20_SQCAL_OFST (8)
918 +#define RG_USB20_SQTH_OFST (0)
919 +
920 +//U3D_U2PHYACR3
921 +#define RG_USB20_HSTX_DBIST_OFST (28)
922 +#define RG_USB20_HSTX_BIST_EN_OFST (26)
923 +#define RG_USB20_HSTX_I_EN_MODE_OFST (24)
924 +#define RG_USB20_HSRX_TMODE_EN_OFST (23)
925 +#define RG_USB20_HSRX_BIAS_EN_SEL_OFST (20)
926 +#define RG_USB20_USB11_TMODE_EN_OFST (19)
927 +#define RG_USB20_TMODE_FS_LS_TX_EN_OFST (18)
928 +#define RG_USB20_TMODE_FS_LS_RCV_EN_OFST (17)
929 +#define RG_USB20_TMODE_FS_LS_MODE_OFST (16)
930 +#define RG_USB20_HS_TERM_EN_MODE_OFST (13)
931 +#define RG_USB20_PUPD_BIST_EN_OFST (12)
932 +#define RG_USB20_EN_PU_DM_OFST (11)
933 +#define RG_USB20_EN_PD_DM_OFST (10)
934 +#define RG_USB20_EN_PU_DP_OFST (9)
935 +#define RG_USB20_EN_PD_DP_OFST (8)
936 +#define RG_USB20_PHY_REV_OFST (0)
937 +
938 +//U3D_U2PHYACR4
939 +#define RG_USB20_DP_100K_MODE_OFST (18)
940 +#define RG_USB20_DM_100K_EN_OFST (17)
941 +#define USB20_DP_100K_EN_OFST (16)
942 +#define USB20_GPIO_DM_I_OFST (15)
943 +#define USB20_GPIO_DP_I_OFST (14)
944 +#define USB20_GPIO_DM_OE_OFST (13)
945 +#define USB20_GPIO_DP_OE_OFST (12)
946 +#define RG_USB20_GPIO_CTL_OFST (9)
947 +#define USB20_GPIO_MODE_OFST (8)
948 +#define RG_USB20_TX_BIAS_EN_OFST (5)
949 +#define RG_USB20_TX_VCMPDN_EN_OFST (4)
950 +#define RG_USB20_HS_SQ_EN_MODE_OFST (2)
951 +#define RG_USB20_HS_RCV_EN_MODE_OFST (0)
952 +
953 +//U3D_U2PHYAMON0
954 +#define RGO_USB20_GPIO_DM_O_OFST (1)
955 +#define RGO_USB20_GPIO_DP_O_OFST (0)
956 +
957 +//U3D_U2PHYDCR0
958 +#define RG_USB20_CDR_TST_OFST (30)
959 +#define RG_USB20_GATED_ENB_OFST (29)
960 +#define RG_USB20_TESTMODE_OFST (26)
961 +#define RG_USB20_PLL_STABLE_OFST (25)
962 +#define RG_USB20_PLL_FORCE_ON_OFST (24)
963 +#define RG_USB20_PHYD_RESERVE_OFST (8)
964 +#define RG_USB20_EBTHRLD_OFST (7)
965 +#define RG_USB20_EARLY_HSTX_I_OFST (6)
966 +#define RG_USB20_TX_TST_OFST (5)
967 +#define RG_USB20_NEGEDGE_ENB_OFST (4)
968 +#define RG_USB20_CDR_FILT_OFST (0)
969 +
970 +//U3D_U2PHYDCR1
971 +#define RG_USB20_PROBE_SEL_OFST (24)
972 +#define RG_USB20_DRVVBUS_OFST (23)
973 +#define RG_DEBUG_EN_OFST (22)
974 +#define RG_USB20_OTG_PROBE_OFST (20)
975 +#define RG_USB20_SW_PLLMODE_OFST (18)
976 +#define RG_USB20_BERTH_OFST (16)
977 +#define RG_USB20_LBMODE_OFST (13)
978 +#define RG_USB20_FORCE_TAP_OFST (12)
979 +#define RG_USB20_TAPSEL_OFST (0)
980 +
981 +//U3D_U2PHYDTM0
982 +#define RG_UART_MODE_OFST (30)
983 +#define FORCE_UART_I_OFST (29)
984 +#define FORCE_UART_BIAS_EN_OFST (28)
985 +#define FORCE_UART_TX_OE_OFST (27)
986 +#define FORCE_UART_EN_OFST (26)
987 +#define FORCE_USB_CLKEN_OFST (25)
988 +#define FORCE_DRVVBUS_OFST (24)
989 +#define FORCE_DATAIN_OFST (23)
990 +#define FORCE_TXVALID_OFST (22)
991 +#define FORCE_DM_PULLDOWN_OFST (21)
992 +#define FORCE_DP_PULLDOWN_OFST (20)
993 +#define FORCE_XCVRSEL_OFST (19)
994 +#define FORCE_SUSPENDM_OFST (18)
995 +#define FORCE_TERMSEL_OFST (17)
996 +#define FORCE_OPMODE_OFST (16)
997 +#define UTMI_MUXSEL_OFST (15)
998 +#define RG_RESET_OFST (14)
999 +#define RG_DATAIN_OFST (10)
1000 +#define RG_TXVALIDH_OFST (9)
1001 +#define RG_TXVALID_OFST (8)
1002 +#define RG_DMPULLDOWN_OFST (7)
1003 +#define RG_DPPULLDOWN_OFST (6)
1004 +#define RG_XCVRSEL_OFST (4)
1005 +#define RG_SUSPENDM_OFST (3)
1006 +#define RG_TERMSEL_OFST (2)
1007 +#define RG_OPMODE_OFST (0)
1008 +
1009 +//U3D_U2PHYDTM1
1010 +#define RG_USB20_PRBS7_EN_OFST (31)
1011 +#define RG_USB20_PRBS7_BITCNT_OFST (24)
1012 +#define RG_USB20_CLK48M_EN_OFST (23)
1013 +#define RG_USB20_CLK60M_EN_OFST (22)
1014 +#define RG_UART_I_OFST (19)
1015 +#define RG_UART_BIAS_EN_OFST (18)
1016 +#define RG_UART_TX_OE_OFST (17)
1017 +#define RG_UART_EN_OFST (16)
1018 +#define FORCE_VBUSVALID_OFST (13)
1019 +#define FORCE_SESSEND_OFST (12)
1020 +#define FORCE_BVALID_OFST (11)
1021 +#define FORCE_AVALID_OFST (10)
1022 +#define FORCE_IDDIG_OFST (9)
1023 +#define FORCE_IDPULLUP_OFST (8)
1024 +#define RG_VBUSVALID_OFST (5)
1025 +#define RG_SESSEND_OFST (4)
1026 +#define RG_BVALID_OFST (3)
1027 +#define RG_AVALID_OFST (2)
1028 +#define RG_IDDIG_OFST (1)
1029 +#define RG_IDPULLUP_OFST (0)
1030 +
1031 +//U3D_U2PHYDMON0
1032 +#define RG_USB20_PRBS7_BERTH_OFST (0)
1033 +
1034 +//U3D_U2PHYDMON1
1035 +#define USB20_UART_O_OFST (31)
1036 +#define RGO_USB20_LB_PASS_OFST (30)
1037 +#define RGO_USB20_LB_DONE_OFST (29)
1038 +#define AD_USB20_BVALID_OFST (28)
1039 +#define USB20_IDDIG_OFST (27)
1040 +#define AD_USB20_VBUSVALID_OFST (26)
1041 +#define AD_USB20_SESSEND_OFST (25)
1042 +#define AD_USB20_AVALID_OFST (24)
1043 +#define USB20_LINE_STATE_OFST (22)
1044 +#define USB20_HST_DISCON_OFST (21)
1045 +#define USB20_TX_READY_OFST (20)
1046 +#define USB20_RX_ERROR_OFST (19)
1047 +#define USB20_RX_ACTIVE_OFST (18)
1048 +#define USB20_RX_VALIDH_OFST (17)
1049 +#define USB20_RX_VALID_OFST (16)
1050 +#define USB20_DATA_OUT_OFST (0)
1051 +
1052 +//U3D_U2PHYDMON2
1053 +#define RGO_TXVALID_CNT_OFST (24)
1054 +#define RGO_RXACTIVE_CNT_OFST (16)
1055 +#define RGO_USB20_LB_BERCNT_OFST (8)
1056 +#define USB20_PROBE_OUT_OFST (0)
1057 +
1058 +//U3D_U2PHYDMON3
1059 +#define RGO_USB20_PRBS7_ERRCNT_OFST (16)
1060 +#define RGO_USB20_PRBS7_DONE_OFST (3)
1061 +#define RGO_USB20_PRBS7_LOCK_OFST (2)
1062 +#define RGO_USB20_PRBS7_PASS_OFST (1)
1063 +#define RGO_USB20_PRBS7_PASSTH_OFST (0)
1064 +
1065 +//U3D_U2PHYBC12C
1066 +#define RG_SIFSLV_CHGDT_DEGLCH_CNT_OFST (28)
1067 +#define RG_SIFSLV_CHGDT_CTRL_CNT_OFST (24)
1068 +#define RG_SIFSLV_CHGDT_FORCE_MODE_OFST (16)
1069 +#define RG_CHGDT_ISRC_LEV_OFST (14)
1070 +#define RG_CHGDT_VDATSRC_OFST (13)
1071 +#define RG_CHGDT_BGVREF_SEL_OFST (10)
1072 +#define RG_CHGDT_RDVREF_SEL_OFST (8)
1073 +#define RG_CHGDT_ISRC_DP_OFST (7)
1074 +#define RG_SIFSLV_CHGDT_OPOUT_DM_OFST (6)
1075 +#define RG_CHGDT_VDAT_DM_OFST (5)
1076 +#define RG_CHGDT_OPOUT_DP_OFST (4)
1077 +#define RG_SIFSLV_CHGDT_VDAT_DP_OFST (3)
1078 +#define RG_SIFSLV_CHGDT_COMP_EN_OFST (2)
1079 +#define RG_SIFSLV_CHGDT_OPDRV_EN_OFST (1)
1080 +#define RG_CHGDT_EN_OFST (0)
1081 +
1082 +//U3D_U2PHYBC12C1
1083 +#define RG_CHGDT_REV_OFST (0)
1084 +
1085 +//U3D_REGFCOM
1086 +#define RG_PAGE_OFST (24)
1087 +#define I2C_MODE_OFST (16)
1088 +
1089 +
1090 +///////////////////////////////////////////////////////////////////////////////
1091 +
1092 +struct u3phya_reg {
1093 + //0x0
1094 + PHY_LE32 reg0;
1095 + PHY_LE32 reg1;
1096 + PHY_LE32 reg2;
1097 + PHY_LE32 reg3;
1098 + //0x10
1099 + PHY_LE32 reg4;
1100 + PHY_LE32 reg5;
1101 + PHY_LE32 reg6;
1102 + PHY_LE32 reg7;
1103 + //0x20
1104 + PHY_LE32 reg8;
1105 + PHY_LE32 reg9;
1106 + PHY_LE32 rega;
1107 + PHY_LE32 regb;
1108 + //0x30
1109 + PHY_LE32 regc;
1110 + PHY_LE32 regd;
1111 + PHY_LE32 rege;
1112 +};
1113 +
1114 +//U3D_reg0
1115 +#define RG_SSUSB_BGR_EN (0x1<<31) //31:31
1116 +#define RG_SSUSB_CHPEN (0x1<<30) //30:30
1117 +#define RG_SSUSB_BG_DIV (0x3<<28) //29:28
1118 +#define RG_SSUSB_INTR_EN (0x1<<26) //26:26
1119 +#define RG_SSUSB_MPX_OUT_SEL (0x3<<24) //25:24
1120 +#define RG_SSUSB_MPX_SEL (0xff<<16) //23:16
1121 +#define RG_SSUSB_REF_EN (0x1<<15) //15:15
1122 +#define RG_SSUSB_VRT_VREF_SEL (0xf<<11) //14:11
1123 +#define RG_SSUSB_BG_RASEL (0x3<<9) //10:9
1124 +#define RG_SSUSB_BG_RBSEL (0x3<<7) //8:7
1125 +#define RG_SSUSB_BG_MONEN (0x1<<6) //6:6
1126 +#define RG_PCIE_CLKDRV_OFFSET (0x3<<0) //1:0
1127 +
1128 +//U3D_reg1
1129 +#define RG_PCIE_CLKDRV_SLEW (0x3<<30) //31:30
1130 +#define RG_PCIE_CLKDRV_AMP (0x7<<27) //29:27
1131 +#define RG_SSUSB_XTAL_TST_A2DCK_EN (0x1<<26) //26:26
1132 +#define RG_SSUSB_XTAL_MON_EN (0x1<<25) //25:25
1133 +#define RG_SSUSB_XTAL_HYS (0x1<<24) //24:24
1134 +#define RG_SSUSB_XTAL_TOP_RESERVE (0xffff<<8) //23:8
1135 +#define RG_SSUSB_SYSPLL_RESERVE (0xf<<4) //7:4
1136 +#define RG_SSUSB_SYSPLL_FBSEL (0x3<<2) //3:2
1137 +#define RG_SSUSB_SYSPLL_PREDIV (0x3<<0) //1:0
1138 +
1139 +//U3D_reg2
1140 +#define RG_SSUSB_SYSPLL_LF (0x1<<31) //31:31
1141 +#define RG_SSUSB_SYSPLL_FBDIV (0x7f<<24) //30:24
1142 +#define RG_SSUSB_SYSPLL_POSDIV (0x3<<22) //23:22
1143 +#define RG_SSUSB_SYSPLL_VCO_DIV_SEL (0x1<<21) //21:21
1144 +#define RG_SSUSB_SYSPLL_BLP (0x1<<20) //20:20
1145 +#define RG_SSUSB_SYSPLL_BP (0x1<<19) //19:19
1146 +#define RG_SSUSB_SYSPLL_BR (0x1<<18) //18:18
1147 +#define RG_SSUSB_SYSPLL_BC (0x1<<17) //17:17
1148 +#define RG_SSUSB_SYSPLL_DIVEN (0x7<<14) //16:14
1149 +#define RG_SSUSB_SYSPLL_FPEN (0x1<<13) //13:13
1150 +#define RG_SSUSB_SYSPLL_MONCK_EN (0x1<<12) //12:12
1151 +#define RG_SSUSB_SYSPLL_MONVC_EN (0x1<<11) //11:11
1152 +#define RG_SSUSB_SYSPLL_MONREF_EN (0x1<<10) //10:10
1153 +#define RG_SSUSB_SYSPLL_VOD_EN (0x1<<9) //9:9
1154 +#define RG_SSUSB_SYSPLL_CK_SEL (0x1<<8) //8:8
1155 +
1156 +//U3D_reg3
1157 +#define RG_SSUSB_SYSPLL_TOP_RESERVE (0xffff<<16) //31:16
1158 +
1159 +//U3D_reg4
1160 +#define RG_SSUSB_SYSPLL_PCW_NCPO (0x7fffffff<<1) //31:1
1161 +
1162 +//U3D_reg5
1163 +#define RG_SSUSB_SYSPLL_DDS_PI_C (0x7<<29) //31:29
1164 +#define RG_SSUSB_SYSPLL_DDS_HF_EN (0x1<<28) //28:28
1165 +#define RG_SSUSB_SYSPLL_DDS_PREDIV2 (0x1<<27) //27:27
1166 +#define RG_SSUSB_SYSPLL_DDS_POSTDIV2 (0x1<<26) //26:26
1167 +#define RG_SSUSB_SYSPLL_DDS_PI_PL_EN (0x1<<25) //25:25
1168 +#define RG_SSUSB_SYSPLL_DDS_PI_RST_SEL (0x1<<24) //24:24
1169 +#define RG_SSUSB_SYSPLL_DDS_MONEN (0x1<<23) //23:23
1170 +#define RG_SSUSB_SYSPLL_DDS_LPF_EN (0x1<<22) //22:22
1171 +#define RG_SSUSB_SYSPLL_CLK_PH_INV (0x1<<21) //21:21
1172 +#define RG_SSUSB_SYSPLL_DDS_SEL_EXT (0x1<<20) //20:20
1173 +#define RG_SSUSB_SYSPLL_DDS_DMY (0xffff<<0) //15:0
1174 +
1175 +//U3D_reg6
1176 +#define RG_SSUSB_TX250MCK_INVB (0x1<<31) //31:31
1177 +#define RG_SSUSB_IDRV_ITAILOP_EN (0x1<<30) //30:30
1178 +#define RG_SSUSB_IDRV_CALIB (0x3f<<24) //29:24
1179 +#define RG_SSUSB_TX_R50_FON (0x1<<23) //23:23
1180 +#define RG_SSUSB_TX_SR (0x7<<20) //22:20
1181 +#define RG_SSUSB_TX_EIDLE_CM (0xf<<16) //19:16
1182 +#define RG_SSUSB_RXDET_RSEL (0x3<<14) //15:14
1183 +#define RG_SSUSB_RXDET_VTHSEL (0x3<<12) //13:12
1184 +#define RG_SSUSB_CKMON_EN (0x1<<11) //11:11
1185 +#define RG_SSUSB_CKMON_SEL (0x7<<8) //10:8
1186 +#define RG_SSUSB_TX_VLMON_EN (0x1<<7) //7:7
1187 +#define RG_SSUSB_TX_VLMON_SEL (0x1<<6) //6:6
1188 +#define RG_SSUSB_RXLBTX_EN (0x1<<5) //5:5
1189 +#define RG_SSUSB_TXLBRX_EN (0x1<<4) //4:4
1190 +
1191 +//U3D_reg7
1192 +#define RG_SSUSB_RESERVE (0xfffff<<12) //31:12
1193 +#define RG_SSUSB_PLL_CKCTRL (0x3<<10) //11:10
1194 +#define RG_SSUSB_PLL_POSDIV (0x3<<8) //9:8
1195 +#define RG_SSUSB_PLL_AUTOK_LOAD (0x1<<7) //7:7
1196 +#define RG_SSUSB_PLL_LOAD_RSTB (0x1<<6) //6:6
1197 +#define RG_SSUSB_PLL_EP_EN (0x1<<5) //5:5
1198 +#define RG_SSUSB_PLL_VOD_EN (0x1<<4) //4:4
1199 +#define RG_SSUSB_PLL_V11_EN (0x1<<3) //3:3
1200 +#define RG_SSUSB_PLL_MONREF_EN (0x1<<2) //2:2
1201 +#define RG_SSUSB_PLL_MONCK_EN (0x1<<1) //1:1
1202 +#define RG_SSUSB_PLL_MONVC_EN (0x1<<0) //0:0
1203 +
1204 +//U3D_reg8
1205 +#define RG_SSUSB_PLL_RESERVE (0xffff<<0) //15:0
1206 +
1207 +//U3D_reg9
1208 +#define RG_SSUSB_PLL_DDS_DMY (0xffff<<16) //31:16
1209 +#define RG_SSUSB_PLL_SSC_PRD (0xffff<<0) //15:0
1210 +
1211 +//U3D_regA
1212 +#define RG_SSUSB_PLL_SSC_PHASE_INI (0x1<<31) //31:31
1213 +#define RG_SSUSB_PLL_SSC_TRI_EN (0x1<<30) //30:30
1214 +#define RG_SSUSB_PLL_CLK_PH_INV (0x1<<29) //29:29
1215 +#define RG_SSUSB_PLL_DDS_LPF_EN (0x1<<28) //28:28
1216 +#define RG_SSUSB_PLL_DDS_VADJ (0x7<<21) //23:21
1217 +#define RG_SSUSB_PLL_DDS_MONEN (0x1<<20) //20:20
1218 +#define RG_SSUSB_PLL_DDS_PS_VADJ (0x7<<17) //19:17
1219 +#define RG_SSUSB_PLL_DDS_SEL_EXT (0x1<<16) //16:16
1220 +#define RG_SSUSB_CDR_PD_DIV_BYPASS (0x1<<15) //15:15
1221 +#define RG_SSUSB_CDR_PD_DIV_SEL (0x1<<14) //14:14
1222 +#define RG_SSUSB_CDR_CPBIAS_SEL (0x1<<13) //13:13
1223 +#define RG_SSUSB_CDR_OSCDET_EN (0x1<<12) //12:12
1224 +#define RG_SSUSB_CDR_MONMUX (0x1<<11) //11:11
1225 +#define RG_SSUSB_CDR_CKCTRL (0x3<<9) //10:9
1226 +#define RG_SSUSB_CDR_ACCEN (0x1<<8) //8:8
1227 +#define RG_SSUSB_CDR_BYPASS (0x3<<6) //7:6
1228 +#define RG_SSUSB_CDR_PI_SLEW (0x3<<4) //5:4
1229 +#define RG_SSUSB_CDR_EPEN (0x1<<3) //3:3
1230 +#define RG_SSUSB_CDR_AUTOK_LOAD (0x1<<2) //2:2
1231 +#define RG_SSUSB_CDR_LOAD_RSTB (0x1<<1) //1:1
1232 +#define RG_SSUSB_CDR_MONEN (0x1<<0) //0:0
1233 +
1234 +//U3D_regB
1235 +#define RG_SSUSB_CDR_MONEN_DIG (0x1<<31) //31:31
1236 +#define RG_SSUSB_CDR_REGOD (0x3<<29) //30:29
1237 +#define RG_SSUSB_RX_DAC_EN (0x1<<26) //26:26
1238 +#define RG_SSUSB_RX_DAC_PWD (0x1<<25) //25:25
1239 +#define RG_SSUSB_EQ_CURSEL (0x1<<24) //24:24
1240 +#define RG_SSUSB_RX_DAC_MUX (0x1f<<19) //23:19
1241 +#define RG_SSUSB_RX_R2T_EN (0x1<<18) //18:18
1242 +#define RG_SSUSB_RX_T2R_EN (0x1<<17) //17:17
1243 +#define RG_SSUSB_RX_50_LOWER (0x7<<14) //16:14
1244 +#define RG_SSUSB_RX_50_TAR (0x3<<12) //13:12
1245 +#define RG_SSUSB_RX_SW_CTRL (0xf<<7) //10:7
1246 +#define RG_PCIE_SIGDET_VTH (0x3<<5) //6:5
1247 +#define RG_PCIE_SIGDET_LPF (0x3<<3) //4:3
1248 +#define RG_SSUSB_LFPS_MON_EN (0x1<<2) //2:2
1249 +
1250 +//U3D_regC
1251 +#define RG_SSUSB_RXAFE_DCMON_SEL (0xf<<28) //31:28
1252 +#define RG_SSUSB_CDR_RESERVE (0xff<<16) //23:16
1253 +#define RG_SSUSB_RXAFE_RESERVE (0xff<<8) //15:8
1254 +#define RG_PCIE_RX_RESERVE (0xff<<0) //7:0
1255 +
1256 +//U3D_redD
1257 +#define RGS_SSUSB_CDR_NO_OSC (0x1<<8) //8:8
1258 +#define RGS_SSUSB_RX_DEBUG_RESERVE (0xff<<0) //7:0
1259 +
1260 +//U3D_regE
1261 +#define RG_SSUSB_INT_BIAS_SEL (0x1<<4) //4:4
1262 +#define RG_SSUSB_EXT_BIAS_SEL (0x1<<3) //3:3
1263 +#define RG_SSUSB_RX_P1_ENTRY_PASS (0x1<<2) //2:2
1264 +#define RG_SSUSB_RX_PD_RST (0x1<<1) //1:1
1265 +#define RG_SSUSB_RX_PD_RST_PASS (0x1<<0) //0:0
1266 +
1267 +
1268 +/* OFFSET */
1269 +
1270 +//U3D_reg0
1271 +#define RG_SSUSB_BGR_EN_OFST (31)
1272 +#define RG_SSUSB_CHPEN_OFST (30)
1273 +#define RG_SSUSB_BG_DIV_OFST (28)
1274 +#define RG_SSUSB_INTR_EN_OFST (26)
1275 +#define RG_SSUSB_MPX_OUT_SEL_OFST (24)
1276 +#define RG_SSUSB_MPX_SEL_OFST (16)
1277 +#define RG_SSUSB_REF_EN_OFST (15)
1278 +#define RG_SSUSB_VRT_VREF_SEL_OFST (11)
1279 +#define RG_SSUSB_BG_RASEL_OFST (9)
1280 +#define RG_SSUSB_BG_RBSEL_OFST (7)
1281 +#define RG_SSUSB_BG_MONEN_OFST (6)
1282 +#define RG_PCIE_CLKDRV_OFFSET_OFST (0)
1283 +
1284 +//U3D_reg1
1285 +#define RG_PCIE_CLKDRV_SLEW_OFST (30)
1286 +#define RG_PCIE_CLKDRV_AMP_OFST (27)
1287 +#define RG_SSUSB_XTAL_TST_A2DCK_EN_OFST (26)
1288 +#define RG_SSUSB_XTAL_MON_EN_OFST (25)
1289 +#define RG_SSUSB_XTAL_HYS_OFST (24)
1290 +#define RG_SSUSB_XTAL_TOP_RESERVE_OFST (8)
1291 +#define RG_SSUSB_SYSPLL_RESERVE_OFST (4)
1292 +#define RG_SSUSB_SYSPLL_FBSEL_OFST (2)
1293 +#define RG_SSUSB_SYSPLL_PREDIV_OFST (0)
1294 +
1295 +//U3D_reg2
1296 +#define RG_SSUSB_SYSPLL_LF_OFST (31)
1297 +#define RG_SSUSB_SYSPLL_FBDIV_OFST (24)
1298 +#define RG_SSUSB_SYSPLL_POSDIV_OFST (22)
1299 +#define RG_SSUSB_SYSPLL_VCO_DIV_SEL_OFST (21)
1300 +#define RG_SSUSB_SYSPLL_BLP_OFST (20)
1301 +#define RG_SSUSB_SYSPLL_BP_OFST (19)
1302 +#define RG_SSUSB_SYSPLL_BR_OFST (18)
1303 +#define RG_SSUSB_SYSPLL_BC_OFST (17)
1304 +#define RG_SSUSB_SYSPLL_DIVEN_OFST (14)
1305 +#define RG_SSUSB_SYSPLL_FPEN_OFST (13)
1306 +#define RG_SSUSB_SYSPLL_MONCK_EN_OFST (12)
1307 +#define RG_SSUSB_SYSPLL_MONVC_EN_OFST (11)
1308 +#define RG_SSUSB_SYSPLL_MONREF_EN_OFST (10)
1309 +#define RG_SSUSB_SYSPLL_VOD_EN_OFST (9)
1310 +#define RG_SSUSB_SYSPLL_CK_SEL_OFST (8)
1311 +
1312 +//U3D_reg3
1313 +#define RG_SSUSB_SYSPLL_TOP_RESERVE_OFST (16)
1314 +
1315 +//U3D_reg4
1316 +#define RG_SSUSB_SYSPLL_PCW_NCPO_OFST (1)
1317 +
1318 +//U3D_reg5
1319 +#define RG_SSUSB_SYSPLL_DDS_PI_C_OFST (29)
1320 +#define RG_SSUSB_SYSPLL_DDS_HF_EN_OFST (28)
1321 +#define RG_SSUSB_SYSPLL_DDS_PREDIV2_OFST (27)
1322 +#define RG_SSUSB_SYSPLL_DDS_POSTDIV2_OFST (26)
1323 +#define RG_SSUSB_SYSPLL_DDS_PI_PL_EN_OFST (25)
1324 +#define RG_SSUSB_SYSPLL_DDS_PI_RST_SEL_OFST (24)
1325 +#define RG_SSUSB_SYSPLL_DDS_MONEN_OFST (23)
1326 +#define RG_SSUSB_SYSPLL_DDS_LPF_EN_OFST (22)
1327 +#define RG_SSUSB_SYSPLL_CLK_PH_INV_OFST (21)
1328 +#define RG_SSUSB_SYSPLL_DDS_SEL_EXT_OFST (20)
1329 +#define RG_SSUSB_SYSPLL_DDS_DMY_OFST (0)
1330 +
1331 +//U3D_reg6
1332 +#define RG_SSUSB_TX250MCK_INVB_OFST (31)
1333 +#define RG_SSUSB_IDRV_ITAILOP_EN_OFST (30)
1334 +#define RG_SSUSB_IDRV_CALIB_OFST (24)
1335 +#define RG_SSUSB_TX_R50_FON_OFST (23)
1336 +#define RG_SSUSB_TX_SR_OFST (20)
1337 +#define RG_SSUSB_TX_EIDLE_CM_OFST (16)
1338 +#define RG_SSUSB_RXDET_RSEL_OFST (14)
1339 +#define RG_SSUSB_RXDET_VTHSEL_OFST (12)
1340 +#define RG_SSUSB_CKMON_EN_OFST (11)
1341 +#define RG_SSUSB_CKMON_SEL_OFST (8)
1342 +#define RG_SSUSB_TX_VLMON_EN_OFST (7)
1343 +#define RG_SSUSB_TX_VLMON_SEL_OFST (6)
1344 +#define RG_SSUSB_RXLBTX_EN_OFST (5)
1345 +#define RG_SSUSB_TXLBRX_EN_OFST (4)
1346 +
1347 +//U3D_reg7
1348 +#define RG_SSUSB_RESERVE_OFST (12)
1349 +#define RG_SSUSB_PLL_CKCTRL_OFST (10)
1350 +#define RG_SSUSB_PLL_POSDIV_OFST (8)
1351 +#define RG_SSUSB_PLL_AUTOK_LOAD_OFST (7)
1352 +#define RG_SSUSB_PLL_LOAD_RSTB_OFST (6)
1353 +#define RG_SSUSB_PLL_EP_EN_OFST (5)
1354 +#define RG_SSUSB_PLL_VOD_EN_OFST (4)
1355 +#define RG_SSUSB_PLL_V11_EN_OFST (3)
1356 +#define RG_SSUSB_PLL_MONREF_EN_OFST (2)
1357 +#define RG_SSUSB_PLL_MONCK_EN_OFST (1)
1358 +#define RG_SSUSB_PLL_MONVC_EN_OFST (0)
1359 +
1360 +//U3D_reg8
1361 +#define RG_SSUSB_PLL_RESERVE_OFST (0)
1362 +
1363 +//U3D_reg9
1364 +#define RG_SSUSB_PLL_DDS_DMY_OFST (16)
1365 +#define RG_SSUSB_PLL_SSC_PRD_OFST (0)
1366 +
1367 +//U3D_regA
1368 +#define RG_SSUSB_PLL_SSC_PHASE_INI_OFST (31)
1369 +#define RG_SSUSB_PLL_SSC_TRI_EN_OFST (30)
1370 +#define RG_SSUSB_PLL_CLK_PH_INV_OFST (29)
1371 +#define RG_SSUSB_PLL_DDS_LPF_EN_OFST (28)
1372 +#define RG_SSUSB_PLL_DDS_VADJ_OFST (21)
1373 +#define RG_SSUSB_PLL_DDS_MONEN_OFST (20)
1374 +#define RG_SSUSB_PLL_DDS_PS_VADJ_OFST (17)
1375 +#define RG_SSUSB_PLL_DDS_SEL_EXT_OFST (16)
1376 +#define RG_SSUSB_CDR_PD_DIV_BYPASS_OFST (15)
1377 +#define RG_SSUSB_CDR_PD_DIV_SEL_OFST (14)
1378 +#define RG_SSUSB_CDR_CPBIAS_SEL_OFST (13)
1379 +#define RG_SSUSB_CDR_OSCDET_EN_OFST (12)
1380 +#define RG_SSUSB_CDR_MONMUX_OFST (11)
1381 +#define RG_SSUSB_CDR_CKCTRL_OFST (9)
1382 +#define RG_SSUSB_CDR_ACCEN_OFST (8)
1383 +#define RG_SSUSB_CDR_BYPASS_OFST (6)
1384 +#define RG_SSUSB_CDR_PI_SLEW_OFST (4)
1385 +#define RG_SSUSB_CDR_EPEN_OFST (3)
1386 +#define RG_SSUSB_CDR_AUTOK_LOAD_OFST (2)
1387 +#define RG_SSUSB_CDR_LOAD_RSTB_OFST (1)
1388 +#define RG_SSUSB_CDR_MONEN_OFST (0)
1389 +
1390 +//U3D_regB
1391 +#define RG_SSUSB_CDR_MONEN_DIG_OFST (31)
1392 +#define RG_SSUSB_CDR_REGOD_OFST (29)
1393 +#define RG_SSUSB_RX_DAC_EN_OFST (26)
1394 +#define RG_SSUSB_RX_DAC_PWD_OFST (25)
1395 +#define RG_SSUSB_EQ_CURSEL_OFST (24)
1396 +#define RG_SSUSB_RX_DAC_MUX_OFST (19)
1397 +#define RG_SSUSB_RX_R2T_EN_OFST (18)
1398 +#define RG_SSUSB_RX_T2R_EN_OFST (17)
1399 +#define RG_SSUSB_RX_50_LOWER_OFST (14)
1400 +#define RG_SSUSB_RX_50_TAR_OFST (12)
1401 +#define RG_SSUSB_RX_SW_CTRL_OFST (7)
1402 +#define RG_PCIE_SIGDET_VTH_OFST (5)
1403 +#define RG_PCIE_SIGDET_LPF_OFST (3)
1404 +#define RG_SSUSB_LFPS_MON_EN_OFST (2)
1405 +
1406 +//U3D_regC
1407 +#define RG_SSUSB_RXAFE_DCMON_SEL_OFST (28)
1408 +#define RG_SSUSB_CDR_RESERVE_OFST (16)
1409 +#define RG_SSUSB_RXAFE_RESERVE_OFST (8)
1410 +#define RG_PCIE_RX_RESERVE_OFST (0)
1411 +
1412 +//U3D_redD
1413 +#define RGS_SSUSB_CDR_NO_OSC_OFST (8)
1414 +#define RGS_SSUSB_RX_DEBUG_RESERVE_OFST (0)
1415 +
1416 +//U3D_regE
1417 +#define RG_SSUSB_INT_BIAS_SEL_OFST (4)
1418 +#define RG_SSUSB_EXT_BIAS_SEL_OFST (3)
1419 +#define RG_SSUSB_RX_P1_ENTRY_PASS_OFST (2)
1420 +#define RG_SSUSB_RX_PD_RST_OFST (1)
1421 +#define RG_SSUSB_RX_PD_RST_PASS_OFST (0)
1422 +
1423 +///////////////////////////////////////////////////////////////////////////////
1424 +
1425 +struct u3phya_da_reg {
1426 + //0x0
1427 + PHY_LE32 reg0;
1428 + PHY_LE32 reg1;
1429 + PHY_LE32 reg4;
1430 + PHY_LE32 reg5;
1431 + //0x10
1432 + PHY_LE32 reg6;
1433 + PHY_LE32 reg7;
1434 + PHY_LE32 reg8;
1435 + PHY_LE32 reg9;
1436 + //0x20
1437 + PHY_LE32 reg10;
1438 + PHY_LE32 reg12;
1439 + PHY_LE32 reg13;
1440 + PHY_LE32 reg14;
1441 + //0x30
1442 + PHY_LE32 reg15;
1443 + PHY_LE32 reg16;
1444 + PHY_LE32 reg19;
1445 + PHY_LE32 reg20;
1446 + //0x40
1447 + PHY_LE32 reg21;
1448 + PHY_LE32 reg23;
1449 + PHY_LE32 reg25;
1450 + PHY_LE32 reg26;
1451 + //0x50
1452 + PHY_LE32 reg28;
1453 + PHY_LE32 reg29;
1454 + PHY_LE32 reg30;
1455 + PHY_LE32 reg31;
1456 + //0x60
1457 + PHY_LE32 reg32;
1458 + PHY_LE32 reg33;
1459 +};
1460 +
1461 +//U3D_reg0
1462 +#define RG_PCIE_SPEED_PE2D (0x1<<24) //24:24
1463 +#define RG_PCIE_SPEED_PE2H (0x1<<23) //23:23
1464 +#define RG_PCIE_SPEED_PE1D (0x1<<22) //22:22
1465 +#define RG_PCIE_SPEED_PE1H (0x1<<21) //21:21
1466 +#define RG_PCIE_SPEED_U3 (0x1<<20) //20:20
1467 +#define RG_SSUSB_XTAL_EXT_EN_PE2D (0x3<<18) //19:18
1468 +#define RG_SSUSB_XTAL_EXT_EN_PE2H (0x3<<16) //17:16
1469 +#define RG_SSUSB_XTAL_EXT_EN_PE1D (0x3<<14) //15:14
1470 +#define RG_SSUSB_XTAL_EXT_EN_PE1H (0x3<<12) //13:12
1471 +#define RG_SSUSB_XTAL_EXT_EN_U3 (0x3<<10) //11:10
1472 +#define RG_SSUSB_CDR_REFCK_SEL_PE2D (0x3<<8) //9:8
1473 +#define RG_SSUSB_CDR_REFCK_SEL_PE2H (0x3<<6) //7:6
1474 +#define RG_SSUSB_CDR_REFCK_SEL_PE1D (0x3<<4) //5:4
1475 +#define RG_SSUSB_CDR_REFCK_SEL_PE1H (0x3<<2) //3:2
1476 +#define RG_SSUSB_CDR_REFCK_SEL_U3 (0x3<<0) //1:0
1477 +
1478 +//U3D_reg1
1479 +#define RG_USB20_REFCK_SEL_PE2D (0x1<<30) //30:30
1480 +#define RG_USB20_REFCK_SEL_PE2H (0x1<<29) //29:29
1481 +#define RG_USB20_REFCK_SEL_PE1D (0x1<<28) //28:28
1482 +#define RG_USB20_REFCK_SEL_PE1H (0x1<<27) //27:27
1483 +#define RG_USB20_REFCK_SEL_U3 (0x1<<26) //26:26
1484 +#define RG_PCIE_REFCK_DIV4_PE2D (0x1<<25) //25:25
1485 +#define RG_PCIE_REFCK_DIV4_PE2H (0x1<<24) //24:24
1486 +#define RG_PCIE_REFCK_DIV4_PE1D (0x1<<18) //18:18
1487 +#define RG_PCIE_REFCK_DIV4_PE1H (0x1<<17) //17:17
1488 +#define RG_PCIE_REFCK_DIV4_U3 (0x1<<16) //16:16
1489 +#define RG_PCIE_MODE_PE2D (0x1<<8) //8:8
1490 +#define RG_PCIE_MODE_PE2H (0x1<<3) //3:3
1491 +#define RG_PCIE_MODE_PE1D (0x1<<2) //2:2
1492 +#define RG_PCIE_MODE_PE1H (0x1<<1) //1:1
1493 +#define RG_PCIE_MODE_U3 (0x1<<0) //0:0
1494 +
1495 +//U3D_reg4
1496 +#define RG_SSUSB_PLL_DIVEN_PE2D (0x7<<22) //24:22
1497 +#define RG_SSUSB_PLL_DIVEN_PE2H (0x7<<19) //21:19
1498 +#define RG_SSUSB_PLL_DIVEN_PE1D (0x7<<16) //18:16
1499 +#define RG_SSUSB_PLL_DIVEN_PE1H (0x7<<13) //15:13
1500 +#define RG_SSUSB_PLL_DIVEN_U3 (0x7<<10) //12:10
1501 +#define RG_SSUSB_PLL_BC_PE2D (0x3<<8) //9:8
1502 +#define RG_SSUSB_PLL_BC_PE2H (0x3<<6) //7:6
1503 +#define RG_SSUSB_PLL_BC_PE1D (0x3<<4) //5:4
1504 +#define RG_SSUSB_PLL_BC_PE1H (0x3<<2) //3:2
1505 +#define RG_SSUSB_PLL_BC_U3 (0x3<<0) //1:0
1506 +
1507 +//U3D_reg5
1508 +#define RG_SSUSB_PLL_BR_PE2D (0x7<<27) //29:27
1509 +#define RG_SSUSB_PLL_BR_PE2H (0x7<<24) //26:24
1510 +#define RG_SSUSB_PLL_BR_PE1D (0x7<<21) //23:21
1511 +#define RG_SSUSB_PLL_BR_PE1H (0x7<<18) //20:18
1512 +#define RG_SSUSB_PLL_BR_U3 (0x7<<15) //17:15
1513 +#define RG_SSUSB_PLL_IC_PE2D (0x7<<12) //14:12
1514 +#define RG_SSUSB_PLL_IC_PE2H (0x7<<9) //11:9
1515 +#define RG_SSUSB_PLL_IC_PE1D (0x7<<6) //8:6
1516 +#define RG_SSUSB_PLL_IC_PE1H (0x7<<3) //5:3
1517 +#define RG_SSUSB_PLL_IC_U3 (0x7<<0) //2:0
1518 +
1519 +//U3D_reg6
1520 +#define RG_SSUSB_PLL_IR_PE2D (0xf<<24) //27:24
1521 +#define RG_SSUSB_PLL_IR_PE2H (0xf<<16) //19:16
1522 +#define RG_SSUSB_PLL_IR_PE1D (0xf<<8) //11:8
1523 +#define RG_SSUSB_PLL_IR_PE1H (0xf<<4) //7:4
1524 +#define RG_SSUSB_PLL_IR_U3 (0xf<<0) //3:0
1525 +
1526 +//U3D_reg7
1527 +#define RG_SSUSB_PLL_BP_PE2D (0xf<<24) //27:24
1528 +#define RG_SSUSB_PLL_BP_PE2H (0xf<<16) //19:16
1529 +#define RG_SSUSB_PLL_BP_PE1D (0xf<<8) //11:8
1530 +#define RG_SSUSB_PLL_BP_PE1H (0xf<<4) //7:4
1531 +#define RG_SSUSB_PLL_BP_U3 (0xf<<0) //3:0
1532 +
1533 +//U3D_reg8
1534 +#define RG_SSUSB_PLL_FBKSEL_PE2D (0x3<<24) //25:24
1535 +#define RG_SSUSB_PLL_FBKSEL_PE2H (0x3<<16) //17:16
1536 +#define RG_SSUSB_PLL_FBKSEL_PE1D (0x3<<8) //9:8
1537 +#define RG_SSUSB_PLL_FBKSEL_PE1H (0x3<<2) //3:2
1538 +#define RG_SSUSB_PLL_FBKSEL_U3 (0x3<<0) //1:0
1539 +
1540 +//U3D_reg9
1541 +#define RG_SSUSB_PLL_FBKDIV_PE2H (0x7f<<24) //30:24
1542 +#define RG_SSUSB_PLL_FBKDIV_PE1D (0x7f<<16) //22:16
1543 +#define RG_SSUSB_PLL_FBKDIV_PE1H (0x7f<<8) //14:8
1544 +#define RG_SSUSB_PLL_FBKDIV_U3 (0x7f<<0) //6:0
1545 +
1546 +//U3D_reg10
1547 +#define RG_SSUSB_PLL_PREDIV_PE2D (0x3<<26) //27:26
1548 +#define RG_SSUSB_PLL_PREDIV_PE2H (0x3<<24) //25:24
1549 +#define RG_SSUSB_PLL_PREDIV_PE1D (0x3<<18) //19:18
1550 +#define RG_SSUSB_PLL_PREDIV_PE1H (0x3<<16) //17:16
1551 +#define RG_SSUSB_PLL_PREDIV_U3 (0x3<<8) //9:8
1552 +#define RG_SSUSB_PLL_FBKDIV_PE2D (0x7f<<0) //6:0
1553 +
1554 +//U3D_reg12
1555 +#define RG_SSUSB_PLL_PCW_NCPO_U3 (0x7fffffff<<0) //30:0
1556 +
1557 +//U3D_reg13
1558 +#define RG_SSUSB_PLL_PCW_NCPO_PE1H (0x7fffffff<<0) //30:0
1559 +
1560 +//U3D_reg14
1561 +#define RG_SSUSB_PLL_PCW_NCPO_PE1D (0x7fffffff<<0) //30:0
1562 +
1563 +//U3D_reg15
1564 +#define RG_SSUSB_PLL_PCW_NCPO_PE2H (0x7fffffff<<0) //30:0
1565 +
1566 +//U3D_reg16
1567 +#define RG_SSUSB_PLL_PCW_NCPO_PE2D (0x7fffffff<<0) //30:0
1568 +
1569 +//U3D_reg19
1570 +#define RG_SSUSB_PLL_SSC_DELTA1_PE1H (0xffff<<16) //31:16
1571 +#define RG_SSUSB_PLL_SSC_DELTA1_U3 (0xffff<<0) //15:0
1572 +
1573 +//U3D_reg20
1574 +#define RG_SSUSB_PLL_SSC_DELTA1_PE2H (0xffff<<16) //31:16
1575 +#define RG_SSUSB_PLL_SSC_DELTA1_PE1D (0xffff<<0) //15:0
1576 +
1577 +//U3D_reg21
1578 +#define RG_SSUSB_PLL_SSC_DELTA_U3 (0xffff<<16) //31:16
1579 +#define RG_SSUSB_PLL_SSC_DELTA1_PE2D (0xffff<<0) //15:0
1580 +
1581 +//U3D_reg23
1582 +#define RG_SSUSB_PLL_SSC_DELTA_PE1D (0xffff<<16) //31:16
1583 +#define RG_SSUSB_PLL_SSC_DELTA_PE1H (0xffff<<0) //15:0
1584 +
1585 +//U3D_reg25
1586 +#define RG_SSUSB_PLL_SSC_DELTA_PE2D (0xffff<<16) //31:16
1587 +#define RG_SSUSB_PLL_SSC_DELTA_PE2H (0xffff<<0) //15:0
1588 +
1589 +//U3D_reg26
1590 +#define RG_SSUSB_PLL_REFCKDIV_PE2D (0x1<<25) //25:25
1591 +#define RG_SSUSB_PLL_REFCKDIV_PE2H (0x1<<24) //24:24
1592 +#define RG_SSUSB_PLL_REFCKDIV_PE1D (0x1<<16) //16:16
1593 +#define RG_SSUSB_PLL_REFCKDIV_PE1H (0x1<<8) //8:8
1594 +#define RG_SSUSB_PLL_REFCKDIV_U3 (0x1<<0) //0:0
1595 +
1596 +//U3D_reg28
1597 +#define RG_SSUSB_CDR_BPA_PE2D (0x3<<24) //25:24
1598 +#define RG_SSUSB_CDR_BPA_PE2H (0x3<<16) //17:16
1599 +#define RG_SSUSB_CDR_BPA_PE1D (0x3<<10) //11:10
1600 +#define RG_SSUSB_CDR_BPA_PE1H (0x3<<8) //9:8
1601 +#define RG_SSUSB_CDR_BPA_U3 (0x3<<0) //1:0
1602 +
1603 +//U3D_reg29
1604 +#define RG_SSUSB_CDR_BPB_PE2D (0x7<<24) //26:24
1605 +#define RG_SSUSB_CDR_BPB_PE2H (0x7<<16) //18:16
1606 +#define RG_SSUSB_CDR_BPB_PE1D (0x7<<6) //8:6
1607 +#define RG_SSUSB_CDR_BPB_PE1H (0x7<<3) //5:3
1608 +#define RG_SSUSB_CDR_BPB_U3 (0x7<<0) //2:0
1609 +
1610 +//U3D_reg30
1611 +#define RG_SSUSB_CDR_BR_PE2D (0x7<<24) //26:24
1612 +#define RG_SSUSB_CDR_BR_PE2H (0x7<<16) //18:16
1613 +#define RG_SSUSB_CDR_BR_PE1D (0x7<<6) //8:6
1614 +#define RG_SSUSB_CDR_BR_PE1H (0x7<<3) //5:3
1615 +#define RG_SSUSB_CDR_BR_U3 (0x7<<0) //2:0
1616 +
1617 +//U3D_reg31
1618 +#define RG_SSUSB_CDR_FBDIV_PE2H (0x7f<<24) //30:24
1619 +#define RG_SSUSB_CDR_FBDIV_PE1D (0x7f<<16) //22:16
1620 +#define RG_SSUSB_CDR_FBDIV_PE1H (0x7f<<8) //14:8
1621 +#define RG_SSUSB_CDR_FBDIV_U3 (0x7f<<0) //6:0
1622 +
1623 +//U3D_reg32
1624 +#define RG_SSUSB_EQ_RSTEP1_PE2D (0x3<<30) //31:30
1625 +#define RG_SSUSB_EQ_RSTEP1_PE2H (0x3<<28) //29:28
1626 +#define RG_SSUSB_EQ_RSTEP1_PE1D (0x3<<26) //27:26
1627 +#define RG_SSUSB_EQ_RSTEP1_PE1H (0x3<<24) //25:24
1628 +#define RG_SSUSB_EQ_RSTEP1_U3 (0x3<<22) //23:22
1629 +#define RG_SSUSB_LFPS_DEGLITCH_PE2D (0x3<<20) //21:20
1630 +#define RG_SSUSB_LFPS_DEGLITCH_PE2H (0x3<<18) //19:18
1631 +#define RG_SSUSB_LFPS_DEGLITCH_PE1D (0x3<<16) //17:16
1632 +#define RG_SSUSB_LFPS_DEGLITCH_PE1H (0x3<<14) //15:14
1633 +#define RG_SSUSB_LFPS_DEGLITCH_U3 (0x3<<12) //13:12
1634 +#define RG_SSUSB_CDR_KVSEL_PE2D (0x1<<11) //11:11
1635 +#define RG_SSUSB_CDR_KVSEL_PE2H (0x1<<10) //10:10
1636 +#define RG_SSUSB_CDR_KVSEL_PE1D (0x1<<9) //9:9
1637 +#define RG_SSUSB_CDR_KVSEL_PE1H (0x1<<8) //8:8
1638 +#define RG_SSUSB_CDR_KVSEL_U3 (0x1<<7) //7:7
1639 +#define RG_SSUSB_CDR_FBDIV_PE2D (0x7f<<0) //6:0
1640 +
1641 +//U3D_reg33
1642 +#define RG_SSUSB_RX_CMPWD_PE2D (0x1<<26) //26:26
1643 +#define RG_SSUSB_RX_CMPWD_PE2H (0x1<<25) //25:25
1644 +#define RG_SSUSB_RX_CMPWD_PE1D (0x1<<24) //24:24
1645 +#define RG_SSUSB_RX_CMPWD_PE1H (0x1<<23) //23:23
1646 +#define RG_SSUSB_RX_CMPWD_U3 (0x1<<16) //16:16
1647 +#define RG_SSUSB_EQ_RSTEP2_PE2D (0x3<<8) //9:8
1648 +#define RG_SSUSB_EQ_RSTEP2_PE2H (0x3<<6) //7:6
1649 +#define RG_SSUSB_EQ_RSTEP2_PE1D (0x3<<4) //5:4
1650 +#define RG_SSUSB_EQ_RSTEP2_PE1H (0x3<<2) //3:2
1651 +#define RG_SSUSB_EQ_RSTEP2_U3 (0x3<<0) //1:0
1652 +
1653 +
1654 +/* OFFSET */
1655 +
1656 +//U3D_reg0
1657 +#define RG_PCIE_SPEED_PE2D_OFST (24)
1658 +#define RG_PCIE_SPEED_PE2H_OFST (23)
1659 +#define RG_PCIE_SPEED_PE1D_OFST (22)
1660 +#define RG_PCIE_SPEED_PE1H_OFST (21)
1661 +#define RG_PCIE_SPEED_U3_OFST (20)
1662 +#define RG_SSUSB_XTAL_EXT_EN_PE2D_OFST (18)
1663 +#define RG_SSUSB_XTAL_EXT_EN_PE2H_OFST (16)
1664 +#define RG_SSUSB_XTAL_EXT_EN_PE1D_OFST (14)
1665 +#define RG_SSUSB_XTAL_EXT_EN_PE1H_OFST (12)
1666 +#define RG_SSUSB_XTAL_EXT_EN_U3_OFST (10)
1667 +#define RG_SSUSB_CDR_REFCK_SEL_PE2D_OFST (8)
1668 +#define RG_SSUSB_CDR_REFCK_SEL_PE2H_OFST (6)
1669 +#define RG_SSUSB_CDR_REFCK_SEL_PE1D_OFST (4)
1670 +#define RG_SSUSB_CDR_REFCK_SEL_PE1H_OFST (2)
1671 +#define RG_SSUSB_CDR_REFCK_SEL_U3_OFST (0)
1672 +
1673 +//U3D_reg1
1674 +#define RG_USB20_REFCK_SEL_PE2D_OFST (30)
1675 +#define RG_USB20_REFCK_SEL_PE2H_OFST (29)
1676 +#define RG_USB20_REFCK_SEL_PE1D_OFST (28)
1677 +#define RG_USB20_REFCK_SEL_PE1H_OFST (27)
1678 +#define RG_USB20_REFCK_SEL_U3_OFST (26)
1679 +#define RG_PCIE_REFCK_DIV4_PE2D_OFST (25)
1680 +#define RG_PCIE_REFCK_DIV4_PE2H_OFST (24)
1681 +#define RG_PCIE_REFCK_DIV4_PE1D_OFST (18)
1682 +#define RG_PCIE_REFCK_DIV4_PE1H_OFST (17)
1683 +#define RG_PCIE_REFCK_DIV4_U3_OFST (16)
1684 +#define RG_PCIE_MODE_PE2D_OFST (8)
1685 +#define RG_PCIE_MODE_PE2H_OFST (3)
1686 +#define RG_PCIE_MODE_PE1D_OFST (2)
1687 +#define RG_PCIE_MODE_PE1H_OFST (1)
1688 +#define RG_PCIE_MODE_U3_OFST (0)
1689 +
1690 +//U3D_reg4
1691 +#define RG_SSUSB_PLL_DIVEN_PE2D_OFST (22)
1692 +#define RG_SSUSB_PLL_DIVEN_PE2H_OFST (19)
1693 +#define RG_SSUSB_PLL_DIVEN_PE1D_OFST (16)
1694 +#define RG_SSUSB_PLL_DIVEN_PE1H_OFST (13)
1695 +#define RG_SSUSB_PLL_DIVEN_U3_OFST (10)
1696 +#define RG_SSUSB_PLL_BC_PE2D_OFST (8)
1697 +#define RG_SSUSB_PLL_BC_PE2H_OFST (6)
1698 +#define RG_SSUSB_PLL_BC_PE1D_OFST (4)
1699 +#define RG_SSUSB_PLL_BC_PE1H_OFST (2)
1700 +#define RG_SSUSB_PLL_BC_U3_OFST (0)
1701 +
1702 +//U3D_reg5
1703 +#define RG_SSUSB_PLL_BR_PE2D_OFST (27)
1704 +#define RG_SSUSB_PLL_BR_PE2H_OFST (24)
1705 +#define RG_SSUSB_PLL_BR_PE1D_OFST (21)
1706 +#define RG_SSUSB_PLL_BR_PE1H_OFST (18)
1707 +#define RG_SSUSB_PLL_BR_U3_OFST (15)
1708 +#define RG_SSUSB_PLL_IC_PE2D_OFST (12)
1709 +#define RG_SSUSB_PLL_IC_PE2H_OFST (9)
1710 +#define RG_SSUSB_PLL_IC_PE1D_OFST (6)
1711 +#define RG_SSUSB_PLL_IC_PE1H_OFST (3)
1712 +#define RG_SSUSB_PLL_IC_U3_OFST (0)
1713 +
1714 +//U3D_reg6
1715 +#define RG_SSUSB_PLL_IR_PE2D_OFST (24)
1716 +#define RG_SSUSB_PLL_IR_PE2H_OFST (16)
1717 +#define RG_SSUSB_PLL_IR_PE1D_OFST (8)
1718 +#define RG_SSUSB_PLL_IR_PE1H_OFST (4)
1719 +#define RG_SSUSB_PLL_IR_U3_OFST (0)
1720 +
1721 +//U3D_reg7
1722 +#define RG_SSUSB_PLL_BP_PE2D_OFST (24)
1723 +#define RG_SSUSB_PLL_BP_PE2H_OFST (16)
1724 +#define RG_SSUSB_PLL_BP_PE1D_OFST (8)
1725 +#define RG_SSUSB_PLL_BP_PE1H_OFST (4)
1726 +#define RG_SSUSB_PLL_BP_U3_OFST (0)
1727 +
1728 +//U3D_reg8
1729 +#define RG_SSUSB_PLL_FBKSEL_PE2D_OFST (24)
1730 +#define RG_SSUSB_PLL_FBKSEL_PE2H_OFST (16)
1731 +#define RG_SSUSB_PLL_FBKSEL_PE1D_OFST (8)
1732 +#define RG_SSUSB_PLL_FBKSEL_PE1H_OFST (2)
1733 +#define RG_SSUSB_PLL_FBKSEL_U3_OFST (0)
1734 +
1735 +//U3D_reg9
1736 +#define RG_SSUSB_PLL_FBKDIV_PE2H_OFST (24)
1737 +#define RG_SSUSB_PLL_FBKDIV_PE1D_OFST (16)
1738 +#define RG_SSUSB_PLL_FBKDIV_PE1H_OFST (8)
1739 +#define RG_SSUSB_PLL_FBKDIV_U3_OFST (0)
1740 +
1741 +//U3D_reg10
1742 +#define RG_SSUSB_PLL_PREDIV_PE2D_OFST (26)
1743 +#define RG_SSUSB_PLL_PREDIV_PE2H_OFST (24)
1744 +#define RG_SSUSB_PLL_PREDIV_PE1D_OFST (18)
1745 +#define RG_SSUSB_PLL_PREDIV_PE1H_OFST (16)
1746 +#define RG_SSUSB_PLL_PREDIV_U3_OFST (8)
1747 +#define RG_SSUSB_PLL_FBKDIV_PE2D_OFST (0)
1748 +
1749 +//U3D_reg12
1750 +#define RG_SSUSB_PLL_PCW_NCPO_U3_OFST (0)
1751 +
1752 +//U3D_reg13
1753 +#define RG_SSUSB_PLL_PCW_NCPO_PE1H_OFST (0)
1754 +
1755 +//U3D_reg14
1756 +#define RG_SSUSB_PLL_PCW_NCPO_PE1D_OFST (0)
1757 +
1758 +//U3D_reg15
1759 +#define RG_SSUSB_PLL_PCW_NCPO_PE2H_OFST (0)
1760 +
1761 +//U3D_reg16
1762 +#define RG_SSUSB_PLL_PCW_NCPO_PE2D_OFST (0)
1763 +
1764 +//U3D_reg19
1765 +#define RG_SSUSB_PLL_SSC_DELTA1_PE1H_OFST (16)
1766 +#define RG_SSUSB_PLL_SSC_DELTA1_U3_OFST (0)
1767 +
1768 +//U3D_reg20
1769 +#define RG_SSUSB_PLL_SSC_DELTA1_PE2H_OFST (16)
1770 +#define RG_SSUSB_PLL_SSC_DELTA1_PE1D_OFST (0)
1771 +
1772 +//U3D_reg21
1773 +#define RG_SSUSB_PLL_SSC_DELTA_U3_OFST (16)
1774 +#define RG_SSUSB_PLL_SSC_DELTA1_PE2D_OFST (0)
1775 +
1776 +//U3D_reg23
1777 +#define RG_SSUSB_PLL_SSC_DELTA_PE1D_OFST (16)
1778 +#define RG_SSUSB_PLL_SSC_DELTA_PE1H_OFST (0)
1779 +
1780 +//U3D_reg25
1781 +#define RG_SSUSB_PLL_SSC_DELTA_PE2D_OFST (16)
1782 +#define RG_SSUSB_PLL_SSC_DELTA_PE2H_OFST (0)
1783 +
1784 +//U3D_reg26
1785 +#define RG_SSUSB_PLL_REFCKDIV_PE2D_OFST (25)
1786 +#define RG_SSUSB_PLL_REFCKDIV_PE2H_OFST (24)
1787 +#define RG_SSUSB_PLL_REFCKDIV_PE1D_OFST (16)
1788 +#define RG_SSUSB_PLL_REFCKDIV_PE1H_OFST (8)
1789 +#define RG_SSUSB_PLL_REFCKDIV_U3_OFST (0)
1790 +
1791 +//U3D_reg28
1792 +#define RG_SSUSB_CDR_BPA_PE2D_OFST (24)
1793 +#define RG_SSUSB_CDR_BPA_PE2H_OFST (16)
1794 +#define RG_SSUSB_CDR_BPA_PE1D_OFST (10)
1795 +#define RG_SSUSB_CDR_BPA_PE1H_OFST (8)
1796 +#define RG_SSUSB_CDR_BPA_U3_OFST (0)
1797 +
1798 +//U3D_reg29
1799 +#define RG_SSUSB_CDR_BPB_PE2D_OFST (24)
1800 +#define RG_SSUSB_CDR_BPB_PE2H_OFST (16)
1801 +#define RG_SSUSB_CDR_BPB_PE1D_OFST (6)
1802 +#define RG_SSUSB_CDR_BPB_PE1H_OFST (3)
1803 +#define RG_SSUSB_CDR_BPB_U3_OFST (0)
1804 +
1805 +//U3D_reg30
1806 +#define RG_SSUSB_CDR_BR_PE2D_OFST (24)
1807 +#define RG_SSUSB_CDR_BR_PE2H_OFST (16)
1808 +#define RG_SSUSB_CDR_BR_PE1D_OFST (6)
1809 +#define RG_SSUSB_CDR_BR_PE1H_OFST (3)
1810 +#define RG_SSUSB_CDR_BR_U3_OFST (0)
1811 +
1812 +//U3D_reg31
1813 +#define RG_SSUSB_CDR_FBDIV_PE2H_OFST (24)
1814 +#define RG_SSUSB_CDR_FBDIV_PE1D_OFST (16)
1815 +#define RG_SSUSB_CDR_FBDIV_PE1H_OFST (8)
1816 +#define RG_SSUSB_CDR_FBDIV_U3_OFST (0)
1817 +
1818 +//U3D_reg32
1819 +#define RG_SSUSB_EQ_RSTEP1_PE2D_OFST (30)
1820 +#define RG_SSUSB_EQ_RSTEP1_PE2H_OFST (28)
1821 +#define RG_SSUSB_EQ_RSTEP1_PE1D_OFST (26)
1822 +#define RG_SSUSB_EQ_RSTEP1_PE1H_OFST (24)
1823 +#define RG_SSUSB_EQ_RSTEP1_U3_OFST (22)
1824 +#define RG_SSUSB_LFPS_DEGLITCH_PE2D_OFST (20)
1825 +#define RG_SSUSB_LFPS_DEGLITCH_PE2H_OFST (18)
1826 +#define RG_SSUSB_LFPS_DEGLITCH_PE1D_OFST (16)
1827 +#define RG_SSUSB_LFPS_DEGLITCH_PE1H_OFST (14)
1828 +#define RG_SSUSB_LFPS_DEGLITCH_U3_OFST (12)
1829 +#define RG_SSUSB_CDR_KVSEL_PE2D_OFST (11)
1830 +#define RG_SSUSB_CDR_KVSEL_PE2H_OFST (10)
1831 +#define RG_SSUSB_CDR_KVSEL_PE1D_OFST (9)
1832 +#define RG_SSUSB_CDR_KVSEL_PE1H_OFST (8)
1833 +#define RG_SSUSB_CDR_KVSEL_U3_OFST (7)
1834 +#define RG_SSUSB_CDR_FBDIV_PE2D_OFST (0)
1835 +
1836 +//U3D_reg33
1837 +#define RG_SSUSB_RX_CMPWD_PE2D_OFST (26)
1838 +#define RG_SSUSB_RX_CMPWD_PE2H_OFST (25)
1839 +#define RG_SSUSB_RX_CMPWD_PE1D_OFST (24)
1840 +#define RG_SSUSB_RX_CMPWD_PE1H_OFST (23)
1841 +#define RG_SSUSB_RX_CMPWD_U3_OFST (16)
1842 +#define RG_SSUSB_EQ_RSTEP2_PE2D_OFST (8)
1843 +#define RG_SSUSB_EQ_RSTEP2_PE2H_OFST (6)
1844 +#define RG_SSUSB_EQ_RSTEP2_PE1D_OFST (4)
1845 +#define RG_SSUSB_EQ_RSTEP2_PE1H_OFST (2)
1846 +#define RG_SSUSB_EQ_RSTEP2_U3_OFST (0)
1847 +
1848 +
1849 +///////////////////////////////////////////////////////////////////////////////
1850 +
1851 +struct u3phyd_reg {
1852 + //0x0
1853 + PHY_LE32 phyd_mix0;
1854 + PHY_LE32 phyd_mix1;
1855 + PHY_LE32 phyd_lfps0;
1856 + PHY_LE32 phyd_lfps1;
1857 + //0x10
1858 + PHY_LE32 phyd_impcal0;
1859 + PHY_LE32 phyd_impcal1;
1860 + PHY_LE32 phyd_txpll0;
1861 + PHY_LE32 phyd_txpll1;
1862 + //0x20
1863 + PHY_LE32 phyd_txpll2;
1864 + PHY_LE32 phyd_fl0;
1865 + PHY_LE32 phyd_mix2;
1866 + PHY_LE32 phyd_rx0;
1867 + //0x30
1868 + PHY_LE32 phyd_t2rlb;
1869 + PHY_LE32 phyd_cppat;
1870 + PHY_LE32 phyd_mix3;
1871 + PHY_LE32 phyd_ebufctl;
1872 + //0x40
1873 + PHY_LE32 phyd_pipe0;
1874 + PHY_LE32 phyd_pipe1;
1875 + PHY_LE32 phyd_mix4;
1876 + PHY_LE32 phyd_ckgen0;
1877 + //0x50
1878 + PHY_LE32 phyd_mix5;
1879 + PHY_LE32 phyd_reserved;
1880 + PHY_LE32 phyd_cdr0;
1881 + PHY_LE32 phyd_cdr1;
1882 + //0x60
1883 + PHY_LE32 phyd_pll_0;
1884 + PHY_LE32 phyd_pll_1;
1885 + PHY_LE32 phyd_bcn_det_1;
1886 + PHY_LE32 phyd_bcn_det_2;
1887 + //0x70
1888 + PHY_LE32 eq0;
1889 + PHY_LE32 eq1;
1890 + PHY_LE32 eq2;
1891 + PHY_LE32 eq3;
1892 + //0x80
1893 + PHY_LE32 eq_eye0;
1894 + PHY_LE32 eq_eye1;
1895 + PHY_LE32 eq_eye2;
1896 + PHY_LE32 eq_dfe0;
1897 + //0x90
1898 + PHY_LE32 eq_dfe1;
1899 + PHY_LE32 eq_dfe2;
1900 + PHY_LE32 eq_dfe3;
1901 + PHY_LE32 reserve0;
1902 + //0xa0
1903 + PHY_LE32 phyd_mon0;
1904 + PHY_LE32 phyd_mon1;
1905 + PHY_LE32 phyd_mon2;
1906 + PHY_LE32 phyd_mon3;
1907 + //0xb0
1908 + PHY_LE32 phyd_mon4;
1909 + PHY_LE32 phyd_mon5;
1910 + PHY_LE32 phyd_mon6;
1911 + PHY_LE32 phyd_mon7;
1912 + //0xc0
1913 + PHY_LE32 phya_rx_mon0;
1914 + PHY_LE32 phya_rx_mon1;
1915 + PHY_LE32 phya_rx_mon2;
1916 + PHY_LE32 phya_rx_mon3;
1917 + //0xd0
1918 + PHY_LE32 phya_rx_mon4;
1919 + PHY_LE32 phya_rx_mon5;
1920 + PHY_LE32 phyd_cppat2;
1921 + PHY_LE32 eq_eye3;
1922 + //0xe0
1923 + PHY_LE32 kband_out;
1924 + PHY_LE32 kband_out1;
1925 +};
1926 +
1927 +//U3D_PHYD_MIX0
1928 +#define RG_SSUSB_P_P3_TX_NG (0x1<<31) //31:31
1929 +#define RG_SSUSB_TSEQ_EN (0x1<<30) //30:30
1930 +#define RG_SSUSB_TSEQ_POLEN (0x1<<29) //29:29
1931 +#define RG_SSUSB_TSEQ_POL (0x1<<28) //28:28
1932 +#define RG_SSUSB_P_P3_PCLK_NG (0x1<<27) //27:27
1933 +#define RG_SSUSB_TSEQ_TH (0x7<<24) //26:24
1934 +#define RG_SSUSB_PRBS_BERTH (0xff<<16) //23:16
1935 +#define RG_SSUSB_DISABLE_PHY_U2_ON (0x1<<15) //15:15
1936 +#define RG_SSUSB_DISABLE_PHY_U2_OFF (0x1<<14) //14:14
1937 +#define RG_SSUSB_PRBS_EN (0x1<<13) //13:13
1938 +#define RG_SSUSB_BPSLOCK (0x1<<12) //12:12
1939 +#define RG_SSUSB_RTCOMCNT (0xf<<8) //11:8
1940 +#define RG_SSUSB_COMCNT (0xf<<4) //7:4
1941 +#define RG_SSUSB_PRBSEL_CALIB (0xf<<0) //3:0
1942 +
1943 +//U3D_PHYD_MIX1
1944 +#define RG_SSUSB_SLEEP_EN (0x1<<31) //31:31
1945 +#define RG_SSUSB_PRBSEL_PCS (0x7<<28) //30:28
1946 +#define RG_SSUSB_TXLFPS_PRD (0xf<<24) //27:24
1947 +#define RG_SSUSB_P_RX_P0S_CK (0x1<<23) //23:23
1948 +#define RG_SSUSB_P_TX_P0S_CK (0x1<<22) //22:22
1949 +#define RG_SSUSB_PDNCTL (0x3f<<16) //21:16
1950 +#define RG_SSUSB_TX_DRV_EN (0x1<<15) //15:15
1951 +#define RG_SSUSB_TX_DRV_SEL (0x1<<14) //14:14
1952 +#define RG_SSUSB_TX_DRV_DLY (0x3f<<8) //13:8
1953 +#define RG_SSUSB_BERT_EN (0x1<<7) //7:7
1954 +#define RG_SSUSB_SCP_TH (0x7<<4) //6:4
1955 +#define RG_SSUSB_SCP_EN (0x1<<3) //3:3
1956 +#define RG_SSUSB_RXANSIDEC_TEST (0x7<<0) //2:0
1957 +
1958 +//U3D_PHYD_LFPS0
1959 +#define RG_SSUSB_LFPS_PWD (0x1<<30) //30:30
1960 +#define RG_SSUSB_FORCE_LFPS_PWD (0x1<<29) //29:29
1961 +#define RG_SSUSB_RXLFPS_OVF (0x1f<<24) //28:24
1962 +#define RG_SSUSB_P3_ENTRY_SEL (0x1<<23) //23:23
1963 +#define RG_SSUSB_P3_ENTRY (0x1<<22) //22:22
1964 +#define RG_SSUSB_RXLFPS_CDRSEL (0x3<<20) //21:20
1965 +#define RG_SSUSB_RXLFPS_CDRTH (0xf<<16) //19:16
1966 +#define RG_SSUSB_LOCK5G_BLOCK (0x1<<15) //15:15
1967 +#define RG_SSUSB_TFIFO_EXT_D_SEL (0x1<<14) //14:14
1968 +#define RG_SSUSB_TFIFO_NO_EXTEND (0x1<<13) //13:13
1969 +#define RG_SSUSB_RXLFPS_LOB (0x1f<<8) //12:8
1970 +#define RG_SSUSB_TXLFPS_EN (0x1<<7) //7:7
1971 +#define RG_SSUSB_TXLFPS_SEL (0x1<<6) //6:6
1972 +#define RG_SSUSB_RXLFPS_CDRLOCK (0x1<<5) //5:5
1973 +#define RG_SSUSB_RXLFPS_UPB (0x1f<<0) //4:0
1974 +
1975 +//U3D_PHYD_LFPS1
1976 +#define RG_SSUSB_RX_IMP_BIAS (0xf<<28) //31:28
1977 +#define RG_SSUSB_TX_IMP_BIAS (0xf<<24) //27:24
1978 +#define RG_SSUSB_FWAKE_TH (0x3f<<16) //21:16
1979 +#define RG_SSUSB_RXLFPS_UDF (0x1f<<8) //12:8
1980 +#define RG_SSUSB_RXLFPS_P0IDLETH (0xff<<0) //7:0
1981 +
1982 +//U3D_PHYD_IMPCAL0
1983 +#define RG_SSUSB_FORCE_TX_IMPSEL (0x1<<31) //31:31
1984 +#define RG_SSUSB_TX_IMPCAL_EN (0x1<<30) //30:30
1985 +#define RG_SSUSB_FORCE_TX_IMPCAL_EN (0x1<<29) //29:29
1986 +#define RG_SSUSB_TX_IMPSEL (0x1f<<24) //28:24
1987 +#define RG_SSUSB_TX_IMPCAL_CALCYC (0x3f<<16) //21:16
1988 +#define RG_SSUSB_TX_IMPCAL_STBCYC (0x1f<<10) //14:10
1989 +#define RG_SSUSB_TX_IMPCAL_CYCCNT (0x3ff<<0) //9:0
1990 +
1991 +//U3D_PHYD_IMPCAL1
1992 +#define RG_SSUSB_FORCE_RX_IMPSEL (0x1<<31) //31:31
1993 +#define RG_SSUSB_RX_IMPCAL_EN (0x1<<30) //30:30
1994 +#define RG_SSUSB_FORCE_RX_IMPCAL_EN (0x1<<29) //29:29
1995 +#define RG_SSUSB_RX_IMPSEL (0x1f<<24) //28:24
1996 +#define RG_SSUSB_RX_IMPCAL_CALCYC (0x3f<<16) //21:16
1997 +#define RG_SSUSB_RX_IMPCAL_STBCYC (0x1f<<10) //14:10
1998 +#define RG_SSUSB_RX_IMPCAL_CYCCNT (0x3ff<<0) //9:0
1999 +
2000 +//U3D_PHYD_TXPLL0
2001 +#define RG_SSUSB_TXPLL_DDSEN_CYC (0x1f<<27) //31:27
2002 +#define RG_SSUSB_TXPLL_ON (0x1<<26) //26:26
2003 +#define RG_SSUSB_FORCE_TXPLLON (0x1<<25) //25:25
2004 +#define RG_SSUSB_TXPLL_STBCYC (0x1ff<<16) //24:16
2005 +#define RG_SSUSB_TXPLL_NCPOCHG_CYC (0xf<<12) //15:12
2006 +#define RG_SSUSB_TXPLL_NCPOEN_CYC (0x3<<10) //11:10
2007 +#define RG_SSUSB_TXPLL_DDSRSTB_CYC (0x7<<0) //2:0
2008 +
2009 +//U3D_PHYD_TXPLL1
2010 +#define RG_SSUSB_PLL_NCPO_EN (0x1<<31) //31:31
2011 +#define RG_SSUSB_PLL_FIFO_START_MAN (0x1<<30) //30:30
2012 +#define RG_SSUSB_PLL_NCPO_CHG (0x1<<28) //28:28
2013 +#define RG_SSUSB_PLL_DDS_RSTB (0x1<<27) //27:27
2014 +#define RG_SSUSB_PLL_DDS_PWDB (0x1<<26) //26:26
2015 +#define RG_SSUSB_PLL_DDSEN (0x1<<25) //25:25
2016 +#define RG_SSUSB_PLL_AUTOK_VCO (0x1<<24) //24:24
2017 +#define RG_SSUSB_PLL_PWD (0x1<<23) //23:23
2018 +#define RG_SSUSB_RX_AFE_PWD (0x1<<22) //22:22
2019 +#define RG_SSUSB_PLL_TCADJ (0x3f<<16) //21:16
2020 +#define RG_SSUSB_FORCE_CDR_TCADJ (0x1<<15) //15:15
2021 +#define RG_SSUSB_FORCE_CDR_AUTOK_VCO (0x1<<14) //14:14
2022 +#define RG_SSUSB_FORCE_CDR_PWD (0x1<<13) //13:13
2023 +#define RG_SSUSB_FORCE_PLL_NCPO_EN (0x1<<12) //12:12
2024 +#define RG_SSUSB_FORCE_PLL_FIFO_START_MAN (0x1<<11) //11:11
2025 +#define RG_SSUSB_FORCE_PLL_NCPO_CHG (0x1<<9) //9:9
2026 +#define RG_SSUSB_FORCE_PLL_DDS_RSTB (0x1<<8) //8:8
2027 +#define RG_SSUSB_FORCE_PLL_DDS_PWDB (0x1<<7) //7:7
2028 +#define RG_SSUSB_FORCE_PLL_DDSEN (0x1<<6) //6:6
2029 +#define RG_SSUSB_FORCE_PLL_TCADJ (0x1<<5) //5:5
2030 +#define RG_SSUSB_FORCE_PLL_AUTOK_VCO (0x1<<4) //4:4
2031 +#define RG_SSUSB_FORCE_PLL_PWD (0x1<<3) //3:3
2032 +#define RG_SSUSB_FLT_1_DISPERR_B (0x1<<2) //2:2
2033 +
2034 +//U3D_PHYD_TXPLL2
2035 +#define RG_SSUSB_TX_LFPS_EN (0x1<<31) //31:31
2036 +#define RG_SSUSB_FORCE_TX_LFPS_EN (0x1<<30) //30:30
2037 +#define RG_SSUSB_TX_LFPS (0x1<<29) //29:29
2038 +#define RG_SSUSB_FORCE_TX_LFPS (0x1<<28) //28:28
2039 +#define RG_SSUSB_RXPLL_STB (0x1<<27) //27:27
2040 +#define RG_SSUSB_TXPLL_STB (0x1<<26) //26:26
2041 +#define RG_SSUSB_FORCE_RXPLL_STB (0x1<<25) //25:25
2042 +#define RG_SSUSB_FORCE_TXPLL_STB (0x1<<24) //24:24
2043 +#define RG_SSUSB_RXPLL_REFCKSEL (0x1<<16) //16:16
2044 +#define RG_SSUSB_RXPLL_STBMODE (0x1<<11) //11:11
2045 +#define RG_SSUSB_RXPLL_ON (0x1<<10) //10:10
2046 +#define RG_SSUSB_FORCE_RXPLLON (0x1<<9) //9:9
2047 +#define RG_SSUSB_FORCE_RX_AFE_PWD (0x1<<8) //8:8
2048 +#define RG_SSUSB_CDR_AUTOK_VCO (0x1<<7) //7:7
2049 +#define RG_SSUSB_CDR_PWD (0x1<<6) //6:6
2050 +#define RG_SSUSB_CDR_TCADJ (0x3f<<0) //5:0
2051 +
2052 +//U3D_PHYD_FL0
2053 +#define RG_SSUSB_RX_FL_TARGET (0xffff<<16) //31:16
2054 +#define RG_SSUSB_RX_FL_CYCLECNT (0xffff<<0) //15:0
2055 +
2056 +//U3D_PHYD_MIX2
2057 +#define RG_SSUSB_RX_EQ_RST (0x1<<31) //31:31
2058 +#define RG_SSUSB_RX_EQ_RST_SEL (0x1<<30) //30:30
2059 +#define RG_SSUSB_RXVAL_RST (0x1<<29) //29:29
2060 +#define RG_SSUSB_RXVAL_CNT (0x1f<<24) //28:24
2061 +#define RG_SSUSB_CDROS_EN (0x1<<18) //18:18
2062 +#define RG_SSUSB_CDR_LCKOP (0x3<<16) //17:16
2063 +#define RG_SSUSB_RX_FL_LOCKTH (0xf<<8) //11:8
2064 +#define RG_SSUSB_RX_FL_OFFSET (0xff<<0) //7:0
2065 +
2066 +//U3D_PHYD_RX0
2067 +#define RG_SSUSB_T2RLB_BERTH (0xff<<24) //31:24
2068 +#define RG_SSUSB_T2RLB_PAT (0xff<<16) //23:16
2069 +#define RG_SSUSB_T2RLB_EN (0x1<<15) //15:15
2070 +#define RG_SSUSB_T2RLB_BPSCRAMB (0x1<<14) //14:14
2071 +#define RG_SSUSB_T2RLB_SERIAL (0x1<<13) //13:13
2072 +#define RG_SSUSB_T2RLB_MODE (0x3<<11) //12:11
2073 +#define RG_SSUSB_RX_SAOSC_EN (0x1<<10) //10:10
2074 +#define RG_SSUSB_RX_SAOSC_EN_SEL (0x1<<9) //9:9
2075 +#define RG_SSUSB_RX_DFE_OPTION (0x1<<8) //8:8
2076 +#define RG_SSUSB_RX_DFE_EN (0x1<<7) //7:7
2077 +#define RG_SSUSB_RX_DFE_EN_SEL (0x1<<6) //6:6
2078 +#define RG_SSUSB_RX_EQ_EN (0x1<<5) //5:5
2079 +#define RG_SSUSB_RX_EQ_EN_SEL (0x1<<4) //4:4
2080 +#define RG_SSUSB_RX_SAOSC_RST (0x1<<3) //3:3
2081 +#define RG_SSUSB_RX_SAOSC_RST_SEL (0x1<<2) //2:2
2082 +#define RG_SSUSB_RX_DFE_RST (0x1<<1) //1:1
2083 +#define RG_SSUSB_RX_DFE_RST_SEL (0x1<<0) //0:0
2084 +
2085 +//U3D_PHYD_T2RLB
2086 +#define RG_SSUSB_EQTRAIN_CH_MODE (0x1<<28) //28:28
2087 +#define RG_SSUSB_PRB_OUT_CPPAT (0x1<<27) //27:27
2088 +#define RG_SSUSB_BPANSIENC (0x1<<26) //26:26
2089 +#define RG_SSUSB_VALID_EN (0x1<<25) //25:25
2090 +#define RG_SSUSB_EBUF_SRST (0x1<<24) //24:24
2091 +#define RG_SSUSB_K_EMP (0xf<<20) //23:20
2092 +#define RG_SSUSB_K_FUL (0xf<<16) //19:16
2093 +#define RG_SSUSB_T2RLB_BDATRST (0xf<<12) //15:12
2094 +#define RG_SSUSB_P_T2RLB_SKP_EN (0x1<<10) //10:10
2095 +#define RG_SSUSB_T2RLB_PATMODE (0x3<<8) //9:8
2096 +#define RG_SSUSB_T2RLB_TSEQCNT (0xff<<0) //7:0
2097 +
2098 +//U3D_PHYD_CPPAT
2099 +#define RG_SSUSB_CPPAT_PROGRAM_EN (0x1<<24) //24:24
2100 +#define RG_SSUSB_CPPAT_TOZ (0x3<<21) //22:21
2101 +#define RG_SSUSB_CPPAT_PRBS_EN (0x1<<20) //20:20
2102 +#define RG_SSUSB_CPPAT_OUT_TMP2 (0xf<<16) //19:16
2103 +#define RG_SSUSB_CPPAT_OUT_TMP1 (0xff<<8) //15:8
2104 +#define RG_SSUSB_CPPAT_OUT_TMP0 (0xff<<0) //7:0
2105 +
2106 +//U3D_PHYD_MIX3
2107 +#define RG_SSUSB_CDR_TCADJ_MINUS (0x1<<31) //31:31
2108 +#define RG_SSUSB_P_CDROS_EN (0x1<<30) //30:30
2109 +#define RG_SSUSB_P_P2_TX_DRV_DIS (0x1<<28) //28:28
2110 +#define RG_SSUSB_CDR_TCADJ_OFFSET (0x7<<24) //26:24
2111 +#define RG_SSUSB_PLL_TCADJ_MINUS (0x1<<23) //23:23
2112 +#define RG_SSUSB_FORCE_PLL_BIAS_LPF_EN (0x1<<20) //20:20
2113 +#define RG_SSUSB_PLL_BIAS_LPF_EN (0x1<<19) //19:19
2114 +#define RG_SSUSB_PLL_TCADJ_OFFSET (0x7<<16) //18:16
2115 +#define RG_SSUSB_FORCE_PLL_SSCEN (0x1<<15) //15:15
2116 +#define RG_SSUSB_PLL_SSCEN (0x1<<14) //14:14
2117 +#define RG_SSUSB_FORCE_CDR_PI_PWD (0x1<<13) //13:13
2118 +#define RG_SSUSB_CDR_PI_PWD (0x1<<12) //12:12
2119 +#define RG_SSUSB_CDR_PI_MODE (0x1<<11) //11:11
2120 +#define RG_SSUSB_TXPLL_SSCEN_CYC (0x3ff<<0) //9:0
2121 +
2122 +//U3D_PHYD_EBUFCTL
2123 +#define RG_SSUSB_EBUFCTL (0xffffffff<<0) //31:0
2124 +
2125 +//U3D_PHYD_PIPE0
2126 +#define RG_SSUSB_RXTERMINATION (0x1<<30) //30:30
2127 +#define RG_SSUSB_RXEQTRAINING (0x1<<29) //29:29
2128 +#define RG_SSUSB_RXPOLARITY (0x1<<28) //28:28
2129 +#define RG_SSUSB_TXDEEMPH (0x3<<26) //27:26
2130 +#define RG_SSUSB_POWERDOWN (0x3<<24) //25:24
2131 +#define RG_SSUSB_TXONESZEROS (0x1<<23) //23:23
2132 +#define RG_SSUSB_TXELECIDLE (0x1<<22) //22:22
2133 +#define RG_SSUSB_TXDETECTRX (0x1<<21) //21:21
2134 +#define RG_SSUSB_PIPE_SEL (0x1<<20) //20:20
2135 +#define RG_SSUSB_TXDATAK (0xf<<16) //19:16
2136 +#define RG_SSUSB_CDR_STABLE_SEL (0x1<<15) //15:15
2137 +#define RG_SSUSB_CDR_STABLE (0x1<<14) //14:14
2138 +#define RG_SSUSB_CDR_RSTB_SEL (0x1<<13) //13:13
2139 +#define RG_SSUSB_CDR_RSTB (0x1<<12) //12:12
2140 +#define RG_SSUSB_P_ERROR_SEL (0x3<<4) //5:4
2141 +#define RG_SSUSB_TXMARGIN (0x7<<1) //3:1
2142 +#define RG_SSUSB_TXCOMPLIANCE (0x1<<0) //0:0
2143 +
2144 +//U3D_PHYD_PIPE1
2145 +#define RG_SSUSB_TXDATA (0xffffffff<<0) //31:0
2146 +
2147 +//U3D_PHYD_MIX4
2148 +#define RG_SSUSB_CDROS_CNT (0x3f<<24) //29:24
2149 +#define RG_SSUSB_T2RLB_BER_EN (0x1<<16) //16:16
2150 +#define RG_SSUSB_T2RLB_BER_RATE (0xffff<<0) //15:0
2151 +
2152 +//U3D_PHYD_CKGEN0
2153 +#define RG_SSUSB_RFIFO_IMPLAT (0x1<<27) //27:27
2154 +#define RG_SSUSB_TFIFO_PSEL (0x7<<24) //26:24
2155 +#define RG_SSUSB_CKGEN_PSEL (0x3<<8) //9:8
2156 +#define RG_SSUSB_RXCK_INV (0x1<<0) //0:0
2157 +
2158 +//U3D_PHYD_MIX5
2159 +#define RG_SSUSB_PRB_SEL (0xffff<<16) //31:16
2160 +#define RG_SSUSB_RXPLL_STBCYC (0x7ff<<0) //10:0
2161 +
2162 +//U3D_PHYD_RESERVED
2163 +#define RG_SSUSB_PHYD_RESERVE (0xffffffff<<0) //31:0
2164 +//#define RG_SSUSB_RX_SIGDET_SEL (0x1<<11)
2165 +//#define RG_SSUSB_RX_SIGDET_EN (0x1<<12)
2166 +//#define RG_SSUSB_RX_PI_CAL_MANUAL_SEL (0x1<<9)
2167 +//#define RG_SSUSB_RX_PI_CAL_MANUAL_EN (0x1<<10)
2168 +
2169 +//U3D_PHYD_CDR0
2170 +#define RG_SSUSB_CDR_BIC_LTR (0xf<<28) //31:28
2171 +#define RG_SSUSB_CDR_BIC_LTD0 (0xf<<24) //27:24
2172 +#define RG_SSUSB_CDR_BC_LTD1 (0x1f<<16) //20:16
2173 +#define RG_SSUSB_CDR_BC_LTR (0x1f<<8) //12:8
2174 +#define RG_SSUSB_CDR_BC_LTD0 (0x1f<<0) //4:0
2175 +
2176 +//U3D_PHYD_CDR1
2177 +#define RG_SSUSB_CDR_BIR_LTD1 (0x1f<<24) //28:24
2178 +#define RG_SSUSB_CDR_BIR_LTR (0x1f<<16) //20:16
2179 +#define RG_SSUSB_CDR_BIR_LTD0 (0x1f<<8) //12:8
2180 +#define RG_SSUSB_CDR_BW_SEL (0x3<<6) //7:6
2181 +#define RG_SSUSB_CDR_BIC_LTD1 (0xf<<0) //3:0
2182 +
2183 +//U3D_PHYD_PLL_0
2184 +#define RG_SSUSB_FORCE_CDR_BAND_5G (0x1<<28) //28:28
2185 +#define RG_SSUSB_FORCE_CDR_BAND_2P5G (0x1<<27) //27:27
2186 +#define RG_SSUSB_FORCE_PLL_BAND_5G (0x1<<26) //26:26
2187 +#define RG_SSUSB_FORCE_PLL_BAND_2P5G (0x1<<25) //25:25
2188 +#define RG_SSUSB_P_EQ_T_SEL (0x3ff<<15) //24:15
2189 +#define RG_SSUSB_PLL_ISO_EN_CYC (0x3ff<<5) //14:5
2190 +#define RG_SSUSB_PLLBAND_RECAL (0x1<<4) //4:4
2191 +#define RG_SSUSB_PLL_DDS_ISO_EN (0x1<<3) //3:3
2192 +#define RG_SSUSB_FORCE_PLL_DDS_ISO_EN (0x1<<2) //2:2
2193 +#define RG_SSUSB_PLL_DDS_PWR_ON (0x1<<1) //1:1
2194 +#define RG_SSUSB_FORCE_PLL_DDS_PWR_ON (0x1<<0) //0:0
2195 +
2196 +//U3D_PHYD_PLL_1
2197 +#define RG_SSUSB_CDR_BAND_5G (0xff<<24) //31:24
2198 +#define RG_SSUSB_CDR_BAND_2P5G (0xff<<16) //23:16
2199 +#define RG_SSUSB_PLL_BAND_5G (0xff<<8) //15:8
2200 +#define RG_SSUSB_PLL_BAND_2P5G (0xff<<0) //7:0
2201 +
2202 +//U3D_PHYD_BCN_DET_1
2203 +#define RG_SSUSB_P_BCN_OBS_PRD (0xffff<<16) //31:16
2204 +#define RG_SSUSB_U_BCN_OBS_PRD (0xffff<<0) //15:0
2205 +
2206 +//U3D_PHYD_BCN_DET_2
2207 +#define RG_SSUSB_P_BCN_OBS_SEL (0xfff<<16) //27:16
2208 +#define RG_SSUSB_BCN_DET_DIS (0x1<<12) //12:12
2209 +#define RG_SSUSB_U_BCN_OBS_SEL (0xfff<<0) //11:0
2210 +
2211 +//U3D_EQ0
2212 +#define RG_SSUSB_EQ_DLHL_LFI (0x7f<<24) //30:24
2213 +#define RG_SSUSB_EQ_DHHL_LFI (0x7f<<16) //22:16
2214 +#define RG_SSUSB_EQ_DD0HOS_LFI (0x7f<<8) //14:8
2215 +#define RG_SSUSB_EQ_DD0LOS_LFI (0x7f<<0) //6:0
2216 +
2217 +//U3D_EQ1
2218 +#define RG_SSUSB_EQ_DD1HOS_LFI (0x7f<<24) //30:24
2219 +#define RG_SSUSB_EQ_DD1LOS_LFI (0x7f<<16) //22:16
2220 +#define RG_SSUSB_EQ_DE0OS_LFI (0x7f<<8) //14:8
2221 +#define RG_SSUSB_EQ_DE1OS_LFI (0x7f<<0) //6:0
2222 +
2223 +//U3D_EQ2
2224 +#define RG_SSUSB_EQ_DLHLOS_LFI (0x7f<<24) //30:24
2225 +#define RG_SSUSB_EQ_DHHLOS_LFI (0x7f<<16) //22:16
2226 +#define RG_SSUSB_EQ_STOPTIME (0x1<<14) //14:14
2227 +#define RG_SSUSB_EQ_DHHL_LF_SEL (0x7<<11) //13:11
2228 +#define RG_SSUSB_EQ_DSAOS_LF_SEL (0x7<<8) //10:8
2229 +#define RG_SSUSB_EQ_STARTTIME (0x3<<6) //7:6
2230 +#define RG_SSUSB_EQ_DLEQ_LF_SEL (0x7<<3) //5:3
2231 +#define RG_SSUSB_EQ_DLHL_LF_SEL (0x7<<0) //2:0
2232 +
2233 +//U3D_EQ3
2234 +#define RG_SSUSB_EQ_DLEQ_LFI_GEN2 (0xf<<28) //31:28
2235 +#define RG_SSUSB_EQ_DLEQ_LFI_GEN1 (0xf<<24) //27:24
2236 +#define RG_SSUSB_EQ_DEYE0OS_LFI (0x7f<<16) //22:16
2237 +#define RG_SSUSB_EQ_DEYE1OS_LFI (0x7f<<8) //14:8
2238 +#define RG_SSUSB_EQ_TRI_DET_EN (0x1<<7) //7:7
2239 +#define RG_SSUSB_EQ_TRI_DET_TH (0x7f<<0) //6:0
2240 +
2241 +//U3D_EQ_EYE0
2242 +#define RG_SSUSB_EQ_EYE_XOFFSET (0x7f<<25) //31:25
2243 +#define RG_SSUSB_EQ_EYE_MON_EN (0x1<<24) //24:24
2244 +#define RG_SSUSB_EQ_EYE0_Y (0x7f<<16) //22:16
2245 +#define RG_SSUSB_EQ_EYE1_Y (0x7f<<8) //14:8
2246 +#define RG_SSUSB_EQ_PILPO_ROUT (0x1<<7) //7:7
2247 +#define RG_SSUSB_EQ_PI_KPGAIN (0x7<<4) //6:4
2248 +#define RG_SSUSB_EQ_EYE_CNT_EN (0x1<<3) //3:3
2249 +
2250 +//U3D_EQ_EYE1
2251 +#define RG_SSUSB_EQ_SIGDET (0x7f<<24) //30:24
2252 +#define RG_SSUSB_EQ_EYE_MASK (0x3ff<<7) //16:7
2253 +
2254 +//U3D_EQ_EYE2
2255 +#define RG_SSUSB_EQ_RX500M_CK_SEL (0x1<<31) //31:31
2256 +#define RG_SSUSB_EQ_SD_CNT1 (0x3f<<24) //29:24
2257 +#define RG_SSUSB_EQ_ISIFLAG_SEL (0x3<<22) //23:22
2258 +#define RG_SSUSB_EQ_SD_CNT0 (0x3f<<16) //21:16
2259 +
2260 +//U3D_EQ_DFE0
2261 +#define RG_SSUSB_EQ_LEQMAX (0xf<<28) //31:28
2262 +#define RG_SSUSB_EQ_DFEX_EN (0x1<<27) //27:27
2263 +#define RG_SSUSB_EQ_DFEX_LF_SEL (0x7<<24) //26:24
2264 +#define RG_SSUSB_EQ_CHK_EYE_H (0x1<<23) //23:23
2265 +#define RG_SSUSB_EQ_PIEYE_INI (0x7f<<16) //22:16
2266 +#define RG_SSUSB_EQ_PI90_INI (0x7f<<8) //14:8
2267 +#define RG_SSUSB_EQ_PI0_INI (0x7f<<0) //6:0
2268 +
2269 +//U3D_EQ_DFE1
2270 +#define RG_SSUSB_EQ_REV (0xffff<<16) //31:16
2271 +#define RG_SSUSB_EQ_DFEYEN_DUR (0x7<<12) //14:12
2272 +#define RG_SSUSB_EQ_DFEXEN_DUR (0x7<<8) //10:8
2273 +#define RG_SSUSB_EQ_DFEX_RST (0x1<<7) //7:7
2274 +#define RG_SSUSB_EQ_GATED_RXD_B (0x1<<6) //6:6
2275 +#define RG_SSUSB_EQ_PI90CK_SEL (0x3<<4) //5:4
2276 +#define RG_SSUSB_EQ_DFEX_DIS (0x1<<2) //2:2
2277 +#define RG_SSUSB_EQ_DFEYEN_STOP_DIS (0x1<<1) //1:1
2278 +#define RG_SSUSB_EQ_DFEXEN_SEL (0x1<<0) //0:0
2279 +
2280 +//U3D_EQ_DFE2
2281 +#define RG_SSUSB_EQ_MON_SEL (0x1f<<24) //28:24
2282 +#define RG_SSUSB_EQ_LEQOSC_DLYCNT (0x7<<16) //18:16
2283 +#define RG_SSUSB_EQ_DLEQOS_LFI (0x1f<<8) //12:8
2284 +#define RG_SSUSB_EQ_LEQ_STOP_TO (0x3<<0) //1:0
2285 +
2286 +//U3D_EQ_DFE3
2287 +#define RG_SSUSB_EQ_RESERVED (0xffffffff<<0) //31:0
2288 +
2289 +//U3D_PHYD_MON0
2290 +#define RGS_SSUSB_BERT_BERC (0xffff<<16) //31:16
2291 +#define RGS_SSUSB_LFPS (0xf<<12) //15:12
2292 +#define RGS_SSUSB_TRAINDEC (0x7<<8) //10:8
2293 +#define RGS_SSUSB_SCP_PAT (0xff<<0) //7:0
2294 +
2295 +//U3D_PHYD_MON1
2296 +#define RGS_SSUSB_RX_FL_OUT (0xffff<<0) //15:0
2297 +
2298 +//U3D_PHYD_MON2
2299 +#define RGS_SSUSB_T2RLB_ERRCNT (0xffff<<16) //31:16
2300 +#define RGS_SSUSB_RETRACK (0xf<<12) //15:12
2301 +#define RGS_SSUSB_RXPLL_LOCK (0x1<<10) //10:10
2302 +#define RGS_SSUSB_CDR_VCOCAL_CPLT_D (0x1<<9) //9:9
2303 +#define RGS_SSUSB_PLL_VCOCAL_CPLT_D (0x1<<8) //8:8
2304 +#define RGS_SSUSB_PDNCTL (0xff<<0) //7:0
2305 +
2306 +//U3D_PHYD_MON3
2307 +#define RGS_SSUSB_TSEQ_ERRCNT (0xffff<<16) //31:16
2308 +#define RGS_SSUSB_PRBS_ERRCNT (0xffff<<0) //15:0
2309 +
2310 +//U3D_PHYD_MON4
2311 +#define RGS_SSUSB_RX_LSLOCK_CNT (0xf<<24) //27:24
2312 +#define RGS_SSUSB_SCP_DETCNT (0xff<<16) //23:16
2313 +#define RGS_SSUSB_TSEQ_DETCNT (0xffff<<0) //15:0
2314 +
2315 +//U3D_PHYD_MON5
2316 +#define RGS_SSUSB_EBUFMSG (0xffff<<16) //31:16
2317 +#define RGS_SSUSB_BERT_LOCK (0x1<<15) //15:15
2318 +#define RGS_SSUSB_SCP_DET (0x1<<14) //14:14
2319 +#define RGS_SSUSB_TSEQ_DET (0x1<<13) //13:13
2320 +#define RGS_SSUSB_EBUF_UDF (0x1<<12) //12:12
2321 +#define RGS_SSUSB_EBUF_OVF (0x1<<11) //11:11
2322 +#define RGS_SSUSB_PRBS_PASSTH (0x1<<10) //10:10
2323 +#define RGS_SSUSB_PRBS_PASS (0x1<<9) //9:9
2324 +#define RGS_SSUSB_PRBS_LOCK (0x1<<8) //8:8
2325 +#define RGS_SSUSB_T2RLB_ERR (0x1<<6) //6:6
2326 +#define RGS_SSUSB_T2RLB_PASSTH (0x1<<5) //5:5
2327 +#define RGS_SSUSB_T2RLB_PASS (0x1<<4) //4:4
2328 +#define RGS_SSUSB_T2RLB_LOCK (0x1<<3) //3:3
2329 +#define RGS_SSUSB_RX_IMPCAL_DONE (0x1<<2) //2:2
2330 +#define RGS_SSUSB_TX_IMPCAL_DONE (0x1<<1) //1:1
2331 +#define RGS_SSUSB_RXDETECTED (0x1<<0) //0:0
2332 +
2333 +//U3D_PHYD_MON6
2334 +#define RGS_SSUSB_SIGCAL_DONE (0x1<<30) //30:30
2335 +#define RGS_SSUSB_SIGCAL_CAL_OUT (0x1<<29) //29:29
2336 +#define RGS_SSUSB_SIGCAL_OFFSET (0x1f<<24) //28:24
2337 +#define RGS_SSUSB_RX_IMP_SEL (0x1f<<16) //20:16
2338 +#define RGS_SSUSB_TX_IMP_SEL (0x1f<<8) //12:8
2339 +#define RGS_SSUSB_TFIFO_MSG (0xf<<4) //7:4
2340 +#define RGS_SSUSB_RFIFO_MSG (0xf<<0) //3:0
2341 +
2342 +//U3D_PHYD_MON7
2343 +#define RGS_SSUSB_FT_OUT (0xff<<8) //15:8
2344 +#define RGS_SSUSB_PRB_OUT (0xff<<0) //7:0
2345 +
2346 +//U3D_PHYA_RX_MON0
2347 +#define RGS_SSUSB_EQ_DCLEQ (0xf<<24) //27:24
2348 +#define RGS_SSUSB_EQ_DCD0H (0x7f<<16) //22:16
2349 +#define RGS_SSUSB_EQ_DCD0L (0x7f<<8) //14:8
2350 +#define RGS_SSUSB_EQ_DCD1H (0x7f<<0) //6:0
2351 +
2352 +//U3D_PHYA_RX_MON1
2353 +#define RGS_SSUSB_EQ_DCD1L (0x7f<<24) //30:24
2354 +#define RGS_SSUSB_EQ_DCE0 (0x7f<<16) //22:16
2355 +#define RGS_SSUSB_EQ_DCE1 (0x7f<<8) //14:8
2356 +#define RGS_SSUSB_EQ_DCHHL (0x7f<<0) //6:0
2357 +
2358 +//U3D_PHYA_RX_MON2
2359 +#define RGS_SSUSB_EQ_LEQ_STOP (0x1<<31) //31:31
2360 +#define RGS_SSUSB_EQ_DCLHL (0x7f<<24) //30:24
2361 +#define RGS_SSUSB_EQ_STATUS (0xff<<16) //23:16
2362 +#define RGS_SSUSB_EQ_DCEYE0 (0x7f<<8) //14:8
2363 +#define RGS_SSUSB_EQ_DCEYE1 (0x7f<<0) //6:0
2364 +
2365 +//U3D_PHYA_RX_MON3
2366 +#define RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_0 (0xfffff<<0) //19:0
2367 +
2368 +//U3D_PHYA_RX_MON4
2369 +#define RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_1 (0xfffff<<0) //19:0
2370 +
2371 +//U3D_PHYA_RX_MON5
2372 +#define RGS_SSUSB_EQ_DCLEQOS (0x1f<<8) //12:8
2373 +#define RGS_SSUSB_EQ_EYE_CNT_RDY (0x1<<7) //7:7
2374 +#define RGS_SSUSB_EQ_PILPO (0x7f<<0) //6:0
2375 +
2376 +//U3D_PHYD_CPPAT2
2377 +#define RG_SSUSB_CPPAT_OUT_H_TMP2 (0xf<<16) //19:16
2378 +#define RG_SSUSB_CPPAT_OUT_H_TMP1 (0xff<<8) //15:8
2379 +#define RG_SSUSB_CPPAT_OUT_H_TMP0 (0xff<<0) //7:0
2380 +
2381 +//U3D_EQ_EYE3
2382 +#define RG_SSUSB_EQ_LEQ_SHIFT (0x7<<24) //26:24
2383 +#define RG_SSUSB_EQ_EYE_CNT (0xfffff<<0) //19:0
2384 +
2385 +//U3D_KBAND_OUT
2386 +#define RGS_SSUSB_CDR_BAND_5G (0xff<<24) //31:24
2387 +#define RGS_SSUSB_CDR_BAND_2P5G (0xff<<16) //23:16
2388 +#define RGS_SSUSB_PLL_BAND_5G (0xff<<8) //15:8
2389 +#define RGS_SSUSB_PLL_BAND_2P5G (0xff<<0) //7:0
2390 +
2391 +//U3D_KBAND_OUT1
2392 +#define RGS_SSUSB_CDR_VCOCAL_FAIL (0x1<<24) //24:24
2393 +#define RGS_SSUSB_CDR_VCOCAL_STATE (0xff<<16) //23:16
2394 +#define RGS_SSUSB_PLL_VCOCAL_FAIL (0x1<<8) //8:8
2395 +#define RGS_SSUSB_PLL_VCOCAL_STATE (0xff<<0) //7:0
2396 +
2397 +
2398 +/* OFFSET */
2399 +
2400 +//U3D_PHYD_MIX0
2401 +#define RG_SSUSB_P_P3_TX_NG_OFST (31)
2402 +#define RG_SSUSB_TSEQ_EN_OFST (30)
2403 +#define RG_SSUSB_TSEQ_POLEN_OFST (29)
2404 +#define RG_SSUSB_TSEQ_POL_OFST (28)
2405 +#define RG_SSUSB_P_P3_PCLK_NG_OFST (27)
2406 +#define RG_SSUSB_TSEQ_TH_OFST (24)
2407 +#define RG_SSUSB_PRBS_BERTH_OFST (16)
2408 +#define RG_SSUSB_DISABLE_PHY_U2_ON_OFST (15)
2409 +#define RG_SSUSB_DISABLE_PHY_U2_OFF_OFST (14)
2410 +#define RG_SSUSB_PRBS_EN_OFST (13)
2411 +#define RG_SSUSB_BPSLOCK_OFST (12)
2412 +#define RG_SSUSB_RTCOMCNT_OFST (8)
2413 +#define RG_SSUSB_COMCNT_OFST (4)
2414 +#define RG_SSUSB_PRBSEL_CALIB_OFST (0)
2415 +
2416 +//U3D_PHYD_MIX1
2417 +#define RG_SSUSB_SLEEP_EN_OFST (31)
2418 +#define RG_SSUSB_PRBSEL_PCS_OFST (28)
2419 +#define RG_SSUSB_TXLFPS_PRD_OFST (24)
2420 +#define RG_SSUSB_P_RX_P0S_CK_OFST (23)
2421 +#define RG_SSUSB_P_TX_P0S_CK_OFST (22)
2422 +#define RG_SSUSB_PDNCTL_OFST (16)
2423 +#define RG_SSUSB_TX_DRV_EN_OFST (15)
2424 +#define RG_SSUSB_TX_DRV_SEL_OFST (14)
2425 +#define RG_SSUSB_TX_DRV_DLY_OFST (8)
2426 +#define RG_SSUSB_BERT_EN_OFST (7)
2427 +#define RG_SSUSB_SCP_TH_OFST (4)
2428 +#define RG_SSUSB_SCP_EN_OFST (3)
2429 +#define RG_SSUSB_RXANSIDEC_TEST_OFST (0)
2430 +
2431 +//U3D_PHYD_LFPS0
2432 +#define RG_SSUSB_LFPS_PWD_OFST (30)
2433 +#define RG_SSUSB_FORCE_LFPS_PWD_OFST (29)
2434 +#define RG_SSUSB_RXLFPS_OVF_OFST (24)
2435 +#define RG_SSUSB_P3_ENTRY_SEL_OFST (23)
2436 +#define RG_SSUSB_P3_ENTRY_OFST (22)
2437 +#define RG_SSUSB_RXLFPS_CDRSEL_OFST (20)
2438 +#define RG_SSUSB_RXLFPS_CDRTH_OFST (16)
2439 +#define RG_SSUSB_LOCK5G_BLOCK_OFST (15)
2440 +#define RG_SSUSB_TFIFO_EXT_D_SEL_OFST (14)
2441 +#define RG_SSUSB_TFIFO_NO_EXTEND_OFST (13)
2442 +#define RG_SSUSB_RXLFPS_LOB_OFST (8)
2443 +#define RG_SSUSB_TXLFPS_EN_OFST (7)
2444 +#define RG_SSUSB_TXLFPS_SEL_OFST (6)
2445 +#define RG_SSUSB_RXLFPS_CDRLOCK_OFST (5)
2446 +#define RG_SSUSB_RXLFPS_UPB_OFST (0)
2447 +
2448 +//U3D_PHYD_LFPS1
2449 +#define RG_SSUSB_RX_IMP_BIAS_OFST (28)
2450 +#define RG_SSUSB_TX_IMP_BIAS_OFST (24)
2451 +#define RG_SSUSB_FWAKE_TH_OFST (16)
2452 +#define RG_SSUSB_RXLFPS_UDF_OFST (8)
2453 +#define RG_SSUSB_RXLFPS_P0IDLETH_OFST (0)
2454 +
2455 +//U3D_PHYD_IMPCAL0
2456 +#define RG_SSUSB_FORCE_TX_IMPSEL_OFST (31)
2457 +#define RG_SSUSB_TX_IMPCAL_EN_OFST (30)
2458 +#define RG_SSUSB_FORCE_TX_IMPCAL_EN_OFST (29)
2459 +#define RG_SSUSB_TX_IMPSEL_OFST (24)
2460 +#define RG_SSUSB_TX_IMPCAL_CALCYC_OFST (16)
2461 +#define RG_SSUSB_TX_IMPCAL_STBCYC_OFST (10)
2462 +#define RG_SSUSB_TX_IMPCAL_CYCCNT_OFST (0)
2463 +
2464 +//U3D_PHYD_IMPCAL1
2465 +#define RG_SSUSB_FORCE_RX_IMPSEL_OFST (31)
2466 +#define RG_SSUSB_RX_IMPCAL_EN_OFST (30)
2467 +#define RG_SSUSB_FORCE_RX_IMPCAL_EN_OFST (29)
2468 +#define RG_SSUSB_RX_IMPSEL_OFST (24)
2469 +#define RG_SSUSB_RX_IMPCAL_CALCYC_OFST (16)
2470 +#define RG_SSUSB_RX_IMPCAL_STBCYC_OFST (10)
2471 +#define RG_SSUSB_RX_IMPCAL_CYCCNT_OFST (0)
2472 +
2473 +//U3D_PHYD_TXPLL0
2474 +#define RG_SSUSB_TXPLL_DDSEN_CYC_OFST (27)
2475 +#define RG_SSUSB_TXPLL_ON_OFST (26)
2476 +#define RG_SSUSB_FORCE_TXPLLON_OFST (25)
2477 +#define RG_SSUSB_TXPLL_STBCYC_OFST (16)
2478 +#define RG_SSUSB_TXPLL_NCPOCHG_CYC_OFST (12)
2479 +#define RG_SSUSB_TXPLL_NCPOEN_CYC_OFST (10)
2480 +#define RG_SSUSB_TXPLL_DDSRSTB_CYC_OFST (0)
2481 +
2482 +//U3D_PHYD_TXPLL1
2483 +#define RG_SSUSB_PLL_NCPO_EN_OFST (31)
2484 +#define RG_SSUSB_PLL_FIFO_START_MAN_OFST (30)
2485 +#define RG_SSUSB_PLL_NCPO_CHG_OFST (28)
2486 +#define RG_SSUSB_PLL_DDS_RSTB_OFST (27)
2487 +#define RG_SSUSB_PLL_DDS_PWDB_OFST (26)
2488 +#define RG_SSUSB_PLL_DDSEN_OFST (25)
2489 +#define RG_SSUSB_PLL_AUTOK_VCO_OFST (24)
2490 +#define RG_SSUSB_PLL_PWD_OFST (23)
2491 +#define RG_SSUSB_RX_AFE_PWD_OFST (22)
2492 +#define RG_SSUSB_PLL_TCADJ_OFST (16)
2493 +#define RG_SSUSB_FORCE_CDR_TCADJ_OFST (15)
2494 +#define RG_SSUSB_FORCE_CDR_AUTOK_VCO_OFST (14)
2495 +#define RG_SSUSB_FORCE_CDR_PWD_OFST (13)
2496 +#define RG_SSUSB_FORCE_PLL_NCPO_EN_OFST (12)
2497 +#define RG_SSUSB_FORCE_PLL_FIFO_START_MAN_OFST (11)
2498 +#define RG_SSUSB_FORCE_PLL_NCPO_CHG_OFST (9)
2499 +#define RG_SSUSB_FORCE_PLL_DDS_RSTB_OFST (8)
2500 +#define RG_SSUSB_FORCE_PLL_DDS_PWDB_OFST (7)
2501 +#define RG_SSUSB_FORCE_PLL_DDSEN_OFST (6)
2502 +#define RG_SSUSB_FORCE_PLL_TCADJ_OFST (5)
2503 +#define RG_SSUSB_FORCE_PLL_AUTOK_VCO_OFST (4)
2504 +#define RG_SSUSB_FORCE_PLL_PWD_OFST (3)
2505 +#define RG_SSUSB_FLT_1_DISPERR_B_OFST (2)
2506 +
2507 +//U3D_PHYD_TXPLL2
2508 +#define RG_SSUSB_TX_LFPS_EN_OFST (31)
2509 +#define RG_SSUSB_FORCE_TX_LFPS_EN_OFST (30)
2510 +#define RG_SSUSB_TX_LFPS_OFST (29)
2511 +#define RG_SSUSB_FORCE_TX_LFPS_OFST (28)
2512 +#define RG_SSUSB_RXPLL_STB_OFST (27)
2513 +#define RG_SSUSB_TXPLL_STB_OFST (26)
2514 +#define RG_SSUSB_FORCE_RXPLL_STB_OFST (25)
2515 +#define RG_SSUSB_FORCE_TXPLL_STB_OFST (24)
2516 +#define RG_SSUSB_RXPLL_REFCKSEL_OFST (16)
2517 +#define RG_SSUSB_RXPLL_STBMODE_OFST (11)
2518 +#define RG_SSUSB_RXPLL_ON_OFST (10)
2519 +#define RG_SSUSB_FORCE_RXPLLON_OFST (9)
2520 +#define RG_SSUSB_FORCE_RX_AFE_PWD_OFST (8)
2521 +#define RG_SSUSB_CDR_AUTOK_VCO_OFST (7)
2522 +#define RG_SSUSB_CDR_PWD_OFST (6)
2523 +#define RG_SSUSB_CDR_TCADJ_OFST (0)
2524 +
2525 +//U3D_PHYD_FL0
2526 +#define RG_SSUSB_RX_FL_TARGET_OFST (16)
2527 +#define RG_SSUSB_RX_FL_CYCLECNT_OFST (0)
2528 +
2529 +//U3D_PHYD_MIX2
2530 +#define RG_SSUSB_RX_EQ_RST_OFST (31)
2531 +#define RG_SSUSB_RX_EQ_RST_SEL_OFST (30)
2532 +#define RG_SSUSB_RXVAL_RST_OFST (29)
2533 +#define RG_SSUSB_RXVAL_CNT_OFST (24)
2534 +#define RG_SSUSB_CDROS_EN_OFST (18)
2535 +#define RG_SSUSB_CDR_LCKOP_OFST (16)
2536 +#define RG_SSUSB_RX_FL_LOCKTH_OFST (8)
2537 +#define RG_SSUSB_RX_FL_OFFSET_OFST (0)
2538 +
2539 +//U3D_PHYD_RX0
2540 +#define RG_SSUSB_T2RLB_BERTH_OFST (24)
2541 +#define RG_SSUSB_T2RLB_PAT_OFST (16)
2542 +#define RG_SSUSB_T2RLB_EN_OFST (15)
2543 +#define RG_SSUSB_T2RLB_BPSCRAMB_OFST (14)
2544 +#define RG_SSUSB_T2RLB_SERIAL_OFST (13)
2545 +#define RG_SSUSB_T2RLB_MODE_OFST (11)
2546 +#define RG_SSUSB_RX_SAOSC_EN_OFST (10)
2547 +#define RG_SSUSB_RX_SAOSC_EN_SEL_OFST (9)
2548 +#define RG_SSUSB_RX_DFE_OPTION_OFST (8)
2549 +#define RG_SSUSB_RX_DFE_EN_OFST (7)
2550 +#define RG_SSUSB_RX_DFE_EN_SEL_OFST (6)
2551 +#define RG_SSUSB_RX_EQ_EN_OFST (5)
2552 +#define RG_SSUSB_RX_EQ_EN_SEL_OFST (4)
2553 +#define RG_SSUSB_RX_SAOSC_RST_OFST (3)
2554 +#define RG_SSUSB_RX_SAOSC_RST_SEL_OFST (2)
2555 +#define RG_SSUSB_RX_DFE_RST_OFST (1)
2556 +#define RG_SSUSB_RX_DFE_RST_SEL_OFST (0)
2557 +
2558 +//U3D_PHYD_T2RLB
2559 +#define RG_SSUSB_EQTRAIN_CH_MODE_OFST (28)
2560 +#define RG_SSUSB_PRB_OUT_CPPAT_OFST (27)
2561 +#define RG_SSUSB_BPANSIENC_OFST (26)
2562 +#define RG_SSUSB_VALID_EN_OFST (25)
2563 +#define RG_SSUSB_EBUF_SRST_OFST (24)
2564 +#define RG_SSUSB_K_EMP_OFST (20)
2565 +#define RG_SSUSB_K_FUL_OFST (16)
2566 +#define RG_SSUSB_T2RLB_BDATRST_OFST (12)
2567 +#define RG_SSUSB_P_T2RLB_SKP_EN_OFST (10)
2568 +#define RG_SSUSB_T2RLB_PATMODE_OFST (8)
2569 +#define RG_SSUSB_T2RLB_TSEQCNT_OFST (0)
2570 +
2571 +//U3D_PHYD_CPPAT
2572 +#define RG_SSUSB_CPPAT_PROGRAM_EN_OFST (24)
2573 +#define RG_SSUSB_CPPAT_TOZ_OFST (21)
2574 +#define RG_SSUSB_CPPAT_PRBS_EN_OFST (20)
2575 +#define RG_SSUSB_CPPAT_OUT_TMP2_OFST (16)
2576 +#define RG_SSUSB_CPPAT_OUT_TMP1_OFST (8)
2577 +#define RG_SSUSB_CPPAT_OUT_TMP0_OFST (0)
2578 +
2579 +//U3D_PHYD_MIX3
2580 +#define RG_SSUSB_CDR_TCADJ_MINUS_OFST (31)
2581 +#define RG_SSUSB_P_CDROS_EN_OFST (30)
2582 +#define RG_SSUSB_P_P2_TX_DRV_DIS_OFST (28)
2583 +#define RG_SSUSB_CDR_TCADJ_OFFSET_OFST (24)
2584 +#define RG_SSUSB_PLL_TCADJ_MINUS_OFST (23)
2585 +#define RG_SSUSB_FORCE_PLL_BIAS_LPF_EN_OFST (20)
2586 +#define RG_SSUSB_PLL_BIAS_LPF_EN_OFST (19)
2587 +#define RG_SSUSB_PLL_TCADJ_OFFSET_OFST (16)
2588 +#define RG_SSUSB_FORCE_PLL_SSCEN_OFST (15)
2589 +#define RG_SSUSB_PLL_SSCEN_OFST (14)
2590 +#define RG_SSUSB_FORCE_CDR_PI_PWD_OFST (13)
2591 +#define RG_SSUSB_CDR_PI_PWD_OFST (12)
2592 +#define RG_SSUSB_CDR_PI_MODE_OFST (11)
2593 +#define RG_SSUSB_TXPLL_SSCEN_CYC_OFST (0)
2594 +
2595 +//U3D_PHYD_EBUFCTL
2596 +#define RG_SSUSB_EBUFCTL_OFST (0)
2597 +
2598 +//U3D_PHYD_PIPE0
2599 +#define RG_SSUSB_RXTERMINATION_OFST (30)
2600 +#define RG_SSUSB_RXEQTRAINING_OFST (29)
2601 +#define RG_SSUSB_RXPOLARITY_OFST (28)
2602 +#define RG_SSUSB_TXDEEMPH_OFST (26)
2603 +#define RG_SSUSB_POWERDOWN_OFST (24)
2604 +#define RG_SSUSB_TXONESZEROS_OFST (23)
2605 +#define RG_SSUSB_TXELECIDLE_OFST (22)
2606 +#define RG_SSUSB_TXDETECTRX_OFST (21)
2607 +#define RG_SSUSB_PIPE_SEL_OFST (20)
2608 +#define RG_SSUSB_TXDATAK_OFST (16)
2609 +#define RG_SSUSB_CDR_STABLE_SEL_OFST (15)
2610 +#define RG_SSUSB_CDR_STABLE_OFST (14)
2611 +#define RG_SSUSB_CDR_RSTB_SEL_OFST (13)
2612 +#define RG_SSUSB_CDR_RSTB_OFST (12)
2613 +#define RG_SSUSB_P_ERROR_SEL_OFST (4)
2614 +#define RG_SSUSB_TXMARGIN_OFST (1)
2615 +#define RG_SSUSB_TXCOMPLIANCE_OFST (0)
2616 +
2617 +//U3D_PHYD_PIPE1
2618 +#define RG_SSUSB_TXDATA_OFST (0)
2619 +
2620 +//U3D_PHYD_MIX4
2621 +#define RG_SSUSB_CDROS_CNT_OFST (24)
2622 +#define RG_SSUSB_T2RLB_BER_EN_OFST (16)
2623 +#define RG_SSUSB_T2RLB_BER_RATE_OFST (0)
2624 +
2625 +//U3D_PHYD_CKGEN0
2626 +#define RG_SSUSB_RFIFO_IMPLAT_OFST (27)
2627 +#define RG_SSUSB_TFIFO_PSEL_OFST (24)
2628 +#define RG_SSUSB_CKGEN_PSEL_OFST (8)
2629 +#define RG_SSUSB_RXCK_INV_OFST (0)
2630 +
2631 +//U3D_PHYD_MIX5
2632 +#define RG_SSUSB_PRB_SEL_OFST (16)
2633 +#define RG_SSUSB_RXPLL_STBCYC_OFST (0)
2634 +
2635 +//U3D_PHYD_RESERVED
2636 +#define RG_SSUSB_PHYD_RESERVE_OFST (0)
2637 +//#define RG_SSUSB_RX_SIGDET_SEL_OFST (11)
2638 +//#define RG_SSUSB_RX_SIGDET_EN_OFST (12)
2639 +//#define RG_SSUSB_RX_PI_CAL_MANUAL_SEL_OFST (9)
2640 +//#define RG_SSUSB_RX_PI_CAL_MANUAL_EN_OFST (10)
2641 +
2642 +//U3D_PHYD_CDR0
2643 +#define RG_SSUSB_CDR_BIC_LTR_OFST (28)
2644 +#define RG_SSUSB_CDR_BIC_LTD0_OFST (24)
2645 +#define RG_SSUSB_CDR_BC_LTD1_OFST (16)
2646 +#define RG_SSUSB_CDR_BC_LTR_OFST (8)
2647 +#define RG_SSUSB_CDR_BC_LTD0_OFST (0)
2648 +
2649 +//U3D_PHYD_CDR1
2650 +#define RG_SSUSB_CDR_BIR_LTD1_OFST (24)
2651 +#define RG_SSUSB_CDR_BIR_LTR_OFST (16)
2652 +#define RG_SSUSB_CDR_BIR_LTD0_OFST (8)
2653 +#define RG_SSUSB_CDR_BW_SEL_OFST (6)
2654 +#define RG_SSUSB_CDR_BIC_LTD1_OFST (0)
2655 +
2656 +//U3D_PHYD_PLL_0
2657 +#define RG_SSUSB_FORCE_CDR_BAND_5G_OFST (28)
2658 +#define RG_SSUSB_FORCE_CDR_BAND_2P5G_OFST (27)
2659 +#define RG_SSUSB_FORCE_PLL_BAND_5G_OFST (26)
2660 +#define RG_SSUSB_FORCE_PLL_BAND_2P5G_OFST (25)
2661 +#define RG_SSUSB_P_EQ_T_SEL_OFST (15)
2662 +#define RG_SSUSB_PLL_ISO_EN_CYC_OFST (5)
2663 +#define RG_SSUSB_PLLBAND_RECAL_OFST (4)
2664 +#define RG_SSUSB_PLL_DDS_ISO_EN_OFST (3)
2665 +#define RG_SSUSB_FORCE_PLL_DDS_ISO_EN_OFST (2)
2666 +#define RG_SSUSB_PLL_DDS_PWR_ON_OFST (1)
2667 +#define RG_SSUSB_FORCE_PLL_DDS_PWR_ON_OFST (0)
2668 +
2669 +//U3D_PHYD_PLL_1
2670 +#define RG_SSUSB_CDR_BAND_5G_OFST (24)
2671 +#define RG_SSUSB_CDR_BAND_2P5G_OFST (16)
2672 +#define RG_SSUSB_PLL_BAND_5G_OFST (8)
2673 +#define RG_SSUSB_PLL_BAND_2P5G_OFST (0)
2674 +
2675 +//U3D_PHYD_BCN_DET_1
2676 +#define RG_SSUSB_P_BCN_OBS_PRD_OFST (16)
2677 +#define RG_SSUSB_U_BCN_OBS_PRD_OFST (0)
2678 +
2679 +//U3D_PHYD_BCN_DET_2
2680 +#define RG_SSUSB_P_BCN_OBS_SEL_OFST (16)
2681 +#define RG_SSUSB_BCN_DET_DIS_OFST (12)
2682 +#define RG_SSUSB_U_BCN_OBS_SEL_OFST (0)
2683 +
2684 +//U3D_EQ0
2685 +#define RG_SSUSB_EQ_DLHL_LFI_OFST (24)
2686 +#define RG_SSUSB_EQ_DHHL_LFI_OFST (16)
2687 +#define RG_SSUSB_EQ_DD0HOS_LFI_OFST (8)
2688 +#define RG_SSUSB_EQ_DD0LOS_LFI_OFST (0)
2689 +
2690 +//U3D_EQ1
2691 +#define RG_SSUSB_EQ_DD1HOS_LFI_OFST (24)
2692 +#define RG_SSUSB_EQ_DD1LOS_LFI_OFST (16)
2693 +#define RG_SSUSB_EQ_DE0OS_LFI_OFST (8)
2694 +#define RG_SSUSB_EQ_DE1OS_LFI_OFST (0)
2695 +
2696 +//U3D_EQ2
2697 +#define RG_SSUSB_EQ_DLHLOS_LFI_OFST (24)
2698 +#define RG_SSUSB_EQ_DHHLOS_LFI_OFST (16)
2699 +#define RG_SSUSB_EQ_STOPTIME_OFST (14)
2700 +#define RG_SSUSB_EQ_DHHL_LF_SEL_OFST (11)
2701 +#define RG_SSUSB_EQ_DSAOS_LF_SEL_OFST (8)
2702 +#define RG_SSUSB_EQ_STARTTIME_OFST (6)
2703 +#define RG_SSUSB_EQ_DLEQ_LF_SEL_OFST (3)
2704 +#define RG_SSUSB_EQ_DLHL_LF_SEL_OFST (0)
2705 +
2706 +//U3D_EQ3
2707 +#define RG_SSUSB_EQ_DLEQ_LFI_GEN2_OFST (28)
2708 +#define RG_SSUSB_EQ_DLEQ_LFI_GEN1_OFST (24)
2709 +#define RG_SSUSB_EQ_DEYE0OS_LFI_OFST (16)
2710 +#define RG_SSUSB_EQ_DEYE1OS_LFI_OFST (8)
2711 +#define RG_SSUSB_EQ_TRI_DET_EN_OFST (7)
2712 +#define RG_SSUSB_EQ_TRI_DET_TH_OFST (0)
2713 +
2714 +//U3D_EQ_EYE0
2715 +#define RG_SSUSB_EQ_EYE_XOFFSET_OFST (25)
2716 +#define RG_SSUSB_EQ_EYE_MON_EN_OFST (24)
2717 +#define RG_SSUSB_EQ_EYE0_Y_OFST (16)
2718 +#define RG_SSUSB_EQ_EYE1_Y_OFST (8)
2719 +#define RG_SSUSB_EQ_PILPO_ROUT_OFST (7)
2720 +#define RG_SSUSB_EQ_PI_KPGAIN_OFST (4)
2721 +#define RG_SSUSB_EQ_EYE_CNT_EN_OFST (3)
2722 +
2723 +//U3D_EQ_EYE1
2724 +#define RG_SSUSB_EQ_SIGDET_OFST (24)
2725 +#define RG_SSUSB_EQ_EYE_MASK_OFST (7)
2726 +
2727 +//U3D_EQ_EYE2
2728 +#define RG_SSUSB_EQ_RX500M_CK_SEL_OFST (31)
2729 +#define RG_SSUSB_EQ_SD_CNT1_OFST (24)
2730 +#define RG_SSUSB_EQ_ISIFLAG_SEL_OFST (22)
2731 +#define RG_SSUSB_EQ_SD_CNT0_OFST (16)
2732 +
2733 +//U3D_EQ_DFE0
2734 +#define RG_SSUSB_EQ_LEQMAX_OFST (28)
2735 +#define RG_SSUSB_EQ_DFEX_EN_OFST (27)
2736 +#define RG_SSUSB_EQ_DFEX_LF_SEL_OFST (24)
2737 +#define RG_SSUSB_EQ_CHK_EYE_H_OFST (23)
2738 +#define RG_SSUSB_EQ_PIEYE_INI_OFST (16)
2739 +#define RG_SSUSB_EQ_PI90_INI_OFST (8)
2740 +#define RG_SSUSB_EQ_PI0_INI_OFST (0)
2741 +
2742 +//U3D_EQ_DFE1
2743 +#define RG_SSUSB_EQ_REV_OFST (16)
2744 +#define RG_SSUSB_EQ_DFEYEN_DUR_OFST (12)
2745 +#define RG_SSUSB_EQ_DFEXEN_DUR_OFST (8)
2746 +#define RG_SSUSB_EQ_DFEX_RST_OFST (7)
2747 +#define RG_SSUSB_EQ_GATED_RXD_B_OFST (6)
2748 +#define RG_SSUSB_EQ_PI90CK_SEL_OFST (4)
2749 +#define RG_SSUSB_EQ_DFEX_DIS_OFST (2)
2750 +#define RG_SSUSB_EQ_DFEYEN_STOP_DIS_OFST (1)
2751 +#define RG_SSUSB_EQ_DFEXEN_SEL_OFST (0)
2752 +
2753 +//U3D_EQ_DFE2
2754 +#define RG_SSUSB_EQ_MON_SEL_OFST (24)
2755 +#define RG_SSUSB_EQ_LEQOSC_DLYCNT_OFST (16)
2756 +#define RG_SSUSB_EQ_DLEQOS_LFI_OFST (8)
2757 +#define RG_SSUSB_EQ_LEQ_STOP_TO_OFST (0)
2758 +
2759 +//U3D_EQ_DFE3
2760 +#define RG_SSUSB_EQ_RESERVED_OFST (0)
2761 +
2762 +//U3D_PHYD_MON0
2763 +#define RGS_SSUSB_BERT_BERC_OFST (16)
2764 +#define RGS_SSUSB_LFPS_OFST (12)
2765 +#define RGS_SSUSB_TRAINDEC_OFST (8)
2766 +#define RGS_SSUSB_SCP_PAT_OFST (0)
2767 +
2768 +//U3D_PHYD_MON1
2769 +#define RGS_SSUSB_RX_FL_OUT_OFST (0)
2770 +
2771 +//U3D_PHYD_MON2
2772 +#define RGS_SSUSB_T2RLB_ERRCNT_OFST (16)
2773 +#define RGS_SSUSB_RETRACK_OFST (12)
2774 +#define RGS_SSUSB_RXPLL_LOCK_OFST (10)
2775 +#define RGS_SSUSB_CDR_VCOCAL_CPLT_D_OFST (9)
2776 +#define RGS_SSUSB_PLL_VCOCAL_CPLT_D_OFST (8)
2777 +#define RGS_SSUSB_PDNCTL_OFST (0)
2778 +
2779 +//U3D_PHYD_MON3
2780 +#define RGS_SSUSB_TSEQ_ERRCNT_OFST (16)
2781 +#define RGS_SSUSB_PRBS_ERRCNT_OFST (0)
2782 +
2783 +//U3D_PHYD_MON4
2784 +#define RGS_SSUSB_RX_LSLOCK_CNT_OFST (24)
2785 +#define RGS_SSUSB_SCP_DETCNT_OFST (16)
2786 +#define RGS_SSUSB_TSEQ_DETCNT_OFST (0)
2787 +
2788 +//U3D_PHYD_MON5
2789 +#define RGS_SSUSB_EBUFMSG_OFST (16)
2790 +#define RGS_SSUSB_BERT_LOCK_OFST (15)
2791 +#define RGS_SSUSB_SCP_DET_OFST (14)
2792 +#define RGS_SSUSB_TSEQ_DET_OFST (13)
2793 +#define RGS_SSUSB_EBUF_UDF_OFST (12)
2794 +#define RGS_SSUSB_EBUF_OVF_OFST (11)
2795 +#define RGS_SSUSB_PRBS_PASSTH_OFST (10)
2796 +#define RGS_SSUSB_PRBS_PASS_OFST (9)
2797 +#define RGS_SSUSB_PRBS_LOCK_OFST (8)
2798 +#define RGS_SSUSB_T2RLB_ERR_OFST (6)
2799 +#define RGS_SSUSB_T2RLB_PASSTH_OFST (5)
2800 +#define RGS_SSUSB_T2RLB_PASS_OFST (4)
2801 +#define RGS_SSUSB_T2RLB_LOCK_OFST (3)
2802 +#define RGS_SSUSB_RX_IMPCAL_DONE_OFST (2)
2803 +#define RGS_SSUSB_TX_IMPCAL_DONE_OFST (1)
2804 +#define RGS_SSUSB_RXDETECTED_OFST (0)
2805 +
2806 +//U3D_PHYD_MON6
2807 +#define RGS_SSUSB_SIGCAL_DONE_OFST (30)
2808 +#define RGS_SSUSB_SIGCAL_CAL_OUT_OFST (29)
2809 +#define RGS_SSUSB_SIGCAL_OFFSET_OFST (24)
2810 +#define RGS_SSUSB_RX_IMP_SEL_OFST (16)
2811 +#define RGS_SSUSB_TX_IMP_SEL_OFST (8)
2812 +#define RGS_SSUSB_TFIFO_MSG_OFST (4)
2813 +#define RGS_SSUSB_RFIFO_MSG_OFST (0)
2814 +
2815 +//U3D_PHYD_MON7
2816 +#define RGS_SSUSB_FT_OUT_OFST (8)
2817 +#define RGS_SSUSB_PRB_OUT_OFST (0)
2818 +
2819 +//U3D_PHYA_RX_MON0
2820 +#define RGS_SSUSB_EQ_DCLEQ_OFST (24)
2821 +#define RGS_SSUSB_EQ_DCD0H_OFST (16)
2822 +#define RGS_SSUSB_EQ_DCD0L_OFST (8)
2823 +#define RGS_SSUSB_EQ_DCD1H_OFST (0)
2824 +
2825 +//U3D_PHYA_RX_MON1
2826 +#define RGS_SSUSB_EQ_DCD1L_OFST (24)
2827 +#define RGS_SSUSB_EQ_DCE0_OFST (16)
2828 +#define RGS_SSUSB_EQ_DCE1_OFST (8)
2829 +#define RGS_SSUSB_EQ_DCHHL_OFST (0)
2830 +
2831 +//U3D_PHYA_RX_MON2
2832 +#define RGS_SSUSB_EQ_LEQ_STOP_OFST (31)
2833 +#define RGS_SSUSB_EQ_DCLHL_OFST (24)
2834 +#define RGS_SSUSB_EQ_STATUS_OFST (16)
2835 +#define RGS_SSUSB_EQ_DCEYE0_OFST (8)
2836 +#define RGS_SSUSB_EQ_DCEYE1_OFST (0)
2837 +
2838 +//U3D_PHYA_RX_MON3
2839 +#define RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_0_OFST (0)
2840 +
2841 +//U3D_PHYA_RX_MON4
2842 +#define RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_1_OFST (0)
2843 +
2844 +//U3D_PHYA_RX_MON5
2845 +#define RGS_SSUSB_EQ_DCLEQOS_OFST (8)
2846 +#define RGS_SSUSB_EQ_EYE_CNT_RDY_OFST (7)
2847 +#define RGS_SSUSB_EQ_PILPO_OFST (0)
2848 +
2849 +//U3D_PHYD_CPPAT2
2850 +#define RG_SSUSB_CPPAT_OUT_H_TMP2_OFST (16)
2851 +#define RG_SSUSB_CPPAT_OUT_H_TMP1_OFST (8)
2852 +#define RG_SSUSB_CPPAT_OUT_H_TMP0_OFST (0)
2853 +
2854 +//U3D_EQ_EYE3
2855 +#define RG_SSUSB_EQ_LEQ_SHIFT_OFST (24)
2856 +#define RG_SSUSB_EQ_EYE_CNT_OFST (0)
2857 +
2858 +//U3D_KBAND_OUT
2859 +#define RGS_SSUSB_CDR_BAND_5G_OFST (24)
2860 +#define RGS_SSUSB_CDR_BAND_2P5G_OFST (16)
2861 +#define RGS_SSUSB_PLL_BAND_5G_OFST (8)
2862 +#define RGS_SSUSB_PLL_BAND_2P5G_OFST (0)
2863 +
2864 +//U3D_KBAND_OUT1
2865 +#define RGS_SSUSB_CDR_VCOCAL_FAIL_OFST (24)
2866 +#define RGS_SSUSB_CDR_VCOCAL_STATE_OFST (16)
2867 +#define RGS_SSUSB_PLL_VCOCAL_FAIL_OFST (8)
2868 +#define RGS_SSUSB_PLL_VCOCAL_STATE_OFST (0)
2869 +
2870 +
2871 +///////////////////////////////////////////////////////////////////////////////
2872 +
2873 +struct u3phyd_bank2_reg {
2874 + //0x0
2875 + PHY_LE32 b2_phyd_top1;
2876 + PHY_LE32 b2_phyd_top2;
2877 + PHY_LE32 b2_phyd_top3;
2878 + PHY_LE32 b2_phyd_top4;
2879 + //0x10
2880 + PHY_LE32 b2_phyd_top5;
2881 + PHY_LE32 b2_phyd_top6;
2882 + PHY_LE32 b2_phyd_top7;
2883 + PHY_LE32 b2_phyd_p_sigdet1;
2884 + //0x20
2885 + PHY_LE32 b2_phyd_p_sigdet2;
2886 + PHY_LE32 b2_phyd_p_sigdet_cal1;
2887 + PHY_LE32 b2_phyd_rxdet1;
2888 + PHY_LE32 b2_phyd_rxdet2;
2889 + //0x30
2890 + PHY_LE32 b2_phyd_misc0;
2891 + PHY_LE32 b2_phyd_misc2;
2892 + PHY_LE32 b2_phyd_misc3;
2893 + PHY_LE32 reserve0;
2894 + //0x40
2895 + PHY_LE32 b2_rosc_0;
2896 + PHY_LE32 b2_rosc_1;
2897 + PHY_LE32 b2_rosc_2;
2898 + PHY_LE32 b2_rosc_3;
2899 + //0x50
2900 + PHY_LE32 b2_rosc_4;
2901 + PHY_LE32 b2_rosc_5;
2902 + PHY_LE32 b2_rosc_6;
2903 + PHY_LE32 b2_rosc_7;
2904 + //0x60
2905 + PHY_LE32 b2_rosc_8;
2906 + PHY_LE32 b2_rosc_9;
2907 + PHY_LE32 b2_rosc_a;
2908 + PHY_LE32 reserve1;
2909 + //0x70~0xd0
2910 + PHY_LE32 reserve2[28];
2911 + //0xe0
2912 + PHY_LE32 phyd_version;
2913 + PHY_LE32 phyd_model;
2914 +};
2915 +
2916 +//U3D_B2_PHYD_TOP1
2917 +#define RG_SSUSB_PCIE2_K_EMP (0xf<<28) //31:28
2918 +#define RG_SSUSB_PCIE2_K_FUL (0xf<<24) //27:24
2919 +#define RG_SSUSB_TX_EIDLE_LP_EN (0x1<<17) //17:17
2920 +#define RG_SSUSB_FORCE_TX_EIDLE_LP_EN (0x1<<16) //16:16
2921 +#define RG_SSUSB_SIGDET_EN (0x1<<15) //15:15
2922 +#define RG_SSUSB_FORCE_SIGDET_EN (0x1<<14) //14:14
2923 +#define RG_SSUSB_CLKRX_EN (0x1<<13) //13:13
2924 +#define RG_SSUSB_FORCE_CLKRX_EN (0x1<<12) //12:12
2925 +#define RG_SSUSB_CLKTX_EN (0x1<<11) //11:11
2926 +#define RG_SSUSB_FORCE_CLKTX_EN (0x1<<10) //10:10
2927 +#define RG_SSUSB_CLK_REQ_N_I (0x1<<9) //9:9
2928 +#define RG_SSUSB_FORCE_CLK_REQ_N_I (0x1<<8) //8:8
2929 +#define RG_SSUSB_RATE (0x1<<6) //6:6
2930 +#define RG_SSUSB_FORCE_RATE (0x1<<5) //5:5
2931 +#define RG_SSUSB_PCIE_MODE_SEL (0x1<<4) //4:4
2932 +#define RG_SSUSB_FORCE_PCIE_MODE_SEL (0x1<<3) //3:3
2933 +#define RG_SSUSB_PHY_MODE (0x3<<1) //2:1
2934 +#define RG_SSUSB_FORCE_PHY_MODE (0x1<<0) //0:0
2935 +
2936 +//U3D_B2_PHYD_TOP2
2937 +#define RG_SSUSB_FORCE_IDRV_6DB (0x1<<30) //30:30
2938 +#define RG_SSUSB_IDRV_6DB (0x3f<<24) //29:24
2939 +#define RG_SSUSB_FORCE_IDEM_3P5DB (0x1<<22) //22:22
2940 +#define RG_SSUSB_IDEM_3P5DB (0x3f<<16) //21:16
2941 +#define RG_SSUSB_FORCE_IDRV_3P5DB (0x1<<14) //14:14
2942 +#define RG_SSUSB_IDRV_3P5DB (0x3f<<8) //13:8
2943 +#define RG_SSUSB_FORCE_IDRV_0DB (0x1<<6) //6:6
2944 +#define RG_SSUSB_IDRV_0DB (0x3f<<0) //5:0
2945 +
2946 +//U3D_B2_PHYD_TOP3
2947 +#define RG_SSUSB_TX_BIASI (0x7<<25) //27:25
2948 +#define RG_SSUSB_FORCE_TX_BIASI_EN (0x1<<24) //24:24
2949 +#define RG_SSUSB_TX_BIASI_EN (0x1<<16) //16:16
2950 +#define RG_SSUSB_FORCE_TX_BIASI (0x1<<13) //13:13
2951 +#define RG_SSUSB_FORCE_IDEM_6DB (0x1<<8) //8:8
2952 +#define RG_SSUSB_IDEM_6DB (0x3f<<0) //5:0
2953 +
2954 +//U3D_B2_PHYD_TOP4
2955 +#define RG_SSUSB_G1_CDR_BIC_LTR (0xf<<28) //31:28
2956 +#define RG_SSUSB_G1_CDR_BIC_LTD0 (0xf<<24) //27:24
2957 +#define RG_SSUSB_G1_CDR_BC_LTD1 (0x1f<<16) //20:16
2958 +#define RG_SSUSB_G1_CDR_BC_LTR (0x1f<<8) //12:8
2959 +#define RG_SSUSB_G1_CDR_BC_LTD0 (0x1f<<0) //4:0
2960 +
2961 +//U3D_B2_PHYD_TOP5
2962 +#define RG_SSUSB_G1_CDR_BIR_LTD1 (0x1f<<24) //28:24
2963 +#define RG_SSUSB_G1_CDR_BIR_LTR (0x1f<<16) //20:16
2964 +#define RG_SSUSB_G1_CDR_BIR_LTD0 (0x1f<<8) //12:8
2965 +#define RG_SSUSB_G1_CDR_BIC_LTD1 (0xf<<0) //3:0
2966 +
2967 +//U3D_B2_PHYD_TOP6
2968 +#define RG_SSUSB_G2_CDR_BIC_LTR (0xf<<28) //31:28
2969 +#define RG_SSUSB_G2_CDR_BIC_LTD0 (0xf<<24) //27:24
2970 +#define RG_SSUSB_G2_CDR_BC_LTD1 (0x1f<<16) //20:16
2971 +#define RG_SSUSB_G2_CDR_BC_LTR (0x1f<<8) //12:8
2972 +#define RG_SSUSB_G2_CDR_BC_LTD0 (0x1f<<0) //4:0
2973 +
2974 +//U3D_B2_PHYD_TOP7
2975 +#define RG_SSUSB_G2_CDR_BIR_LTD1 (0x1f<<24) //28:24
2976 +#define RG_SSUSB_G2_CDR_BIR_LTR (0x1f<<16) //20:16
2977 +#define RG_SSUSB_G2_CDR_BIR_LTD0 (0x1f<<8) //12:8
2978 +#define RG_SSUSB_G2_CDR_BIC_LTD1 (0xf<<0) //3:0
2979 +
2980 +//U3D_B2_PHYD_P_SIGDET1
2981 +#define RG_SSUSB_P_SIGDET_FLT_DIS (0x1<<31) //31:31
2982 +#define RG_SSUSB_P_SIGDET_FLT_G2_DEAST_SEL (0x7f<<24) //30:24
2983 +#define RG_SSUSB_P_SIGDET_FLT_G1_DEAST_SEL (0x7f<<16) //22:16
2984 +#define RG_SSUSB_P_SIGDET_FLT_P2_AST_SEL (0x7f<<8) //14:8
2985 +#define RG_SSUSB_P_SIGDET_FLT_PX_AST_SEL (0x7f<<0) //6:0
2986 +
2987 +//U3D_B2_PHYD_P_SIGDET2
2988 +#define RG_SSUSB_P_SIGDET_RX_VAL_S (0x1<<29) //29:29
2989 +#define RG_SSUSB_P_SIGDET_L0S_DEAS_SEL (0x1<<28) //28:28
2990 +#define RG_SSUSB_P_SIGDET_L0_EXIT_S (0x1<<27) //27:27
2991 +#define RG_SSUSB_P_SIGDET_L0S_EXIT_T_S (0x3<<25) //26:25
2992 +#define RG_SSUSB_P_SIGDET_L0S_EXIT_S (0x1<<24) //24:24
2993 +#define RG_SSUSB_P_SIGDET_L0S_ENTRY_S (0x1<<16) //16:16
2994 +#define RG_SSUSB_P_SIGDET_PRB_SEL (0x1<<10) //10:10
2995 +#define RG_SSUSB_P_SIGDET_BK_SIG_T (0x3<<8) //9:8
2996 +#define RG_SSUSB_P_SIGDET_P2_RXLFPS (0x1<<6) //6:6
2997 +#define RG_SSUSB_P_SIGDET_NON_BK_AD (0x1<<5) //5:5
2998 +#define RG_SSUSB_P_SIGDET_BK_B_RXEQ (0x1<<4) //4:4
2999 +#define RG_SSUSB_P_SIGDET_G2_KO_SEL (0x3<<2) //3:2
3000 +#define RG_SSUSB_P_SIGDET_G1_KO_SEL (0x3<<0) //1:0
3001 +
3002 +//U3D_B2_PHYD_P_SIGDET_CAL1
3003 +#define RG_SSUSB_P_SIGDET_CAL_OFFSET (0x1f<<24) //28:24
3004 +#define RG_SSUSB_P_FORCE_SIGDET_CAL_OFFSET (0x1<<16) //16:16
3005 +#define RG_SSUSB_P_SIGDET_CAL_EN (0x1<<8) //8:8
3006 +#define RG_SSUSB_P_FORCE_SIGDET_CAL_EN (0x1<<3) //3:3
3007 +#define RG_SSUSB_P_SIGDET_FLT_EN (0x1<<2) //2:2
3008 +#define RG_SSUSB_P_SIGDET_SAMPLE_PRD (0x1<<1) //1:1
3009 +#define RG_SSUSB_P_SIGDET_REK (0x1<<0) //0:0
3010 +
3011 +//U3D_B2_PHYD_RXDET1
3012 +#define RG_SSUSB_RXDET_PRB_SEL (0x1<<31) //31:31
3013 +#define RG_SSUSB_FORCE_CMDET (0x1<<30) //30:30
3014 +#define RG_SSUSB_RXDET_EN (0x1<<29) //29:29
3015 +#define RG_SSUSB_FORCE_RXDET_EN (0x1<<28) //28:28
3016 +#define RG_SSUSB_RXDET_K_TWICE (0x1<<27) //27:27
3017 +#define RG_SSUSB_RXDET_STB3_SET (0x1ff<<18) //26:18
3018 +#define RG_SSUSB_RXDET_STB2_SET (0x1ff<<9) //17:9
3019 +#define RG_SSUSB_RXDET_STB1_SET (0x1ff<<0) //8:0
3020 +
3021 +//U3D_B2_PHYD_RXDET2
3022 +#define RG_SSUSB_PHYD_TRAINDEC_FORCE_CGEN (0x1<<31) //31:31
3023 +#define RG_SSUSB_PHYD_BERTLB_FORCE_CGEN (0x1<<30) //30:30
3024 +#define RG_SSUSB_PHYD_T2RLB_FORCE_CGEN (0x1<<29) //29:29
3025 +#define RG_SSUSB_PDN_T_SEL (0x3<<18) //19:18
3026 +#define RG_SSUSB_RXDET_STB3_SET_P3 (0x1ff<<9) //17:9
3027 +#define RG_SSUSB_RXDET_STB2_SET_P3 (0x1ff<<0) //8:0
3028 +
3029 +//U3D_B2_PHYD_MISC0
3030 +#define RG_SSUSB_FORCE_PLL_DDS_HF_EN (0x1<<22) //22:22
3031 +#define RG_SSUSB_PLL_DDS_HF_EN_MAN (0x1<<21) //21:21
3032 +#define RG_SSUSB_RXLFPS_ENTXDRV (0x1<<20) //20:20
3033 +#define RG_SSUSB_RX_FL_UNLOCKTH (0xf<<16) //19:16
3034 +#define RG_SSUSB_LFPS_PSEL (0x1<<15) //15:15
3035 +#define RG_SSUSB_RX_SIGDET_EN (0x1<<14) //14:14
3036 +#define RG_SSUSB_RX_SIGDET_EN_SEL (0x1<<13) //13:13
3037 +#define RG_SSUSB_RX_PI_CAL_EN (0x1<<12) //12:12
3038 +#define RG_SSUSB_RX_PI_CAL_EN_SEL (0x1<<11) //11:11
3039 +#define RG_SSUSB_P3_CLS_CK_SEL (0x1<<10) //10:10
3040 +#define RG_SSUSB_T2RLB_PSEL (0x3<<8) //9:8
3041 +#define RG_SSUSB_PPCTL_PSEL (0x7<<5) //7:5
3042 +#define RG_SSUSB_PHYD_TX_DATA_INV (0x1<<4) //4:4
3043 +#define RG_SSUSB_BERTLB_PSEL (0x3<<2) //3:2
3044 +#define RG_SSUSB_RETRACK_DIS (0x1<<1) //1:1
3045 +#define RG_SSUSB_PPERRCNT_CLR (0x1<<0) //0:0
3046 +
3047 +//U3D_B2_PHYD_MISC2
3048 +#define RG_SSUSB_FRC_PLL_DDS_PREDIV2 (0x1<<31) //31:31
3049 +#define RG_SSUSB_FRC_PLL_DDS_IADJ (0xf<<27) //30:27
3050 +#define RG_SSUSB_P_SIGDET_125FILTER (0x1<<26) //26:26
3051 +#define RG_SSUSB_P_SIGDET_RST_FILTER (0x1<<25) //25:25
3052 +#define RG_SSUSB_P_SIGDET_EID_USE_RAW (0x1<<24) //24:24
3053 +#define RG_SSUSB_P_SIGDET_LTD_USE_RAW (0x1<<23) //23:23
3054 +#define RG_SSUSB_EIDLE_BF_RXDET (0x1<<22) //22:22
3055 +#define RG_SSUSB_EIDLE_LP_STBCYC (0x1ff<<13) //21:13
3056 +#define RG_SSUSB_TX_EIDLE_LP_POSTDLY (0x3f<<7) //12:7
3057 +#define RG_SSUSB_TX_EIDLE_LP_PREDLY (0x3f<<1) //6:1
3058 +#define RG_SSUSB_TX_EIDLE_LP_EN_ADV (0x1<<0) //0:0
3059 +
3060 +//U3D_B2_PHYD_MISC3
3061 +#define RGS_SSUSB_DDS_CALIB_C_STATE (0x7<<16) //18:16
3062 +#define RGS_SSUSB_PPERRCNT (0xffff<<0) //15:0
3063 +
3064 +//U3D_B2_ROSC_0
3065 +#define RG_SSUSB_RING_OSC_CNTEND (0x1ff<<23) //31:23
3066 +#define RG_SSUSB_XTAL_OSC_CNTEND (0x7f<<16) //22:16
3067 +#define RG_SSUSB_RING_OSC_EN (0x1<<3) //3:3
3068 +#define RG_SSUSB_RING_OSC_FORCE_EN (0x1<<2) //2:2
3069 +#define RG_SSUSB_FRC_RING_BYPASS_DET (0x1<<1) //1:1
3070 +#define RG_SSUSB_RING_BYPASS_DET (0x1<<0) //0:0
3071 +
3072 +//U3D_B2_ROSC_1
3073 +#define RG_SSUSB_RING_OSC_FRC_P3 (0x1<<20) //20:20
3074 +#define RG_SSUSB_RING_OSC_P3 (0x1<<19) //19:19
3075 +#define RG_SSUSB_RING_OSC_FRC_RECAL (0x3<<17) //18:17
3076 +#define RG_SSUSB_RING_OSC_RECAL (0x1<<16) //16:16
3077 +#define RG_SSUSB_RING_OSC_SEL (0xff<<8) //15:8
3078 +#define RG_SSUSB_RING_OSC_FRC_SEL (0x1<<0) //0:0
3079 +
3080 +//U3D_B2_ROSC_2
3081 +#define RG_SSUSB_RING_DET_STRCYC2 (0xffff<<16) //31:16
3082 +#define RG_SSUSB_RING_DET_STRCYC1 (0xffff<<0) //15:0
3083 +
3084 +//U3D_B2_ROSC_3
3085 +#define RG_SSUSB_RING_DET_DETWIN1 (0xffff<<16) //31:16
3086 +#define RG_SSUSB_RING_DET_STRCYC3 (0xffff<<0) //15:0
3087 +
3088 +//U3D_B2_ROSC_4
3089 +#define RG_SSUSB_RING_DET_DETWIN3 (0xffff<<16) //31:16
3090 +#define RG_SSUSB_RING_DET_DETWIN2 (0xffff<<0) //15:0
3091 +
3092 +//U3D_B2_ROSC_5
3093 +#define RG_SSUSB_RING_DET_LBOND1 (0xffff<<16) //31:16
3094 +#define RG_SSUSB_RING_DET_UBOND1 (0xffff<<0) //15:0
3095 +
3096 +//U3D_B2_ROSC_6
3097 +#define RG_SSUSB_RING_DET_LBOND2 (0xffff<<16) //31:16
3098 +#define RG_SSUSB_RING_DET_UBOND2 (0xffff<<0) //15:0
3099 +
3100 +//U3D_B2_ROSC_7
3101 +#define RG_SSUSB_RING_DET_LBOND3 (0xffff<<16) //31:16
3102 +#define RG_SSUSB_RING_DET_UBOND3 (0xffff<<0) //15:0
3103 +
3104 +//U3D_B2_ROSC_8
3105 +#define RG_SSUSB_RING_RESERVE (0xffff<<16) //31:16
3106 +#define RG_SSUSB_ROSC_PROB_SEL (0xf<<2) //5:2
3107 +#define RG_SSUSB_RING_FREQMETER_EN (0x1<<1) //1:1
3108 +#define RG_SSUSB_RING_DET_BPS_UBOND (0x1<<0) //0:0
3109 +
3110 +//U3D_B2_ROSC_9
3111 +#define RGS_FM_RING_CNT (0xffff<<16) //31:16
3112 +#define RGS_SSUSB_RING_OSC_STATE (0x3<<10) //11:10
3113 +#define RGS_SSUSB_RING_OSC_STABLE (0x1<<9) //9:9
3114 +#define RGS_SSUSB_RING_OSC_CAL_FAIL (0x1<<8) //8:8
3115 +#define RGS_SSUSB_RING_OSC_CAL (0xff<<0) //7:0
3116 +
3117 +//U3D_B2_ROSC_A
3118 +#define RGS_SSUSB_ROSC_PROB_OUT (0xff<<0) //7:0
3119 +
3120 +//U3D_PHYD_VERSION
3121 +#define RGS_SSUSB_PHYD_VERSION (0xffffffff<<0) //31:0
3122 +
3123 +//U3D_PHYD_MODEL
3124 +#define RGS_SSUSB_PHYD_MODEL (0xffffffff<<0) //31:0
3125 +
3126 +
3127 +/* OFFSET */
3128 +
3129 +//U3D_B2_PHYD_TOP1
3130 +#define RG_SSUSB_PCIE2_K_EMP_OFST (28)
3131 +#define RG_SSUSB_PCIE2_K_FUL_OFST (24)
3132 +#define RG_SSUSB_TX_EIDLE_LP_EN_OFST (17)
3133 +#define RG_SSUSB_FORCE_TX_EIDLE_LP_EN_OFST (16)
3134 +#define RG_SSUSB_SIGDET_EN_OFST (15)
3135 +#define RG_SSUSB_FORCE_SIGDET_EN_OFST (14)
3136 +#define RG_SSUSB_CLKRX_EN_OFST (13)
3137 +#define RG_SSUSB_FORCE_CLKRX_EN_OFST (12)
3138 +#define RG_SSUSB_CLKTX_EN_OFST (11)
3139 +#define RG_SSUSB_FORCE_CLKTX_EN_OFST (10)
3140 +#define RG_SSUSB_CLK_REQ_N_I_OFST (9)
3141 +#define RG_SSUSB_FORCE_CLK_REQ_N_I_OFST (8)
3142 +#define RG_SSUSB_RATE_OFST (6)
3143 +#define RG_SSUSB_FORCE_RATE_OFST (5)
3144 +#define RG_SSUSB_PCIE_MODE_SEL_OFST (4)
3145 +#define RG_SSUSB_FORCE_PCIE_MODE_SEL_OFST (3)
3146 +#define RG_SSUSB_PHY_MODE_OFST (1)
3147 +#define RG_SSUSB_FORCE_PHY_MODE_OFST (0)
3148 +
3149 +//U3D_B2_PHYD_TOP2
3150 +#define RG_SSUSB_FORCE_IDRV_6DB_OFST (30)
3151 +#define RG_SSUSB_IDRV_6DB_OFST (24)
3152 +#define RG_SSUSB_FORCE_IDEM_3P5DB_OFST (22)
3153 +#define RG_SSUSB_IDEM_3P5DB_OFST (16)
3154 +#define RG_SSUSB_FORCE_IDRV_3P5DB_OFST (14)
3155 +#define RG_SSUSB_IDRV_3P5DB_OFST (8)
3156 +#define RG_SSUSB_FORCE_IDRV_0DB_OFST (6)
3157 +#define RG_SSUSB_IDRV_0DB_OFST (0)
3158 +
3159 +//U3D_B2_PHYD_TOP3
3160 +#define RG_SSUSB_TX_BIASI_OFST (25)
3161 +#define RG_SSUSB_FORCE_TX_BIASI_EN_OFST (24)
3162 +#define RG_SSUSB_TX_BIASI_EN_OFST (16)
3163 +#define RG_SSUSB_FORCE_TX_BIASI_OFST (13)
3164 +#define RG_SSUSB_FORCE_IDEM_6DB_OFST (8)
3165 +#define RG_SSUSB_IDEM_6DB_OFST (0)
3166 +
3167 +//U3D_B2_PHYD_TOP4
3168 +#define RG_SSUSB_G1_CDR_BIC_LTR_OFST (28)
3169 +#define RG_SSUSB_G1_CDR_BIC_LTD0_OFST (24)
3170 +#define RG_SSUSB_G1_CDR_BC_LTD1_OFST (16)
3171 +#define RG_SSUSB_G1_CDR_BC_LTR_OFST (8)
3172 +#define RG_SSUSB_G1_CDR_BC_LTD0_OFST (0)
3173 +
3174 +//U3D_B2_PHYD_TOP5
3175 +#define RG_SSUSB_G1_CDR_BIR_LTD1_OFST (24)
3176 +#define RG_SSUSB_G1_CDR_BIR_LTR_OFST (16)
3177 +#define RG_SSUSB_G1_CDR_BIR_LTD0_OFST (8)
3178 +#define RG_SSUSB_G1_CDR_BIC_LTD1_OFST (0)
3179 +
3180 +//U3D_B2_PHYD_TOP6
3181 +#define RG_SSUSB_G2_CDR_BIC_LTR_OFST (28)
3182 +#define RG_SSUSB_G2_CDR_BIC_LTD0_OFST (24)
3183 +#define RG_SSUSB_G2_CDR_BC_LTD1_OFST (16)
3184 +#define RG_SSUSB_G2_CDR_BC_LTR_OFST (8)
3185 +#define RG_SSUSB_G2_CDR_BC_LTD0_OFST (0)
3186 +
3187 +//U3D_B2_PHYD_TOP7
3188 +#define RG_SSUSB_G2_CDR_BIR_LTD1_OFST (24)
3189 +#define RG_SSUSB_G2_CDR_BIR_LTR_OFST (16)
3190 +#define RG_SSUSB_G2_CDR_BIR_LTD0_OFST (8)
3191 +#define RG_SSUSB_G2_CDR_BIC_LTD1_OFST (0)
3192 +
3193 +//U3D_B2_PHYD_P_SIGDET1
3194 +#define RG_SSUSB_P_SIGDET_FLT_DIS_OFST (31)
3195 +#define RG_SSUSB_P_SIGDET_FLT_G2_DEAST_SEL_OFST (24)
3196 +#define RG_SSUSB_P_SIGDET_FLT_G1_DEAST_SEL_OFST (16)
3197 +#define RG_SSUSB_P_SIGDET_FLT_P2_AST_SEL_OFST (8)
3198 +#define RG_SSUSB_P_SIGDET_FLT_PX_AST_SEL_OFST (0)
3199 +
3200 +//U3D_B2_PHYD_P_SIGDET2
3201 +#define RG_SSUSB_P_SIGDET_RX_VAL_S_OFST (29)
3202 +#define RG_SSUSB_P_SIGDET_L0S_DEAS_SEL_OFST (28)
3203 +#define RG_SSUSB_P_SIGDET_L0_EXIT_S_OFST (27)
3204 +#define RG_SSUSB_P_SIGDET_L0S_EXIT_T_S_OFST (25)
3205 +#define RG_SSUSB_P_SIGDET_L0S_EXIT_S_OFST (24)
3206 +#define RG_SSUSB_P_SIGDET_L0S_ENTRY_S_OFST (16)
3207 +#define RG_SSUSB_P_SIGDET_PRB_SEL_OFST (10)
3208 +#define RG_SSUSB_P_SIGDET_BK_SIG_T_OFST (8)
3209 +#define RG_SSUSB_P_SIGDET_P2_RXLFPS_OFST (6)
3210 +#define RG_SSUSB_P_SIGDET_NON_BK_AD_OFST (5)
3211 +#define RG_SSUSB_P_SIGDET_BK_B_RXEQ_OFST (4)
3212 +#define RG_SSUSB_P_SIGDET_G2_KO_SEL_OFST (2)
3213 +#define RG_SSUSB_P_SIGDET_G1_KO_SEL_OFST (0)
3214 +
3215 +//U3D_B2_PHYD_P_SIGDET_CAL1
3216 +#define RG_SSUSB_P_SIGDET_CAL_OFFSET_OFST (24)
3217 +#define RG_SSUSB_P_FORCE_SIGDET_CAL_OFFSET_OFST (16)
3218 +#define RG_SSUSB_P_SIGDET_CAL_EN_OFST (8)
3219 +#define RG_SSUSB_P_FORCE_SIGDET_CAL_EN_OFST (3)
3220 +#define RG_SSUSB_P_SIGDET_FLT_EN_OFST (2)
3221 +#define RG_SSUSB_P_SIGDET_SAMPLE_PRD_OFST (1)
3222 +#define RG_SSUSB_P_SIGDET_REK_OFST (0)
3223 +
3224 +//U3D_B2_PHYD_RXDET1
3225 +#define RG_SSUSB_RXDET_PRB_SEL_OFST (31)
3226 +#define RG_SSUSB_FORCE_CMDET_OFST (30)
3227 +#define RG_SSUSB_RXDET_EN_OFST (29)
3228 +#define RG_SSUSB_FORCE_RXDET_EN_OFST (28)
3229 +#define RG_SSUSB_RXDET_K_TWICE_OFST (27)
3230 +#define RG_SSUSB_RXDET_STB3_SET_OFST (18)
3231 +#define RG_SSUSB_RXDET_STB2_SET_OFST (9)
3232 +#define RG_SSUSB_RXDET_STB1_SET_OFST (0)
3233 +
3234 +//U3D_B2_PHYD_RXDET2
3235 +#define RG_SSUSB_PHYD_TRAINDEC_FORCE_CGEN_OFST (31)
3236 +#define RG_SSUSB_PHYD_BERTLB_FORCE_CGEN_OFST (30)
3237 +#define RG_SSUSB_PHYD_T2RLB_FORCE_CGEN_OFST (29)
3238 +#define RG_SSUSB_PDN_T_SEL_OFST (18)
3239 +#define RG_SSUSB_RXDET_STB3_SET_P3_OFST (9)
3240 +#define RG_SSUSB_RXDET_STB2_SET_P3_OFST (0)
3241 +
3242 +//U3D_B2_PHYD_MISC0
3243 +#define RG_SSUSB_FORCE_PLL_DDS_HF_EN_OFST (22)
3244 +#define RG_SSUSB_PLL_DDS_HF_EN_MAN_OFST (21)
3245 +#define RG_SSUSB_RXLFPS_ENTXDRV_OFST (20)
3246 +#define RG_SSUSB_RX_FL_UNLOCKTH_OFST (16)
3247 +#define RG_SSUSB_LFPS_PSEL_OFST (15)
3248 +#define RG_SSUSB_RX_SIGDET_EN_OFST (14)
3249 +#define RG_SSUSB_RX_SIGDET_EN_SEL_OFST (13)
3250 +#define RG_SSUSB_RX_PI_CAL_EN_OFST (12)
3251 +#define RG_SSUSB_RX_PI_CAL_EN_SEL_OFST (11)
3252 +#define RG_SSUSB_P3_CLS_CK_SEL_OFST (10)
3253 +#define RG_SSUSB_T2RLB_PSEL_OFST (8)
3254 +#define RG_SSUSB_PPCTL_PSEL_OFST (5)
3255 +#define RG_SSUSB_PHYD_TX_DATA_INV_OFST (4)
3256 +#define RG_SSUSB_BERTLB_PSEL_OFST (2)
3257 +#define RG_SSUSB_RETRACK_DIS_OFST (1)
3258 +#define RG_SSUSB_PPERRCNT_CLR_OFST (0)
3259 +
3260 +//U3D_B2_PHYD_MISC2
3261 +#define RG_SSUSB_FRC_PLL_DDS_PREDIV2_OFST (31)
3262 +#define RG_SSUSB_FRC_PLL_DDS_IADJ_OFST (27)
3263 +#define RG_SSUSB_P_SIGDET_125FILTER_OFST (26)
3264 +#define RG_SSUSB_P_SIGDET_RST_FILTER_OFST (25)
3265 +#define RG_SSUSB_P_SIGDET_EID_USE_RAW_OFST (24)
3266 +#define RG_SSUSB_P_SIGDET_LTD_USE_RAW_OFST (23)
3267 +#define RG_SSUSB_EIDLE_BF_RXDET_OFST (22)
3268 +#define RG_SSUSB_EIDLE_LP_STBCYC_OFST (13)
3269 +#define RG_SSUSB_TX_EIDLE_LP_POSTDLY_OFST (7)
3270 +#define RG_SSUSB_TX_EIDLE_LP_PREDLY_OFST (1)
3271 +#define RG_SSUSB_TX_EIDLE_LP_EN_ADV_OFST (0)
3272 +
3273 +//U3D_B2_PHYD_MISC3
3274 +#define RGS_SSUSB_DDS_CALIB_C_STATE_OFST (16)
3275 +#define RGS_SSUSB_PPERRCNT_OFST (0)
3276 +
3277 +//U3D_B2_ROSC_0
3278 +#define RG_SSUSB_RING_OSC_CNTEND_OFST (23)
3279 +#define RG_SSUSB_XTAL_OSC_CNTEND_OFST (16)
3280 +#define RG_SSUSB_RING_OSC_EN_OFST (3)
3281 +#define RG_SSUSB_RING_OSC_FORCE_EN_OFST (2)
3282 +#define RG_SSUSB_FRC_RING_BYPASS_DET_OFST (1)
3283 +#define RG_SSUSB_RING_BYPASS_DET_OFST (0)
3284 +
3285 +//U3D_B2_ROSC_1
3286 +#define RG_SSUSB_RING_OSC_FRC_P3_OFST (20)
3287 +#define RG_SSUSB_RING_OSC_P3_OFST (19)
3288 +#define RG_SSUSB_RING_OSC_FRC_RECAL_OFST (17)
3289 +#define RG_SSUSB_RING_OSC_RECAL_OFST (16)
3290 +#define RG_SSUSB_RING_OSC_SEL_OFST (8)
3291 +#define RG_SSUSB_RING_OSC_FRC_SEL_OFST (0)
3292 +
3293 +//U3D_B2_ROSC_2
3294 +#define RG_SSUSB_RING_DET_STRCYC2_OFST (16)
3295 +#define RG_SSUSB_RING_DET_STRCYC1_OFST (0)
3296 +
3297 +//U3D_B2_ROSC_3
3298 +#define RG_SSUSB_RING_DET_DETWIN1_OFST (16)
3299 +#define RG_SSUSB_RING_DET_STRCYC3_OFST (0)
3300 +
3301 +//U3D_B2_ROSC_4
3302 +#define RG_SSUSB_RING_DET_DETWIN3_OFST (16)
3303 +#define RG_SSUSB_RING_DET_DETWIN2_OFST (0)
3304 +
3305 +//U3D_B2_ROSC_5
3306 +#define RG_SSUSB_RING_DET_LBOND1_OFST (16)
3307 +#define RG_SSUSB_RING_DET_UBOND1_OFST (0)
3308 +
3309 +//U3D_B2_ROSC_6
3310 +#define RG_SSUSB_RING_DET_LBOND2_OFST (16)
3311 +#define RG_SSUSB_RING_DET_UBOND2_OFST (0)
3312 +
3313 +//U3D_B2_ROSC_7
3314 +#define RG_SSUSB_RING_DET_LBOND3_OFST (16)
3315 +#define RG_SSUSB_RING_DET_UBOND3_OFST (0)
3316 +
3317 +//U3D_B2_ROSC_8
3318 +#define RG_SSUSB_RING_RESERVE_OFST (16)
3319 +#define RG_SSUSB_ROSC_PROB_SEL_OFST (2)
3320 +#define RG_SSUSB_RING_FREQMETER_EN_OFST (1)
3321 +#define RG_SSUSB_RING_DET_BPS_UBOND_OFST (0)
3322 +
3323 +//U3D_B2_ROSC_9
3324 +#define RGS_FM_RING_CNT_OFST (16)
3325 +#define RGS_SSUSB_RING_OSC_STATE_OFST (10)
3326 +#define RGS_SSUSB_RING_OSC_STABLE_OFST (9)
3327 +#define RGS_SSUSB_RING_OSC_CAL_FAIL_OFST (8)
3328 +#define RGS_SSUSB_RING_OSC_CAL_OFST (0)
3329 +
3330 +//U3D_B2_ROSC_A
3331 +#define RGS_SSUSB_ROSC_PROB_OUT_OFST (0)
3332 +
3333 +//U3D_PHYD_VERSION
3334 +#define RGS_SSUSB_PHYD_VERSION_OFST (0)
3335 +
3336 +//U3D_PHYD_MODEL
3337 +#define RGS_SSUSB_PHYD_MODEL_OFST (0)
3338 +
3339 +
3340 +///////////////////////////////////////////////////////////////////////////////
3341 +
3342 +struct sifslv_chip_reg {
3343 + PHY_LE32 xtalbias;
3344 + PHY_LE32 syspll1;
3345 + PHY_LE32 gpio_ctla;
3346 + PHY_LE32 gpio_ctlb;
3347 + PHY_LE32 gpio_ctlc;
3348 +};
3349 +
3350 +//U3D_GPIO_CTLA
3351 +#define RG_C60802_GPIO_CTLA (0xffffffff<<0) //31:0
3352 +
3353 +//U3D_GPIO_CTLB
3354 +#define RG_C60802_GPIO_CTLB (0xffffffff<<0) //31:0
3355 +
3356 +//U3D_GPIO_CTLC
3357 +#define RG_C60802_GPIO_CTLC (0xffffffff<<0) //31:0
3358 +
3359 +/* OFFSET */
3360 +
3361 +//U3D_GPIO_CTLA
3362 +#define RG_C60802_GPIO_CTLA_OFST (0)
3363 +
3364 +//U3D_GPIO_CTLB
3365 +#define RG_C60802_GPIO_CTLB_OFST (0)
3366 +
3367 +//U3D_GPIO_CTLC
3368 +#define RG_C60802_GPIO_CTLC_OFST (0)
3369 +
3370 +///////////////////////////////////////////////////////////////////////////////
3371 +
3372 +struct sifslv_fm_feg {
3373 + //0x0
3374 + PHY_LE32 fmcr0;
3375 + PHY_LE32 fmcr1;
3376 + PHY_LE32 fmcr2;
3377 + PHY_LE32 fmmonr0;
3378 + //0x10
3379 + PHY_LE32 fmmonr1;
3380 +};
3381 +
3382 +//U3D_FMCR0
3383 +#define RG_LOCKTH (0xf<<28) //31:28
3384 +#define RG_MONCLK_SEL (0x3<<26) //27:26
3385 +#define RG_FM_MODE (0x1<<25) //25:25
3386 +#define RG_FREQDET_EN (0x1<<24) //24:24
3387 +#define RG_CYCLECNT (0xffffff<<0) //23:0
3388 +
3389 +//U3D_FMCR1
3390 +#define RG_TARGET (0xffffffff<<0) //31:0
3391 +
3392 +//U3D_FMCR2
3393 +#define RG_OFFSET (0xffffffff<<0) //31:0
3394 +
3395 +//U3D_FMMONR0
3396 +#define USB_FM_OUT (0xffffffff<<0) //31:0
3397 +
3398 +//U3D_FMMONR1
3399 +#define RG_MONCLK_SEL_3 (0x1<<9) //9:9
3400 +#define RG_FRCK_EN (0x1<<8) //8:8
3401 +#define USBPLL_LOCK (0x1<<1) //1:1
3402 +#define USB_FM_VLD (0x1<<0) //0:0
3403 +
3404 +
3405 +/* OFFSET */
3406 +
3407 +//U3D_FMCR0
3408 +#define RG_LOCKTH_OFST (28)
3409 +#define RG_MONCLK_SEL_OFST (26)
3410 +#define RG_FM_MODE_OFST (25)
3411 +#define RG_FREQDET_EN_OFST (24)
3412 +#define RG_CYCLECNT_OFST (0)
3413 +
3414 +//U3D_FMCR1
3415 +#define RG_TARGET_OFST (0)
3416 +
3417 +//U3D_FMCR2
3418 +#define RG_OFFSET_OFST (0)
3419 +
3420 +//U3D_FMMONR0
3421 +#define USB_FM_OUT_OFST (0)
3422 +
3423 +//U3D_FMMONR1
3424 +#define RG_MONCLK_SEL_3_OFST (9)
3425 +#define RG_FRCK_EN_OFST (8)
3426 +#define USBPLL_LOCK_OFST (1)
3427 +#define USB_FM_VLD_OFST (0)
3428 +
3429 +
3430 +///////////////////////////////////////////////////////////////////////////////
3431 +
3432 +PHY_INT32 phy_init(struct u3phy_info *info);
3433 +PHY_INT32 phy_change_pipe_phase(struct u3phy_info *info, PHY_INT32 phy_drv, PHY_INT32 pipe_phase);
3434 +PHY_INT32 eyescan_init(struct u3phy_info *info);
3435 +PHY_INT32 phy_eyescan(struct u3phy_info *info, PHY_INT32 x_t1, PHY_INT32 y_t1, PHY_INT32 x_br, PHY_INT32 y_br, PHY_INT32 delta_x, PHY_INT32 delta_y
3436 + , PHY_INT32 eye_cnt, PHY_INT32 num_cnt, PHY_INT32 PI_cal_en, PHY_INT32 num_ignore_cnt);
3437 +PHY_INT32 u2_save_cur_en(struct u3phy_info *info);
3438 +PHY_INT32 u2_save_cur_re(struct u3phy_info *info);
3439 +PHY_INT32 u2_slew_rate_calibration(struct u3phy_info *info);
3440 +
3441 +#endif
3442 +#endif
3443 Index: linux-3.10.44/drivers/usb/host/mtk-phy-ahb.c
3444 ===================================================================
3445 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
3446 +++ linux-3.10.44/drivers/usb/host/mtk-phy-ahb.c 2014-07-02 11:20:15.821675026 +0100
3447 @@ -0,0 +1,58 @@
3448 +#include "mtk-phy.h"
3449 +#ifdef CONFIG_U3D_HAL_SUPPORT
3450 +#include "mu3d_hal_osal.h"
3451 +#endif
3452 +
3453 +#ifdef CONFIG_U3_PHY_AHB_SUPPORT
3454 +#include <linux/gfp.h>
3455 +#include <linux/kernel.h>
3456 +#include <linux/slab.h>
3457 +
3458 +#ifndef CONFIG_U3D_HAL_SUPPORT
3459 +#define os_writel(addr,data) {\
3460 + (*((volatile PHY_UINT32*)(addr)) = data);\
3461 + }
3462 +#define os_readl(addr) *((volatile PHY_UINT32*)(addr))
3463 +#define os_writelmsk(addr, data, msk) \
3464 + { os_writel(addr, ((os_readl(addr) & ~(msk)) | ((data) & (msk)))); \
3465 + }
3466 +#define os_setmsk(addr, msk) \
3467 + { os_writel(addr, os_readl(addr) | msk); \
3468 + }
3469 +#define os_clrmsk(addr, msk) \
3470 + { os_writel(addr, os_readl(addr) &~ msk); \
3471 + }
3472 +/*msk the data first, then umsk with the umsk.*/
3473 +#define os_writelmskumsk(addr, data, msk, umsk) \
3474 +{\
3475 + os_writel(addr, ((os_readl(addr) & ~(msk)) | ((data) & (msk))) & (umsk));\
3476 +}
3477 +
3478 +#endif
3479 +
3480 +PHY_INT32 U3PhyWriteReg32(PHY_UINT32 addr, PHY_UINT32 data)
3481 +{
3482 + os_writel(addr, data);
3483 +
3484 + return 0;
3485 +}
3486 +
3487 +PHY_INT32 U3PhyReadReg32(PHY_UINT32 addr)
3488 +{
3489 + return os_readl(addr);
3490 +}
3491 +
3492 +PHY_INT32 U3PhyWriteReg8(PHY_UINT32 addr, PHY_UINT8 data)
3493 +{
3494 + os_writelmsk(addr&0xfffffffc, data<<((addr%4)*8), 0xff<<((addr%4)*8));
3495 +
3496 + return 0;
3497 +}
3498 +
3499 +PHY_INT8 U3PhyReadReg8(PHY_UINT32 addr)
3500 +{
3501 + return ((os_readl(addr)>>((addr%4)*8))&0xff);
3502 +}
3503 +
3504 +#endif
3505 +
3506 Index: linux-3.10.44/drivers/usb/host/mtk-phy.c
3507 ===================================================================
3508 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
3509 +++ linux-3.10.44/drivers/usb/host/mtk-phy.c 2014-07-02 11:20:15.821675026 +0100
3510 @@ -0,0 +1,102 @@
3511 +#include <linux/gfp.h>
3512 +#include <linux/kernel.h>
3513 +#include <linux/slab.h>
3514 +#define U3_PHY_LIB
3515 +#include "mtk-phy.h"
3516 +#ifdef CONFIG_PROJECT_7621
3517 +#include "mtk-phy-7621.h"
3518 +#endif
3519 +#ifdef CONFIG_PROJECT_PHY
3520 +static struct u3phy_operator project_operators = {
3521 + .init = phy_init,
3522 + .change_pipe_phase = phy_change_pipe_phase,
3523 + .eyescan_init = eyescan_init,
3524 + .eyescan = phy_eyescan,
3525 + .u2_slew_rate_calibration = u2_slew_rate_calibration,
3526 +};
3527 +#endif
3528 +
3529 +
3530 +PHY_INT32 u3phy_init(){
3531 +#ifndef CONFIG_PROJECT_PHY
3532 + PHY_INT32 u3phy_version;
3533 +#endif
3534 +
3535 + if(u3phy != NULL){
3536 + return PHY_TRUE;
3537 + }
3538 +
3539 + u3phy = kmalloc(sizeof(struct u3phy_info), GFP_NOIO);
3540 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
3541 + u3phy_p1 = kmalloc(sizeof(struct u3phy_info), GFP_NOIO);
3542 +#endif
3543 +#ifdef CONFIG_U3_PHY_GPIO_SUPPORT
3544 + u3phy->phyd_version_addr = 0x2000e4;
3545 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
3546 + u3phy_p1->phyd_version_addr = 0x2000e4;
3547 +#endif
3548 +#else
3549 + u3phy->phyd_version_addr = U3_PHYD_B2_BASE + 0xe4;
3550 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
3551 + u3phy_p1->phyd_version_addr = U3_PHYD_B2_BASE_P1 + 0xe4;
3552 +#endif
3553 +#endif
3554 +
3555 +#ifdef CONFIG_PROJECT_PHY
3556 +
3557 + u3phy->u2phy_regs = (struct u2phy_reg *)U2_PHY_BASE;
3558 + u3phy->u3phyd_regs = (struct u3phyd_reg *)U3_PHYD_BASE;
3559 + u3phy->u3phyd_bank2_regs = (struct u3phyd_bank2_reg *)U3_PHYD_B2_BASE;
3560 + u3phy->u3phya_regs = (struct u3phya_reg *)U3_PHYA_BASE;
3561 + u3phy->u3phya_da_regs = (struct u3phya_da_reg *)U3_PHYA_DA_BASE;
3562 + u3phy->sifslv_chip_regs = (struct sifslv_chip_reg *)SIFSLV_CHIP_BASE;
3563 + u3phy->sifslv_fm_regs = (struct sifslv_fm_feg *)SIFSLV_FM_FEG_BASE;
3564 + u3phy_ops = &project_operators;
3565 +
3566 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
3567 + u3phy_p1->u2phy_regs = (struct u2phy_reg *)U2_PHY_BASE_P1;
3568 + u3phy_p1->u3phyd_regs = (struct u3phyd_reg *)U3_PHYD_BASE_P1;
3569 + u3phy_p1->u3phyd_bank2_regs = (struct u3phyd_bank2_reg *)U3_PHYD_B2_BASE_P1;
3570 + u3phy_p1->u3phya_regs = (struct u3phya_reg *)U3_PHYA_BASE_P1;
3571 + u3phy_p1->u3phya_da_regs = (struct u3phya_da_reg *)U3_PHYA_DA_BASE_P1;
3572 + u3phy_p1->sifslv_chip_regs = (struct sifslv_chip_reg *)SIFSLV_CHIP_BASE;
3573 + u3phy_p1->sifslv_fm_regs = (struct sifslv_fm_feg *)SIFSLV_FM_FEG_BASE;
3574 +#endif
3575 +#endif
3576 +
3577 + return PHY_TRUE;
3578 +}
3579 +
3580 +PHY_INT32 U3PhyWriteField8(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask, PHY_INT32 value){
3581 + PHY_INT8 cur_value;
3582 + PHY_INT8 new_value;
3583 +
3584 + cur_value = U3PhyReadReg8(addr);
3585 + new_value = (cur_value & (~mask)) | (value << offset);
3586 + //udelay(i2cdelayus);
3587 + U3PhyWriteReg8(addr, new_value);
3588 + return PHY_TRUE;
3589 +}
3590 +
3591 +PHY_INT32 U3PhyWriteField32(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask, PHY_INT32 value){
3592 + PHY_INT32 cur_value;
3593 + PHY_INT32 new_value;
3594 +
3595 + cur_value = U3PhyReadReg32(addr);
3596 + new_value = (cur_value & (~mask)) | ((value << offset) & mask);
3597 + U3PhyWriteReg32(addr, new_value);
3598 + //DRV_MDELAY(100);
3599 +
3600 + return PHY_TRUE;
3601 +}
3602 +
3603 +PHY_INT32 U3PhyReadField8(PHY_INT32 addr,PHY_INT32 offset,PHY_INT32 mask){
3604 +
3605 + return ((U3PhyReadReg8(addr) & mask) >> offset);
3606 +}
3607 +
3608 +PHY_INT32 U3PhyReadField32(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask){
3609 +
3610 + return ((U3PhyReadReg32(addr) & mask) >> offset);
3611 +}
3612 +
3613 Index: linux-3.10.44/drivers/usb/host/mtk-phy.h
3614 ===================================================================
3615 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
3616 +++ linux-3.10.44/drivers/usb/host/mtk-phy.h 2014-07-02 11:20:15.821675026 +0100
3617 @@ -0,0 +1,179 @@
3618 +#ifndef __MTK_PHY_NEW_H
3619 +#define __MTK_PHY_NEW_H
3620 +
3621 +//#define CONFIG_U3D_HAL_SUPPORT
3622 +
3623 +/* include system library */
3624 +#include <linux/gfp.h>
3625 +#include <linux/kernel.h>
3626 +#include <linux/slab.h>
3627 +#include <linux/delay.h>
3628 +
3629 +/* Choose PHY R/W implementation */
3630 +//#define CONFIG_U3_PHY_GPIO_SUPPORT //SW I2C implemented by GPIO
3631 +#define CONFIG_U3_PHY_AHB_SUPPORT //AHB, only on SoC
3632 +
3633 +/* Choose PHY version */
3634 +//Select your project by defining one of the followings
3635 +#define CONFIG_PROJECT_7621 //7621
3636 +#define CONFIG_PROJECT_PHY
3637 +
3638 +/* BASE ADDRESS DEFINE, should define this on ASIC */
3639 +#define PHY_BASE 0xBE1D0000
3640 +#define SIFSLV_FM_FEG_BASE (PHY_BASE+0x100)
3641 +#define SIFSLV_CHIP_BASE (PHY_BASE+0x700)
3642 +#define U2_PHY_BASE (PHY_BASE+0x800)
3643 +#define U3_PHYD_BASE (PHY_BASE+0x900)
3644 +#define U3_PHYD_B2_BASE (PHY_BASE+0xa00)
3645 +#define U3_PHYA_BASE (PHY_BASE+0xb00)
3646 +#define U3_PHYA_DA_BASE (PHY_BASE+0xc00)
3647 +
3648 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
3649 +#define SIFSLV_FM_FEG_BASE_P1 (PHY_BASE+0x100)
3650 +#define SIFSLV_CHIP_BASE_P1 (PHY_BASE+0x700)
3651 +#define U2_PHY_BASE_P1 (PHY_BASE+0x1000)
3652 +#define U3_PHYD_BASE_P1 (PHY_BASE+0x1100)
3653 +#define U3_PHYD_B2_BASE_P1 (PHY_BASE+0x1200)
3654 +#define U3_PHYA_BASE_P1 (PHY_BASE+0x1300)
3655 +#define U3_PHYA_DA_BASE_P1 (PHY_BASE+0x1400)
3656 +#endif
3657 +
3658 +/*
3659 +
3660 +0x00000100 MODULE ssusb_sifslv_fmreg ssusb_sifslv_fmreg
3661 +0x00000700 MODULE ssusb_sifslv_ippc ssusb_sifslv_ippc
3662 +0x00000800 MODULE ssusb_sifslv_u2phy_com ssusb_sifslv_u2_phy_com_T28
3663 +0x00000900 MODULE ssusb_sifslv_u3phyd ssusb_sifslv_u3phyd_T28
3664 +0x00000a00 MODULE ssusb_sifslv_u3phyd_bank2 ssusb_sifslv_u3phyd_bank2_T28
3665 +0x00000b00 MODULE ssusb_sifslv_u3phya ssusb_sifslv_u3phya_T28
3666 +0x00000c00 MODULE ssusb_sifslv_u3phya_da ssusb_sifslv_u3phya_da_T28
3667 +*/
3668 +
3669 +
3670 +/* TYPE DEFINE */
3671 +typedef unsigned int PHY_UINT32;
3672 +typedef int PHY_INT32;
3673 +typedef unsigned short PHY_UINT16;
3674 +typedef short PHY_INT16;
3675 +typedef unsigned char PHY_UINT8;
3676 +typedef char PHY_INT8;
3677 +
3678 +typedef PHY_UINT32 __bitwise PHY_LE32;
3679 +
3680 +/* CONSTANT DEFINE */
3681 +#define PHY_FALSE 0
3682 +#define PHY_TRUE 1
3683 +
3684 +/* MACRO DEFINE */
3685 +#define DRV_WriteReg32(addr,data) ((*(volatile PHY_UINT32 *)(addr)) = (unsigned long)(data))
3686 +#define DRV_Reg32(addr) (*(volatile PHY_UINT32 *)(addr))
3687 +
3688 +#define DRV_MDELAY mdelay
3689 +#define DRV_MSLEEP msleep
3690 +#define DRV_UDELAY udelay
3691 +#define DRV_USLEEP usleep
3692 +
3693 +/* PHY FUNCTION DEFINE, implemented in platform files, ex. ahb, gpio */
3694 +PHY_INT32 U3PhyWriteReg32(PHY_UINT32 addr, PHY_UINT32 data);
3695 +PHY_INT32 U3PhyReadReg32(PHY_UINT32 addr);
3696 +PHY_INT32 U3PhyWriteReg8(PHY_UINT32 addr, PHY_UINT8 data);
3697 +PHY_INT8 U3PhyReadReg8(PHY_UINT32 addr);
3698 +
3699 +/* PHY GENERAL USAGE FUNC, implemented in mtk-phy.c */
3700 +PHY_INT32 U3PhyWriteField8(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask, PHY_INT32 value);
3701 +PHY_INT32 U3PhyWriteField32(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask, PHY_INT32 value);
3702 +PHY_INT32 U3PhyReadField8(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask);
3703 +PHY_INT32 U3PhyReadField32(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask);
3704 +
3705 +struct u3phy_info {
3706 + PHY_INT32 phy_version;
3707 + PHY_INT32 phyd_version_addr;
3708 +
3709 +#ifdef CONFIG_PROJECT_PHY
3710 + struct u2phy_reg *u2phy_regs;
3711 + struct u3phya_reg *u3phya_regs;
3712 + struct u3phya_da_reg *u3phya_da_regs;
3713 + struct u3phyd_reg *u3phyd_regs;
3714 + struct u3phyd_bank2_reg *u3phyd_bank2_regs;
3715 + struct sifslv_chip_reg *sifslv_chip_regs;
3716 + struct sifslv_fm_feg *sifslv_fm_regs;
3717 +#endif
3718 +};
3719 +
3720 +struct u3phy_operator {
3721 + PHY_INT32 (*init) (struct u3phy_info *info);
3722 + PHY_INT32 (*change_pipe_phase) (struct u3phy_info *info, PHY_INT32 phy_drv, PHY_INT32 pipe_phase);
3723 + PHY_INT32 (*eyescan_init) (struct u3phy_info *info);
3724 + PHY_INT32 (*eyescan) (struct u3phy_info *info, PHY_INT32 x_t1, PHY_INT32 y_t1, PHY_INT32 x_br, PHY_INT32 y_br, PHY_INT32 delta_x, PHY_INT32 delta_y, PHY_INT32 eye_cnt, PHY_INT32 num_cnt, PHY_INT32 PI_cal_en, PHY_INT32 num_ignore_cnt);
3725 + PHY_INT32 (*u2_save_current_entry) (struct u3phy_info *info);
3726 + PHY_INT32 (*u2_save_current_recovery) (struct u3phy_info *info);
3727 + PHY_INT32 (*u2_slew_rate_calibration) (struct u3phy_info *info);
3728 +};
3729 +
3730 +#ifdef U3_PHY_LIB
3731 +#define AUTOEXT
3732 +#else
3733 +#define AUTOEXT extern
3734 +#endif
3735 +
3736 +AUTOEXT struct u3phy_info *u3phy;
3737 +AUTOEXT struct u3phy_info *u3phy_p1;
3738 +AUTOEXT struct u3phy_operator *u3phy_ops;
3739 +
3740 +/*********eye scan required*********/
3741 +
3742 +#define LO_BYTE(x) ((PHY_UINT8)((x) & 0xFF))
3743 +#define HI_BYTE(x) ((PHY_UINT8)(((x) & 0xFF00) >> 8))
3744 +
3745 +typedef enum
3746 +{
3747 + SCAN_UP,
3748 + SCAN_DN
3749 +} enumScanDir;
3750 +
3751 +struct strucScanRegion
3752 +{
3753 + PHY_INT8 bX_tl;
3754 + PHY_INT8 bY_tl;
3755 + PHY_INT8 bX_br;
3756 + PHY_INT8 bY_br;
3757 + PHY_INT8 bDeltaX;
3758 + PHY_INT8 bDeltaY;
3759 +};
3760 +
3761 +struct strucTestCycle
3762 +{
3763 + PHY_UINT16 wEyeCnt;
3764 + PHY_INT8 bNumOfEyeCnt;
3765 + PHY_INT8 bPICalEn;
3766 + PHY_INT8 bNumOfIgnoreCnt;
3767 +};
3768 +
3769 +#define ERRCNT_MAX 128
3770 +#define CYCLE_COUNT_MAX 15
3771 +
3772 +/// the map resolution is 128 x 128 pts
3773 +#define MAX_X 127
3774 +#define MAX_Y 127
3775 +#define MIN_X 0
3776 +#define MIN_Y 0
3777 +
3778 +PHY_INT32 u3phy_init(void);
3779 +
3780 +AUTOEXT struct strucScanRegion _rEye1;
3781 +AUTOEXT struct strucScanRegion _rEye2;
3782 +AUTOEXT struct strucTestCycle _rTestCycle;
3783 +AUTOEXT PHY_UINT8 _bXcurr;
3784 +AUTOEXT PHY_UINT8 _bYcurr;
3785 +AUTOEXT enumScanDir _eScanDir;
3786 +AUTOEXT PHY_INT8 _fgXChged;
3787 +AUTOEXT PHY_INT8 _bPIResult;
3788 +/* use local variable instead to save memory use */
3789 +#if 0
3790 +AUTOEXT PHY_UINT32 pwErrCnt0[CYCLE_COUNT_MAX][ERRCNT_MAX][ERRCNT_MAX];
3791 +AUTOEXT PHY_UINT32 pwErrCnt1[CYCLE_COUNT_MAX][ERRCNT_MAX][ERRCNT_MAX];
3792 +#endif
3793 +
3794 +/***********************************/
3795 +#endif
3796 +
3797 Index: linux-3.10.44/drivers/usb/host/pci-quirks.h
3798 ===================================================================
3799 --- linux-3.10.44.orig/drivers/usb/host/pci-quirks.h 2014-07-02 11:20:14.589675072 +0100
3800 +++ linux-3.10.44/drivers/usb/host/pci-quirks.h 2014-07-02 11:20:15.821675026 +0100
3801 @@ -1,7 +1,7 @@
3802 #ifndef __LINUX_USB_PCI_QUIRKS_H
3803 #define __LINUX_USB_PCI_QUIRKS_H
3804
3805 -#ifdef CONFIG_PCI
3806 +#if defined (CONFIG_PCI) && !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
3807 void uhci_reset_hc(struct pci_dev *pdev, unsigned long base);
3808 int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base);
3809 #endif /* CONFIG_PCI */
3810 Index: linux-3.10.44/drivers/usb/host/xhci-dbg.c
3811 ===================================================================
3812 --- linux-3.10.44.orig/drivers/usb/host/xhci-dbg.c 2014-06-16 21:43:06.000000000 +0100
3813 +++ linux-3.10.44/drivers/usb/host/xhci-dbg.c 2014-07-02 11:20:15.821675026 +0100
3814 @@ -21,6 +21,9 @@
3815 */
3816
3817 #include "xhci.h"
3818 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
3819 +#include "xhci-mtk.h"
3820 +#endif
3821
3822 #define XHCI_INIT_VALUE 0x0
3823
3824 Index: linux-3.10.44/drivers/usb/host/xhci-mem.c
3825 ===================================================================
3826 --- linux-3.10.44.orig/drivers/usb/host/xhci-mem.c 2014-06-16 21:43:06.000000000 +0100
3827 +++ linux-3.10.44/drivers/usb/host/xhci-mem.c 2014-07-02 11:20:15.821675026 +0100
3828 @@ -65,6 +65,9 @@
3829
3830 static void xhci_segment_free(struct xhci_hcd *xhci, struct xhci_segment *seg)
3831 {
3832 + if (!seg)
3833 + return;
3834 +
3835 if (seg->trbs) {
3836 dma_pool_free(xhci->segment_pool, seg->trbs, seg->dma);
3837 seg->trbs = NULL;
3838 @@ -1446,9 +1449,17 @@
3839 max_burst = (usb_endpoint_maxp(&ep->desc)
3840 & 0x1800) >> 11;
3841 }
3842 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
3843 + if ((max_packet % 4 == 2) && (max_packet % 16 != 14) && (max_burst == 0) && usb_endpoint_dir_in(&ep->desc))
3844 + max_packet += 2;
3845 +#endif
3846 break;
3847 case USB_SPEED_FULL:
3848 case USB_SPEED_LOW:
3849 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
3850 + if ((max_packet % 4 == 2) && (max_packet % 16 != 14) && (max_burst == 0) && usb_endpoint_dir_in(&ep->desc))
3851 + max_packet += 2;
3852 +#endif
3853 break;
3854 default:
3855 BUG();
3856 Index: linux-3.10.44/drivers/usb/host/xhci-mtk-power.c
3857 ===================================================================
3858 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
3859 +++ linux-3.10.44/drivers/usb/host/xhci-mtk-power.c 2014-07-02 11:20:15.821675026 +0100
3860 @@ -0,0 +1,115 @@
3861 +#include "xhci-mtk.h"
3862 +#include "xhci-mtk-power.h"
3863 +#include "xhci.h"
3864 +#include <linux/kernel.h> /* printk() */
3865 +#include <linux/slab.h>
3866 +#include <linux/delay.h>
3867 +
3868 +static int g_num_u3_port;
3869 +static int g_num_u2_port;
3870 +
3871 +
3872 +void enableXhciAllPortPower(struct xhci_hcd *xhci){
3873 + int i;
3874 + u32 port_id, temp;
3875 + u32 __iomem *addr;
3876 +
3877 + g_num_u3_port = SSUSB_U3_PORT_NUM(readl(SSUSB_IP_CAP));
3878 + g_num_u2_port = SSUSB_U2_PORT_NUM(readl(SSUSB_IP_CAP));
3879 +
3880 + for(i=1; i<=g_num_u3_port; i++){
3881 + port_id=i;
3882 + addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(port_id-1 & 0xff);
3883 + temp = xhci_readl(xhci, addr);
3884 + temp = xhci_port_state_to_neutral(temp);
3885 + temp |= PORT_POWER;
3886 + xhci_writel(xhci, temp, addr);
3887 + }
3888 + for(i=1; i<=g_num_u2_port; i++){
3889 + port_id=i+g_num_u3_port;
3890 + addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(port_id-1 & 0xff);
3891 + temp = xhci_readl(xhci, addr);
3892 + temp = xhci_port_state_to_neutral(temp);
3893 + temp |= PORT_POWER;
3894 + xhci_writel(xhci, temp, addr);
3895 + }
3896 +}
3897 +
3898 +void enableAllClockPower(){
3899 +
3900 + int i;
3901 + u32 temp;
3902 +
3903 + g_num_u3_port = SSUSB_U3_PORT_NUM(readl(SSUSB_IP_CAP));
3904 + g_num_u2_port = SSUSB_U2_PORT_NUM(readl(SSUSB_IP_CAP));
3905 +
3906 + //2. Enable xHC
3907 + writel(readl(SSUSB_IP_PW_CTRL) | (SSUSB_IP_SW_RST), SSUSB_IP_PW_CTRL);
3908 + writel(readl(SSUSB_IP_PW_CTRL) & (~SSUSB_IP_SW_RST), SSUSB_IP_PW_CTRL);
3909 + writel(readl(SSUSB_IP_PW_CTRL_1) & (~SSUSB_IP_PDN), SSUSB_IP_PW_CTRL_1);
3910 +
3911 + //1. Enable target ports
3912 + for(i=0; i<g_num_u3_port; i++){
3913 + temp = readl(SSUSB_U3_CTRL(i));
3914 + temp = temp & (~SSUSB_U3_PORT_PDN) & (~SSUSB_U3_PORT_DIS);
3915 + writel(temp, SSUSB_U3_CTRL(i));
3916 + }
3917 + for(i=0; i<g_num_u2_port; i++){
3918 + temp = readl(SSUSB_U2_CTRL(i));
3919 + temp = temp & (~SSUSB_U2_PORT_PDN) & (~SSUSB_U2_PORT_DIS);
3920 + writel(temp, SSUSB_U2_CTRL(i));
3921 + }
3922 + msleep(100);
3923 +}
3924 +
3925 +
3926 +//(X)disable clock/power of a port
3927 +//(X)if all ports are disabled, disable IP ctrl power
3928 +//disable all ports and IP clock/power, this is just mention HW that the power/clock of port
3929 +//and IP could be disable if suspended.
3930 +//If doesn't not disable all ports at first, the IP clock/power will never be disabled
3931 +//(some U2 and U3 ports are binded to the same connection, that is, they will never enter suspend at the same time
3932 +//port_index: port number
3933 +//port_rev: 0x2 - USB2.0, 0x3 - USB3.0 (SuperSpeed)
3934 +void disablePortClockPower(void){
3935 + int i;
3936 + u32 temp;
3937 +
3938 + g_num_u3_port = SSUSB_U3_PORT_NUM(readl(SSUSB_IP_CAP));
3939 + g_num_u2_port = SSUSB_U2_PORT_NUM(readl(SSUSB_IP_CAP));
3940 +
3941 + for(i=0; i<g_num_u3_port; i++){
3942 + temp = readl(SSUSB_U3_CTRL(i));
3943 + temp = temp | (SSUSB_U3_PORT_PDN);
3944 + writel(temp, SSUSB_U3_CTRL(i));
3945 + }
3946 + for(i=0; i<g_num_u2_port; i++){
3947 + temp = readl(SSUSB_U2_CTRL(i));
3948 + temp = temp | (SSUSB_U2_PORT_PDN);
3949 + writel(temp, SSUSB_U2_CTRL(i));
3950 + }
3951 + writel(readl(SSUSB_IP_PW_CTRL_1) | (SSUSB_IP_PDN), SSUSB_IP_PW_CTRL_1);
3952 +}
3953 +
3954 +//if IP ctrl power is disabled, enable it
3955 +//enable clock/power of a port
3956 +//port_index: port number
3957 +//port_rev: 0x2 - USB2.0, 0x3 - USB3.0 (SuperSpeed)
3958 +void enablePortClockPower(int port_index, int port_rev){
3959 + int i;
3960 + u32 temp;
3961 +
3962 + writel(readl(SSUSB_IP_PW_CTRL_1) & (~SSUSB_IP_PDN), SSUSB_IP_PW_CTRL_1);
3963 +
3964 + if(port_rev == 0x3){
3965 + temp = readl(SSUSB_U3_CTRL(port_index));
3966 + temp = temp & (~SSUSB_U3_PORT_PDN);
3967 + writel(temp, SSUSB_U3_CTRL(port_index));
3968 + }
3969 + else if(port_rev == 0x2){
3970 + temp = readl(SSUSB_U2_CTRL(port_index));
3971 + temp = temp & (~SSUSB_U2_PORT_PDN);
3972 + writel(temp, SSUSB_U2_CTRL(port_index));
3973 + }
3974 +}
3975 +
3976 Index: linux-3.10.44/drivers/usb/host/xhci-mtk-power.h
3977 ===================================================================
3978 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
3979 +++ linux-3.10.44/drivers/usb/host/xhci-mtk-power.h 2014-07-02 11:20:15.821675026 +0100
3980 @@ -0,0 +1,13 @@
3981 +#ifndef _XHCI_MTK_POWER_H
3982 +#define _XHCI_MTK_POWER_H
3983 +
3984 +#include <linux/usb.h>
3985 +#include "xhci.h"
3986 +#include "xhci-mtk.h"
3987 +
3988 +void enableXhciAllPortPower(struct xhci_hcd *xhci);
3989 +void enableAllClockPower(void);
3990 +void disablePortClockPower(void);
3991 +void enablePortClockPower(int port_index, int port_rev);
3992 +
3993 +#endif
3994 Index: linux-3.10.44/drivers/usb/host/xhci-mtk-scheduler.c
3995 ===================================================================
3996 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
3997 +++ linux-3.10.44/drivers/usb/host/xhci-mtk-scheduler.c 2014-07-02 11:20:15.821675026 +0100
3998 @@ -0,0 +1,608 @@
3999 +#include "xhci-mtk-scheduler.h"
4000 +#include <linux/kernel.h> /* printk() */
4001 +
4002 +static struct sch_ep **ss_out_eps[MAX_EP_NUM];
4003 +static struct sch_ep **ss_in_eps[MAX_EP_NUM];
4004 +static struct sch_ep **hs_eps[MAX_EP_NUM]; //including tt isoc
4005 +static struct sch_ep **tt_intr_eps[MAX_EP_NUM];
4006 +
4007 +
4008 +int mtk_xhci_scheduler_init(void){
4009 + int i;
4010 +
4011 + for(i=0; i<MAX_EP_NUM; i++){
4012 + ss_out_eps[i] = NULL;
4013 + }
4014 + for(i=0; i<MAX_EP_NUM; i++){
4015 + ss_in_eps[i] = NULL;
4016 + }
4017 + for(i=0; i<MAX_EP_NUM; i++){
4018 + hs_eps[i] = NULL;
4019 + }
4020 + for(i=0; i<MAX_EP_NUM; i++){
4021 + tt_intr_eps[i] = NULL;
4022 + }
4023 + return 0;
4024 +}
4025 +
4026 +int add_sch_ep(int dev_speed, int is_in, int isTT, int ep_type, int maxp, int interval, int burst
4027 + , int mult, int offset, int repeat, int pkts, int cs_count, int burst_mode
4028 + , int bw_cost, mtk_u32 *ep, struct sch_ep *tmp_ep){
4029 +
4030 + struct sch_ep **ep_array;
4031 + int i;
4032 +
4033 + if(is_in && dev_speed == USB_SPEED_SUPER ){
4034 + ep_array = (struct sch_ep **)ss_in_eps;
4035 + }
4036 + else if(dev_speed == USB_SPEED_SUPER){
4037 + ep_array = (struct sch_ep **)ss_out_eps;
4038 + }
4039 + else if(dev_speed == USB_SPEED_HIGH || (isTT && ep_type == USB_EP_ISOC)){
4040 + ep_array = (struct sch_ep **)hs_eps;
4041 + }
4042 + else{
4043 + ep_array = (struct sch_ep **)tt_intr_eps;
4044 + }
4045 + for(i=0; i<MAX_EP_NUM; i++){
4046 + if(ep_array[i] == NULL){
4047 + tmp_ep->dev_speed = dev_speed;
4048 + tmp_ep->isTT = isTT;
4049 + tmp_ep->is_in = is_in;
4050 + tmp_ep->ep_type = ep_type;
4051 + tmp_ep->maxp = maxp;
4052 + tmp_ep->interval = interval;
4053 + tmp_ep->burst = burst;
4054 + tmp_ep->mult = mult;
4055 + tmp_ep->offset = offset;
4056 + tmp_ep->repeat = repeat;
4057 + tmp_ep->pkts = pkts;
4058 + tmp_ep->cs_count = cs_count;
4059 + tmp_ep->burst_mode = burst_mode;
4060 + tmp_ep->bw_cost = bw_cost;
4061 + tmp_ep->ep = ep;
4062 + ep_array[i] = tmp_ep;
4063 + return SCH_SUCCESS;
4064 + }
4065 + }
4066 + return SCH_FAIL;
4067 +}
4068 +
4069 +int count_ss_bw(int is_in, int ep_type, int maxp, int interval, int burst, int mult, int offset, int repeat
4070 + , int td_size){
4071 + int i, j, k;
4072 + int bw_required[3];
4073 + int final_bw_required;
4074 + int bw_required_per_repeat;
4075 + int tmp_bw_required;
4076 + struct sch_ep *cur_sch_ep;
4077 + struct sch_ep **ep_array;
4078 + int cur_offset;
4079 + int cur_ep_offset;
4080 + int tmp_offset;
4081 + int tmp_interval;
4082 + int ep_offset;
4083 + int ep_interval;
4084 + int ep_repeat;
4085 + int ep_mult;
4086 +
4087 + if(is_in){
4088 + ep_array = (struct sch_ep **)ss_in_eps;
4089 + }
4090 + else{
4091 + ep_array = (struct sch_ep **)ss_out_eps;
4092 + }
4093 +
4094 + bw_required[0] = 0;
4095 + bw_required[1] = 0;
4096 + bw_required[2] = 0;
4097 +
4098 + if(repeat == 0){
4099 + final_bw_required = 0;
4100 + for(i=0; i<MAX_EP_NUM; i++){
4101 + cur_sch_ep = ep_array[i];
4102 + if(cur_sch_ep == NULL){
4103 + continue;
4104 + }
4105 + ep_interval = cur_sch_ep->interval;
4106 + ep_offset = cur_sch_ep->offset;
4107 + if(cur_sch_ep->repeat == 0){
4108 + if(ep_interval >= interval){
4109 + tmp_offset = ep_offset + ep_interval - offset;
4110 + tmp_interval = interval;
4111 + }
4112 + else{
4113 + tmp_offset = offset + interval - ep_offset;
4114 + tmp_interval = ep_interval;
4115 + }
4116 + if(tmp_offset % tmp_interval == 0){
4117 + final_bw_required += cur_sch_ep->bw_cost;
4118 + }
4119 + }
4120 + else{
4121 + ep_repeat = cur_sch_ep->repeat;
4122 + ep_mult = cur_sch_ep->mult;
4123 + for(k=0; k<=ep_mult; k++){
4124 + cur_ep_offset = ep_offset+(k*ep_mult);
4125 + if(ep_interval >= interval){
4126 + tmp_offset = cur_ep_offset + ep_interval - offset;
4127 + tmp_interval = interval;
4128 + }
4129 + else{
4130 + tmp_offset = offset + interval - cur_ep_offset;
4131 + tmp_interval = ep_interval;
4132 + }
4133 + if(tmp_offset % tmp_interval == 0){
4134 + final_bw_required += cur_sch_ep->bw_cost;
4135 + break;
4136 + }
4137 + }
4138 + }
4139 + }
4140 + final_bw_required += td_size;
4141 + }
4142 + else{
4143 + bw_required_per_repeat = maxp * (burst+1);
4144 + for(j=0; j<=mult; j++){
4145 + tmp_bw_required = 0;
4146 + cur_offset = offset+(j*repeat);
4147 + for(i=0; i<MAX_EP_NUM; i++){
4148 + cur_sch_ep = ep_array[i];
4149 + if(cur_sch_ep == NULL){
4150 + continue;
4151 + }
4152 + ep_interval = cur_sch_ep->interval;
4153 + ep_offset = cur_sch_ep->offset;
4154 + if(cur_sch_ep->repeat == 0){
4155 + if(ep_interval >= interval){
4156 + tmp_offset = ep_offset + ep_interval - cur_offset;
4157 + tmp_interval = interval;
4158 + }
4159 + else{
4160 + tmp_offset = cur_offset + interval - ep_offset;
4161 + tmp_interval = ep_interval;
4162 + }
4163 + if(tmp_offset % tmp_interval == 0){
4164 + tmp_bw_required += cur_sch_ep->bw_cost;
4165 + }
4166 + }
4167 + else{
4168 + ep_repeat = cur_sch_ep->repeat;
4169 + ep_mult = cur_sch_ep->mult;
4170 + for(k=0; k<=ep_mult; k++){
4171 + cur_ep_offset = ep_offset+(k*ep_repeat);
4172 + if(ep_interval >= interval){
4173 + tmp_offset = cur_ep_offset + ep_interval - cur_offset;
4174 + tmp_interval = interval;
4175 + }
4176 + else{
4177 + tmp_offset = cur_offset + interval - cur_ep_offset;
4178 + tmp_interval = ep_interval;
4179 + }
4180 + if(tmp_offset % tmp_interval == 0){
4181 + tmp_bw_required += cur_sch_ep->bw_cost;
4182 + break;
4183 + }
4184 + }
4185 + }
4186 + }
4187 + bw_required[j] = tmp_bw_required;
4188 + }
4189 + final_bw_required = SS_BW_BOUND;
4190 + for(j=0; j<=mult; j++){
4191 + if(bw_required[j] < final_bw_required){
4192 + final_bw_required = bw_required[j];
4193 + }
4194 + }
4195 + final_bw_required += bw_required_per_repeat;
4196 + }
4197 + return final_bw_required;
4198 +}
4199 +
4200 +int count_hs_bw(int ep_type, int maxp, int interval, int offset, int td_size){
4201 + int i;
4202 + int bw_required;
4203 + struct sch_ep *cur_sch_ep;
4204 + int tmp_offset;
4205 + int tmp_interval;
4206 + int ep_offset;
4207 + int ep_interval;
4208 + int cur_tt_isoc_interval; //for isoc tt check
4209 +
4210 + bw_required = 0;
4211 + for(i=0; i<MAX_EP_NUM; i++){
4212 +
4213 + cur_sch_ep = (struct sch_ep *)hs_eps[i];
4214 + if(cur_sch_ep == NULL){
4215 + continue;
4216 + }
4217 + ep_offset = cur_sch_ep->offset;
4218 + ep_interval = cur_sch_ep->interval;
4219 +
4220 + if(cur_sch_ep->isTT && cur_sch_ep->ep_type == USB_EP_ISOC){
4221 + cur_tt_isoc_interval = ep_interval<<3;
4222 + if(ep_interval >= interval){
4223 + tmp_offset = ep_offset + cur_tt_isoc_interval - offset;
4224 + tmp_interval = interval;
4225 + }
4226 + else{
4227 + tmp_offset = offset + interval - ep_offset;
4228 + tmp_interval = cur_tt_isoc_interval;
4229 + }
4230 + if(cur_sch_ep->is_in){
4231 + if((tmp_offset%tmp_interval >=2) && (tmp_offset%tmp_interval <= cur_sch_ep->cs_count)){
4232 + bw_required += 188;
4233 + }
4234 + }
4235 + else{
4236 + if(tmp_offset%tmp_interval <= cur_sch_ep->cs_count){
4237 + bw_required += 188;
4238 + }
4239 + }
4240 + }
4241 + else{
4242 + if(ep_interval >= interval){
4243 + tmp_offset = ep_offset + ep_interval - offset;
4244 + tmp_interval = interval;
4245 + }
4246 + else{
4247 + tmp_offset = offset + interval - ep_offset;
4248 + tmp_interval = ep_interval;
4249 + }
4250 + if(tmp_offset%tmp_interval == 0){
4251 + bw_required += cur_sch_ep->bw_cost;
4252 + }
4253 + }
4254 + }
4255 + bw_required += td_size;
4256 + return bw_required;
4257 +}
4258 +
4259 +int count_tt_isoc_bw(int is_in, int maxp, int interval, int offset, int td_size){
4260 + char is_cs;
4261 + int mframe_idx, frame_idx, s_frame, s_mframe, cur_mframe;
4262 + int bw_required, max_bw;
4263 + int ss_cs_count;
4264 + int cs_mframe;
4265 + int max_frame;
4266 + int i,j;
4267 + struct sch_ep *cur_sch_ep;
4268 + int ep_offset;
4269 + int ep_interval;
4270 + int ep_cs_count;
4271 + int tt_isoc_interval; //for isoc tt check
4272 + int cur_tt_isoc_interval; //for isoc tt check
4273 + int tmp_offset;
4274 + int tmp_interval;
4275 +
4276 + is_cs = 0;
4277 +
4278 + tt_isoc_interval = interval<<3; //frame to mframe
4279 + if(is_in){
4280 + is_cs = 1;
4281 + }
4282 + s_frame = offset/8;
4283 + s_mframe = offset%8;
4284 + ss_cs_count = (maxp + (188 - 1))/188;
4285 + if(is_cs){
4286 + cs_mframe = offset%8 + 2 + ss_cs_count;
4287 + if (cs_mframe <= 6)
4288 + ss_cs_count += 2;
4289 + else if (cs_mframe == 7)
4290 + ss_cs_count++;
4291 + else if (cs_mframe > 8)
4292 + return -1;
4293 + }
4294 + max_bw = 0;
4295 + if(is_in){
4296 + i=2;
4297 + }
4298 + for(cur_mframe = offset+i; i<ss_cs_count; cur_mframe++, i++){
4299 + bw_required = 0;
4300 + for(j=0; j<MAX_EP_NUM; j++){
4301 + cur_sch_ep = (struct sch_ep *)hs_eps[j];
4302 + if(cur_sch_ep == NULL){
4303 + continue;
4304 + }
4305 + ep_offset = cur_sch_ep->offset;
4306 + ep_interval = cur_sch_ep->interval;
4307 + if(cur_sch_ep->isTT && cur_sch_ep->ep_type == USB_EP_ISOC){
4308 + //isoc tt
4309 + //check if mframe offset overlap
4310 + //if overlap, add 188 to the bw
4311 + cur_tt_isoc_interval = ep_interval<<3;
4312 + if(cur_tt_isoc_interval >= tt_isoc_interval){
4313 + tmp_offset = (ep_offset+cur_tt_isoc_interval) - cur_mframe;
4314 + tmp_interval = tt_isoc_interval;
4315 + }
4316 + else{
4317 + tmp_offset = (cur_mframe+tt_isoc_interval) - ep_offset;
4318 + tmp_interval = cur_tt_isoc_interval;
4319 + }
4320 + if(cur_sch_ep->is_in){
4321 + if((tmp_offset%tmp_interval >=2) && (tmp_offset%tmp_interval <= cur_sch_ep->cs_count)){
4322 + bw_required += 188;
4323 + }
4324 + }
4325 + else{
4326 + if(tmp_offset%tmp_interval <= cur_sch_ep->cs_count){
4327 + bw_required += 188;
4328 + }
4329 + }
4330 +
4331 + }
4332 + else if(cur_sch_ep->ep_type == USB_EP_INT || cur_sch_ep->ep_type == USB_EP_ISOC){
4333 + //check if mframe
4334 + if(ep_interval >= tt_isoc_interval){
4335 + tmp_offset = (ep_offset+ep_interval) - cur_mframe;
4336 + tmp_interval = tt_isoc_interval;
4337 + }
4338 + else{
4339 + tmp_offset = (cur_mframe+tt_isoc_interval) - ep_offset;
4340 + tmp_interval = ep_interval;
4341 + }
4342 + if(tmp_offset%tmp_interval == 0){
4343 + bw_required += cur_sch_ep->bw_cost;
4344 + }
4345 + }
4346 + }
4347 + bw_required += 188;
4348 + if(bw_required > max_bw){
4349 + max_bw = bw_required;
4350 + }
4351 + }
4352 + return max_bw;
4353 +}
4354 +
4355 +int count_tt_intr_bw(int interval, int frame_offset){
4356 + //check all eps in tt_intr_eps
4357 + int ret;
4358 + int i,j;
4359 + int ep_offset;
4360 + int ep_interval;
4361 + int tmp_offset;
4362 + int tmp_interval;
4363 + ret = SCH_SUCCESS;
4364 + struct sch_ep *cur_sch_ep;
4365 +
4366 + for(i=0; i<MAX_EP_NUM; i++){
4367 + cur_sch_ep = (struct sch_ep *)tt_intr_eps[i];
4368 + if(cur_sch_ep == NULL){
4369 + continue;
4370 + }
4371 + ep_offset = cur_sch_ep->offset;
4372 + ep_interval = cur_sch_ep->interval;
4373 + if(ep_interval >= interval){
4374 + tmp_offset = ep_offset + ep_interval - frame_offset;
4375 + tmp_interval = interval;
4376 + }
4377 + else{
4378 + tmp_offset = frame_offset + interval - ep_offset;
4379 + tmp_interval = ep_interval;
4380 + }
4381 +
4382 + if(tmp_offset%tmp_interval==0){
4383 + return SCH_FAIL;
4384 + }
4385 + }
4386 + return SCH_SUCCESS;
4387 +}
4388 +
4389 +struct sch_ep * mtk_xhci_scheduler_remove_ep(int dev_speed, int is_in, int isTT, int ep_type, mtk_u32 *ep){
4390 + int i;
4391 + struct sch_ep **ep_array;
4392 + struct sch_ep *cur_ep;
4393 +
4394 + if (is_in && dev_speed == USB_SPEED_SUPER) {
4395 + ep_array = (struct sch_ep **)ss_in_eps;
4396 + }
4397 + else if (dev_speed == USB_SPEED_SUPER) {
4398 + ep_array = (struct sch_ep **)ss_out_eps;
4399 + }
4400 + else if (dev_speed == USB_SPEED_HIGH || (isTT && ep_type == USB_EP_ISOC)) {
4401 + ep_array = (struct sch_ep **)hs_eps;
4402 + }
4403 + else {
4404 + ep_array = (struct sch_ep **)tt_intr_eps;
4405 + }
4406 + for (i = 0; i < MAX_EP_NUM; i++) {
4407 + cur_ep = (struct sch_ep *)ep_array[i];
4408 + if(cur_ep != NULL && cur_ep->ep == ep){
4409 + ep_array[i] = NULL;
4410 + return cur_ep;
4411 + }
4412 + }
4413 + return NULL;
4414 +}
4415 +
4416 +int mtk_xhci_scheduler_add_ep(int dev_speed, int is_in, int isTT, int ep_type, int maxp, int interval, int burst
4417 + , int mult, mtk_u32 *ep, mtk_u32 *ep_ctx, struct sch_ep *sch_ep){
4418 + mtk_u32 bPkts = 0;
4419 + mtk_u32 bCsCount = 0;
4420 + mtk_u32 bBm = 1;
4421 + mtk_u32 bOffset = 0;
4422 + mtk_u32 bRepeat = 0;
4423 + int ret;
4424 + struct mtk_xhci_ep_ctx *temp_ep_ctx;
4425 + int td_size;
4426 + int mframe_idx, frame_idx;
4427 + int bw_cost;
4428 + int cur_bw, best_bw, best_bw_idx,repeat, max_repeat, best_bw_repeat;
4429 + int cur_offset, cs_mframe;
4430 + int break_out;
4431 + int frame_interval;
4432 +
4433 + printk(KERN_ERR "add_ep parameters, dev_speed %d, is_in %d, isTT %d, ep_type %d, maxp %d, interval %d, burst %d, mult %d, ep 0x%x, ep_ctx 0x%x, sch_ep 0x%x\n", dev_speed, is_in, isTT, ep_type, maxp
4434 + , interval, burst, mult, ep, ep_ctx, sch_ep);
4435 + if(isTT && ep_type == USB_EP_INT && ((dev_speed == USB_SPEED_LOW) || (dev_speed == USB_SPEED_FULL))){
4436 + frame_interval = interval >> 3;
4437 + for(frame_idx=0; frame_idx<frame_interval; frame_idx++){
4438 + printk(KERN_ERR "check tt_intr_bw interval %d, frame_idx %d\n", frame_interval, frame_idx);
4439 + if(count_tt_intr_bw(frame_interval, frame_idx) == SCH_SUCCESS){
4440 + printk(KERN_ERR "check OK............\n");
4441 + bOffset = frame_idx<<3;
4442 + bPkts = 1;
4443 + bCsCount = 3;
4444 + bw_cost = maxp;
4445 + bRepeat = 0;
4446 + if(add_sch_ep(dev_speed, is_in, isTT, ep_type, maxp, frame_interval, burst, mult
4447 + , bOffset, bRepeat, bPkts, bCsCount, bBm, maxp, ep, sch_ep) == SCH_FAIL){
4448 + return SCH_FAIL;
4449 + }
4450 + ret = SCH_SUCCESS;
4451 + break;
4452 + }
4453 + }
4454 + }
4455 + else if(isTT && ep_type == USB_EP_ISOC){
4456 + best_bw = HS_BW_BOUND;
4457 + best_bw_idx = -1;
4458 + cur_bw = 0;
4459 + td_size = maxp;
4460 + break_out = 0;
4461 + frame_interval = interval>>3;
4462 + for(frame_idx=0; frame_idx<frame_interval && !break_out; frame_idx++){
4463 + for(mframe_idx=0; mframe_idx<8; mframe_idx++){
4464 + cur_offset = (frame_idx*8) + mframe_idx;
4465 + cur_bw = count_tt_isoc_bw(is_in, maxp, frame_interval, cur_offset, td_size);
4466 + if(cur_bw > 0 && cur_bw < best_bw){
4467 + best_bw_idx = cur_offset;
4468 + best_bw = cur_bw;
4469 + if(cur_bw == td_size || cur_bw < (HS_BW_BOUND>>1)){
4470 + break_out = 1;
4471 + break;
4472 + }
4473 + }
4474 + }
4475 + }
4476 + if(best_bw_idx == -1){
4477 + return SCH_FAIL;
4478 + }
4479 + else{
4480 + bOffset = best_bw_idx;
4481 + bPkts = 1;
4482 + bCsCount = (maxp + (188 - 1)) / 188;
4483 + if(is_in){
4484 + cs_mframe = bOffset%8 + 2 + bCsCount;
4485 + if (cs_mframe <= 6)
4486 + bCsCount += 2;
4487 + else if (cs_mframe == 7)
4488 + bCsCount++;
4489 + }
4490 + bw_cost = 188;
4491 + bRepeat = 0;
4492 + if(add_sch_ep( dev_speed, is_in, isTT, ep_type, maxp, interval, burst, mult
4493 + , bOffset, bRepeat, bPkts, bCsCount, bBm, bw_cost, ep, sch_ep) == SCH_FAIL){
4494 + return SCH_FAIL;
4495 + }
4496 + ret = SCH_SUCCESS;
4497 + }
4498 + }
4499 + else if((dev_speed == USB_SPEED_FULL || dev_speed == USB_SPEED_LOW) && ep_type == USB_EP_INT){
4500 + bPkts = 1;
4501 + ret = SCH_SUCCESS;
4502 + }
4503 + else if(dev_speed == USB_SPEED_FULL && ep_type == USB_EP_ISOC){
4504 + bPkts = 1;
4505 + ret = SCH_SUCCESS;
4506 + }
4507 + else if(dev_speed == USB_SPEED_HIGH && (ep_type == USB_EP_INT || ep_type == USB_EP_ISOC)){
4508 + best_bw = HS_BW_BOUND;
4509 + best_bw_idx = -1;
4510 + cur_bw = 0;
4511 + td_size = maxp*(burst+1);
4512 + for(cur_offset = 0; cur_offset<interval; cur_offset++){
4513 + cur_bw = count_hs_bw(ep_type, maxp, interval, cur_offset, td_size);
4514 + if(cur_bw > 0 && cur_bw < best_bw){
4515 + best_bw_idx = cur_offset;
4516 + best_bw = cur_bw;
4517 + if(cur_bw == td_size || cur_bw < (HS_BW_BOUND>>1)){
4518 + break;
4519 + }
4520 + }
4521 + }
4522 + if(best_bw_idx == -1){
4523 + return SCH_FAIL;
4524 + }
4525 + else{
4526 + bOffset = best_bw_idx;
4527 + bPkts = burst + 1;
4528 + bCsCount = 0;
4529 + bw_cost = td_size;
4530 + bRepeat = 0;
4531 + if(add_sch_ep(dev_speed, is_in, isTT, ep_type, maxp, interval, burst, mult
4532 + , bOffset, bRepeat, bPkts, bCsCount, bBm, bw_cost, ep, sch_ep) == SCH_FAIL){
4533 + return SCH_FAIL;
4534 + }
4535 + ret = SCH_SUCCESS;
4536 + }
4537 + }
4538 + else if(dev_speed == USB_SPEED_SUPER && (ep_type == USB_EP_INT || ep_type == USB_EP_ISOC)){
4539 + best_bw = SS_BW_BOUND;
4540 + best_bw_idx = -1;
4541 + cur_bw = 0;
4542 + td_size = maxp * (mult+1) * (burst+1);
4543 + if(mult == 0){
4544 + max_repeat = 0;
4545 + }
4546 + else{
4547 + max_repeat = (interval-1)/(mult+1);
4548 + }
4549 + break_out = 0;
4550 + for(frame_idx = 0; (frame_idx < interval) && !break_out; frame_idx++){
4551 + for(repeat = max_repeat; repeat >= 0; repeat--){
4552 + cur_bw = count_ss_bw(is_in, ep_type, maxp, interval, burst, mult, frame_idx
4553 + , repeat, td_size);
4554 + printk(KERN_ERR "count_ss_bw, frame_idx %d, repeat %d, td_size %d, result bw %d\n"
4555 + , frame_idx, repeat, td_size, cur_bw);
4556 + if(cur_bw > 0 && cur_bw < best_bw){
4557 + best_bw_idx = frame_idx;
4558 + best_bw_repeat = repeat;
4559 + best_bw = cur_bw;
4560 + if(cur_bw <= td_size || cur_bw < (HS_BW_BOUND>>1)){
4561 + break_out = 1;
4562 + break;
4563 + }
4564 + }
4565 + }
4566 + }
4567 + printk(KERN_ERR "final best idx %d, best repeat %d\n", best_bw_idx, best_bw_repeat);
4568 + if(best_bw_idx == -1){
4569 + return SCH_FAIL;
4570 + }
4571 + else{
4572 + bOffset = best_bw_idx;
4573 + bCsCount = 0;
4574 + bRepeat = best_bw_repeat;
4575 + if(bRepeat == 0){
4576 + bw_cost = (burst+1)*(mult+1)*maxp;
4577 + bPkts = (burst+1)*(mult+1);
4578 + }
4579 + else{
4580 + bw_cost = (burst+1)*maxp;
4581 + bPkts = (burst+1);
4582 + }
4583 + if(add_sch_ep(dev_speed, is_in, isTT, ep_type, maxp, interval, burst, mult
4584 + , bOffset, bRepeat, bPkts, bCsCount, bBm, bw_cost, ep, sch_ep) == SCH_FAIL){
4585 + return SCH_FAIL;
4586 + }
4587 + ret = SCH_SUCCESS;
4588 + }
4589 + }
4590 + else{
4591 + bPkts = 1;
4592 + ret = SCH_SUCCESS;
4593 + }
4594 + if(ret == SCH_SUCCESS){
4595 + temp_ep_ctx = (struct mtk_xhci_ep_ctx *)ep_ctx;
4596 + temp_ep_ctx->reserved[0] |= (BPKTS(bPkts) | BCSCOUNT(bCsCount) | BBM(bBm));
4597 + temp_ep_ctx->reserved[1] |= (BOFFSET(bOffset) | BREPEAT(bRepeat));
4598 +
4599 + printk(KERN_DEBUG "[DBG] BPKTS: %x, BCSCOUNT: %x, BBM: %x\n", bPkts, bCsCount, bBm);
4600 + printk(KERN_DEBUG "[DBG] BOFFSET: %x, BREPEAT: %x\n", bOffset, bRepeat);
4601 + return SCH_SUCCESS;
4602 + }
4603 + else{
4604 + return SCH_FAIL;
4605 + }
4606 +}
4607 Index: linux-3.10.44/drivers/usb/host/xhci-mtk-scheduler.h
4608 ===================================================================
4609 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
4610 +++ linux-3.10.44/drivers/usb/host/xhci-mtk-scheduler.h 2014-07-02 11:20:15.821675026 +0100
4611 @@ -0,0 +1,77 @@
4612 +#ifndef _XHCI_MTK_SCHEDULER_H
4613 +#define _XHCI_MTK_SCHEDULER_H
4614 +
4615 +#define MTK_SCH_NEW 1
4616 +
4617 +#define SCH_SUCCESS 1
4618 +#define SCH_FAIL 0
4619 +
4620 +#define MAX_EP_NUM 64
4621 +#define SS_BW_BOUND 51000
4622 +#define HS_BW_BOUND 6144
4623 +
4624 +#define USB_EP_CONTROL 0
4625 +#define USB_EP_ISOC 1
4626 +#define USB_EP_BULK 2
4627 +#define USB_EP_INT 3
4628 +
4629 +#define USB_SPEED_LOW 1
4630 +#define USB_SPEED_FULL 2
4631 +#define USB_SPEED_HIGH 3
4632 +#define USB_SPEED_SUPER 5
4633 +
4634 +/* mtk scheduler bitmasks */
4635 +#define BPKTS(p) ((p) & 0x3f)
4636 +#define BCSCOUNT(p) (((p) & 0x7) << 8)
4637 +#define BBM(p) ((p) << 11)
4638 +#define BOFFSET(p) ((p) & 0x3fff)
4639 +#define BREPEAT(p) (((p) & 0x7fff) << 16)
4640 +
4641 +
4642 +#if 1
4643 +typedef unsigned int mtk_u32;
4644 +typedef unsigned long long mtk_u64;
4645 +#endif
4646 +
4647 +#define NULL ((void *)0)
4648 +
4649 +struct mtk_xhci_ep_ctx {
4650 + mtk_u32 ep_info;
4651 + mtk_u32 ep_info2;
4652 + mtk_u64 deq;
4653 + mtk_u32 tx_info;
4654 + /* offset 0x14 - 0x1f reserved for HC internal use */
4655 + mtk_u32 reserved[3];
4656 +};
4657 +
4658 +
4659 +struct sch_ep
4660 +{
4661 + //device info
4662 + int dev_speed;
4663 + int isTT;
4664 + //ep info
4665 + int is_in;
4666 + int ep_type;
4667 + int maxp;
4668 + int interval;
4669 + int burst;
4670 + int mult;
4671 + //scheduling info
4672 + int offset;
4673 + int repeat;
4674 + int pkts;
4675 + int cs_count;
4676 + int burst_mode;
4677 + //other
4678 + int bw_cost; //bandwidth cost in each repeat; including overhead
4679 + mtk_u32 *ep; //address of usb_endpoint pointer
4680 +};
4681 +
4682 +int mtk_xhci_scheduler_init(void);
4683 +int mtk_xhci_scheduler_add_ep(int dev_speed, int is_in, int isTT, int ep_type, int maxp, int interval, int burst
4684 + , int mult, mtk_u32 *ep, mtk_u32 *ep_ctx, struct sch_ep *sch_ep);
4685 +struct sch_ep * mtk_xhci_scheduler_remove_ep(int dev_speed, int is_in, int isTT, int ep_type, mtk_u32 *ep);
4686 +
4687 +
4688 +#endif
4689 Index: linux-3.10.44/drivers/usb/host/xhci-mtk.c
4690 ===================================================================
4691 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
4692 +++ linux-3.10.44/drivers/usb/host/xhci-mtk.c 2014-07-02 11:20:15.821675026 +0100
4693 @@ -0,0 +1,265 @@
4694 +#include "xhci-mtk.h"
4695 +#include "xhci-mtk-power.h"
4696 +#include "xhci.h"
4697 +#include "mtk-phy.h"
4698 +#ifdef CONFIG_C60802_SUPPORT
4699 +#include "mtk-phy-c60802.h"
4700 +#endif
4701 +#include "xhci-mtk-scheduler.h"
4702 +#include <linux/kernel.h> /* printk() */
4703 +#include <linux/slab.h>
4704 +#include <linux/delay.h>
4705 +#include <asm/uaccess.h>
4706 +#include <linux/dma-mapping.h>
4707 +#include <linux/platform_device.h>
4708 +
4709 +void setInitialReg(void )
4710 +{
4711 + __u32 __iomem *addr;
4712 + u32 temp;
4713 +
4714 + /* set SSUSB DMA burst size to 128B */
4715 + addr = SSUSB_U3_XHCI_BASE + SSUSB_HDMA_CFG;
4716 + temp = SSUSB_HDMA_CFG_MT7621_VALUE;
4717 + writel(temp, addr);
4718 +
4719 + /* extend U3 LTSSM Polling.LFPS timeout value */
4720 + addr = SSUSB_U3_XHCI_BASE + U3_LTSSM_TIMING_PARAMETER3;
4721 + temp = U3_LTSSM_TIMING_PARAMETER3_VALUE;
4722 + writel(temp, addr);
4723 +
4724 + /* EOF */
4725 + addr = SSUSB_U3_XHCI_BASE + SYNC_HS_EOF;
4726 + temp = SYNC_HS_EOF_VALUE;
4727 + writel(temp, addr);
4728 +
4729 +#if defined (CONFIG_PERIODIC_ENP)
4730 + /* HSCH_CFG1: SCH2_FIFO_DEPTH */
4731 + addr = SSUSB_U3_XHCI_BASE + HSCH_CFG1;
4732 + temp = readl(addr);
4733 + temp &= ~(0x3 << SCH2_FIFO_DEPTH_OFFSET);
4734 + writel(temp, addr);
4735 +#endif
4736 +
4737 + /* Doorbell handling */
4738 + addr = SIFSLV_IPPC + SSUSB_IP_SPAR0;
4739 + temp = 0x1;
4740 + writel(temp, addr);
4741 +
4742 + /* Set SW PLL Stable mode to 1 for U2 LPM device remote wakeup */
4743 + /* Port 0 */
4744 + addr = U2_PHY_BASE + U2_PHYD_CR1;
4745 + temp = readl(addr);
4746 + temp &= ~(0x3 << 18);
4747 + temp |= (1 << 18);
4748 + writel(temp, addr);
4749 +
4750 + /* Port 1 */
4751 + addr = U2_PHY_BASE_P1 + U2_PHYD_CR1;
4752 + temp = readl(addr);
4753 + temp &= ~(0x3 << 18);
4754 + temp |= (1 << 18);
4755 + writel(temp, addr);
4756 +}
4757 +
4758 +
4759 +void setLatchSel(void){
4760 + __u32 __iomem *latch_sel_addr;
4761 + u32 latch_sel_value;
4762 + latch_sel_addr = U3_PIPE_LATCH_SEL_ADD;
4763 + latch_sel_value = ((U3_PIPE_LATCH_TX)<<2) | (U3_PIPE_LATCH_RX);
4764 + writel(latch_sel_value, latch_sel_addr);
4765 +}
4766 +
4767 +void reinitIP(void){
4768 + __u32 __iomem *ip_reset_addr;
4769 + u32 ip_reset_value;
4770 +
4771 + enableAllClockPower();
4772 + mtk_xhci_scheduler_init();
4773 +}
4774 +
4775 +void dbg_prb_out(void){
4776 + mtk_probe_init(0x0f0f0f0f);
4777 + mtk_probe_out(0xffffffff);
4778 + mtk_probe_out(0x01010101);
4779 + mtk_probe_out(0x02020202);
4780 + mtk_probe_out(0x04040404);
4781 + mtk_probe_out(0x08080808);
4782 + mtk_probe_out(0x10101010);
4783 + mtk_probe_out(0x20202020);
4784 + mtk_probe_out(0x40404040);
4785 + mtk_probe_out(0x80808080);
4786 + mtk_probe_out(0x55555555);
4787 + mtk_probe_out(0xaaaaaaaa);
4788 +}
4789 +
4790 +
4791 +
4792 +///////////////////////////////////////////////////////////////////////////////
4793 +
4794 +#define RET_SUCCESS 0
4795 +#define RET_FAIL 1
4796 +
4797 +static int dbg_u3w(int argc, char**argv)
4798 +{
4799 + int u4TimingValue;
4800 + char u1TimingValue;
4801 + int u4TimingAddress;
4802 +
4803 + if (argc<3)
4804 + {
4805 + printk(KERN_ERR "Arg: address value\n");
4806 + return RET_FAIL;
4807 + }
4808 + u3phy_init();
4809 +
4810 + u4TimingAddress = (int)simple_strtol(argv[1], &argv[1], 16);
4811 + u4TimingValue = (int)simple_strtol(argv[2], &argv[2], 16);
4812 + u1TimingValue = u4TimingValue & 0xff;
4813 + /* access MMIO directly */
4814 + writel(u1TimingValue, u4TimingAddress);
4815 + printk(KERN_ERR "Write done\n");
4816 + return RET_SUCCESS;
4817 +
4818 +}
4819 +
4820 +static int dbg_u3r(int argc, char**argv)
4821 +{
4822 + char u1ReadTimingValue;
4823 + int u4TimingAddress;
4824 + if (argc<2)
4825 + {
4826 + printk(KERN_ERR "Arg: address\n");
4827 + return 0;
4828 + }
4829 + u3phy_init();
4830 + mdelay(500);
4831 + u4TimingAddress = (int)simple_strtol(argv[1], &argv[1], 16);
4832 + /* access MMIO directly */
4833 + u1ReadTimingValue = readl(u4TimingAddress);
4834 + printk(KERN_ERR "Value = 0x%x\n", u1ReadTimingValue);
4835 + return 0;
4836 +}
4837 +
4838 +static int dbg_u3init(int argc, char**argv)
4839 +{
4840 + int ret;
4841 + ret = u3phy_init();
4842 + printk(KERN_ERR "phy registers and operations initial done\n");
4843 + if(u3phy_ops->u2_slew_rate_calibration){
4844 + u3phy_ops->u2_slew_rate_calibration(u3phy);
4845 + }
4846 + else{
4847 + printk(KERN_ERR "WARN: PHY doesn't implement u2 slew rate calibration function\n");
4848 + }
4849 + if(u3phy_ops->init(u3phy) == PHY_TRUE)
4850 + return RET_SUCCESS;
4851 + return RET_FAIL;
4852 +}
4853 +
4854 +void dbg_setU1U2(int argc, char**argv){
4855 + struct xhci_hcd *xhci;
4856 + int u1_value;
4857 + int u2_value;
4858 + u32 port_id, temp;
4859 + u32 __iomem *addr;
4860 +
4861 + if (argc<3)
4862 + {
4863 + printk(KERN_ERR "Arg: u1value u2value\n");
4864 + return RET_FAIL;
4865 + }
4866 +
4867 + u1_value = (int)simple_strtol(argv[1], &argv[1], 10);
4868 + u2_value = (int)simple_strtol(argv[2], &argv[2], 10);
4869 + addr = (SSUSB_U3_XHCI_BASE + 0x424);
4870 + temp = readl(addr);
4871 + temp = temp & (~(0x0000ffff));
4872 + temp = temp | u1_value | (u2_value<<8);
4873 + writel(temp, addr);
4874 +}
4875 +///////////////////////////////////////////////////////////////////////////////
4876 +
4877 +int call_function(char *buf)
4878 +{
4879 + int i;
4880 + int argc;
4881 + char *argv[80];
4882 +
4883 + argc = 0;
4884 + do
4885 + {
4886 + argv[argc] = strsep(&buf, " ");
4887 + printk(KERN_DEBUG "[%d] %s\r\n", argc, argv[argc]);
4888 + argc++;
4889 + } while (buf);
4890 + if (!strcmp("dbg.r", argv[0]))
4891 + dbg_prb_out();
4892 + else if (!strcmp("dbg.u3w", argv[0]))
4893 + dbg_u3w(argc, argv);
4894 + else if (!strcmp("dbg.u3r", argv[0]))
4895 + dbg_u3r(argc, argv);
4896 + else if (!strcmp("dbg.u3i", argv[0]))
4897 + dbg_u3init(argc, argv);
4898 + else if (!strcmp("pw.u1u2", argv[0]))
4899 + dbg_setU1U2(argc, argv);
4900 + return 0;
4901 +}
4902 +
4903 +long xhci_mtk_test_unlock_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
4904 +{
4905 + char w_buf[200];
4906 + char r_buf[200] = "this is a test";
4907 + int len = 200;
4908 +
4909 + switch (cmd) {
4910 + case IOCTL_READ:
4911 + copy_to_user((char *) arg, r_buf, len);
4912 + printk(KERN_DEBUG "IOCTL_READ: %s\r\n", r_buf);
4913 + break;
4914 + case IOCTL_WRITE:
4915 + copy_from_user(w_buf, (char *) arg, len);
4916 + printk(KERN_DEBUG "IOCTL_WRITE: %s\r\n", w_buf);
4917 +
4918 + //invoke function
4919 + return call_function(w_buf);
4920 + break;
4921 + default:
4922 + return -ENOTTY;
4923 + }
4924 +
4925 + return len;
4926 +}
4927 +
4928 +int xhci_mtk_test_open(struct inode *inode, struct file *file)
4929 +{
4930 +
4931 + printk(KERN_DEBUG "xhci_mtk_test open: successful\n");
4932 + return 0;
4933 +}
4934 +
4935 +int xhci_mtk_test_release(struct inode *inode, struct file *file)
4936 +{
4937 +
4938 + printk(KERN_DEBUG "xhci_mtk_test release: successful\n");
4939 + return 0;
4940 +}
4941 +
4942 +ssize_t xhci_mtk_test_read(struct file *file, char *buf, size_t count, loff_t *ptr)
4943 +{
4944 +
4945 + printk(KERN_DEBUG "xhci_mtk_test read: returning zero bytes\n");
4946 + return 0;
4947 +}
4948 +
4949 +ssize_t xhci_mtk_test_write(struct file *file, const char *buf, size_t count, loff_t * ppos)
4950 +{
4951 +
4952 + printk(KERN_DEBUG "xhci_mtk_test write: accepting zero bytes\n");
4953 + return 0;
4954 +}
4955 +
4956 +
4957 +
4958 +
4959 Index: linux-3.10.44/drivers/usb/host/xhci-mtk.h
4960 ===================================================================
4961 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
4962 +++ linux-3.10.44/drivers/usb/host/xhci-mtk.h 2014-07-02 11:20:15.821675026 +0100
4963 @@ -0,0 +1,120 @@
4964 +#ifndef _XHCI_MTK_H
4965 +#define _XHCI_MTK_H
4966 +
4967 +#include <linux/usb.h>
4968 +#include "xhci.h"
4969 +
4970 +#define SSUSB_U3_XHCI_BASE 0xBE1C0000
4971 +#define SSUSB_U3_MAC_BASE 0xBE1C2400
4972 +#define SSUSB_U3_SYS_BASE 0xBE1C2600
4973 +#define SSUSB_U2_SYS_BASE 0xBE1C3400
4974 +#define SSUB_SIF_SLV_TOP 0xBE1D0000
4975 +#define SIFSLV_IPPC (SSUB_SIF_SLV_TOP + 0x700)
4976 +
4977 +#define U3_PIPE_LATCH_SEL_ADD SSUSB_U3_MAC_BASE + 0x130
4978 +#define U3_PIPE_LATCH_TX 0
4979 +#define U3_PIPE_LATCH_RX 0
4980 +
4981 +#define U3_UX_EXIT_LFPS_TIMING_PAR 0xa0
4982 +#define U3_REF_CK_PAR 0xb0
4983 +#define U3_RX_UX_EXIT_LFPS_REF_OFFSET 8
4984 +#define U3_RX_UX_EXIT_LFPS_REF 3
4985 +#define U3_REF_CK_VAL 10
4986 +
4987 +#define U3_TIMING_PULSE_CTRL 0xb4
4988 +#define CNT_1US_VALUE 63 //62.5MHz:63, 70MHz:70, 80MHz:80, 100MHz:100, 125MHz:125
4989 +
4990 +#define USB20_TIMING_PARAMETER 0x40
4991 +#define TIME_VALUE_1US 63 //62.5MHz:63, 80MHz:80, 100MHz:100, 125MHz:125
4992 +
4993 +#define LINK_PM_TIMER 0x8
4994 +#define PM_LC_TIMEOUT_VALUE 3
4995 +
4996 +#define XHCI_IMOD 0x624
4997 +#define XHCI_IMOD_MT7621_VALUE 0x10
4998 +
4999 +#define SSUSB_HDMA_CFG 0x950
5000 +#define SSUSB_HDMA_CFG_MT7621_VALUE 0x10E0E0C
5001 +
5002 +#define U3_LTSSM_TIMING_PARAMETER3 0x2514
5003 +#define U3_LTSSM_TIMING_PARAMETER3_VALUE 0x3E8012C
5004 +
5005 +#define U2_PHYD_CR1 0x64
5006 +
5007 +#define SSUSB_IP_SPAR0 0xC8
5008 +
5009 +#define SYNC_HS_EOF 0x938
5010 +#define SYNC_HS_EOF_VALUE 0x201F3
5011 +
5012 +#define HSCH_CFG1 0x960
5013 +#define SCH2_FIFO_DEPTH_OFFSET 16
5014 +
5015 +
5016 +#define SSUSB_IP_PW_CTRL (SIFSLV_IPPC+0x0)
5017 +#define SSUSB_IP_SW_RST (1<<0)
5018 +#define SSUSB_IP_PW_CTRL_1 (SIFSLV_IPPC+0x4)
5019 +#define SSUSB_IP_PDN (1<<0)
5020 +#define SSUSB_U3_CTRL(p) (SIFSLV_IPPC+0x30+(p*0x08))
5021 +#define SSUSB_U3_PORT_DIS (1<<0)
5022 +#define SSUSB_U3_PORT_PDN (1<<1)
5023 +#define SSUSB_U3_PORT_HOST_SEL (1<<2)
5024 +#define SSUSB_U3_PORT_CKBG_EN (1<<3)
5025 +#define SSUSB_U3_PORT_MAC_RST (1<<4)
5026 +#define SSUSB_U3_PORT_PHYD_RST (1<<5)
5027 +#define SSUSB_U2_CTRL(p) (SIFSLV_IPPC+(0x50)+(p*0x08))
5028 +#define SSUSB_U2_PORT_DIS (1<<0)
5029 +#define SSUSB_U2_PORT_PDN (1<<1)
5030 +#define SSUSB_U2_PORT_HOST_SEL (1<<2)
5031 +#define SSUSB_U2_PORT_CKBG_EN (1<<3)
5032 +#define SSUSB_U2_PORT_MAC_RST (1<<4)
5033 +#define SSUSB_U2_PORT_PHYD_RST (1<<5)
5034 +#define SSUSB_IP_CAP (SIFSLV_IPPC+0x024)
5035 +
5036 +#define SSUSB_U3_PORT_NUM(p) (p & 0xff)
5037 +#define SSUSB_U2_PORT_NUM(p) ((p>>8) & 0xff)
5038 +
5039 +
5040 +#define XHCI_MTK_TEST_MAJOR 234
5041 +#define DEVICE_NAME "xhci_mtk_test"
5042 +
5043 +#define CLI_MAGIC 'CLI'
5044 +#define IOCTL_READ _IOR(CLI_MAGIC, 0, int)
5045 +#define IOCTL_WRITE _IOW(CLI_MAGIC, 1, int)
5046 +
5047 +void reinitIP(void);
5048 +void setInitialReg(void);
5049 +void dbg_prb_out(void);
5050 +int call_function(char *buf);
5051 +
5052 +long xhci_mtk_test_unlock_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
5053 +int xhci_mtk_test_open(struct inode *inode, struct file *file);
5054 +int xhci_mtk_test_release(struct inode *inode, struct file *file);
5055 +ssize_t xhci_mtk_test_read(struct file *file, char *buf, size_t count, loff_t *ptr);
5056 +ssize_t xhci_mtk_test_write(struct file *file, const char *buf, size_t count, loff_t * ppos);
5057 +
5058 +/*
5059 + mediatek probe out
5060 +*/
5061 +/************************************************************************************/
5062 +
5063 +#define SW_PRB_OUT_ADDR (SIFSLV_IPPC+0xc0)
5064 +#define PRB_MODULE_SEL_ADDR (SIFSLV_IPPC+0xbc)
5065 +
5066 +static inline void mtk_probe_init(const u32 byte){
5067 + __u32 __iomem *ptr = (__u32 __iomem *) PRB_MODULE_SEL_ADDR;
5068 + writel(byte, ptr);
5069 +}
5070 +
5071 +static inline void mtk_probe_out(const u32 value){
5072 + __u32 __iomem *ptr = (__u32 __iomem *) SW_PRB_OUT_ADDR;
5073 + writel(value, ptr);
5074 +}
5075 +
5076 +static inline u32 mtk_probe_value(void){
5077 + __u32 __iomem *ptr = (__u32 __iomem *) SW_PRB_OUT_ADDR;
5078 +
5079 + return readl(ptr);
5080 +}
5081 +
5082 +
5083 +#endif
5084 Index: linux-3.10.44/drivers/usb/host/xhci-plat.c
5085 ===================================================================
5086 --- linux-3.10.44.orig/drivers/usb/host/xhci-plat.c 2014-06-16 21:43:06.000000000 +0100
5087 +++ linux-3.10.44/drivers/usb/host/xhci-plat.c 2014-07-02 11:20:15.821675026 +0100
5088 @@ -25,6 +25,13 @@
5089 * dev struct in order to setup MSI
5090 */
5091 xhci->quirks |= XHCI_PLAT;
5092 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5093 + /* MTK host controller gives a spurious successful event after a
5094 + * short transfer. Ignore it.
5095 + */
5096 + xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
5097 + xhci->quirks |= XHCI_LPM_SUPPORT;
5098 +#endif
5099 }
5100
5101 /* called during probe() after chip reset completes */
5102 @@ -96,20 +103,32 @@
5103
5104 driver = &xhci_plat_xhci_driver;
5105
5106 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5107 + irq = XHC_IRQ;
5108 +#else
5109 irq = platform_get_irq(pdev, 0);
5110 +#endif
5111 +
5112 if (irq < 0)
5113 return -ENODEV;
5114
5115 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5116 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
5117 if (!res)
5118 return -ENODEV;
5119 +#endif
5120
5121 hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev));
5122 if (!hcd)
5123 return -ENOMEM;
5124
5125 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5126 + hcd->rsrc_start = (uint32_t)XHC_IO_START;
5127 + hcd->rsrc_len = XHC_IO_LENGTH;
5128 +#else
5129 hcd->rsrc_start = res->start;
5130 hcd->rsrc_len = resource_size(res);
5131 +#endif
5132
5133 if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len,
5134 driver->description)) {
5135 Index: linux-3.10.44/drivers/usb/host/xhci-ring.c
5136 ===================================================================
5137 --- linux-3.10.44.orig/drivers/usb/host/xhci-ring.c 2014-06-16 21:43:06.000000000 +0100
5138 +++ linux-3.10.44/drivers/usb/host/xhci-ring.c 2014-07-02 11:20:15.821675026 +0100
5139 @@ -236,7 +236,6 @@
5140 */
5141 if (!chain && !more_trbs_coming)
5142 break;
5143 -
5144 /* If we're not dealing with 0.95 hardware or
5145 * isoc rings on AMD 0.96 host,
5146 * carry over the chain bit of the previous TRB
5147 @@ -273,16 +272,20 @@
5148 static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
5149 unsigned int num_trbs)
5150 {
5151 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5152 int num_trbs_in_deq_seg;
5153 +#endif
5154
5155 if (ring->num_trbs_free < num_trbs)
5156 return 0;
5157
5158 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5159 if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) {
5160 num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs;
5161 if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg)
5162 return 0;
5163 }
5164 +#endif
5165
5166 return 1;
5167 }
5168 @@ -2910,6 +2913,7 @@
5169 next = ring->enqueue;
5170
5171 while (last_trb(xhci, ring, ring->enq_seg, next)) {
5172 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5173 /* If we're not dealing with 0.95 hardware or isoc rings
5174 * on AMD 0.96 host, clear the chain bit.
5175 */
5176 @@ -2919,7 +2923,9 @@
5177 next->link.control &= cpu_to_le32(~TRB_CHAIN);
5178 else
5179 next->link.control |= cpu_to_le32(TRB_CHAIN);
5180 -
5181 +#else
5182 + next->link.control &= cpu_to_le32(~TRB_CHAIN);
5183 +#endif
5184 wmb();
5185 next->link.control ^= cpu_to_le32(TRB_CYCLE);
5186
5187 @@ -3049,6 +3055,9 @@
5188 start_trb->field[3] |= cpu_to_le32(start_cycle);
5189 else
5190 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
5191 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5192 + wmb();
5193 +#endif
5194 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
5195 }
5196
5197 @@ -3108,6 +3117,29 @@
5198 return (remainder >> 10) << 17;
5199 }
5200
5201 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5202 +static u32 mtk_xhci_td_remainder(unsigned int td_transfer_size, unsigned int td_running_total, unsigned int maxp, unsigned trb_buffer_length)
5203 +{
5204 + u32 max = 31;
5205 + int remainder, td_packet_count, packet_transferred;
5206 +
5207 + //0 for the last TRB
5208 + //FIXME: need to workaround if there is ZLP in this TD
5209 + if (td_running_total + trb_buffer_length == td_transfer_size)
5210 + return 0;
5211 +
5212 + //FIXME: need to take care of high-bandwidth (MAX_ESIT)
5213 + packet_transferred = (td_running_total /*+ trb_buffer_length*/) / maxp;
5214 + td_packet_count = DIV_ROUND_UP(td_transfer_size, maxp);
5215 + remainder = td_packet_count - packet_transferred;
5216 +
5217 + if (remainder > max)
5218 + return max << 17;
5219 + else
5220 + return remainder << 17;
5221 +}
5222 +#endif
5223 +
5224 /*
5225 * For xHCI 1.0 host controllers, TD size is the number of max packet sized
5226 * packets remaining in the TD (*not* including this TRB).
5227 @@ -3245,6 +3277,7 @@
5228 }
5229
5230 /* Set the TRB length, TD size, and interrupter fields. */
5231 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5232 if (xhci->hci_version < 0x100) {
5233 remainder = xhci_td_remainder(
5234 urb->transfer_buffer_length -
5235 @@ -3254,6 +3287,13 @@
5236 trb_buff_len, total_packet_count, urb,
5237 num_trbs - 1);
5238 }
5239 +#else
5240 + if (num_trbs > 1)
5241 + remainder = mtk_xhci_td_remainder(urb->transfer_buffer_length,
5242 + running_total, urb->ep->desc.wMaxPacketSize, trb_buff_len);
5243 +#endif
5244 +
5245 +
5246 length_field = TRB_LEN(trb_buff_len) |
5247 remainder |
5248 TRB_INTR_TARGET(0);
5249 @@ -3316,6 +3356,9 @@
5250 int running_total, trb_buff_len, ret;
5251 unsigned int total_packet_count;
5252 u64 addr;
5253 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5254 + int max_packet;
5255 +#endif
5256
5257 if (urb->num_sgs)
5258 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
5259 @@ -3341,6 +3384,25 @@
5260 running_total += TRB_MAX_BUFF_SIZE;
5261 }
5262 /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
5263 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5264 + switch(urb->dev->speed){
5265 + case USB_SPEED_SUPER:
5266 + max_packet = urb->ep->desc.wMaxPacketSize;
5267 + break;
5268 + case USB_SPEED_HIGH:
5269 + case USB_SPEED_FULL:
5270 + case USB_SPEED_LOW:
5271 + case USB_SPEED_WIRELESS:
5272 + case USB_SPEED_UNKNOWN:
5273 + default:
5274 + max_packet = urb->ep->desc.wMaxPacketSize & 0x7ff;
5275 + break;
5276 + }
5277 + if((urb->transfer_flags & URB_ZERO_PACKET)
5278 + && ((urb->transfer_buffer_length % max_packet) == 0)){
5279 + num_trbs++;
5280 + }
5281 +#endif
5282
5283 ret = prepare_transfer(xhci, xhci->devs[slot_id],
5284 ep_index, urb->stream_id,
5285 @@ -3400,6 +3462,7 @@
5286 field |= TRB_ISP;
5287
5288 /* Set the TRB length, TD size, and interrupter fields. */
5289 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5290 if (xhci->hci_version < 0x100) {
5291 remainder = xhci_td_remainder(
5292 urb->transfer_buffer_length -
5293 @@ -3409,6 +3472,10 @@
5294 trb_buff_len, total_packet_count, urb,
5295 num_trbs - 1);
5296 }
5297 +#else
5298 + remainder = mtk_xhci_td_remainder(urb->transfer_buffer_length, running_total, max_packet, trb_buff_len);
5299 +#endif
5300 +
5301 length_field = TRB_LEN(trb_buff_len) |
5302 remainder |
5303 TRB_INTR_TARGET(0);
5304 @@ -3498,7 +3565,11 @@
5305 field |= 0x1;
5306
5307 /* xHCI 1.0 6.4.1.2.1: Transfer Type field */
5308 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5309 + if (1) {
5310 +#else
5311 if (xhci->hci_version == 0x100) {
5312 +#endif
5313 if (urb->transfer_buffer_length > 0) {
5314 if (setup->bRequestType & USB_DIR_IN)
5315 field |= TRB_TX_TYPE(TRB_DATA_IN);
5316 @@ -3522,7 +3593,12 @@
5317 field = TRB_TYPE(TRB_DATA);
5318
5319 length_field = TRB_LEN(urb->transfer_buffer_length) |
5320 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5321 xhci_td_remainder(urb->transfer_buffer_length) |
5322 +#else
5323 + //CC: MTK style, no scatter-gather for control transfer
5324 + 0 |
5325 +#endif
5326 TRB_INTR_TARGET(0);
5327 if (urb->transfer_buffer_length > 0) {
5328 if (setup->bRequestType & USB_DIR_IN)
5329 @@ -3533,7 +3609,7 @@
5330 length_field,
5331 field | ep_ring->cycle_state);
5332 }
5333 -
5334 +
5335 /* Save the DMA address of the last TRB in the TD */
5336 td->last_trb = ep_ring->enqueue;
5337
5338 @@ -3645,6 +3721,9 @@
5339 u64 start_addr, addr;
5340 int i, j;
5341 bool more_trbs_coming;
5342 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5343 + int max_packet;
5344 +#endif
5345
5346 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
5347
5348 @@ -3658,6 +3737,21 @@
5349 start_trb = &ep_ring->enqueue->generic;
5350 start_cycle = ep_ring->cycle_state;
5351
5352 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5353 + switch(urb->dev->speed){
5354 + case USB_SPEED_SUPER:
5355 + max_packet = urb->ep->desc.wMaxPacketSize;
5356 + break;
5357 + case USB_SPEED_HIGH:
5358 + case USB_SPEED_FULL:
5359 + case USB_SPEED_LOW:
5360 + case USB_SPEED_WIRELESS:
5361 + case USB_SPEED_UNKNOWN:
5362 + max_packet = urb->ep->desc.wMaxPacketSize & 0x7ff;
5363 + break;
5364 + }
5365 +#endif
5366 +
5367 urb_priv = urb->hcpriv;
5368 /* Queue the first TRB, even if it's zero-length */
5369 for (i = 0; i < num_tds; i++) {
5370 @@ -3729,9 +3823,13 @@
5371 } else {
5372 td->last_trb = ep_ring->enqueue;
5373 field |= TRB_IOC;
5374 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5375 + if (!(xhci->quirks & XHCI_AVOID_BEI)) {
5376 +#else
5377 if (xhci->hci_version == 0x100 &&
5378 !(xhci->quirks &
5379 XHCI_AVOID_BEI)) {
5380 +#endif
5381 /* Set BEI bit except for the last td */
5382 if (i < num_tds - 1)
5383 field |= TRB_BEI;
5384 @@ -3746,6 +3844,7 @@
5385 trb_buff_len = td_remain_len;
5386
5387 /* Set the TRB length, TD size, & interrupter fields. */
5388 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5389 if (xhci->hci_version < 0x100) {
5390 remainder = xhci_td_remainder(
5391 td_len - running_total);
5392 @@ -3755,6 +3854,10 @@
5393 total_packet_count, urb,
5394 (trbs_per_td - j - 1));
5395 }
5396 +#else
5397 + remainder = mtk_xhci_td_remainder(urb->transfer_buffer_length, running_total, max_packet, trb_buff_len);
5398 +#endif
5399 +
5400 length_field = TRB_LEN(trb_buff_len) |
5401 remainder |
5402 TRB_INTR_TARGET(0);
5403 Index: linux-3.10.44/drivers/usb/host/xhci.c
5404 ===================================================================
5405 --- linux-3.10.44.orig/drivers/usb/host/xhci.c 2014-06-16 21:43:06.000000000 +0100
5406 +++ linux-3.10.44/drivers/usb/host/xhci.c 2014-07-02 11:20:15.825675026 +0100
5407 @@ -30,6 +30,16 @@
5408
5409 #include "xhci.h"
5410
5411 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5412 +#include <asm/uaccess.h>
5413 +#include <linux/dma-mapping.h>
5414 +#include <linux/platform_device.h>
5415 +#include "mtk-phy.h"
5416 +#include "xhci-mtk-scheduler.h"
5417 +#include "xhci-mtk-power.h"
5418 +#include "xhci-mtk.h"
5419 +#endif
5420 +
5421 #define DRIVER_AUTHOR "Sarah Sharp"
5422 #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
5423
5424 @@ -38,6 +48,18 @@
5425 module_param(link_quirk, int, S_IRUGO | S_IWUSR);
5426 MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
5427
5428 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5429 +long xhci_mtk_test_unlock_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
5430 +static struct file_operations xhci_mtk_test_fops = {
5431 + .owner = THIS_MODULE,
5432 + .read = xhci_mtk_test_read,
5433 + .write = xhci_mtk_test_write,
5434 + .unlocked_ioctl = xhci_mtk_test_unlock_ioctl,
5435 + .open = xhci_mtk_test_open,
5436 + .release = xhci_mtk_test_release,
5437 +};
5438 +#endif
5439 +
5440 /* TODO: copied from ehci-hcd.c - can this be refactored? */
5441 /*
5442 * xhci_handshake - spin reading hc until handshake completes or fails
5443 @@ -189,7 +211,7 @@
5444 return ret;
5445 }
5446
5447 -#ifdef CONFIG_PCI
5448 +#if defined (CONFIG_PCI) && !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5449 static int xhci_free_msi(struct xhci_hcd *xhci)
5450 {
5451 int i;
5452 @@ -389,6 +411,7 @@
5453 return ret;
5454 }
5455 hcd->irq = pdev->irq;
5456 +
5457 return 0;
5458 }
5459
5460 @@ -430,6 +453,11 @@
5461 xhci_dbg(xhci, "Attempting compliance mode recovery\n");
5462 hcd = xhci->shared_hcd;
5463
5464 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5465 + temp |= (1 << 31);
5466 + xhci_writel(xhci, temp, xhci->usb3_ports[i]);
5467 +#endif
5468 +
5469 if (hcd->state == HC_STATE_SUSPENDED)
5470 usb_hcd_resume_root_hub(hcd);
5471
5472 @@ -478,6 +506,9 @@
5473 {
5474 const char *dmi_product_name, *dmi_sys_vendor;
5475
5476 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5477 + return true;
5478 +#endif
5479 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
5480 dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
5481 if (!dmi_product_name || !dmi_sys_vendor)
5482 @@ -521,6 +552,10 @@
5483 } else {
5484 xhci_dbg(xhci, "xHCI doesn't need link TRB QUIRK\n");
5485 }
5486 +
5487 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5488 + mtk_xhci_scheduler_init();
5489 +#endif
5490 retval = xhci_mem_init(xhci, GFP_KERNEL);
5491 xhci_dbg(xhci, "Finished xhci_init\n");
5492
5493 @@ -664,7 +699,11 @@
5494 xhci_dbg(xhci, "// Set the interrupt modulation register\n");
5495 temp = xhci_readl(xhci, &xhci->ir_set->irq_control);
5496 temp &= ~ER_IRQ_INTERVAL_MASK;
5497 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5498 + temp |= (u32) 16;
5499 +#else
5500 temp |= (u32) 160;
5501 +#endif
5502 xhci_writel(xhci, temp, &xhci->ir_set->irq_control);
5503
5504 /* Set the HCD state before we enable the irqs */
5505 @@ -685,6 +724,9 @@
5506 xhci_queue_vendor_command(xhci, 0, 0, 0,
5507 TRB_TYPE(TRB_NEC_GET_FW));
5508
5509 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5510 + enableXhciAllPortPower(xhci);
5511 +#endif
5512 xhci_dbg(xhci, "Finished xhci_run for USB2 roothub\n");
5513 return 0;
5514 }
5515 @@ -1002,7 +1044,6 @@
5516
5517 /* If restore operation fails, re-initialize the HC during resume */
5518 if ((temp & STS_SRE) || hibernated) {
5519 -
5520 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
5521 !(xhci_all_ports_seen_u0(xhci))) {
5522 del_timer_sync(&xhci->comp_mode_recovery_timer);
5523 @@ -1586,6 +1627,13 @@
5524 u32 drop_flag;
5525 u32 new_add_flags, new_drop_flags, new_slot_info;
5526 int ret;
5527 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5528 +#if MTK_SCH_NEW
5529 + struct sch_ep *sch_ep = NULL;
5530 + int isTT;
5531 + int ep_type;
5532 +#endif
5533 +#endif
5534
5535 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
5536 if (ret <= 0)
5537 @@ -1637,6 +1685,40 @@
5538
5539 xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
5540
5541 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5542 +#if MTK_SCH_NEW
5543 + slot_ctx = xhci_get_slot_ctx(xhci, xhci->devs[udev->slot_id]->out_ctx);
5544 + if ((slot_ctx->tt_info & 0xff) > 0) {
5545 + isTT = 1;
5546 + }
5547 + else {
5548 + isTT = 0;
5549 + }
5550 + if (usb_endpoint_xfer_int(&ep->desc)) {
5551 + ep_type = USB_EP_INT;
5552 + }
5553 + else if (usb_endpoint_xfer_isoc(&ep->desc)) {
5554 + ep_type = USB_EP_ISOC;
5555 + }
5556 + else if (usb_endpoint_xfer_bulk(&ep->desc)) {
5557 + ep_type = USB_EP_BULK;
5558 + }
5559 + else
5560 + ep_type = USB_EP_CONTROL;
5561 +
5562 + sch_ep = mtk_xhci_scheduler_remove_ep(udev->speed, usb_endpoint_dir_in(&ep->desc)
5563 + , isTT, ep_type, (mtk_u32 *)ep);
5564 + if (sch_ep != NULL) {
5565 + kfree(sch_ep);
5566 + }
5567 + else {
5568 + xhci_dbg(xhci, "[MTK]Doesn't find ep_sch instance when removing endpoint\n");
5569 + }
5570 +#else
5571 + mtk_xhci_scheduler_remove_ep(xhci, udev, ep);
5572 +#endif
5573 +#endif
5574 +
5575 xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x, new slot info = %#x\n",
5576 (unsigned int) ep->desc.bEndpointAddress,
5577 udev->slot_id,
5578 @@ -1672,6 +1754,18 @@
5579 u32 new_add_flags, new_drop_flags, new_slot_info;
5580 struct xhci_virt_device *virt_dev;
5581 int ret = 0;
5582 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5583 + struct xhci_ep_ctx *in_ep_ctx;
5584 +#if MTK_SCH_NEW
5585 + struct sch_ep *sch_ep;
5586 + int isTT;
5587 + int ep_type;
5588 + int maxp = 0;
5589 + int burst = 0;
5590 + int mult = 0;
5591 + int interval;
5592 +#endif
5593 +#endif
5594
5595 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
5596 if (ret <= 0) {
5597 @@ -1734,6 +1828,56 @@
5598 return -ENOMEM;
5599 }
5600
5601 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5602 + in_ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
5603 +#if MTK_SCH_NEW
5604 + slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
5605 + if ((slot_ctx->tt_info & 0xff) > 0) {
5606 + isTT = 1;
5607 + }
5608 + else {
5609 + isTT = 0;
5610 + }
5611 + if (usb_endpoint_xfer_int(&ep->desc)) {
5612 + ep_type = USB_EP_INT;
5613 + }
5614 + else if (usb_endpoint_xfer_isoc(&ep->desc)) {
5615 + ep_type = USB_EP_ISOC;
5616 + }
5617 + else if (usb_endpoint_xfer_bulk(&ep->desc)) {
5618 + ep_type = USB_EP_BULK;
5619 + }
5620 + else
5621 + ep_type = USB_EP_CONTROL;
5622 +
5623 + if (udev->speed == USB_SPEED_FULL || udev->speed == USB_SPEED_HIGH
5624 + || udev->speed == USB_SPEED_LOW) {
5625 + maxp = ep->desc.wMaxPacketSize & 0x7FF;
5626 + burst = ep->desc.wMaxPacketSize >> 11;
5627 + mult = 0;
5628 + }
5629 + else if (udev->speed == USB_SPEED_SUPER) {
5630 + maxp = ep->desc.wMaxPacketSize & 0x7FF;
5631 + burst = ep->ss_ep_comp.bMaxBurst;
5632 + mult = ep->ss_ep_comp.bmAttributes & 0x3;
5633 + }
5634 + interval = (1 << ((in_ep_ctx->ep_info >> 16) & 0xff));
5635 + sch_ep = kmalloc(sizeof(struct sch_ep), GFP_KERNEL);
5636 + if (mtk_xhci_scheduler_add_ep(udev->speed, usb_endpoint_dir_in(&ep->desc),
5637 + isTT, ep_type, maxp, interval, burst, mult, (mtk_u32 *)ep
5638 + , (mtk_u32 *)in_ep_ctx, sch_ep) != SCH_SUCCESS) {
5639 + xhci_err(xhci, "[MTK] not enough bandwidth\n");
5640 +
5641 + return -ENOSPC;
5642 + }
5643 +#else
5644 + if (mtk_xhci_scheduler_add_ep(xhci, udev, ep, in_ep_ctx) != SCH_SUCCESS) {
5645 + xhci_err(xhci, "[MTK] not enough bandwidth\n");
5646 +
5647 + return -ENOSPC;
5648 + }
5649 +#endif
5650 +#endif
5651 ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
5652 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
5653
5654 @@ -2697,7 +2841,7 @@
5655 if (ctrl_ctx->add_flags == cpu_to_le32(SLOT_FLAG) &&
5656 ctrl_ctx->drop_flags == 0)
5657 return 0;
5658 -
5659 +
5660 xhci_dbg(xhci, "New Input Control Context:\n");
5661 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
5662 xhci_dbg_ctx(xhci, virt_dev->in_ctx,
5663 @@ -4233,10 +4377,14 @@
5664 u16 *timeout)
5665 {
5666 if (state == USB3_LPM_U1) {
5667 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5668 if (xhci->quirks & XHCI_INTEL_HOST)
5669 +#endif
5670 return xhci_calculate_intel_u1_timeout(udev, desc);
5671 } else {
5672 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5673 if (xhci->quirks & XHCI_INTEL_HOST)
5674 +#endif
5675 return xhci_calculate_intel_u2_timeout(udev, desc);
5676 }
5677
5678 @@ -4662,7 +4810,9 @@
5679 /* Accept arbitrarily long scatter-gather lists */
5680 hcd->self.sg_tablesize = ~0;
5681 /* XHCI controllers don't stop the ep queue on short packets :| */
5682 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5683 hcd->self.no_stop_on_short = 1;
5684 +#endif
5685
5686 if (usb_hcd_is_primary_hcd(hcd)) {
5687 xhci = kzalloc(sizeof(struct xhci_hcd), GFP_KERNEL);
5688 @@ -4731,6 +4881,10 @@
5689 goto error;
5690 xhci_dbg(xhci, "Reset complete\n");
5691
5692 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5693 + setInitialReg();
5694 +#endif
5695 +
5696 temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
5697 if (HCC_64BIT_ADDR(temp)) {
5698 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
5699 @@ -4755,8 +4909,21 @@
5700 MODULE_AUTHOR(DRIVER_AUTHOR);
5701 MODULE_LICENSE("GPL");
5702
5703 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5704 +static struct platform_device xhci_platform_dev = {
5705 + .name = "xhci-hcd",
5706 + .id = -1,
5707 + .dev = {
5708 + .coherent_dma_mask = 0xffffffff,
5709 + },
5710 +};
5711 +#endif
5712 +
5713 static int __init xhci_hcd_init(void)
5714 {
5715 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5716 + struct platform_device *pPlatformDev;
5717 +#endif
5718 int retval;
5719
5720 retval = xhci_register_pci();
5721 @@ -4769,6 +4936,33 @@
5722 printk(KERN_DEBUG "Problem registering platform driver.");
5723 goto unreg_pci;
5724 }
5725 +
5726 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5727 + retval = register_chrdev(XHCI_MTK_TEST_MAJOR, DEVICE_NAME, &xhci_mtk_test_fops);
5728 +
5729 + u3phy_init();
5730 + if (u3phy_ops->u2_slew_rate_calibration) {
5731 + u3phy_ops->u2_slew_rate_calibration(u3phy);
5732 + u3phy_ops->u2_slew_rate_calibration(u3phy_p1);
5733 + }
5734 + else{
5735 + printk(KERN_ERR "WARN: PHY doesn't implement u2 slew rate calibration function\n");
5736 + }
5737 + u3phy_ops->init(u3phy);
5738 + reinitIP();
5739 +
5740 + pPlatformDev = &xhci_platform_dev;
5741 + memset(pPlatformDev, 0, sizeof(struct platform_device));
5742 + pPlatformDev->name = "xhci-hcd";
5743 + pPlatformDev->id = -1;
5744 + pPlatformDev->dev.coherent_dma_mask = 0xffffffff;
5745 + pPlatformDev->dev.dma_mask = &pPlatformDev->dev.coherent_dma_mask;
5746 +
5747 + retval = platform_device_register(&xhci_platform_dev);
5748 + if (retval < 0)
5749 + xhci_unregister_plat();
5750 +#endif
5751 +
5752 /*
5753 * Check the compiler generated sizes of structures that must be laid
5754 * out in specific ways for hardware access.
5755 @@ -4786,6 +4980,7 @@
5756 BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8);
5757 /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
5758 BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8);
5759 +
5760 return 0;
5761 unreg_pci:
5762 xhci_unregister_pci();
5763 Index: linux-3.10.44/drivers/usb/host/xhci.h
5764 ===================================================================
5765 --- linux-3.10.44.orig/drivers/usb/host/xhci.h 2014-06-16 21:43:06.000000000 +0100
5766 +++ linux-3.10.44/drivers/usb/host/xhci.h 2014-07-02 11:20:15.825675026 +0100
5767 @@ -29,9 +29,24 @@
5768 #include <linux/usb/hcd.h>
5769
5770 /* Code sharing between pci-quirks and xhci hcd */
5771 -#include "xhci-ext-caps.h"
5772 +#include "xhci-ext-caps.h"
5773 #include "pci-quirks.h"
5774
5775 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5776 +#define XHC_IRQ (22 + 8)
5777 +#define XHC_IO_START 0x1E1C0000
5778 +#define XHC_IO_LENGTH 0x10000
5779 +/* mtk scheduler bitmasks */
5780 +#define BPKTS(p) ((p) & 0x3f)
5781 +#define BCSCOUNT(p) (((p) & 0x7) << 8)
5782 +#define BBM(p) ((p) << 11)
5783 +#define BOFFSET(p) ((p) & 0x3fff)
5784 +#define BREPEAT(p) (((p) & 0x7fff) << 16)
5785 +#endif
5786 +
5787 +
5788 +
5789 +
5790 /* xHCI PCI Configuration Registers */
5791 #define XHCI_SBRN_OFFSET (0x60)
5792
5793 @@ -1536,8 +1551,12 @@
5794 /* Compliance Mode Recovery Data */
5795 struct timer_list comp_mode_recovery_timer;
5796 u32 port_status_u0;
5797 +#ifdef CONFIG_USB_MT7621_XHCI_PLATFORM
5798 +#define COMP_MODE_RCVRY_MSECS 5000
5799 +#else
5800 /* Compliance Mode Timer Triggered every 2 seconds */
5801 #define COMP_MODE_RCVRY_MSECS 2000
5802 +#endif
5803 };
5804
5805 /* convert between an HCD pointer and the corresponding EHCI_HCD */
5806 @@ -1703,7 +1722,7 @@
5807 void xhci_free_command(struct xhci_hcd *xhci,
5808 struct xhci_command *command);
5809
5810 -#ifdef CONFIG_PCI
5811 +#if defined (CONFIG_PCI) && !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5812 /* xHCI PCI glue */
5813 int xhci_register_pci(void);
5814 void xhci_unregister_pci(void);
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