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[openwrt/openwrt.git] / target / linux / ramips / patches-3.14 / 0012-MIPS-ralink-add-MT7621-support.patch
1 From c8c69923236f2f3f184ddcc7eb41c113b5cc3223 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sun, 27 Jul 2014 10:57:40 +0100
4 Subject: [PATCH 12/57] MIPS: ralink: add MT7621 support
5
6 Signed-off-by: John Crispin <blogic@openwrt.org>
7 ---
8 arch/mips/include/asm/gic.h | 4 +
9 arch/mips/include/asm/mach-ralink/irq.h | 9 +
10 arch/mips/include/asm/mach-ralink/mt7621.h | 39 ++++
11 arch/mips/kernel/vmlinux.lds.S | 1 +
12 arch/mips/ralink/Kconfig | 18 ++
13 arch/mips/ralink/Makefile | 7 +-
14 arch/mips/ralink/Platform | 5 +
15 arch/mips/ralink/irq-gic.c | 271 ++++++++++++++++++++++++++++
16 arch/mips/ralink/malta-amon.c | 81 +++++++++
17 arch/mips/ralink/mt7621.c | 183 +++++++++++++++++++
18 10 files changed, 617 insertions(+), 1 deletion(-)
19 create mode 100644 arch/mips/include/asm/mach-ralink/irq.h
20 create mode 100644 arch/mips/include/asm/mach-ralink/mt7621.h
21 create mode 100644 arch/mips/ralink/irq-gic.c
22 create mode 100644 arch/mips/ralink/malta-amon.c
23 create mode 100644 arch/mips/ralink/mt7621.c
24
25 Index: linux-3.14.18/arch/mips/include/asm/gic.h
26 ===================================================================
27 --- linux-3.14.18.orig/arch/mips/include/asm/gic.h 2014-09-06 01:34:59.000000000 +0200
28 +++ linux-3.14.18/arch/mips/include/asm/gic.h 2014-11-12 18:15:37.293244085 +0100
29 @@ -19,7 +19,11 @@
30 #define GIC_TRIG_EDGE 1
31 #define GIC_TRIG_LEVEL 0
32
33 +#define GIC_NUM_INTRS 64
34 +
35 +#ifndef GIC_NUM_INTRS
36 #define GIC_NUM_INTRS (24 + NR_CPUS * 2)
37 +#endif
38
39 #define MSK(n) ((1 << (n)) - 1)
40 #define REG32(addr) (*(volatile unsigned int *) (addr))
41 Index: linux-3.14.18/arch/mips/include/asm/mach-ralink/irq.h
42 ===================================================================
43 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
44 +++ linux-3.14.18/arch/mips/include/asm/mach-ralink/irq.h 2014-11-12 18:15:37.297244234 +0100
45 @@ -0,0 +1,9 @@
46 +#ifndef __ASM_MACH_RALINK_IRQ_H
47 +#define __ASM_MACH_RALINK_IRQ_H
48 +
49 +#define GIC_NUM_INTRS 64
50 +#define NR_IRQS 256
51 +
52 +#include_next <irq.h>
53 +
54 +#endif
55 Index: linux-3.14.18/arch/mips/include/asm/mach-ralink/mt7621.h
56 ===================================================================
57 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
58 +++ linux-3.14.18/arch/mips/include/asm/mach-ralink/mt7621.h 2014-11-12 18:15:37.297244234 +0100
59 @@ -0,0 +1,39 @@
60 +/*
61 + * This program is free software; you can redistribute it and/or modify it
62 + * under the terms of the GNU General Public License version 2 as published
63 + * by the Free Software Foundation.
64 + *
65 + * Parts of this file are based on Ralink's 2.6.21 BSP
66 + *
67 + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
68 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
69 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
70 + */
71 +
72 +#ifndef _MT7621_REGS_H_
73 +#define _MT7621_REGS_H_
74 +
75 +#define MT7621_SYSC_BASE 0x1E000000
76 +
77 +#define SYSC_REG_CHIP_NAME0 0x00
78 +#define SYSC_REG_CHIP_NAME1 0x04
79 +#define SYSC_REG_CHIP_REV 0x0c
80 +#define SYSC_REG_SYSTEM_CONFIG0 0x10
81 +#define SYSC_REG_SYSTEM_CONFIG1 0x14
82 +
83 +#define CHIP_REV_PKG_MASK 0x1
84 +#define CHIP_REV_PKG_SHIFT 16
85 +#define CHIP_REV_VER_MASK 0xf
86 +#define CHIP_REV_VER_SHIFT 8
87 +#define CHIP_REV_ECO_MASK 0xf
88 +
89 +#define MT7621_DRAM_BASE 0x0
90 +#define MT7621_DDR2_SIZE_MIN 32
91 +#define MT7621_DDR2_SIZE_MAX 256
92 +
93 +#define MT7621_CHIP_NAME0 0x3637544D
94 +#define MT7621_CHIP_NAME1 0x20203132
95 +
96 +#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8)
97 +
98 +#endif
99 Index: linux-3.14.18/arch/mips/kernel/vmlinux.lds.S
100 ===================================================================
101 --- linux-3.14.18.orig/arch/mips/kernel/vmlinux.lds.S 2014-11-12 18:15:35.441175040 +0100
102 +++ linux-3.14.18/arch/mips/kernel/vmlinux.lds.S 2014-11-12 18:15:37.297244234 +0100
103 @@ -51,6 +51,7 @@
104 /* read-only */
105 _text = .; /* Text and read-only data */
106 .text : {
107 + /*. = . + 0x8000; */
108 TEXT_TEXT
109 SCHED_TEXT
110 LOCK_TEXT
111 Index: linux-3.14.18/arch/mips/ralink/Kconfig
112 ===================================================================
113 --- linux-3.14.18.orig/arch/mips/ralink/Kconfig 2014-09-06 01:34:59.000000000 +0200
114 +++ linux-3.14.18/arch/mips/ralink/Kconfig 2014-11-13 10:37:45.371792998 +0100
115 @@ -7,6 +7,11 @@
116 select CLKSRC_OF
117 select CLKSRC_MMIO
118
119 +config IRQ_INTC
120 + bool
121 + default y
122 + depends on !SOC_MT7621
123 +
124 choice
125 prompt "Ralink SoC selection"
126 default SOC_RT305X
127 @@ -34,6 +39,15 @@
128 select USB_ARCH_HAS_OHCI
129 select USB_ARCH_HAS_EHCI
130
131 + config SOC_MT7621
132 + bool "MT7621"
133 + select MIPS_CPU_SCACHE
134 + select SYS_SUPPORTS_MULTITHREADING
135 + select SYS_SUPPORTS_SMP
136 + select SYS_SUPPORTS_MIPS_CMP
137 + select IRQ_GIC
138 + select HW_HAS_PCI
139 +
140 endchoice
141
142 choice
143 @@ -61,6 +75,10 @@
144 bool "MT7620A eval kit"
145 depends on SOC_MT7620
146
147 + config DTB_MT7621_EVAL
148 + bool "MT7621 eval kit"
149 + depends on SOC_MT7621
150 +
151 endchoice
152
153 endif
154 Index: linux-3.14.18/arch/mips/ralink/Makefile
155 ===================================================================
156 --- linux-3.14.18.orig/arch/mips/ralink/Makefile 2014-11-12 18:15:37.225241550 +0100
157 +++ linux-3.14.18/arch/mips/ralink/Makefile 2014-11-13 10:37:43.947738138 +0100
158 @@ -6,16 +6,21 @@
159 # Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
160 # Copyright (C) 2013 John Crispin <blogic@openwrt.org>
161
162 -obj-y := prom.o of.o reset.o clk.o irq.o timer.o
163 +obj-y := prom.o of.o reset.o clk.o timer.o
164
165 obj-$(CONFIG_CLKEVT_RT3352) += cevt-rt3352.o
166
167 obj-$(CONFIG_RALINK_ILL_ACC) += ill_acc.o
168
169 +obj-$(CONFIG_IRQ_INTC) += irq.o
170 +obj-$(CONFIG_IRQ_GIC) += irq-gic.o
171 +obj-$(CONFIG_MIPS_MT_SMP) += malta-amon.o
172 +
173 obj-$(CONFIG_SOC_RT288X) += rt288x.o
174 obj-$(CONFIG_SOC_RT305X) += rt305x.o
175 obj-$(CONFIG_SOC_RT3883) += rt3883.o
176 obj-$(CONFIG_SOC_MT7620) += mt7620.o
177 +obj-$(CONFIG_SOC_MT7621) += mt7621.o
178
179 obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
180
181 Index: linux-3.14.18/arch/mips/ralink/Platform
182 ===================================================================
183 --- linux-3.14.18.orig/arch/mips/ralink/Platform 2014-09-06 01:34:59.000000000 +0200
184 +++ linux-3.14.18/arch/mips/ralink/Platform 2014-11-12 18:15:37.297244234 +0100
185 @@ -27,3 +27,8 @@
186 #
187 load-$(CONFIG_SOC_MT7620) += 0xffffffff80000000
188 cflags-$(CONFIG_SOC_MT7620) += -I$(srctree)/arch/mips/include/asm/mach-ralink/mt7620
189 +
190 +# Ralink MT7621
191 +#
192 +load-$(CONFIG_SOC_MT7621) += 0xffffffff80001000
193 +cflags-$(CONFIG_SOC_MT7621) += -I$(srctree)/arch/mips/include/asm/mach-ralink/mt7621
194 Index: linux-3.14.18/arch/mips/ralink/irq-gic.c
195 ===================================================================
196 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
197 +++ linux-3.14.18/arch/mips/ralink/irq-gic.c 2014-11-12 18:15:37.297244234 +0100
198 @@ -0,0 +1,271 @@
199 +#include <linux/init.h>
200 +#include <linux/sched.h>
201 +#include <linux/slab.h>
202 +#include <linux/interrupt.h>
203 +#include <linux/kernel_stat.h>
204 +#include <linux/hardirq.h>
205 +#include <linux/preempt.h>
206 +#include <linux/irqdomain.h>
207 +#include <linux/of_platform.h>
208 +#include <linux/of_address.h>
209 +#include <linux/of_irq.h>
210 +
211 +#include <asm/irq_cpu.h>
212 +#include <asm/mipsregs.h>
213 +
214 +#include <asm/irq.h>
215 +#include <asm/setup.h>
216 +
217 +#include <asm/gic.h>
218 +#include <asm/gcmpregs.h>
219 +
220 +#include <asm/mach-ralink/mt7621.h>
221 +
222 +unsigned long _gcmp_base;
223 +static int gic_resched_int_base = 56;
224 +static int gic_call_int_base = 60;
225 +static struct irq_chip *irq_gic;
226 +static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS];
227 +
228 +#if defined(CONFIG_MIPS_MT_SMP)
229 +static int gic_resched_int_base;
230 +static int gic_call_int_base;
231 +
232 +#define GIC_RESCHED_INT(cpu) (gic_resched_int_base+(cpu))
233 +#define GIC_CALL_INT(cpu) (gic_call_int_base+(cpu))
234 +
235 +static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
236 +{
237 + scheduler_ipi();
238 +
239 + return IRQ_HANDLED;
240 +}
241 +
242 +static irqreturn_t
243 +ipi_call_interrupt(int irq, void *dev_id)
244 +{
245 + smp_call_function_interrupt();
246 +
247 + return IRQ_HANDLED;
248 +}
249 +
250 +static struct irqaction irq_resched = {
251 + .handler = ipi_resched_interrupt,
252 + .flags = IRQF_DISABLED|IRQF_PERCPU,
253 + .name = "ipi resched"
254 +};
255 +
256 +static struct irqaction irq_call = {
257 + .handler = ipi_call_interrupt,
258 + .flags = IRQF_DISABLED|IRQF_PERCPU,
259 + .name = "ipi call"
260 +};
261 +
262 +#endif
263 +
264 +static void __init
265 +gic_fill_map(void)
266 +{
267 + int i;
268 +
269 + for (i = 0; i < ARRAY_SIZE(gic_intr_map); i++) {
270 + gic_intr_map[i].cpunum = 0;
271 + gic_intr_map[i].pin = GIC_CPU_INT0;
272 + gic_intr_map[i].polarity = GIC_POL_POS;
273 + gic_intr_map[i].trigtype = GIC_TRIG_LEVEL;
274 + gic_intr_map[i].flags = GIC_FLAG_IPI;
275 + }
276 +
277 +#if defined(CONFIG_MIPS_MT_SMP)
278 + {
279 + int cpu;
280 +
281 + gic_call_int_base = ARRAY_SIZE(gic_intr_map) - nr_cpu_ids;
282 + gic_resched_int_base = gic_call_int_base - nr_cpu_ids;
283 +
284 + i = gic_resched_int_base;
285 +
286 + for (cpu = 0; cpu < nr_cpu_ids; cpu++) {
287 + gic_intr_map[i + cpu].cpunum = cpu;
288 + gic_intr_map[i + cpu].pin = GIC_CPU_INT1;
289 + gic_intr_map[i + cpu].trigtype = GIC_TRIG_EDGE;
290 +
291 + gic_intr_map[i + cpu + nr_cpu_ids].cpunum = cpu;
292 + gic_intr_map[i + cpu + nr_cpu_ids].pin = GIC_CPU_INT2;
293 + gic_intr_map[i + cpu + nr_cpu_ids].trigtype = GIC_TRIG_EDGE;
294 + }
295 + }
296 +#endif
297 +}
298 +
299 +void
300 +gic_irq_ack(struct irq_data *d)
301 +{
302 + int irq = (d->irq - gic_irq_base);
303 +
304 + GIC_CLR_INTR_MASK(irq);
305 +
306 + if (gic_irq_flags[irq] & GIC_TRIG_EDGE)
307 + GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), irq);
308 +}
309 +
310 +void
311 +gic_finish_irq(struct irq_data *d)
312 +{
313 + GIC_SET_INTR_MASK(d->irq - gic_irq_base);
314 +}
315 +
316 +void __init
317 +gic_platform_init(int irqs, struct irq_chip *irq_controller)
318 +{
319 + irq_gic = irq_controller;
320 +}
321 +
322 +static void
323 +gic_irqdispatch(void)
324 +{
325 + unsigned int irq = gic_get_int();
326 +
327 + if (likely(irq < GIC_NUM_INTRS))
328 + do_IRQ(MIPS_GIC_IRQ_BASE + irq);
329 + else {
330 + pr_err("Spurious GIC Interrupt!\n");
331 + spurious_interrupt();
332 + }
333 +
334 +}
335 +
336 +static void
337 +vi_timer_irqdispatch(void)
338 +{
339 + do_IRQ(cp0_compare_irq);
340 +}
341 +
342 +#if defined(CONFIG_MIPS_MT_SMP)
343 +unsigned int
344 +plat_ipi_call_int_xlate(unsigned int cpu)
345 +{
346 + return GIC_CALL_INT(cpu);
347 +}
348 +
349 +unsigned int
350 +plat_ipi_resched_int_xlate(unsigned int cpu)
351 +{
352 + return GIC_RESCHED_INT(cpu);
353 +}
354 +#endif
355 +
356 +asmlinkage void
357 +plat_irq_dispatch(void)
358 +{
359 + unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
360 +
361 + if (unlikely(!pending)) {
362 + pr_err("Spurious CP0 Interrupt!\n");
363 + spurious_interrupt();
364 + } else {
365 + if (pending & CAUSEF_IP7)
366 + do_IRQ(cp0_compare_irq);
367 +
368 + if (pending & (CAUSEF_IP4 | CAUSEF_IP3 | CAUSEF_IP2))
369 + gic_irqdispatch();
370 + }
371 +}
372 +
373 +unsigned int __cpuinit
374 +get_c0_compare_int(void)
375 +{
376 + return CP0_LEGACY_COMPARE_IRQ;
377 +}
378 +
379 +static int
380 +gic_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
381 +{
382 + irq_set_chip_and_handler(irq, irq_gic,
383 +#if defined(CONFIG_MIPS_MT_SMP)
384 + (hw >= gic_resched_int_base) ?
385 + handle_percpu_irq :
386 +#endif
387 + handle_level_irq);
388 +
389 + return 0;
390 +}
391 +
392 +static const struct irq_domain_ops irq_domain_ops = {
393 + .xlate = irq_domain_xlate_onecell,
394 + .map = gic_map,
395 +};
396 +
397 +static int __init
398 +of_gic_init(struct device_node *node,
399 + struct device_node *parent)
400 +{
401 + struct irq_domain *domain;
402 + struct resource gcmp = { 0 }, gic = { 0 };
403 + unsigned int gic_rev;
404 + int i;
405 +
406 + if (of_address_to_resource(node, 0, &gic))
407 + panic("Failed to get gic memory range");
408 + if (request_mem_region(gic.start, resource_size(&gic),
409 + gic.name) < 0)
410 + panic("Failed to request gic memory");
411 + if (of_address_to_resource(node, 2, &gcmp))
412 + panic("Failed to get gic memory range");
413 + if (request_mem_region(gcmp.start, resource_size(&gcmp),
414 + gcmp.name) < 0)
415 + panic("Failed to request gcmp memory");
416 +
417 + _gcmp_base = (unsigned long) ioremap_nocache(gcmp.start, resource_size(&gcmp));
418 + if (!_gcmp_base)
419 + panic("Failed to remap gcmp memory\n");
420 +
421 + if ((GCMPGCB(GCMPB) & GCMP_GCB_GCMPB_GCMPBASE_MSK) != gcmp.start)
422 + panic("Failed to find gcmp core\n");
423 +
424 + /* tell the gcmp where to find the gic */
425 + GCMPGCB(GICBA) = gic.start | GCMP_GCB_GICBA_EN_MSK;
426 + gic_present = 1;
427 + if (cpu_has_vint) {
428 + set_vi_handler(2, gic_irqdispatch);
429 + set_vi_handler(3, gic_irqdispatch);
430 + set_vi_handler(4, gic_irqdispatch);
431 + set_vi_handler(7, vi_timer_irqdispatch);
432 + }
433 +
434 + gic_fill_map();
435 +
436 + gic_init(gic.start, resource_size(&gic), gic_intr_map,
437 + ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE);
438 +
439 + GICREAD(GIC_REG(SHARED, GIC_SH_REVISIONID), gic_rev);
440 + pr_info("gic: revision %d.%d\n", (gic_rev >> 8) & 0xff, gic_rev & 0xff);
441 +
442 + domain = irq_domain_add_legacy(node, GIC_NUM_INTRS, MIPS_GIC_IRQ_BASE,
443 + 0, &irq_domain_ops, NULL);
444 + if (!domain)
445 + panic("Failed to add irqdomain");
446 +
447 +#if defined(CONFIG_MIPS_MT_SMP)
448 + for (i = 0; i < nr_cpu_ids; i++) {
449 + setup_irq(MIPS_GIC_IRQ_BASE + GIC_RESCHED_INT(i), &irq_resched);
450 + setup_irq(MIPS_GIC_IRQ_BASE + GIC_CALL_INT(i), &irq_call);
451 + }
452 +#endif
453 +
454 + change_c0_status(ST0_IM, STATUSF_IP7 | STATUSF_IP4 | STATUSF_IP3 |
455 + STATUSF_IP2);
456 + return 0;
457 +}
458 +
459 +static struct of_device_id __initdata of_irq_ids[] = {
460 + { .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_intc_init },
461 + { .compatible = "ralink,mt7621-gic", .data = of_gic_init },
462 + {},
463 +};
464 +
465 +void __init
466 +arch_init_irq(void)
467 +{
468 + of_irq_init(of_irq_ids);
469 +}
470 Index: linux-3.14.18/arch/mips/ralink/malta-amon.c
471 ===================================================================
472 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
473 +++ linux-3.14.18/arch/mips/ralink/malta-amon.c 2014-11-12 18:15:37.297244234 +0100
474 @@ -0,0 +1,81 @@
475 +/*
476 + * Copyright (C) 2007 MIPS Technologies, Inc.
477 + * All rights reserved.
478 +
479 + * This program is free software; you can distribute it and/or modify it
480 + * under the terms of the GNU General Public License (Version 2) as
481 + * published by the Free Software Foundation.
482 + *
483 + * This program is distributed in the hope it will be useful, but WITHOUT
484 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
485 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
486 + * for more details.
487 + *
488 + * You should have received a copy of the GNU General Public License along
489 + * with this program; if not, write to the Free Software Foundation, Inc.,
490 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
491 + *
492 + * Arbitrary Monitor interface
493 + */
494 +
495 +#include <linux/kernel.h>
496 +#include <linux/init.h>
497 +#include <linux/smp.h>
498 +
499 +#include <asm/addrspace.h>
500 +#include <asm/mips-boards/launch.h>
501 +#include <asm/mipsmtregs.h>
502 +
503 +int amon_cpu_avail(int cpu)
504 +{
505 + struct cpulaunch *launch = (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH);
506 +
507 + if (cpu < 0 || cpu >= NCPULAUNCH) {
508 + pr_debug("avail: cpu%d is out of range\n", cpu);
509 + return 0;
510 + }
511 +
512 + launch += cpu;
513 + if (!(launch->flags & LAUNCH_FREADY)) {
514 + pr_debug("avail: cpu%d is not ready\n", cpu);
515 + return 0;
516 + }
517 + if (launch->flags & (LAUNCH_FGO|LAUNCH_FGONE)) {
518 + pr_debug("avail: too late.. cpu%d is already gone\n", cpu);
519 + return 0;
520 + }
521 +
522 + return 1;
523 +}
524 +
525 +void amon_cpu_start(int cpu,
526 + unsigned long pc, unsigned long sp,
527 + unsigned long gp, unsigned long a0)
528 +{
529 + volatile struct cpulaunch *launch =
530 + (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH);
531 +
532 + if (!amon_cpu_avail(cpu))
533 + return;
534 + if (cpu == smp_processor_id()) {
535 + pr_debug("launch: I am cpu%d!\n", cpu);
536 + return;
537 + }
538 + launch += cpu;
539 +
540 + pr_debug("launch: starting cpu%d\n", cpu);
541 +
542 + launch->pc = pc;
543 + launch->gp = gp;
544 + launch->sp = sp;
545 + launch->a0 = a0;
546 +
547 + smp_wmb(); /* Target must see parameters before go */
548 + launch->flags |= LAUNCH_FGO;
549 + smp_wmb(); /* Target must see go before we poll */
550 +
551 + while ((launch->flags & LAUNCH_FGONE) == 0)
552 + ;
553 + smp_rmb(); /* Target will be updating flags soon */
554 + pr_debug("launch: cpu%d gone!\n", cpu);
555 +}
556 Index: linux-3.14.18/arch/mips/ralink/mt7621.c
557 ===================================================================
558 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
559 +++ linux-3.14.18/arch/mips/ralink/mt7621.c 2014-11-13 10:32:56.960683223 +0100
560 @@ -0,0 +1,183 @@
561 +/*
562 + * This program is free software; you can redistribute it and/or modify it
563 + * under the terms of the GNU General Public License version 2 as published
564 + * by the Free Software Foundation.
565 + *
566 + * Parts of this file are based on Ralink's 2.6.21 BSP
567 + *
568 + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
569 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
570 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
571 + */
572 +
573 +#include <linux/kernel.h>
574 +#include <linux/init.h>
575 +#include <linux/module.h>
576 +#include <asm/gcmpregs.h>
577 +
578 +#include <asm/mipsregs.h>
579 +#include <asm/smp-ops.h>
580 +#include <asm/mach-ralink/ralink_regs.h>
581 +#include <asm/mach-ralink/mt7621.h>
582 +
583 +#include <pinmux.h>
584 +
585 +#include "common.h"
586 +
587 +#define SYSC_REG_SYSCFG 0x10
588 +#define SYSC_REG_CPLL_CLKCFG0 0x2c
589 +#define SYSC_REG_CUR_CLK_STS 0x44
590 +#define CPU_CLK_SEL (BIT(30) | BIT(31))
591 +
592 +#define MT7621_GPIO_MODE_UART1 1
593 +#define MT7621_GPIO_MODE_I2C 2
594 +#define MT7621_GPIO_MODE_UART2 3
595 +#define MT7621_GPIO_MODE_UART3 5
596 +#define MT7621_GPIO_MODE_JTAG 7
597 +#define MT7621_GPIO_MODE_WDT_MASK 0x3
598 +#define MT7621_GPIO_MODE_WDT_SHIFT 8
599 +#define MT7621_GPIO_MODE_WDT_GPIO 1
600 +#define MT7621_GPIO_MODE_PCIE_RST 0
601 +#define MT7621_GPIO_MODE_PCIE_REF 2
602 +#define MT7621_GPIO_MODE_PCIE_MASK 0x3
603 +#define MT7621_GPIO_MODE_PCIE_SHIFT 10
604 +#define MT7621_GPIO_MODE_PCIE_GPIO 1
605 +#define MT7621_GPIO_MODE_MDIO 12
606 +#define MT7621_GPIO_MODE_RGMII1 14
607 +#define MT7621_GPIO_MODE_RGMII2 15
608 +#define MT7621_GPIO_MODE_SPI_MASK 0x3
609 +#define MT7621_GPIO_MODE_SPI_SHIFT 16
610 +#define MT7621_GPIO_MODE_SPI_GPIO 1
611 +#define MT7621_GPIO_MODE_SDHCI_MASK 0x3
612 +#define MT7621_GPIO_MODE_SDHCI_SHIFT 18
613 +#define MT7621_GPIO_MODE_SDHCI_GPIO 1
614 +
615 +static struct rt2880_pmx_func uart1_grp[] = { FUNC("uart", 0, 1, 2) };
616 +static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 3, 2) };
617 +static struct rt2880_pmx_func uart3_grp[] = { FUNC("uart", 0, 5, 4) };
618 +static struct rt2880_pmx_func uart2_grp[] = { FUNC("uart", 0, 9, 4) };
619 +static struct rt2880_pmx_func jtag_grp[] = { FUNC("jtag", 0, 13, 5) };
620 +static struct rt2880_pmx_func wdt_grp[] = {
621 + FUNC("wdt rst", 0, 18, 1),
622 + FUNC("wdt refclk", 2, 18, 1),
623 +};
624 +static struct rt2880_pmx_func pcie_rst_grp[] = {
625 + FUNC("pcie rst", MT7621_GPIO_MODE_PCIE_RST, 19, 1),
626 + FUNC("pcie refclk", MT7621_GPIO_MODE_PCIE_REF, 19, 1)
627 +};
628 +static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 0, 20, 2) };
629 +static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii", 0, 22, 12) };
630 +static struct rt2880_pmx_func spi_grp[] = {
631 + FUNC("spi", 0, 34, 7),
632 + FUNC("nand", 2, 34, 8),
633 +};
634 +static struct rt2880_pmx_func sdhci_grp[] = {
635 + FUNC("sdhci", 0, 41, 8),
636 + FUNC("nand", 2, 41, 8),
637 +};
638 +static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii", 0, 49, 12) };
639 +
640 +static struct rt2880_pmx_group mt7621_pinmux_data[] = {
641 + GRP("uart1", uart1_grp, 1, MT7621_GPIO_MODE_UART1),
642 + GRP("i2c", i2c_grp, 1, MT7621_GPIO_MODE_I2C),
643 + GRP("uart3", uart2_grp, 1, MT7621_GPIO_MODE_UART2),
644 + GRP("uart2", uart3_grp, 1, MT7621_GPIO_MODE_UART3),
645 + GRP("jtag", jtag_grp, 1, MT7621_GPIO_MODE_JTAG),
646 + GRP_G("wdt", wdt_grp, MT7621_GPIO_MODE_WDT_MASK,
647 + MT7621_GPIO_MODE_WDT_GPIO, MT7621_GPIO_MODE_WDT_SHIFT),
648 + GRP_G("pcie", pcie_rst_grp, MT7621_GPIO_MODE_PCIE_MASK,
649 + MT7621_GPIO_MODE_PCIE_GPIO, MT7621_GPIO_MODE_PCIE_SHIFT),
650 + GRP("mdio", mdio_grp, 1, MT7621_GPIO_MODE_MDIO),
651 + GRP("rgmii2", rgmii2_grp, 1, MT7621_GPIO_MODE_RGMII2),
652 + GRP_G("spi", spi_grp, MT7621_GPIO_MODE_SPI_MASK,
653 + MT7621_GPIO_MODE_SPI_GPIO, MT7621_GPIO_MODE_SPI_SHIFT),
654 + GRP_G("sdhci", sdhci_grp, MT7621_GPIO_MODE_SDHCI_MASK,
655 + MT7621_GPIO_MODE_SDHCI_GPIO, MT7621_GPIO_MODE_SDHCI_SHIFT),
656 + GRP("rgmii1", rgmii1_grp, 1, MT7621_GPIO_MODE_RGMII1),
657 + { 0 }
658 +};
659 +
660 +void __init ralink_clk_init(void)
661 +{
662 + int cpu_fdiv = 0;
663 + int cpu_ffrac = 0;
664 + int fbdiv = 0;
665 + u32 clk_sts, syscfg;
666 + u8 clk_sel = 0, xtal_mode;
667 + u32 cpu_clk;
668 +
669 + if ((rt_sysc_r32(SYSC_REG_CPLL_CLKCFG0) & CPU_CLK_SEL) != 0)
670 + clk_sel = 1;
671 +
672 + switch (clk_sel) {
673 + case 0:
674 + clk_sts = rt_sysc_r32(SYSC_REG_CUR_CLK_STS);
675 + cpu_fdiv = ((clk_sts >> 8) & 0x1F);
676 + cpu_ffrac = (clk_sts & 0x1F);
677 + cpu_clk = (500 * cpu_ffrac / cpu_fdiv) * 1000 * 1000;
678 + break;
679 +
680 + case 1:
681 + fbdiv = ((rt_sysc_r32(0x648) >> 4) & 0x7F) + 1;
682 + syscfg = rt_sysc_r32(SYSC_REG_SYSCFG);
683 + xtal_mode = (syscfg >> 6) & 0x7;
684 + if(xtal_mode >= 6) { //25Mhz Xtal
685 + cpu_clk = 25 * fbdiv * 1000 * 1000;
686 + } else if(xtal_mode >=3) { //40Mhz Xtal
687 + cpu_clk = 40 * fbdiv * 1000 * 1000;
688 + } else { // 20Mhz Xtal
689 + cpu_clk = 20 * fbdiv * 1000 * 1000;
690 + }
691 + break;
692 + }
693 + cpu_clk = 880000000;
694 + ralink_clk_add("cpu", cpu_clk);
695 + ralink_clk_add("1e000b00.spi", 50000000);
696 + ralink_clk_add("1e000c00.uartlite", 50000000);
697 + ralink_clk_add("1e000d00.uart", 50000000);
698 +}
699 +
700 +void __init ralink_of_remap(void)
701 +{
702 + rt_sysc_membase = plat_of_remap_node("mtk,mt7621-sysc");
703 + rt_memc_membase = plat_of_remap_node("mtk,mt7621-memc");
704 +
705 + if (!rt_sysc_membase || !rt_memc_membase)
706 + panic("Failed to remap core resources");
707 +}
708 +
709 +void prom_soc_init(struct ralink_soc_info *soc_info)
710 +{
711 + void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7621_SYSC_BASE);
712 + unsigned char *name = NULL;
713 + u32 n0;
714 + u32 n1;
715 + u32 rev;
716 +
717 + n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
718 + n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
719 +
720 + if (n0 == MT7621_CHIP_NAME0 && n1 == MT7621_CHIP_NAME1) {
721 + name = "MT7621";
722 + soc_info->compatible = "mtk,mt7621-soc";
723 + } else {
724 + panic("mt7621: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
725 + }
726 +
727 + rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
728 +
729 + snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
730 + "Mediatek %s ver:%u eco:%u",
731 + name,
732 + (rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
733 + (rev & CHIP_REV_ECO_MASK));
734 +
735 + soc_info->mem_size_min = MT7621_DDR2_SIZE_MIN;
736 + soc_info->mem_size_max = MT7621_DDR2_SIZE_MAX;
737 + soc_info->mem_base = MT7621_DRAM_BASE;
738 +
739 + rt2880_pinmux_data = mt7621_pinmux_data;
740 +
741 + if (register_cmp_smp_ops())
742 + panic("failed to register_vsmp_smp_ops()");
743 +}
OpenWrt Source Repository