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[openwrt/openwrt.git] / target / linux / ramips / patches-3.14 / 0012-MIPS-ralink-add-MT7621-support.patch
1 From c8c69923236f2f3f184ddcc7eb41c113b5cc3223 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sun, 27 Jul 2014 10:57:40 +0100
4 Subject: [PATCH 12/57] MIPS: ralink: add MT7621 support
5
6 Signed-off-by: John Crispin <blogic@openwrt.org>
7 ---
8 arch/mips/include/asm/gic.h | 4 +
9 arch/mips/include/asm/mach-ralink/irq.h | 9 +
10 arch/mips/include/asm/mach-ralink/mt7621.h | 39 ++++
11 arch/mips/kernel/vmlinux.lds.S | 1 +
12 arch/mips/ralink/Kconfig | 18 ++
13 arch/mips/ralink/Makefile | 7 +-
14 arch/mips/ralink/Platform | 5 +
15 arch/mips/ralink/irq-gic.c | 271 ++++++++++++++++++++++++++++
16 arch/mips/ralink/malta-amon.c | 81 +++++++++
17 arch/mips/ralink/mt7621.c | 183 +++++++++++++++++++
18 10 files changed, 617 insertions(+), 1 deletion(-)
19 create mode 100644 arch/mips/include/asm/mach-ralink/irq.h
20 create mode 100644 arch/mips/include/asm/mach-ralink/mt7621.h
21 create mode 100644 arch/mips/ralink/irq-gic.c
22 create mode 100644 arch/mips/ralink/malta-amon.c
23 create mode 100644 arch/mips/ralink/mt7621.c
24
25 --- a/arch/mips/include/asm/gic.h
26 +++ b/arch/mips/include/asm/gic.h
27 @@ -19,7 +19,11 @@
28 #define GIC_TRIG_EDGE 1
29 #define GIC_TRIG_LEVEL 0
30
31 +#define GIC_NUM_INTRS 64
32 +
33 +#ifndef GIC_NUM_INTRS
34 #define GIC_NUM_INTRS (24 + NR_CPUS * 2)
35 +#endif
36
37 #define MSK(n) ((1 << (n)) - 1)
38 #define REG32(addr) (*(volatile unsigned int *) (addr))
39 --- /dev/null
40 +++ b/arch/mips/include/asm/mach-ralink/irq.h
41 @@ -0,0 +1,9 @@
42 +#ifndef __ASM_MACH_RALINK_IRQ_H
43 +#define __ASM_MACH_RALINK_IRQ_H
44 +
45 +#define GIC_NUM_INTRS 64
46 +#define NR_IRQS 256
47 +
48 +#include_next <irq.h>
49 +
50 +#endif
51 --- /dev/null
52 +++ b/arch/mips/include/asm/mach-ralink/mt7621.h
53 @@ -0,0 +1,39 @@
54 +/*
55 + * This program is free software; you can redistribute it and/or modify it
56 + * under the terms of the GNU General Public License version 2 as published
57 + * by the Free Software Foundation.
58 + *
59 + * Parts of this file are based on Ralink's 2.6.21 BSP
60 + *
61 + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
62 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
63 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
64 + */
65 +
66 +#ifndef _MT7621_REGS_H_
67 +#define _MT7621_REGS_H_
68 +
69 +#define MT7621_SYSC_BASE 0x1E000000
70 +
71 +#define SYSC_REG_CHIP_NAME0 0x00
72 +#define SYSC_REG_CHIP_NAME1 0x04
73 +#define SYSC_REG_CHIP_REV 0x0c
74 +#define SYSC_REG_SYSTEM_CONFIG0 0x10
75 +#define SYSC_REG_SYSTEM_CONFIG1 0x14
76 +
77 +#define CHIP_REV_PKG_MASK 0x1
78 +#define CHIP_REV_PKG_SHIFT 16
79 +#define CHIP_REV_VER_MASK 0xf
80 +#define CHIP_REV_VER_SHIFT 8
81 +#define CHIP_REV_ECO_MASK 0xf
82 +
83 +#define MT7621_DRAM_BASE 0x0
84 +#define MT7621_DDR2_SIZE_MIN 32
85 +#define MT7621_DDR2_SIZE_MAX 256
86 +
87 +#define MT7621_CHIP_NAME0 0x3637544D
88 +#define MT7621_CHIP_NAME1 0x20203132
89 +
90 +#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8)
91 +
92 +#endif
93 --- a/arch/mips/kernel/vmlinux.lds.S
94 +++ b/arch/mips/kernel/vmlinux.lds.S
95 @@ -51,6 +51,7 @@ SECTIONS
96 /* read-only */
97 _text = .; /* Text and read-only data */
98 .text : {
99 + /*. = . + 0x8000; */
100 TEXT_TEXT
101 SCHED_TEXT
102 LOCK_TEXT
103 --- a/arch/mips/ralink/Kconfig
104 +++ b/arch/mips/ralink/Kconfig
105 @@ -7,6 +7,11 @@ config CLKEVT_RT3352
106 select CLKSRC_OF
107 select CLKSRC_MMIO
108
109 +config IRQ_INTC
110 + bool
111 + default y
112 + depends on !SOC_MT7621
113 +
114 choice
115 prompt "Ralink SoC selection"
116 default SOC_RT305X
117 @@ -34,6 +39,15 @@ choice
118 select USB_ARCH_HAS_OHCI
119 select USB_ARCH_HAS_EHCI
120
121 + config SOC_MT7621
122 + bool "MT7621"
123 + select MIPS_CPU_SCACHE
124 + select SYS_SUPPORTS_MULTITHREADING
125 + select SYS_SUPPORTS_SMP
126 + select SYS_SUPPORTS_MIPS_CMP
127 + select IRQ_GIC
128 + select HW_HAS_PCI
129 +
130 endchoice
131
132 choice
133 @@ -61,6 +75,10 @@ choice
134 bool "MT7620A eval kit"
135 depends on SOC_MT7620
136
137 + config DTB_MT7621_EVAL
138 + bool "MT7621 eval kit"
139 + depends on SOC_MT7621
140 +
141 endchoice
142
143 endif
144 --- a/arch/mips/ralink/Makefile
145 +++ b/arch/mips/ralink/Makefile
146 @@ -6,16 +6,21 @@
147 # Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
148 # Copyright (C) 2013 John Crispin <blogic@openwrt.org>
149
150 -obj-y := prom.o of.o reset.o clk.o irq.o timer.o
151 +obj-y := prom.o of.o reset.o clk.o timer.o
152
153 obj-$(CONFIG_CLKEVT_RT3352) += cevt-rt3352.o
154
155 obj-$(CONFIG_RALINK_ILL_ACC) += ill_acc.o
156
157 +obj-$(CONFIG_IRQ_INTC) += irq.o
158 +obj-$(CONFIG_IRQ_GIC) += irq-gic.o
159 +obj-$(CONFIG_MIPS_MT_SMP) += malta-amon.o
160 +
161 obj-$(CONFIG_SOC_RT288X) += rt288x.o
162 obj-$(CONFIG_SOC_RT305X) += rt305x.o
163 obj-$(CONFIG_SOC_RT3883) += rt3883.o
164 obj-$(CONFIG_SOC_MT7620) += mt7620.o
165 +obj-$(CONFIG_SOC_MT7621) += mt7621.o
166
167 obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
168
169 --- a/arch/mips/ralink/Platform
170 +++ b/arch/mips/ralink/Platform
171 @@ -27,3 +27,8 @@ cflags-$(CONFIG_SOC_RT3883) += -I$(srctr
172 #
173 load-$(CONFIG_SOC_MT7620) += 0xffffffff80000000
174 cflags-$(CONFIG_SOC_MT7620) += -I$(srctree)/arch/mips/include/asm/mach-ralink/mt7620
175 +
176 +# Ralink MT7621
177 +#
178 +load-$(CONFIG_SOC_MT7621) += 0xffffffff80001000
179 +cflags-$(CONFIG_SOC_MT7621) += -I$(srctree)/arch/mips/include/asm/mach-ralink/mt7621
180 --- /dev/null
181 +++ b/arch/mips/ralink/irq-gic.c
182 @@ -0,0 +1,271 @@
183 +#include <linux/init.h>
184 +#include <linux/sched.h>
185 +#include <linux/slab.h>
186 +#include <linux/interrupt.h>
187 +#include <linux/kernel_stat.h>
188 +#include <linux/hardirq.h>
189 +#include <linux/preempt.h>
190 +#include <linux/irqdomain.h>
191 +#include <linux/of_platform.h>
192 +#include <linux/of_address.h>
193 +#include <linux/of_irq.h>
194 +
195 +#include <asm/irq_cpu.h>
196 +#include <asm/mipsregs.h>
197 +
198 +#include <asm/irq.h>
199 +#include <asm/setup.h>
200 +
201 +#include <asm/gic.h>
202 +#include <asm/gcmpregs.h>
203 +
204 +#include <asm/mach-ralink/mt7621.h>
205 +
206 +unsigned long _gcmp_base;
207 +static int gic_resched_int_base = 56;
208 +static int gic_call_int_base = 60;
209 +static struct irq_chip *irq_gic;
210 +static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS];
211 +
212 +#if defined(CONFIG_MIPS_MT_SMP)
213 +static int gic_resched_int_base;
214 +static int gic_call_int_base;
215 +
216 +#define GIC_RESCHED_INT(cpu) (gic_resched_int_base+(cpu))
217 +#define GIC_CALL_INT(cpu) (gic_call_int_base+(cpu))
218 +
219 +static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
220 +{
221 + scheduler_ipi();
222 +
223 + return IRQ_HANDLED;
224 +}
225 +
226 +static irqreturn_t
227 +ipi_call_interrupt(int irq, void *dev_id)
228 +{
229 + smp_call_function_interrupt();
230 +
231 + return IRQ_HANDLED;
232 +}
233 +
234 +static struct irqaction irq_resched = {
235 + .handler = ipi_resched_interrupt,
236 + .flags = IRQF_DISABLED|IRQF_PERCPU,
237 + .name = "ipi resched"
238 +};
239 +
240 +static struct irqaction irq_call = {
241 + .handler = ipi_call_interrupt,
242 + .flags = IRQF_DISABLED|IRQF_PERCPU,
243 + .name = "ipi call"
244 +};
245 +
246 +#endif
247 +
248 +static void __init
249 +gic_fill_map(void)
250 +{
251 + int i;
252 +
253 + for (i = 0; i < ARRAY_SIZE(gic_intr_map); i++) {
254 + gic_intr_map[i].cpunum = 0;
255 + gic_intr_map[i].pin = GIC_CPU_INT0;
256 + gic_intr_map[i].polarity = GIC_POL_POS;
257 + gic_intr_map[i].trigtype = GIC_TRIG_LEVEL;
258 + gic_intr_map[i].flags = GIC_FLAG_IPI;
259 + }
260 +
261 +#if defined(CONFIG_MIPS_MT_SMP)
262 + {
263 + int cpu;
264 +
265 + gic_call_int_base = ARRAY_SIZE(gic_intr_map) - nr_cpu_ids;
266 + gic_resched_int_base = gic_call_int_base - nr_cpu_ids;
267 +
268 + i = gic_resched_int_base;
269 +
270 + for (cpu = 0; cpu < nr_cpu_ids; cpu++) {
271 + gic_intr_map[i + cpu].cpunum = cpu;
272 + gic_intr_map[i + cpu].pin = GIC_CPU_INT1;
273 + gic_intr_map[i + cpu].trigtype = GIC_TRIG_EDGE;
274 +
275 + gic_intr_map[i + cpu + nr_cpu_ids].cpunum = cpu;
276 + gic_intr_map[i + cpu + nr_cpu_ids].pin = GIC_CPU_INT2;
277 + gic_intr_map[i + cpu + nr_cpu_ids].trigtype = GIC_TRIG_EDGE;
278 + }
279 + }
280 +#endif
281 +}
282 +
283 +void
284 +gic_irq_ack(struct irq_data *d)
285 +{
286 + int irq = (d->irq - gic_irq_base);
287 +
288 + GIC_CLR_INTR_MASK(irq);
289 +
290 + if (gic_irq_flags[irq] & GIC_TRIG_EDGE)
291 + GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), irq);
292 +}
293 +
294 +void
295 +gic_finish_irq(struct irq_data *d)
296 +{
297 + GIC_SET_INTR_MASK(d->irq - gic_irq_base);
298 +}
299 +
300 +void __init
301 +gic_platform_init(int irqs, struct irq_chip *irq_controller)
302 +{
303 + irq_gic = irq_controller;
304 +}
305 +
306 +static void
307 +gic_irqdispatch(void)
308 +{
309 + unsigned int irq = gic_get_int();
310 +
311 + if (likely(irq < GIC_NUM_INTRS))
312 + do_IRQ(MIPS_GIC_IRQ_BASE + irq);
313 + else {
314 + pr_debug("Spurious GIC Interrupt!\n");
315 + spurious_interrupt();
316 + }
317 +
318 +}
319 +
320 +static void
321 +vi_timer_irqdispatch(void)
322 +{
323 + do_IRQ(cp0_compare_irq);
324 +}
325 +
326 +#if defined(CONFIG_MIPS_MT_SMP)
327 +unsigned int
328 +plat_ipi_call_int_xlate(unsigned int cpu)
329 +{
330 + return GIC_CALL_INT(cpu);
331 +}
332 +
333 +unsigned int
334 +plat_ipi_resched_int_xlate(unsigned int cpu)
335 +{
336 + return GIC_RESCHED_INT(cpu);
337 +}
338 +#endif
339 +
340 +asmlinkage void
341 +plat_irq_dispatch(void)
342 +{
343 + unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
344 +
345 + if (unlikely(!pending)) {
346 + pr_err("Spurious CP0 Interrupt!\n");
347 + spurious_interrupt();
348 + } else {
349 + if (pending & CAUSEF_IP7)
350 + do_IRQ(cp0_compare_irq);
351 +
352 + if (pending & (CAUSEF_IP4 | CAUSEF_IP3 | CAUSEF_IP2))
353 + gic_irqdispatch();
354 + }
355 +}
356 +
357 +unsigned int __cpuinit
358 +get_c0_compare_int(void)
359 +{
360 + return CP0_LEGACY_COMPARE_IRQ;
361 +}
362 +
363 +static int
364 +gic_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
365 +{
366 + irq_set_chip_and_handler(irq, irq_gic,
367 +#if defined(CONFIG_MIPS_MT_SMP)
368 + (hw >= gic_resched_int_base) ?
369 + handle_percpu_irq :
370 +#endif
371 + handle_level_irq);
372 +
373 + return 0;
374 +}
375 +
376 +static const struct irq_domain_ops irq_domain_ops = {
377 + .xlate = irq_domain_xlate_onecell,
378 + .map = gic_map,
379 +};
380 +
381 +static int __init
382 +of_gic_init(struct device_node *node,
383 + struct device_node *parent)
384 +{
385 + struct irq_domain *domain;
386 + struct resource gcmp = { 0 }, gic = { 0 };
387 + unsigned int gic_rev;
388 + int i;
389 +
390 + if (of_address_to_resource(node, 0, &gic))
391 + panic("Failed to get gic memory range");
392 + if (request_mem_region(gic.start, resource_size(&gic),
393 + gic.name) < 0)
394 + panic("Failed to request gic memory");
395 + if (of_address_to_resource(node, 2, &gcmp))
396 + panic("Failed to get gic memory range");
397 + if (request_mem_region(gcmp.start, resource_size(&gcmp),
398 + gcmp.name) < 0)
399 + panic("Failed to request gcmp memory");
400 +
401 + _gcmp_base = (unsigned long) ioremap_nocache(gcmp.start, resource_size(&gcmp));
402 + if (!_gcmp_base)
403 + panic("Failed to remap gcmp memory\n");
404 +
405 + if ((GCMPGCB(GCMPB) & GCMP_GCB_GCMPB_GCMPBASE_MSK) != gcmp.start)
406 + panic("Failed to find gcmp core\n");
407 +
408 + /* tell the gcmp where to find the gic */
409 + GCMPGCB(GICBA) = gic.start | GCMP_GCB_GICBA_EN_MSK;
410 + gic_present = 1;
411 + if (cpu_has_vint) {
412 + set_vi_handler(2, gic_irqdispatch);
413 + set_vi_handler(3, gic_irqdispatch);
414 + set_vi_handler(4, gic_irqdispatch);
415 + set_vi_handler(7, vi_timer_irqdispatch);
416 + }
417 +
418 + gic_fill_map();
419 +
420 + gic_init(gic.start, resource_size(&gic), gic_intr_map,
421 + ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE);
422 +
423 + GICREAD(GIC_REG(SHARED, GIC_SH_REVISIONID), gic_rev);
424 + pr_info("gic: revision %d.%d\n", (gic_rev >> 8) & 0xff, gic_rev & 0xff);
425 +
426 + domain = irq_domain_add_legacy(node, GIC_NUM_INTRS, MIPS_GIC_IRQ_BASE,
427 + 0, &irq_domain_ops, NULL);
428 + if (!domain)
429 + panic("Failed to add irqdomain");
430 +
431 +#if defined(CONFIG_MIPS_MT_SMP)
432 + for (i = 0; i < nr_cpu_ids; i++) {
433 + setup_irq(MIPS_GIC_IRQ_BASE + GIC_RESCHED_INT(i), &irq_resched);
434 + setup_irq(MIPS_GIC_IRQ_BASE + GIC_CALL_INT(i), &irq_call);
435 + }
436 +#endif
437 +
438 + change_c0_status(ST0_IM, STATUSF_IP7 | STATUSF_IP4 | STATUSF_IP3 |
439 + STATUSF_IP2);
440 + return 0;
441 +}
442 +
443 +static struct of_device_id __initdata of_irq_ids[] = {
444 + { .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_intc_init },
445 + { .compatible = "ralink,mt7621-gic", .data = of_gic_init },
446 + {},
447 +};
448 +
449 +void __init
450 +arch_init_irq(void)
451 +{
452 + of_irq_init(of_irq_ids);
453 +}
454 --- /dev/null
455 +++ b/arch/mips/ralink/malta-amon.c
456 @@ -0,0 +1,81 @@
457 +/*
458 + * Copyright (C) 2007 MIPS Technologies, Inc.
459 + * All rights reserved.
460 +
461 + * This program is free software; you can distribute it and/or modify it
462 + * under the terms of the GNU General Public License (Version 2) as
463 + * published by the Free Software Foundation.
464 + *
465 + * This program is distributed in the hope it will be useful, but WITHOUT
466 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
467 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
468 + * for more details.
469 + *
470 + * You should have received a copy of the GNU General Public License along
471 + * with this program; if not, write to the Free Software Foundation, Inc.,
472 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
473 + *
474 + * Arbitrary Monitor interface
475 + */
476 +
477 +#include <linux/kernel.h>
478 +#include <linux/init.h>
479 +#include <linux/smp.h>
480 +
481 +#include <asm/addrspace.h>
482 +#include <asm/mips-boards/launch.h>
483 +#include <asm/mipsmtregs.h>
484 +
485 +int amon_cpu_avail(int cpu)
486 +{
487 + struct cpulaunch *launch = (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH);
488 +
489 + if (cpu < 0 || cpu >= NCPULAUNCH) {
490 + pr_debug("avail: cpu%d is out of range\n", cpu);
491 + return 0;
492 + }
493 +
494 + launch += cpu;
495 + if (!(launch->flags & LAUNCH_FREADY)) {
496 + pr_debug("avail: cpu%d is not ready\n", cpu);
497 + return 0;
498 + }
499 + if (launch->flags & (LAUNCH_FGO|LAUNCH_FGONE)) {
500 + pr_debug("avail: too late.. cpu%d is already gone\n", cpu);
501 + return 0;
502 + }
503 +
504 + return 1;
505 +}
506 +
507 +void amon_cpu_start(int cpu,
508 + unsigned long pc, unsigned long sp,
509 + unsigned long gp, unsigned long a0)
510 +{
511 + volatile struct cpulaunch *launch =
512 + (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH);
513 +
514 + if (!amon_cpu_avail(cpu))
515 + return;
516 + if (cpu == smp_processor_id()) {
517 + pr_debug("launch: I am cpu%d!\n", cpu);
518 + return;
519 + }
520 + launch += cpu;
521 +
522 + pr_debug("launch: starting cpu%d\n", cpu);
523 +
524 + launch->pc = pc;
525 + launch->gp = gp;
526 + launch->sp = sp;
527 + launch->a0 = a0;
528 +
529 + smp_wmb(); /* Target must see parameters before go */
530 + launch->flags |= LAUNCH_FGO;
531 + smp_wmb(); /* Target must see go before we poll */
532 +
533 + while ((launch->flags & LAUNCH_FGONE) == 0)
534 + ;
535 + smp_rmb(); /* Target will be updating flags soon */
536 + pr_debug("launch: cpu%d gone!\n", cpu);
537 +}
538 --- /dev/null
539 +++ b/arch/mips/ralink/mt7621.c
540 @@ -0,0 +1,183 @@
541 +/*
542 + * This program is free software; you can redistribute it and/or modify it
543 + * under the terms of the GNU General Public License version 2 as published
544 + * by the Free Software Foundation.
545 + *
546 + * Parts of this file are based on Ralink's 2.6.21 BSP
547 + *
548 + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
549 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
550 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
551 + */
552 +
553 +#include <linux/kernel.h>
554 +#include <linux/init.h>
555 +#include <linux/module.h>
556 +#include <asm/gcmpregs.h>
557 +
558 +#include <asm/mipsregs.h>
559 +#include <asm/smp-ops.h>
560 +#include <asm/mach-ralink/ralink_regs.h>
561 +#include <asm/mach-ralink/mt7621.h>
562 +
563 +#include <pinmux.h>
564 +
565 +#include "common.h"
566 +
567 +#define SYSC_REG_SYSCFG 0x10
568 +#define SYSC_REG_CPLL_CLKCFG0 0x2c
569 +#define SYSC_REG_CUR_CLK_STS 0x44
570 +#define CPU_CLK_SEL (BIT(30) | BIT(31))
571 +
572 +#define MT7621_GPIO_MODE_UART1 1
573 +#define MT7621_GPIO_MODE_I2C 2
574 +#define MT7621_GPIO_MODE_UART2 3
575 +#define MT7621_GPIO_MODE_UART3 5
576 +#define MT7621_GPIO_MODE_JTAG 7
577 +#define MT7621_GPIO_MODE_WDT_MASK 0x3
578 +#define MT7621_GPIO_MODE_WDT_SHIFT 8
579 +#define MT7621_GPIO_MODE_WDT_GPIO 1
580 +#define MT7621_GPIO_MODE_PCIE_RST 0
581 +#define MT7621_GPIO_MODE_PCIE_REF 2
582 +#define MT7621_GPIO_MODE_PCIE_MASK 0x3
583 +#define MT7621_GPIO_MODE_PCIE_SHIFT 10
584 +#define MT7621_GPIO_MODE_PCIE_GPIO 1
585 +#define MT7621_GPIO_MODE_MDIO 12
586 +#define MT7621_GPIO_MODE_RGMII1 14
587 +#define MT7621_GPIO_MODE_RGMII2 15
588 +#define MT7621_GPIO_MODE_SPI_MASK 0x3
589 +#define MT7621_GPIO_MODE_SPI_SHIFT 16
590 +#define MT7621_GPIO_MODE_SPI_GPIO 1
591 +#define MT7621_GPIO_MODE_SDHCI_MASK 0x3
592 +#define MT7621_GPIO_MODE_SDHCI_SHIFT 18
593 +#define MT7621_GPIO_MODE_SDHCI_GPIO 1
594 +
595 +static struct rt2880_pmx_func uart1_grp[] = { FUNC("uart", 0, 1, 2) };
596 +static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 3, 2) };
597 +static struct rt2880_pmx_func uart3_grp[] = { FUNC("uart", 0, 5, 4) };
598 +static struct rt2880_pmx_func uart2_grp[] = { FUNC("uart", 0, 9, 4) };
599 +static struct rt2880_pmx_func jtag_grp[] = { FUNC("jtag", 0, 13, 5) };
600 +static struct rt2880_pmx_func wdt_grp[] = {
601 + FUNC("wdt rst", 0, 18, 1),
602 + FUNC("wdt refclk", 2, 18, 1),
603 +};
604 +static struct rt2880_pmx_func pcie_rst_grp[] = {
605 + FUNC("pcie rst", MT7621_GPIO_MODE_PCIE_RST, 19, 1),
606 + FUNC("pcie refclk", MT7621_GPIO_MODE_PCIE_REF, 19, 1)
607 +};
608 +static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 0, 20, 2) };
609 +static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii", 0, 22, 12) };
610 +static struct rt2880_pmx_func spi_grp[] = {
611 + FUNC("spi", 0, 34, 7),
612 + FUNC("nand", 2, 34, 8),
613 +};
614 +static struct rt2880_pmx_func sdhci_grp[] = {
615 + FUNC("sdhci", 0, 41, 8),
616 + FUNC("nand", 2, 41, 8),
617 +};
618 +static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii", 0, 49, 12) };
619 +
620 +static struct rt2880_pmx_group mt7621_pinmux_data[] = {
621 + GRP("uart1", uart1_grp, 1, MT7621_GPIO_MODE_UART1),
622 + GRP("i2c", i2c_grp, 1, MT7621_GPIO_MODE_I2C),
623 + GRP("uart3", uart2_grp, 1, MT7621_GPIO_MODE_UART2),
624 + GRP("uart2", uart3_grp, 1, MT7621_GPIO_MODE_UART3),
625 + GRP("jtag", jtag_grp, 1, MT7621_GPIO_MODE_JTAG),
626 + GRP_G("wdt", wdt_grp, MT7621_GPIO_MODE_WDT_MASK,
627 + MT7621_GPIO_MODE_WDT_GPIO, MT7621_GPIO_MODE_WDT_SHIFT),
628 + GRP_G("pcie", pcie_rst_grp, MT7621_GPIO_MODE_PCIE_MASK,
629 + MT7621_GPIO_MODE_PCIE_GPIO, MT7621_GPIO_MODE_PCIE_SHIFT),
630 + GRP("mdio", mdio_grp, 1, MT7621_GPIO_MODE_MDIO),
631 + GRP("rgmii2", rgmii2_grp, 1, MT7621_GPIO_MODE_RGMII2),
632 + GRP_G("spi", spi_grp, MT7621_GPIO_MODE_SPI_MASK,
633 + MT7621_GPIO_MODE_SPI_GPIO, MT7621_GPIO_MODE_SPI_SHIFT),
634 + GRP_G("sdhci", sdhci_grp, MT7621_GPIO_MODE_SDHCI_MASK,
635 + MT7621_GPIO_MODE_SDHCI_GPIO, MT7621_GPIO_MODE_SDHCI_SHIFT),
636 + GRP("rgmii1", rgmii1_grp, 1, MT7621_GPIO_MODE_RGMII1),
637 + { 0 }
638 +};
639 +
640 +void __init ralink_clk_init(void)
641 +{
642 + int cpu_fdiv = 0;
643 + int cpu_ffrac = 0;
644 + int fbdiv = 0;
645 + u32 clk_sts, syscfg;
646 + u8 clk_sel = 0, xtal_mode;
647 + u32 cpu_clk;
648 +
649 + if ((rt_sysc_r32(SYSC_REG_CPLL_CLKCFG0) & CPU_CLK_SEL) != 0)
650 + clk_sel = 1;
651 +
652 + switch (clk_sel) {
653 + case 0:
654 + clk_sts = rt_sysc_r32(SYSC_REG_CUR_CLK_STS);
655 + cpu_fdiv = ((clk_sts >> 8) & 0x1F);
656 + cpu_ffrac = (clk_sts & 0x1F);
657 + cpu_clk = (500 * cpu_ffrac / cpu_fdiv) * 1000 * 1000;
658 + break;
659 +
660 + case 1:
661 + fbdiv = ((rt_sysc_r32(0x648) >> 4) & 0x7F) + 1;
662 + syscfg = rt_sysc_r32(SYSC_REG_SYSCFG);
663 + xtal_mode = (syscfg >> 6) & 0x7;
664 + if(xtal_mode >= 6) { //25Mhz Xtal
665 + cpu_clk = 25 * fbdiv * 1000 * 1000;
666 + } else if(xtal_mode >=3) { //40Mhz Xtal
667 + cpu_clk = 40 * fbdiv * 1000 * 1000;
668 + } else { // 20Mhz Xtal
669 + cpu_clk = 20 * fbdiv * 1000 * 1000;
670 + }
671 + break;
672 + }
673 + cpu_clk = 880000000;
674 + ralink_clk_add("cpu", cpu_clk);
675 + ralink_clk_add("1e000b00.spi", 50000000);
676 + ralink_clk_add("1e000c00.uartlite", 50000000);
677 + ralink_clk_add("1e000d00.uart", 50000000);
678 +}
679 +
680 +void __init ralink_of_remap(void)
681 +{
682 + rt_sysc_membase = plat_of_remap_node("mtk,mt7621-sysc");
683 + rt_memc_membase = plat_of_remap_node("mtk,mt7621-memc");
684 +
685 + if (!rt_sysc_membase || !rt_memc_membase)
686 + panic("Failed to remap core resources");
687 +}
688 +
689 +void prom_soc_init(struct ralink_soc_info *soc_info)
690 +{
691 + void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7621_SYSC_BASE);
692 + unsigned char *name = NULL;
693 + u32 n0;
694 + u32 n1;
695 + u32 rev;
696 +
697 + n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
698 + n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
699 +
700 + if (n0 == MT7621_CHIP_NAME0 && n1 == MT7621_CHIP_NAME1) {
701 + name = "MT7621";
702 + soc_info->compatible = "mtk,mt7621-soc";
703 + } else {
704 + panic("mt7621: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
705 + }
706 +
707 + rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
708 +
709 + snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
710 + "Mediatek %s ver:%u eco:%u",
711 + name,
712 + (rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
713 + (rev & CHIP_REV_ECO_MASK));
714 +
715 + soc_info->mem_size_min = MT7621_DDR2_SIZE_MIN;
716 + soc_info->mem_size_max = MT7621_DDR2_SIZE_MAX;
717 + soc_info->mem_base = MT7621_DRAM_BASE;
718 +
719 + rt2880_pinmux_data = mt7621_pinmux_data;
720 +
721 + if (register_cmp_smp_ops())
722 + panic("failed to register_vsmp_smp_ops()");
723 +}
OpenWrt Source Repository