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[openwrt/openwrt.git] / target / linux / ramips / patches-3.14 / 0014-MIPS-ralink-add-MT7621-dts-file.patch
1 From 34e2a5ededc6140f311b3b3c88edf4e18e88126a Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Fri, 24 Jan 2014 17:01:22 +0100
4 Subject: [PATCH 14/57] MIPS: ralink: add MT7621 dts file
5
6 Signed-off-by: John Crispin <blogic@openwrt.org>
7 ---
8 arch/mips/ralink/dts/Makefile | 1 +
9 arch/mips/ralink/dts/mt7621.dtsi | 257 ++++++++++++++++++++++++++++++++++
10 arch/mips/ralink/dts/mt7621_eval.dts | 16 +++
11 3 files changed, 274 insertions(+)
12 create mode 100644 arch/mips/ralink/dts/mt7621.dtsi
13 create mode 100644 arch/mips/ralink/dts/mt7621_eval.dts
14
15 --- a/arch/mips/ralink/dts/Makefile
16 +++ b/arch/mips/ralink/dts/Makefile
17 @@ -2,3 +2,4 @@ obj-$(CONFIG_DTB_RT2880_EVAL) := rt2880_
18 obj-$(CONFIG_DTB_RT305X_EVAL) := rt3052_eval.dtb.o
19 obj-$(CONFIG_DTB_RT3883_EVAL) := rt3883_eval.dtb.o
20 obj-$(CONFIG_DTB_MT7620A_EVAL) := mt7620a_eval.dtb.o
21 +obj-$(CONFIG_DTB_MT7621_EVAL) := mt7621_eval.dtb.o
22 --- /dev/null
23 +++ b/arch/mips/ralink/dts/mt7621.dtsi
24 @@ -0,0 +1,257 @@
25 +/ {
26 + #address-cells = <1>;
27 + #size-cells = <1>;
28 + compatible = "ralink,mtk7620a-soc";
29 +
30 + cpus {
31 + cpu@0 {
32 + compatible = "mips,mips24KEc";
33 + };
34 + };
35 +
36 + cpuintc: cpuintc@0 {
37 + #address-cells = <0>;
38 + #interrupt-cells = <1>;
39 + interrupt-controller;
40 + compatible = "mti,cpu-interrupt-controller";
41 + };
42 +
43 + palmbus@1E000000 {
44 + compatible = "palmbus";
45 + reg = <0x1E000000 0x100000>;
46 + ranges = <0x0 0x1E000000 0x0FFFFF>;
47 +
48 + #address-cells = <1>;
49 + #size-cells = <1>;
50 +
51 + sysc@0 {
52 + compatible = "mtk,mt7621-sysc";
53 + reg = <0x0 0x100>;
54 + };
55 +
56 + wdt@100 {
57 + compatible = "mtk,mt7621-wdt";
58 + reg = <0x100 0x100>;
59 + };
60 +
61 + gpio@600 {
62 + #address-cells = <1>;
63 + #size-cells = <0>;
64 +
65 + compatible = "mtk,mt7621-gpio";
66 + reg = <0x600 0x100>;
67 +
68 + gpio0: bank@0 {
69 + reg = <0>;
70 + compatible = "mtk,mt7621-gpio-bank";
71 + gpio-controller;
72 + #gpio-cells = <2>;
73 + };
74 +
75 + gpio1: bank@1 {
76 + reg = <1>;
77 + compatible = "mtk,mt7621-gpio-bank";
78 + gpio-controller;
79 + #gpio-cells = <2>;
80 + };
81 +
82 + gpio2: bank@2 {
83 + reg = <2>;
84 + compatible = "mtk,mt7621-gpio-bank";
85 + gpio-controller;
86 + #gpio-cells = <2>;
87 + };
88 + };
89 +
90 + memc@5000 {
91 + compatible = "mtk,mt7621-memc";
92 + reg = <0x300 0x100>;
93 + };
94 +
95 + uartlite@c00 {
96 + compatible = "ns16550a";
97 + reg = <0xc00 0x100>;
98 +
99 + interrupt-parent = <&gic>;
100 + interrupts = <26>;
101 +
102 + reg-shift = <2>;
103 + reg-io-width = <4>;
104 + no-loopback-test;
105 + };
106 +
107 + uart@d00 {
108 + compatible = "ns16550a";
109 + reg = <0xd00 0x100>;
110 +
111 + interrupt-parent = <&gic>;
112 + interrupts = <27>;
113 +
114 + fifo-size = <16>;
115 + reg-shift = <2>;
116 + reg-io-width = <4>;
117 + no-loopback-test;
118 + };
119 +
120 + spi@b00 {
121 + status = "okay";
122 +
123 + compatible = "ralink,mt7621-spi";
124 + reg = <0xb00 0x100>;
125 +
126 + resets = <&rstctrl 18>;
127 + reset-names = "spi";
128 +
129 + #address-cells = <1>;
130 + #size-cells = <1>;
131 +
132 +/* pinctrl-names = "default";
133 + pinctrl-0 = <&spi_pins>;*/
134 +
135 + m25p80@0 {
136 + #address-cells = <1>;
137 + #size-cells = <1>;
138 + compatible = "en25q64";
139 + reg = <0 0>;
140 + linux,modalias = "m25p80", "en25q64";
141 + spi-max-frequency = <10000000>;
142 +
143 + m25p,chunked-io;
144 +
145 + partition@0 {
146 + label = "u-boot";
147 + reg = <0x0 0x30000>;
148 + read-only;
149 + };
150 +
151 + partition@30000 {
152 + label = "u-boot-env";
153 + reg = <0x30000 0x10000>;
154 + read-only;
155 + };
156 +
157 + factory: partition@40000 {
158 + label = "factory";
159 + reg = <0x40000 0x10000>;
160 + read-only;
161 + };
162 +
163 + partition@50000 {
164 + label = "firmware";
165 + reg = <0x50000 0x7a0000>;
166 + };
167 +
168 + partition@7f0000 {
169 + label = "test";
170 + reg = <0x7f0000 0x10000>;
171 + };
172 + };
173 + };
174 + };
175 +
176 + rstctrl: rstctrl {
177 + compatible = "ralink,rt2880-reset";
178 + #reset-cells = <1>;
179 + };
180 +
181 + sdhci@1E130000 {
182 + compatible = "ralink,mt7620a-sdhci";
183 + reg = <0x1E130000 4000>;
184 +
185 + interrupt-parent = <&gic>;
186 + interrupts = <20>;
187 + };
188 +
189 + xhci@1E1C0000 {
190 + compatible = "xhci-platform";
191 + reg = <0x1E1C0000 4000>;
192 +
193 + interrupt-parent = <&gic>;
194 + interrupts = <22>;
195 + };
196 +
197 + gic: gic@1fbc0000 {
198 + #address-cells = <0>;
199 + #interrupt-cells = <1>;
200 + interrupt-controller;
201 + compatible = "ralink,mt7621-gic";
202 + reg = < 0x1fbc0000 0x80 /* gic */
203 + 0x1fbf0000 0x8000 /* cpc */
204 + 0x1fbf8000 0x8000 /* gpmc */
205 + >;
206 + };
207 +
208 + nand@1e003000 {
209 + compatible = "mtk,mt7621-nand";
210 + bank-width = <2>;
211 + reg = <0x1e003000 0x800
212 + 0x1e003800 0x800>;
213 + #address-cells = <1>;
214 + #size-cells = <1>;
215 +
216 + partition@0 {
217 + label = "uboot";
218 + reg = <0x00000 0x80000>; /* 64 KB */
219 + };
220 + partition@80000 {
221 + label = "uboot_env";
222 + reg = <0x80000 0x80000>; /* 64 KB */
223 + };
224 + partition@100000 {
225 + label = "factory";
226 + reg = <0x100000 0x40000>;
227 + };
228 + partition@140000 {
229 + label = "rootfs";
230 + reg = <0x140000 0xec0000>;
231 + };
232 + };
233 +
234 + ethernet@1e100000 {
235 + compatible = "ralink,mt7621-eth";
236 + reg = <0x1e100000 10000>;
237 +
238 + #address-cells = <1>;
239 + #size-cells = <0>;
240 +
241 + ralink,port-map = "llllw";
242 +
243 + interrupt-parent = <&gic>;
244 + interrupts = <3>;
245 +
246 +/* resets = <&rstctrl 21 &rstctrl 23>;
247 + reset-names = "fe", "esw";
248 +
249 + port@4 {
250 + compatible = "ralink,mt7620a-gsw-port", "ralink,eth-port";
251 + reg = <4>;
252 +
253 + status = "disabled";
254 + };
255 +
256 + port@5 {
257 + compatible = "ralink,mt7620a-gsw-port", "ralink,eth-port";
258 + reg = <5>;
259 +
260 + status = "disabled";
261 + };
262 +*/
263 + mdio-bus {
264 + #address-cells = <1>;
265 + #size-cells = <0>;
266 +
267 + phy1f: ethernet-phy@1f {
268 + reg = <0x1f>;
269 + phy-mode = "rgmii";
270 +
271 +/* interrupt-parent = <&gic>;
272 + interrupts = <23>;
273 +*/ };
274 + };
275 + };
276 +
277 + gsw@1e110000 {
278 + compatible = "ralink,mt7620a-gsw";
279 + reg = <0x1e110000 8000>;
280 + };
281 +};
282 --- /dev/null
283 +++ b/arch/mips/ralink/dts/mt7621_eval.dts
284 @@ -0,0 +1,16 @@
285 +/dts-v1/;
286 +
287 +/include/ "mt7621.dtsi"
288 +
289 +/ {
290 + compatible = "ralink,mt7621-eval-board", "ralink,mt7621-soc";
291 + model = "Ralink MT7621 evaluation board";
292 +
293 + memory@0 {
294 + reg = <0x0 0x2000000>;
295 + };
296 +
297 + chosen {
298 + bootargs = "console=ttyS0,57600";
299 + };
300 +};
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