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kernel: refresh patches
[openwrt/openwrt.git] / target / linux / ramips / patches-3.14 / 0030-pinctrl-ralink-add-pinctrl-driver.patch
1 From 675c6ddd9432c39f508f9d6bdda17d9c675788cf Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sun, 27 Jul 2014 09:34:05 +0100
4 Subject: [PATCH 30/57] pinctrl: ralink: add pinctrl driver
5
6 Signed-off-by: John Crispin <blogic@openwrt.org>
7 ---
8 arch/mips/Kconfig | 2 +
9 arch/mips/include/asm/mach-ralink/mt7620.h | 41 ++-
10 arch/mips/include/asm/mach-ralink/pinmux.h | 53 ++++
11 arch/mips/include/asm/mach-ralink/rt305x.h | 35 ++-
12 arch/mips/include/asm/mach-ralink/rt3883.h | 16 +-
13 arch/mips/ralink/common.h | 19 --
14 arch/mips/ralink/mt7620.c | 159 +++-------
15 arch/mips/ralink/rt288x.c | 62 ++--
16 arch/mips/ralink/rt305x.c | 151 ++++-----
17 arch/mips/ralink/rt3883.c | 173 +++--------
18 drivers/pinctrl/Kconfig | 5 +
19 drivers/pinctrl/Makefile | 1 +
20 drivers/pinctrl/pinctrl-rt2880.c | 467 ++++++++++++++++++++++++++++
21 13 files changed, 764 insertions(+), 420 deletions(-)
22 create mode 100644 arch/mips/include/asm/mach-ralink/pinmux.h
23 create mode 100644 drivers/pinctrl/pinctrl-rt2880.c
24
25 --- a/arch/mips/Kconfig
26 +++ b/arch/mips/Kconfig
27 @@ -435,6 +435,8 @@ config RALINK
28 select CLKDEV_LOOKUP
29 select ARCH_HAS_RESET_CONTROLLER
30 select RESET_CONTROLLER
31 + select PINCTRL
32 + select PINCTRL_RT2880
33
34 config SGI_IP22
35 bool "SGI IP22 (Indy/Indigo2)"
36 --- a/arch/mips/include/asm/mach-ralink/mt7620.h
37 +++ b/arch/mips/include/asm/mach-ralink/mt7620.h
38 @@ -90,7 +90,6 @@ enum mt762x_soc_type {
39 #define MT7620_DDR2_SIZE_MIN 32
40 #define MT7620_DDR2_SIZE_MAX 256
41
42 -#define MT7620_GPIO_MODE_I2C BIT(0)
43 #define MT7620_GPIO_MODE_UART0_SHIFT 2
44 #define MT7620_GPIO_MODE_UART0_MASK 0x7
45 #define MT7620_GPIO_MODE_UART0(x) ((x) << MT7620_GPIO_MODE_UART0_SHIFT)
46 @@ -102,16 +101,36 @@ enum mt762x_soc_type {
47 #define MT7620_GPIO_MODE_GPIO_UARTF 0x5
48 #define MT7620_GPIO_MODE_GPIO_I2S 0x6
49 #define MT7620_GPIO_MODE_GPIO 0x7
50 -#define MT7620_GPIO_MODE_UART1 BIT(5)
51 -#define MT7620_GPIO_MODE_MDIO BIT(8)
52 -#define MT7620_GPIO_MODE_RGMII1 BIT(9)
53 -#define MT7620_GPIO_MODE_RGMII2 BIT(10)
54 -#define MT7620_GPIO_MODE_SPI BIT(11)
55 -#define MT7620_GPIO_MODE_SPI_REF_CLK BIT(12)
56 -#define MT7620_GPIO_MODE_WLED BIT(13)
57 -#define MT7620_GPIO_MODE_JTAG BIT(15)
58 -#define MT7620_GPIO_MODE_EPHY BIT(15)
59 -#define MT7620_GPIO_MODE_WDT BIT(22)
60 +
61 +#define MT7620_GPIO_MODE_NAND 0
62 +#define MT7620_GPIO_MODE_SD 1
63 +#define MT7620_GPIO_MODE_ND_SD_GPIO 2
64 +#define MT7620_GPIO_MODE_ND_SD_MASK 0x3
65 +#define MT7620_GPIO_MODE_ND_SD_SHIFT 18
66 +
67 +#define MT7620_GPIO_MODE_PCIE_RST 0
68 +#define MT7620_GPIO_MODE_PCIE_REF 1
69 +#define MT7620_GPIO_MODE_PCIE_GPIO 2
70 +#define MT7620_GPIO_MODE_PCIE_MASK 0x3
71 +#define MT7620_GPIO_MODE_PCIE_SHIFT 16
72 +
73 +#define MT7620_GPIO_MODE_WDT_RST 0
74 +#define MT7620_GPIO_MODE_WDT_REF 1
75 +#define MT7620_GPIO_MODE_WDT_GPIO 2
76 +#define MT7620_GPIO_MODE_WDT_MASK 0x3
77 +#define MT7620_GPIO_MODE_WDT_SHIFT 21
78 +
79 +#define MT7620_GPIO_MODE_I2C 0
80 +#define MT7620_GPIO_MODE_UART1 5
81 +#define MT7620_GPIO_MODE_MDIO 8
82 +#define MT7620_GPIO_MODE_RGMII1 9
83 +#define MT7620_GPIO_MODE_RGMII2 10
84 +#define MT7620_GPIO_MODE_SPI 11
85 +#define MT7620_GPIO_MODE_SPI_REF_CLK 12
86 +#define MT7620_GPIO_MODE_WLED 13
87 +#define MT7620_GPIO_MODE_JTAG 15
88 +#define MT7620_GPIO_MODE_EPHY 15
89 +#define MT7620_GPIO_MODE_PA 20
90
91 static inline int mt7620_get_eco(void)
92 {
93 --- /dev/null
94 +++ b/arch/mips/include/asm/mach-ralink/pinmux.h
95 @@ -0,0 +1,53 @@
96 +/*
97 + * This program is free software; you can redistribute it and/or modify
98 + * it under the terms of the GNU General Public License version 2 as
99 + * publishhed by the Free Software Foundation.
100 + *
101 + * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
102 + */
103 +
104 +#ifndef _RT288X_PINMUX_H__
105 +#define _RT288X_PINMUX_H__
106 +
107 +#define FUNC(name, value, pin_first, pin_count) { name, value, pin_first, pin_count }
108 +#define GRP(_name, _func, _mask, _shift) \
109 + { .name = _name, .mask = _mask, .shift = _shift, \
110 + .func = _func, .gpio = _mask, \
111 + .func_count = ARRAY_SIZE(_func) }
112 +
113 +#define GRP_G(_name, _func, _mask, _gpio, _shift) \
114 + { .name = _name, .mask = _mask, .shift = _shift, \
115 + .func = _func, .gpio = _gpio, \
116 + .func_count = ARRAY_SIZE(_func) }
117 +
118 +struct rt2880_pmx_group;
119 +
120 +struct rt2880_pmx_func {
121 + const char *name;
122 + const char value;
123 +
124 + int pin_first;
125 + int pin_count;
126 + int *pins;
127 +
128 + int *groups;
129 + int group_count;
130 +
131 + int enabled;
132 +};
133 +
134 +struct rt2880_pmx_group {
135 + const char *name;
136 + int enabled;
137 +
138 + const u32 shift;
139 + const char mask;
140 + const char gpio;
141 +
142 + struct rt2880_pmx_func *func;
143 + int func_count;
144 +};
145 +
146 +extern struct rt2880_pmx_group *rt2880_pinmux_data;
147 +
148 +#endif
149 --- a/arch/mips/include/asm/mach-ralink/rt305x.h
150 +++ b/arch/mips/include/asm/mach-ralink/rt305x.h
151 @@ -125,24 +125,29 @@ static inline int soc_is_rt5350(void)
152 #define RT305X_GPIO_GE0_TXD0 40
153 #define RT305X_GPIO_GE0_RXCLK 51
154
155 -#define RT305X_GPIO_MODE_I2C BIT(0)
156 -#define RT305X_GPIO_MODE_SPI BIT(1)
157 #define RT305X_GPIO_MODE_UART0_SHIFT 2
158 #define RT305X_GPIO_MODE_UART0_MASK 0x7
159 #define RT305X_GPIO_MODE_UART0(x) ((x) << RT305X_GPIO_MODE_UART0_SHIFT)
160 -#define RT305X_GPIO_MODE_UARTF 0x0
161 -#define RT305X_GPIO_MODE_PCM_UARTF 0x1
162 -#define RT305X_GPIO_MODE_PCM_I2S 0x2
163 -#define RT305X_GPIO_MODE_I2S_UARTF 0x3
164 -#define RT305X_GPIO_MODE_PCM_GPIO 0x4
165 -#define RT305X_GPIO_MODE_GPIO_UARTF 0x5
166 -#define RT305X_GPIO_MODE_GPIO_I2S 0x6
167 -#define RT305X_GPIO_MODE_GPIO 0x7
168 -#define RT305X_GPIO_MODE_UART1 BIT(5)
169 -#define RT305X_GPIO_MODE_JTAG BIT(6)
170 -#define RT305X_GPIO_MODE_MDIO BIT(7)
171 -#define RT305X_GPIO_MODE_SDRAM BIT(8)
172 -#define RT305X_GPIO_MODE_RGMII BIT(9)
173 +#define RT305X_GPIO_MODE_UARTF 0
174 +#define RT305X_GPIO_MODE_PCM_UARTF 1
175 +#define RT305X_GPIO_MODE_PCM_I2S 2
176 +#define RT305X_GPIO_MODE_I2S_UARTF 3
177 +#define RT305X_GPIO_MODE_PCM_GPIO 4
178 +#define RT305X_GPIO_MODE_GPIO_UARTF 5
179 +#define RT305X_GPIO_MODE_GPIO_I2S 6
180 +#define RT305X_GPIO_MODE_GPIO 7
181 +
182 +#define RT305X_GPIO_MODE_I2C 0
183 +#define RT305X_GPIO_MODE_SPI 1
184 +#define RT305X_GPIO_MODE_UART1 5
185 +#define RT305X_GPIO_MODE_JTAG 6
186 +#define RT305X_GPIO_MODE_MDIO 7
187 +#define RT305X_GPIO_MODE_SDRAM 8
188 +#define RT305X_GPIO_MODE_RGMII 9
189 +#define RT5350_GPIO_MODE_PHY_LED 14
190 +#define RT5350_GPIO_MODE_SPI_CS1 21
191 +#define RT3352_GPIO_MODE_LNA 18
192 +#define RT3352_GPIO_MODE_PA 20
193
194 #define RT3352_SYSC_REG_SYSCFG0 0x010
195 #define RT3352_SYSC_REG_SYSCFG1 0x014
196 --- a/arch/mips/include/asm/mach-ralink/rt3883.h
197 +++ b/arch/mips/include/asm/mach-ralink/rt3883.h
198 @@ -112,8 +112,6 @@
199 #define RT3883_CLKCFG1_PCI_CLK_EN BIT(19)
200 #define RT3883_CLKCFG1_UPHY0_CLK_EN BIT(18)
201
202 -#define RT3883_GPIO_MODE_I2C BIT(0)
203 -#define RT3883_GPIO_MODE_SPI BIT(1)
204 #define RT3883_GPIO_MODE_UART0_SHIFT 2
205 #define RT3883_GPIO_MODE_UART0_MASK 0x7
206 #define RT3883_GPIO_MODE_UART0(x) ((x) << RT3883_GPIO_MODE_UART0_SHIFT)
207 @@ -125,11 +123,15 @@
208 #define RT3883_GPIO_MODE_GPIO_UARTF 0x5
209 #define RT3883_GPIO_MODE_GPIO_I2S 0x6
210 #define RT3883_GPIO_MODE_GPIO 0x7
211 -#define RT3883_GPIO_MODE_UART1 BIT(5)
212 -#define RT3883_GPIO_MODE_JTAG BIT(6)
213 -#define RT3883_GPIO_MODE_MDIO BIT(7)
214 -#define RT3883_GPIO_MODE_GE1 BIT(9)
215 -#define RT3883_GPIO_MODE_GE2 BIT(10)
216 +
217 +#define RT3883_GPIO_MODE_I2C 0
218 +#define RT3883_GPIO_MODE_SPI 1
219 +#define RT3883_GPIO_MODE_UART1 5
220 +#define RT3883_GPIO_MODE_JTAG 6
221 +#define RT3883_GPIO_MODE_MDIO 7
222 +#define RT3883_GPIO_MODE_GE1 9
223 +#define RT3883_GPIO_MODE_GE2 10
224 +
225 #define RT3883_GPIO_MODE_PCI_SHIFT 11
226 #define RT3883_GPIO_MODE_PCI_MASK 0x7
227 #define RT3883_GPIO_MODE_PCI (RT3883_GPIO_MODE_PCI_MASK << RT3883_GPIO_MODE_PCI_SHIFT)
228 --- a/arch/mips/ralink/common.h
229 +++ b/arch/mips/ralink/common.h
230 @@ -11,25 +11,6 @@
231
232 #define RAMIPS_SYS_TYPE_LEN 32
233
234 -struct ralink_pinmux_grp {
235 - const char *name;
236 - u32 mask;
237 - int gpio_first;
238 - int gpio_last;
239 -};
240 -
241 -struct ralink_pinmux {
242 - struct ralink_pinmux_grp *mode;
243 - struct ralink_pinmux_grp *uart;
244 - int uart_shift;
245 - u32 uart_mask;
246 - void (*wdt_reset)(void);
247 - struct ralink_pinmux_grp *pci;
248 - int pci_shift;
249 - u32 pci_mask;
250 -};
251 -extern struct ralink_pinmux rt_gpio_pinmux;
252 -
253 struct ralink_soc_info {
254 unsigned char sys_type[RAMIPS_SYS_TYPE_LEN];
255 unsigned char *compatible;
256 --- a/arch/mips/ralink/mt7620.c
257 +++ b/arch/mips/ralink/mt7620.c
258 @@ -17,6 +17,7 @@
259 #include <asm/mipsregs.h>
260 #include <asm/mach-ralink/ralink_regs.h>
261 #include <asm/mach-ralink/mt7620.h>
262 +#include <asm/mach-ralink/pinmux.h>
263
264 #include "common.h"
265
266 @@ -47,118 +48,58 @@ enum mt762x_soc_type mt762x_soc;
267 /* does the board have sdram or ddram */
268 static int dram_type;
269
270 -static struct ralink_pinmux_grp mode_mux[] = {
271 - {
272 - .name = "i2c",
273 - .mask = MT7620_GPIO_MODE_I2C,
274 - .gpio_first = 1,
275 - .gpio_last = 2,
276 - }, {
277 - .name = "spi",
278 - .mask = MT7620_GPIO_MODE_SPI,
279 - .gpio_first = 3,
280 - .gpio_last = 6,
281 - }, {
282 - .name = "uartlite",
283 - .mask = MT7620_GPIO_MODE_UART1,
284 - .gpio_first = 15,
285 - .gpio_last = 16,
286 - }, {
287 - .name = "wdt",
288 - .mask = MT7620_GPIO_MODE_WDT,
289 - .gpio_first = 17,
290 - .gpio_last = 17,
291 - }, {
292 - .name = "mdio",
293 - .mask = MT7620_GPIO_MODE_MDIO,
294 - .gpio_first = 22,
295 - .gpio_last = 23,
296 - }, {
297 - .name = "rgmii1",
298 - .mask = MT7620_GPIO_MODE_RGMII1,
299 - .gpio_first = 24,
300 - .gpio_last = 35,
301 - }, {
302 - .name = "spi refclk",
303 - .mask = MT7620_GPIO_MODE_SPI_REF_CLK,
304 - .gpio_first = 37,
305 - .gpio_last = 39,
306 - }, {
307 - .name = "jtag",
308 - .mask = MT7620_GPIO_MODE_JTAG,
309 - .gpio_first = 40,
310 - .gpio_last = 44,
311 - }, {
312 - /* shared lines with jtag */
313 - .name = "ephy",
314 - .mask = MT7620_GPIO_MODE_EPHY,
315 - .gpio_first = 40,
316 - .gpio_last = 44,
317 - }, {
318 - .name = "nand",
319 - .mask = MT7620_GPIO_MODE_JTAG,
320 - .gpio_first = 45,
321 - .gpio_last = 59,
322 - }, {
323 - .name = "rgmii2",
324 - .mask = MT7620_GPIO_MODE_RGMII2,
325 - .gpio_first = 60,
326 - .gpio_last = 71,
327 - }, {
328 - .name = "wled",
329 - .mask = MT7620_GPIO_MODE_WLED,
330 - .gpio_first = 72,
331 - .gpio_last = 72,
332 - }, {0}
333 -};
334 -
335 -static struct ralink_pinmux_grp uart_mux[] = {
336 - {
337 - .name = "uartf",
338 - .mask = MT7620_GPIO_MODE_UARTF,
339 - .gpio_first = 7,
340 - .gpio_last = 14,
341 - }, {
342 - .name = "pcm uartf",
343 - .mask = MT7620_GPIO_MODE_PCM_UARTF,
344 - .gpio_first = 7,
345 - .gpio_last = 14,
346 - }, {
347 - .name = "pcm i2s",
348 - .mask = MT7620_GPIO_MODE_PCM_I2S,
349 - .gpio_first = 7,
350 - .gpio_last = 14,
351 - }, {
352 - .name = "i2s uartf",
353 - .mask = MT7620_GPIO_MODE_I2S_UARTF,
354 - .gpio_first = 7,
355 - .gpio_last = 14,
356 - }, {
357 - .name = "pcm gpio",
358 - .mask = MT7620_GPIO_MODE_PCM_GPIO,
359 - .gpio_first = 11,
360 - .gpio_last = 14,
361 - }, {
362 - .name = "gpio uartf",
363 - .mask = MT7620_GPIO_MODE_GPIO_UARTF,
364 - .gpio_first = 7,
365 - .gpio_last = 10,
366 - }, {
367 - .name = "gpio i2s",
368 - .mask = MT7620_GPIO_MODE_GPIO_I2S,
369 - .gpio_first = 7,
370 - .gpio_last = 10,
371 - }, {
372 - .name = "gpio",
373 - .mask = MT7620_GPIO_MODE_GPIO,
374 - }, {0}
375 -};
376 -
377 -struct ralink_pinmux rt_gpio_pinmux = {
378 - .mode = mode_mux,
379 - .uart = uart_mux,
380 - .uart_shift = MT7620_GPIO_MODE_UART0_SHIFT,
381 - .uart_mask = MT7620_GPIO_MODE_UART0_MASK,
382 +static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 1, 2) };
383 +static struct rt2880_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) };
384 +static struct rt2880_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) };
385 +static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 0, 22, 2) };
386 +static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 24, 12) };
387 +static struct rt2880_pmx_func refclk_grp[] = { FUNC("spi refclk", 0, 37, 3) };
388 +static struct rt2880_pmx_func ephy_grp[] = { FUNC("ephy", 0, 40, 5) };
389 +static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 60, 12) };
390 +static struct rt2880_pmx_func wled_grp[] = { FUNC("wled", 0, 72, 1) };
391 +static struct rt2880_pmx_func pa_grp[] = { FUNC("pa", 0, 18, 4) };
392 +static struct rt2880_pmx_func uartf_grp[] = {
393 + FUNC("uartf", MT7620_GPIO_MODE_UARTF, 7, 8),
394 + FUNC("pcm uartf", MT7620_GPIO_MODE_PCM_UARTF, 7, 8),
395 + FUNC("pcm i2s", MT7620_GPIO_MODE_PCM_I2S, 7, 8),
396 + FUNC("i2s uartf", MT7620_GPIO_MODE_I2S_UARTF, 7, 8),
397 + FUNC("pcm gpio", MT7620_GPIO_MODE_PCM_GPIO, 11, 4),
398 + FUNC("gpio uartf", MT7620_GPIO_MODE_GPIO_UARTF, 7, 4),
399 + FUNC("gpio i2s", MT7620_GPIO_MODE_GPIO_I2S, 7, 4),
400 +};
401 +static struct rt2880_pmx_func wdt_grp[] = {
402 + FUNC("wdt rst", 0, 17, 1),
403 + FUNC("wdt refclk", 0, 17, 1),
404 + };
405 +static struct rt2880_pmx_func pcie_rst_grp[] = {
406 + FUNC("pcie rst", MT7620_GPIO_MODE_PCIE_RST, 36, 1),
407 + FUNC("pcie refclk", MT7620_GPIO_MODE_PCIE_REF, 36, 1)
408 +};
409 +static struct rt2880_pmx_func nd_sd_grp[] = {
410 + FUNC("nand", MT7620_GPIO_MODE_NAND, 45, 15),
411 + FUNC("sd", MT7620_GPIO_MODE_SD, 45, 15)
412 +};
413 +
414 +static struct rt2880_pmx_group mt7620a_pinmux_data[] = {
415 + GRP("i2c", i2c_grp, 1, MT7620_GPIO_MODE_I2C),
416 + GRP("uartf", uartf_grp, MT7620_GPIO_MODE_UART0_MASK,
417 + MT7620_GPIO_MODE_UART0_SHIFT),
418 + GRP("spi", spi_grp, 1, MT7620_GPIO_MODE_SPI),
419 + GRP("uartlite", uartlite_grp, 1, MT7620_GPIO_MODE_UART1),
420 + GRP_G("wdt", wdt_grp, MT7620_GPIO_MODE_WDT_MASK,
421 + MT7620_GPIO_MODE_WDT_GPIO, MT7620_GPIO_MODE_WDT_SHIFT),
422 + GRP("mdio", mdio_grp, 1, MT7620_GPIO_MODE_MDIO),
423 + GRP("rgmii1", rgmii1_grp, 1, MT7620_GPIO_MODE_RGMII1),
424 + GRP("spi refclk", refclk_grp, 1, MT7620_GPIO_MODE_SPI_REF_CLK),
425 + GRP_G("pcie", pcie_rst_grp, MT7620_GPIO_MODE_PCIE_MASK,
426 + MT7620_GPIO_MODE_PCIE_GPIO, MT7620_GPIO_MODE_PCIE_SHIFT),
427 + GRP_G("nd_sd", nd_sd_grp, MT7620_GPIO_MODE_ND_SD_MASK,
428 + MT7620_GPIO_MODE_ND_SD_GPIO, MT7620_GPIO_MODE_ND_SD_SHIFT),
429 + GRP("rgmii2", rgmii2_grp, 1, MT7620_GPIO_MODE_RGMII2),
430 + GRP("wled", wled_grp, 1, MT7620_GPIO_MODE_WLED),
431 + GRP("ephy", ephy_grp, 1, MT7620_GPIO_MODE_EPHY),
432 + GRP("pa", pa_grp, 1, MT7620_GPIO_MODE_PA),
433 + { 0 }
434 };
435
436 static struct rt2880_pmx_func pwm1_grp_mt7628[] = {
437 --- a/arch/mips/ralink/rt288x.c
438 +++ b/arch/mips/ralink/rt288x.c
439 @@ -17,46 +17,27 @@
440 #include <asm/mipsregs.h>
441 #include <asm/mach-ralink/ralink_regs.h>
442 #include <asm/mach-ralink/rt288x.h>
443 +#include <asm/mach-ralink/pinmux.h>
444
445 #include "common.h"
446
447 -static struct ralink_pinmux_grp mode_mux[] = {
448 - {
449 - .name = "i2c",
450 - .mask = RT2880_GPIO_MODE_I2C,
451 - .gpio_first = 1,
452 - .gpio_last = 2,
453 - }, {
454 - .name = "spi",
455 - .mask = RT2880_GPIO_MODE_SPI,
456 - .gpio_first = 3,
457 - .gpio_last = 6,
458 - }, {
459 - .name = "uartlite",
460 - .mask = RT2880_GPIO_MODE_UART0,
461 - .gpio_first = 7,
462 - .gpio_last = 14,
463 - }, {
464 - .name = "jtag",
465 - .mask = RT2880_GPIO_MODE_JTAG,
466 - .gpio_first = 17,
467 - .gpio_last = 21,
468 - }, {
469 - .name = "mdio",
470 - .mask = RT2880_GPIO_MODE_MDIO,
471 - .gpio_first = 22,
472 - .gpio_last = 23,
473 - }, {
474 - .name = "sdram",
475 - .mask = RT2880_GPIO_MODE_SDRAM,
476 - .gpio_first = 24,
477 - .gpio_last = 39,
478 - }, {
479 - .name = "pci",
480 - .mask = RT2880_GPIO_MODE_PCI,
481 - .gpio_first = 40,
482 - .gpio_last = 71,
483 - }, {0}
484 +static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) };
485 +static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
486 +static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 7, 8) };
487 +static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) };
488 +static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
489 +static struct rt2880_pmx_func sdram_func[] = { FUNC("sdram", 0, 24, 16) };
490 +static struct rt2880_pmx_func pci_func[] = { FUNC("pci", 0, 40, 32) };
491 +
492 +static struct rt2880_pmx_group rt2880_pinmux_data_act[] = {
493 + GRP("i2c", i2c_func, 1, RT2880_GPIO_MODE_I2C),
494 + GRP("spi", spi_func, 1, RT2880_GPIO_MODE_SPI),
495 + GRP("uartlite", uartlite_func, 1, RT2880_GPIO_MODE_UART0),
496 + GRP("jtag", jtag_func, 1, RT2880_GPIO_MODE_JTAG),
497 + GRP("mdio", mdio_func, 1, RT2880_GPIO_MODE_MDIO),
498 + GRP("sdram", sdram_func, 1, RT2880_GPIO_MODE_SDRAM),
499 + GRP("pci", pci_func, 1, RT2880_GPIO_MODE_PCI),
500 + { 0 }
501 };
502
503 static void rt288x_wdt_reset(void)
504 @@ -69,11 +50,6 @@ static void rt288x_wdt_reset(void)
505 rt_sysc_w32(t, SYSC_REG_CLKCFG);
506 }
507
508 -struct ralink_pinmux rt_gpio_pinmux = {
509 - .mode = mode_mux,
510 - .wdt_reset = rt288x_wdt_reset,
511 -};
512 -
513 void __init ralink_clk_init(void)
514 {
515 unsigned long cpu_rate, wmac_rate = 40000000;
516 @@ -141,4 +117,6 @@ void prom_soc_init(struct ralink_soc_inf
517 soc_info->mem_base = RT2880_SDRAM_BASE;
518 soc_info->mem_size_min = RT2880_MEM_SIZE_MIN;
519 soc_info->mem_size_max = RT2880_MEM_SIZE_MAX;
520 +
521 + rt2880_pinmux_data = rt2880_pinmux_data_act;
522 }
523 --- a/arch/mips/ralink/rt305x.c
524 +++ b/arch/mips/ralink/rt305x.c
525 @@ -17,90 +17,76 @@
526 #include <asm/mipsregs.h>
527 #include <asm/mach-ralink/ralink_regs.h>
528 #include <asm/mach-ralink/rt305x.h>
529 +#include <asm/mach-ralink/pinmux.h>
530
531 #include "common.h"
532
533 enum rt305x_soc_type rt305x_soc;
534
535 -static struct ralink_pinmux_grp mode_mux[] = {
536 - {
537 - .name = "i2c",
538 - .mask = RT305X_GPIO_MODE_I2C,
539 - .gpio_first = RT305X_GPIO_I2C_SD,
540 - .gpio_last = RT305X_GPIO_I2C_SCLK,
541 - }, {
542 - .name = "spi",
543 - .mask = RT305X_GPIO_MODE_SPI,
544 - .gpio_first = RT305X_GPIO_SPI_EN,
545 - .gpio_last = RT305X_GPIO_SPI_CLK,
546 - }, {
547 - .name = "uartlite",
548 - .mask = RT305X_GPIO_MODE_UART1,
549 - .gpio_first = RT305X_GPIO_UART1_TXD,
550 - .gpio_last = RT305X_GPIO_UART1_RXD,
551 - }, {
552 - .name = "jtag",
553 - .mask = RT305X_GPIO_MODE_JTAG,
554 - .gpio_first = RT305X_GPIO_JTAG_TDO,
555 - .gpio_last = RT305X_GPIO_JTAG_TDI,
556 - }, {
557 - .name = "mdio",
558 - .mask = RT305X_GPIO_MODE_MDIO,
559 - .gpio_first = RT305X_GPIO_MDIO_MDC,
560 - .gpio_last = RT305X_GPIO_MDIO_MDIO,
561 - }, {
562 - .name = "sdram",
563 - .mask = RT305X_GPIO_MODE_SDRAM,
564 - .gpio_first = RT305X_GPIO_SDRAM_MD16,
565 - .gpio_last = RT305X_GPIO_SDRAM_MD31,
566 - }, {
567 - .name = "rgmii",
568 - .mask = RT305X_GPIO_MODE_RGMII,
569 - .gpio_first = RT305X_GPIO_GE0_TXD0,
570 - .gpio_last = RT305X_GPIO_GE0_RXCLK,
571 - }, {0}
572 +static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) };
573 +static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
574 +static struct rt2880_pmx_func uartf_func[] = {
575 + FUNC("uartf", RT305X_GPIO_MODE_UARTF, 7, 8),
576 + FUNC("pcm uartf", RT305X_GPIO_MODE_PCM_UARTF, 7, 8),
577 + FUNC("pcm i2s", RT305X_GPIO_MODE_PCM_I2S, 7, 8),
578 + FUNC("i2s uartf", RT305X_GPIO_MODE_I2S_UARTF, 7, 8),
579 + FUNC("pcm gpio", RT305X_GPIO_MODE_PCM_GPIO, 11, 4),
580 + FUNC("gpio uartf", RT305X_GPIO_MODE_GPIO_UARTF, 7, 4),
581 + FUNC("gpio i2s", RT305X_GPIO_MODE_GPIO_I2S, 7, 4),
582 +};
583 +static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) };
584 +static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) };
585 +static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
586 +static struct rt2880_pmx_func rt5350_led_func[] = { FUNC("led", 0, 22, 5) };
587 +static struct rt2880_pmx_func rt5350_cs1_func[] = {
588 + FUNC("spi_cs1", 0, 27, 1),
589 + FUNC("wdg_cs1", 1, 27, 1),
590 +};
591 +static struct rt2880_pmx_func sdram_func[] = { FUNC("sdram", 0, 24, 16) };
592 +static struct rt2880_pmx_func rt3352_rgmii_func[] = { FUNC("rgmii", 0, 24, 12) };
593 +static struct rt2880_pmx_func rgmii_func[] = { FUNC("rgmii", 0, 40, 12) };
594 +static struct rt2880_pmx_func rt3352_lna_func[] = { FUNC("lna", 0, 36, 2) };
595 +static struct rt2880_pmx_func rt3352_pa_func[] = { FUNC("pa", 0, 38, 2) };
596 +static struct rt2880_pmx_func rt3352_led_func[] = { FUNC("led", 0, 40, 5) };
597 +
598 +static struct rt2880_pmx_group rt3050_pinmux_data[] = {
599 + GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
600 + GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
601 + GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
602 + RT305X_GPIO_MODE_UART0_SHIFT),
603 + GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1),
604 + GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG),
605 + GRP("mdio", mdio_func, 1, RT305X_GPIO_MODE_MDIO),
606 + GRP("rgmii", rgmii_func, 1, RT305X_GPIO_MODE_RGMII),
607 + GRP("sdram", sdram_func, 1, RT305X_GPIO_MODE_SDRAM),
608 + { 0 }
609 +};
610 +
611 +static struct rt2880_pmx_group rt3352_pinmux_data[] = {
612 + GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
613 + GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
614 + GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
615 + RT305X_GPIO_MODE_UART0_SHIFT),
616 + GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1),
617 + GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG),
618 + GRP("mdio", mdio_func, 1, RT305X_GPIO_MODE_MDIO),
619 + GRP("rgmii", rt3352_rgmii_func, 1, RT305X_GPIO_MODE_RGMII),
620 + GRP("lna", rt3352_lna_func, 1, RT3352_GPIO_MODE_LNA),
621 + GRP("pa", rt3352_pa_func, 1, RT3352_GPIO_MODE_PA),
622 + GRP("led", rt3352_led_func, 1, RT5350_GPIO_MODE_PHY_LED),
623 + { 0 }
624 };
625
626 -static struct ralink_pinmux_grp uart_mux[] = {
627 - {
628 - .name = "uartf",
629 - .mask = RT305X_GPIO_MODE_UARTF,
630 - .gpio_first = RT305X_GPIO_7,
631 - .gpio_last = RT305X_GPIO_14,
632 - }, {
633 - .name = "pcm uartf",
634 - .mask = RT305X_GPIO_MODE_PCM_UARTF,
635 - .gpio_first = RT305X_GPIO_7,
636 - .gpio_last = RT305X_GPIO_14,
637 - }, {
638 - .name = "pcm i2s",
639 - .mask = RT305X_GPIO_MODE_PCM_I2S,
640 - .gpio_first = RT305X_GPIO_7,
641 - .gpio_last = RT305X_GPIO_14,
642 - }, {
643 - .name = "i2s uartf",
644 - .mask = RT305X_GPIO_MODE_I2S_UARTF,
645 - .gpio_first = RT305X_GPIO_7,
646 - .gpio_last = RT305X_GPIO_14,
647 - }, {
648 - .name = "pcm gpio",
649 - .mask = RT305X_GPIO_MODE_PCM_GPIO,
650 - .gpio_first = RT305X_GPIO_10,
651 - .gpio_last = RT305X_GPIO_14,
652 - }, {
653 - .name = "gpio uartf",
654 - .mask = RT305X_GPIO_MODE_GPIO_UARTF,
655 - .gpio_first = RT305X_GPIO_7,
656 - .gpio_last = RT305X_GPIO_10,
657 - }, {
658 - .name = "gpio i2s",
659 - .mask = RT305X_GPIO_MODE_GPIO_I2S,
660 - .gpio_first = RT305X_GPIO_7,
661 - .gpio_last = RT305X_GPIO_10,
662 - }, {
663 - .name = "gpio",
664 - .mask = RT305X_GPIO_MODE_GPIO,
665 - }, {0}
666 +static struct rt2880_pmx_group rt5350_pinmux_data[] = {
667 + GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
668 + GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
669 + GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
670 + RT305X_GPIO_MODE_UART0_SHIFT),
671 + GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1),
672 + GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG),
673 + GRP("led", rt5350_led_func, 1, RT5350_GPIO_MODE_PHY_LED),
674 + GRP("spi_cs1", rt5350_cs1_func, 2, RT5350_GPIO_MODE_SPI_CS1),
675 + { 0 }
676 };
677
678 static void rt305x_wdt_reset(void)
679 @@ -114,14 +100,6 @@ static void rt305x_wdt_reset(void)
680 rt_sysc_w32(t, SYSC_REG_SYSTEM_CONFIG);
681 }
682
683 -struct ralink_pinmux rt_gpio_pinmux = {
684 - .mode = mode_mux,
685 - .uart = uart_mux,
686 - .uart_shift = RT305X_GPIO_MODE_UART0_SHIFT,
687 - .uart_mask = RT305X_GPIO_MODE_UART0_MASK,
688 - .wdt_reset = rt305x_wdt_reset,
689 -};
690 -
691 static unsigned long rt5350_get_mem_size(void)
692 {
693 void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE);
694 @@ -290,11 +268,14 @@ void prom_soc_init(struct ralink_soc_inf
695 soc_info->mem_base = RT305X_SDRAM_BASE;
696 if (soc_is_rt5350()) {
697 soc_info->mem_size = rt5350_get_mem_size();
698 + rt2880_pinmux_data = rt5350_pinmux_data;
699 } else if (soc_is_rt305x() || soc_is_rt3350()) {
700 soc_info->mem_size_min = RT305X_MEM_SIZE_MIN;
701 soc_info->mem_size_max = RT305X_MEM_SIZE_MAX;
702 + rt2880_pinmux_data = rt3050_pinmux_data;
703 } else if (soc_is_rt3352()) {
704 soc_info->mem_size_min = RT3352_MEM_SIZE_MIN;
705 soc_info->mem_size_max = RT3352_MEM_SIZE_MAX;
706 + rt2880_pinmux_data = rt3352_pinmux_data;
707 }
708 }
709 --- a/arch/mips/ralink/rt3883.c
710 +++ b/arch/mips/ralink/rt3883.c
711 @@ -17,132 +17,50 @@
712 #include <asm/mipsregs.h>
713 #include <asm/mach-ralink/ralink_regs.h>
714 #include <asm/mach-ralink/rt3883.h>
715 +#include <asm/mach-ralink/pinmux.h>
716
717 #include "common.h"
718
719 -static struct ralink_pinmux_grp mode_mux[] = {
720 - {
721 - .name = "i2c",
722 - .mask = RT3883_GPIO_MODE_I2C,
723 - .gpio_first = RT3883_GPIO_I2C_SD,
724 - .gpio_last = RT3883_GPIO_I2C_SCLK,
725 - }, {
726 - .name = "spi",
727 - .mask = RT3883_GPIO_MODE_SPI,
728 - .gpio_first = RT3883_GPIO_SPI_CS0,
729 - .gpio_last = RT3883_GPIO_SPI_MISO,
730 - }, {
731 - .name = "uartlite",
732 - .mask = RT3883_GPIO_MODE_UART1,
733 - .gpio_first = RT3883_GPIO_UART1_TXD,
734 - .gpio_last = RT3883_GPIO_UART1_RXD,
735 - }, {
736 - .name = "jtag",
737 - .mask = RT3883_GPIO_MODE_JTAG,
738 - .gpio_first = RT3883_GPIO_JTAG_TDO,
739 - .gpio_last = RT3883_GPIO_JTAG_TCLK,
740 - }, {
741 - .name = "mdio",
742 - .mask = RT3883_GPIO_MODE_MDIO,
743 - .gpio_first = RT3883_GPIO_MDIO_MDC,
744 - .gpio_last = RT3883_GPIO_MDIO_MDIO,
745 - }, {
746 - .name = "ge1",
747 - .mask = RT3883_GPIO_MODE_GE1,
748 - .gpio_first = RT3883_GPIO_GE1_TXD0,
749 - .gpio_last = RT3883_GPIO_GE1_RXCLK,
750 - }, {
751 - .name = "ge2",
752 - .mask = RT3883_GPIO_MODE_GE2,
753 - .gpio_first = RT3883_GPIO_GE2_TXD0,
754 - .gpio_last = RT3883_GPIO_GE2_RXCLK,
755 - }, {
756 - .name = "pci",
757 - .mask = RT3883_GPIO_MODE_PCI,
758 - .gpio_first = RT3883_GPIO_PCI_AD0,
759 - .gpio_last = RT3883_GPIO_PCI_AD31,
760 - }, {
761 - .name = "lna a",
762 - .mask = RT3883_GPIO_MODE_LNA_A,
763 - .gpio_first = RT3883_GPIO_LNA_PE_A0,
764 - .gpio_last = RT3883_GPIO_LNA_PE_A2,
765 - }, {
766 - .name = "lna g",
767 - .mask = RT3883_GPIO_MODE_LNA_G,
768 - .gpio_first = RT3883_GPIO_LNA_PE_G0,
769 - .gpio_last = RT3883_GPIO_LNA_PE_G2,
770 - }, {0}
771 +static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) };
772 +static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
773 +static struct rt2880_pmx_func uartf_func[] = {
774 + FUNC("uartf", RT3883_GPIO_MODE_UARTF, 7, 8),
775 + FUNC("pcm uartf", RT3883_GPIO_MODE_PCM_UARTF, 7, 8),
776 + FUNC("pcm i2s", RT3883_GPIO_MODE_PCM_I2S, 7, 8),
777 + FUNC("i2s uartf", RT3883_GPIO_MODE_I2S_UARTF, 7, 8),
778 + FUNC("pcm gpio", RT3883_GPIO_MODE_PCM_GPIO, 11, 4),
779 + FUNC("gpio uartf", RT3883_GPIO_MODE_GPIO_UARTF, 7, 4),
780 + FUNC("gpio i2s", RT3883_GPIO_MODE_GPIO_I2S, 7, 4),
781 };
782 -
783 -static struct ralink_pinmux_grp uart_mux[] = {
784 - {
785 - .name = "uartf",
786 - .mask = RT3883_GPIO_MODE_UARTF,
787 - .gpio_first = RT3883_GPIO_7,
788 - .gpio_last = RT3883_GPIO_14,
789 - }, {
790 - .name = "pcm uartf",
791 - .mask = RT3883_GPIO_MODE_PCM_UARTF,
792 - .gpio_first = RT3883_GPIO_7,
793 - .gpio_last = RT3883_GPIO_14,
794 - }, {
795 - .name = "pcm i2s",
796 - .mask = RT3883_GPIO_MODE_PCM_I2S,
797 - .gpio_first = RT3883_GPIO_7,
798 - .gpio_last = RT3883_GPIO_14,
799 - }, {
800 - .name = "i2s uartf",
801 - .mask = RT3883_GPIO_MODE_I2S_UARTF,
802 - .gpio_first = RT3883_GPIO_7,
803 - .gpio_last = RT3883_GPIO_14,
804 - }, {
805 - .name = "pcm gpio",
806 - .mask = RT3883_GPIO_MODE_PCM_GPIO,
807 - .gpio_first = RT3883_GPIO_11,
808 - .gpio_last = RT3883_GPIO_14,
809 - }, {
810 - .name = "gpio uartf",
811 - .mask = RT3883_GPIO_MODE_GPIO_UARTF,
812 - .gpio_first = RT3883_GPIO_7,
813 - .gpio_last = RT3883_GPIO_10,
814 - }, {
815 - .name = "gpio i2s",
816 - .mask = RT3883_GPIO_MODE_GPIO_I2S,
817 - .gpio_first = RT3883_GPIO_7,
818 - .gpio_last = RT3883_GPIO_10,
819 - }, {
820 - .name = "gpio",
821 - .mask = RT3883_GPIO_MODE_GPIO,
822 - }, {0}
823 +static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) };
824 +static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) };
825 +static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
826 +static struct rt2880_pmx_func lna_a_func[] = { FUNC("lna a", 0, 32, 3) };
827 +static struct rt2880_pmx_func lna_g_func[] = { FUNC("lna a", 0, 35, 3) };
828 +static struct rt2880_pmx_func pci_func[] = {
829 + FUNC("pci-dev", 0, 40, 32),
830 + FUNC("pci-host2", 1, 40, 32),
831 + FUNC("pci-host1", 2, 40, 32),
832 + FUNC("pci-fnc", 3, 40, 32)
833 };
834 +static struct rt2880_pmx_func ge1_func[] = { FUNC("ge1", 0, 72, 12) };
835 +static struct rt2880_pmx_func ge2_func[] = { FUNC("ge1", 0, 84, 12) };
836
837 -static struct ralink_pinmux_grp pci_mux[] = {
838 - {
839 - .name = "pci-dev",
840 - .mask = 0,
841 - .gpio_first = RT3883_GPIO_PCI_AD0,
842 - .gpio_last = RT3883_GPIO_PCI_AD31,
843 - }, {
844 - .name = "pci-host2",
845 - .mask = 1,
846 - .gpio_first = RT3883_GPIO_PCI_AD0,
847 - .gpio_last = RT3883_GPIO_PCI_AD31,
848 - }, {
849 - .name = "pci-host1",
850 - .mask = 2,
851 - .gpio_first = RT3883_GPIO_PCI_AD0,
852 - .gpio_last = RT3883_GPIO_PCI_AD31,
853 - }, {
854 - .name = "pci-fnc",
855 - .mask = 3,
856 - .gpio_first = RT3883_GPIO_PCI_AD0,
857 - .gpio_last = RT3883_GPIO_PCI_AD31,
858 - }, {
859 - .name = "pci-gpio",
860 - .mask = 7,
861 - .gpio_first = RT3883_GPIO_PCI_AD0,
862 - .gpio_last = RT3883_GPIO_PCI_AD31,
863 - }, {0}
864 +static struct rt2880_pmx_group rt3883_pinmux_data[] = {
865 + GRP("i2c", i2c_func, 1, RT3883_GPIO_MODE_I2C),
866 + GRP("spi", spi_func, 1, RT3883_GPIO_MODE_SPI),
867 + GRP("uartf", uartf_func, RT3883_GPIO_MODE_UART0_MASK,
868 + RT3883_GPIO_MODE_UART0_SHIFT),
869 + GRP("uartlite", uartlite_func, 1, RT3883_GPIO_MODE_UART1),
870 + GRP("jtag", jtag_func, 1, RT3883_GPIO_MODE_JTAG),
871 + GRP("mdio", mdio_func, 1, RT3883_GPIO_MODE_MDIO),
872 + GRP("lna a", lna_a_func, 1, RT3883_GPIO_MODE_LNA_A),
873 + GRP("lna g", lna_g_func, 1, RT3883_GPIO_MODE_LNA_G),
874 + GRP("pci", pci_func, RT3883_GPIO_MODE_PCI_MASK,
875 + RT3883_GPIO_MODE_PCI_SHIFT),
876 + GRP("ge1", ge1_func, 1, RT3883_GPIO_MODE_GE1),
877 + GRP("ge2", ge2_func, 1, RT3883_GPIO_MODE_GE2),
878 + { 0 }
879 };
880
881 static void rt3883_wdt_reset(void)
882 @@ -155,17 +73,6 @@ static void rt3883_wdt_reset(void)
883 rt_sysc_w32(t, RT3883_SYSC_REG_SYSCFG1);
884 }
885
886 -struct ralink_pinmux rt_gpio_pinmux = {
887 - .mode = mode_mux,
888 - .uart = uart_mux,
889 - .uart_shift = RT3883_GPIO_MODE_UART0_SHIFT,
890 - .uart_mask = RT3883_GPIO_MODE_UART0_MASK,
891 - .wdt_reset = rt3883_wdt_reset,
892 - .pci = pci_mux,
893 - .pci_shift = RT3883_GPIO_MODE_PCI_SHIFT,
894 - .pci_mask = RT3883_GPIO_MODE_PCI_MASK,
895 -};
896 -
897 void __init ralink_clk_init(void)
898 {
899 unsigned long cpu_rate, sys_rate;
900 @@ -244,4 +151,6 @@ void prom_soc_init(struct ralink_soc_inf
901 soc_info->mem_base = RT3883_SDRAM_BASE;
902 soc_info->mem_size_min = RT3883_MEM_SIZE_MIN;
903 soc_info->mem_size_max = RT3883_MEM_SIZE_MAX;
904 +
905 + rt2880_pinmux_data = rt3883_pinmux_data;
906 }
907 --- a/drivers/pinctrl/Kconfig
908 +++ b/drivers/pinctrl/Kconfig
909 @@ -198,6 +198,11 @@ config PINCTRL_LANTIQ
910 select PINMUX
911 select PINCONF
912
913 +config PINCTRL_RT2880
914 + bool
915 + depends on RALINK
916 + select PINMUX
917 +
918 config PINCTRL_FALCON
919 bool
920 depends on SOC_FALCON
921 --- a/drivers/pinctrl/Makefile
922 +++ b/drivers/pinctrl/Makefile
923 @@ -45,6 +45,7 @@ obj-$(CONFIG_PINCTRL_DB8500) += pinctrl-
924 obj-$(CONFIG_PINCTRL_DB8540) += pinctrl-nomadik-db8540.o
925 obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o
926 obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
927 +obj-$(CONFIG_PINCTRL_RT2880) += pinctrl-rt2880.o
928 obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
929 obj-$(CONFIG_PINCTRL_SIRF) += sirf/
930 obj-$(CONFIG_PINCTRL_SUNXI) += pinctrl-sunxi.o
931 --- /dev/null
932 +++ b/drivers/pinctrl/pinctrl-rt2880.c
933 @@ -0,0 +1,467 @@
934 +/*
935 + * linux/drivers/pinctrl/pinctrl-rt2880.c
936 + *
937 + * This program is free software; you can redistribute it and/or modify
938 + * it under the terms of the GNU General Public License version 2 as
939 + * publishhed by the Free Software Foundation.
940 + *
941 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
942 + */
943 +
944 +#include <linux/module.h>
945 +#include <linux/device.h>
946 +#include <linux/io.h>
947 +#include <linux/platform_device.h>
948 +#include <linux/slab.h>
949 +#include <linux/of.h>
950 +#include <linux/pinctrl/pinctrl.h>
951 +#include <linux/pinctrl/pinconf.h>
952 +#include <linux/pinctrl/pinmux.h>
953 +#include <linux/pinctrl/consumer.h>
954 +#include <linux/pinctrl/machine.h>
955 +
956 +#include <asm/mach-ralink/ralink_regs.h>
957 +#include <asm/mach-ralink/pinmux.h>
958 +#include <asm/mach-ralink/mt7620.h>
959 +
960 +#include "core.h"
961 +
962 +#define SYSC_REG_GPIO_MODE 0x60
963 +
964 +struct rt2880_priv {
965 + struct device *dev;
966 +
967 + struct pinctrl_pin_desc *pads;
968 + struct pinctrl_desc *desc;
969 +
970 + struct rt2880_pmx_func **func;
971 + int func_count;
972 +
973 + struct rt2880_pmx_group *groups;
974 + const char **group_names;
975 + int group_count;
976 +
977 + uint8_t *gpio;
978 + int max_pins;
979 +};
980 +
981 +struct rt2880_pmx_group *rt2880_pinmux_data = NULL;
982 +
983 +static int rt2880_get_group_count(struct pinctrl_dev *pctrldev)
984 +{
985 + struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
986 +
987 + return p->group_count;
988 +}
989 +
990 +static const char *rt2880_get_group_name(struct pinctrl_dev *pctrldev,
991 + unsigned group)
992 +{
993 + struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
994 +
995 + if (group >= p->group_count)
996 + return NULL;
997 +
998 + return p->group_names[group];
999 +}
1000 +
1001 +static int rt2880_get_group_pins(struct pinctrl_dev *pctrldev,
1002 + unsigned group,
1003 + const unsigned **pins,
1004 + unsigned *num_pins)
1005 +{
1006 + struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
1007 +
1008 + if (group >= p->group_count)
1009 + return -EINVAL;
1010 +
1011 + *pins = p->groups[group].func[0].pins;
1012 + *num_pins = p->groups[group].func[0].pin_count;
1013 +
1014 + return 0;
1015 +}
1016 +
1017 +static void rt2880_pinctrl_dt_free_map(struct pinctrl_dev *pctrldev,
1018 + struct pinctrl_map *map, unsigned num_maps)
1019 +{
1020 + int i;
1021 +
1022 + for (i = 0; i < num_maps; i++)
1023 + if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN ||
1024 + map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
1025 + kfree(map[i].data.configs.configs);
1026 + kfree(map);
1027 +}
1028 +
1029 +static void rt2880_pinctrl_pin_dbg_show(struct pinctrl_dev *pctrldev,
1030 + struct seq_file *s,
1031 + unsigned offset)
1032 +{
1033 + seq_printf(s, "ralink pio");
1034 +}
1035 +
1036 +static void rt2880_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctrldev,
1037 + struct device_node *np,
1038 + struct pinctrl_map **map)
1039 +{
1040 + const char *function;
1041 + int func = of_property_read_string(np, "ralink,function", &function);
1042 + int grps = of_property_count_strings(np, "ralink,group");
1043 + int i;
1044 +
1045 + if (func || !grps)
1046 + return;
1047 +
1048 + for (i = 0; i < grps; i++) {
1049 + const char *group;
1050 +
1051 + of_property_read_string_index(np, "ralink,group", i, &group);
1052 +
1053 + (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1054 + (*map)->name = function;
1055 + (*map)->data.mux.group = group;
1056 + (*map)->data.mux.function = function;
1057 + (*map)++;
1058 + }
1059 +}
1060 +
1061 +static int rt2880_pinctrl_dt_node_to_map(struct pinctrl_dev *pctrldev,
1062 + struct device_node *np_config,
1063 + struct pinctrl_map **map,
1064 + unsigned *num_maps)
1065 +{
1066 + int max_maps = 0;
1067 + struct pinctrl_map *tmp;
1068 + struct device_node *np;
1069 +
1070 + for_each_child_of_node(np_config, np) {
1071 + int ret = of_property_count_strings(np, "ralink,group");
1072 +
1073 + if (ret >= 0)
1074 + max_maps += ret;
1075 + }
1076 +
1077 + if (!max_maps)
1078 + return max_maps;
1079 +
1080 + *map = kzalloc(max_maps * sizeof(struct pinctrl_map), GFP_KERNEL);
1081 + if (!*map)
1082 + return -ENOMEM;
1083 +
1084 + tmp = *map;
1085 +
1086 + for_each_child_of_node(np_config, np)
1087 + rt2880_pinctrl_dt_subnode_to_map(pctrldev, np, &tmp);
1088 + *num_maps = max_maps;
1089 +
1090 + return 0;
1091 +}
1092 +
1093 +static const struct pinctrl_ops rt2880_pctrl_ops = {
1094 + .get_groups_count = rt2880_get_group_count,
1095 + .get_group_name = rt2880_get_group_name,
1096 + .get_group_pins = rt2880_get_group_pins,
1097 + .pin_dbg_show = rt2880_pinctrl_pin_dbg_show,
1098 + .dt_node_to_map = rt2880_pinctrl_dt_node_to_map,
1099 + .dt_free_map = rt2880_pinctrl_dt_free_map,
1100 +};
1101 +
1102 +static int rt2880_pmx_func_count(struct pinctrl_dev *pctrldev)
1103 +{
1104 + struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
1105 +
1106 + return p->func_count;
1107 +}
1108 +
1109 +static const char *rt2880_pmx_func_name(struct pinctrl_dev *pctrldev,
1110 + unsigned func)
1111 +{
1112 + struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
1113 +
1114 + return p->func[func]->name;
1115 +}
1116 +
1117 +static int rt2880_pmx_group_get_groups(struct pinctrl_dev *pctrldev,
1118 + unsigned func,
1119 + const char * const **groups,
1120 + unsigned * const num_groups)
1121 +{
1122 + struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
1123 +
1124 + if (p->func[func]->group_count == 1)
1125 + *groups = &p->group_names[p->func[func]->groups[0]];
1126 + else
1127 + *groups = p->group_names;
1128 +
1129 + *num_groups = p->func[func]->group_count;
1130 +
1131 + return 0;
1132 +}
1133 +
1134 +static int rt2880_pmx_group_enable(struct pinctrl_dev *pctrldev,
1135 + unsigned func,
1136 + unsigned group)
1137 +{
1138 + struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
1139 + u32 mode = 0;
1140 + int i;
1141 +
1142 + /* dont allow double use */
1143 + if (p->groups[group].enabled) {
1144 + dev_err(p->dev, "%s is already enabled\n", p->groups[group].name);
1145 + return -EBUSY;
1146 + }
1147 +
1148 + p->groups[group].enabled = 1;
1149 + p->func[func]->enabled = 1;
1150 +
1151 + mode = rt_sysc_r32(SYSC_REG_GPIO_MODE);
1152 + mode &= ~(p->groups[group].mask << p->groups[group].shift);
1153 +
1154 + /* mark the pins as gpio */
1155 + for (i = 0; i < p->groups[group].func[0].pin_count; i++)
1156 + p->gpio[p->groups[group].func[0].pins[i]] = 1;
1157 +
1158 + /* function 0 is gpio and needs special handling */
1159 + if (func == 0) {
1160 + mode |= p->groups[group].gpio << p->groups[group].shift;
1161 + } else {
1162 + for (i = 0; i < p->func[func]->pin_count; i++)
1163 + p->gpio[p->func[func]->pins[i]] = 0;
1164 + mode |= p->func[func]->value << p->groups[group].shift;
1165 + }
1166 + rt_sysc_w32(mode, SYSC_REG_GPIO_MODE);
1167 +
1168 +
1169 + return 0;
1170 +}
1171 +
1172 +static int rt2880_pmx_group_gpio_request_enable(struct pinctrl_dev *pctrldev,
1173 + struct pinctrl_gpio_range *range,
1174 + unsigned pin)
1175 +{
1176 + struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
1177 +
1178 + if (!p->gpio[pin]) {
1179 + dev_err(p->dev, "pin %d is not set to gpio mux\n", pin);
1180 + return -EINVAL;
1181 + }
1182 +
1183 + return 0;
1184 +}
1185 +
1186 +static const struct pinmux_ops rt2880_pmx_group_ops = {
1187 + .get_functions_count = rt2880_pmx_func_count,
1188 + .get_function_name = rt2880_pmx_func_name,
1189 + .get_function_groups = rt2880_pmx_group_get_groups,
1190 + .enable = rt2880_pmx_group_enable,
1191 + .gpio_request_enable = rt2880_pmx_group_gpio_request_enable,
1192 +};
1193 +
1194 +static struct pinctrl_desc rt2880_pctrl_desc = {
1195 + .owner = THIS_MODULE,
1196 + .name = "rt2880-pinmux",
1197 + .pctlops = &rt2880_pctrl_ops,
1198 + .pmxops = &rt2880_pmx_group_ops,
1199 +};
1200 +
1201 +static struct rt2880_pmx_func gpio_func = {
1202 + .name = "gpio",
1203 +};
1204 +
1205 +static int rt2880_pinmux_index(struct rt2880_priv *p)
1206 +{
1207 + struct rt2880_pmx_func **f;
1208 + struct rt2880_pmx_group *mux = p->groups;
1209 + int i, j, c = 0;
1210 +
1211 + /* count the mux functions */
1212 + while (mux->name) {
1213 + p->group_count++;
1214 + mux++;
1215 + }
1216 +
1217 + /* allocate the group names array needed by the gpio function */
1218 + p->group_names = devm_kzalloc(p->dev, sizeof(char *) * p->group_count, GFP_KERNEL);
1219 + if (!p->group_names)
1220 + return -1;
1221 +
1222 + for (i = 0; i < p->group_count; i++) {
1223 + p->group_names[i] = p->groups[i].name;
1224 + p->func_count += p->groups[i].func_count;
1225 + }
1226 +
1227 + /* we have a dummy function[0] for gpio */
1228 + p->func_count++;
1229 +
1230 + /* allocate our function and group mapping index buffers */
1231 + f = p->func = devm_kzalloc(p->dev, sizeof(struct rt2880_pmx_func) * p->func_count, GFP_KERNEL);
1232 + gpio_func.groups = devm_kzalloc(p->dev, sizeof(int) * p->group_count, GFP_KERNEL);
1233 + if (!f || !gpio_func.groups)
1234 + return -1;
1235 +
1236 + /* add a backpointer to the function so it knows its group */
1237 + gpio_func.group_count = p->group_count;
1238 + for (i = 0; i < gpio_func.group_count; i++)
1239 + gpio_func.groups[i] = i;
1240 +
1241 + f[c] = &gpio_func;
1242 + c++;
1243 +
1244 + /* add remaining functions */
1245 + for (i = 0; i < p->group_count; i++) {
1246 + for (j = 0; j < p->groups[i].func_count; j++) {
1247 + f[c] = &p->groups[i].func[j];
1248 + f[c]->groups = devm_kzalloc(p->dev, sizeof(int), GFP_KERNEL);
1249 + f[c]->groups[0] = i;
1250 + f[c]->group_count = 1;
1251 + c++;
1252 + }
1253 + }
1254 + return 0;
1255 +}
1256 +
1257 +static int rt2880_pinmux_pins(struct rt2880_priv *p)
1258 +{
1259 + int i, j;
1260 +
1261 + /* loop over the functions and initialize the pins array. also work out the highest pin used */
1262 + for (i = 0; i < p->func_count; i++) {
1263 + int pin;
1264 +
1265 + if (!p->func[i]->pin_count)
1266 + continue;
1267 +
1268 + p->func[i]->pins = devm_kzalloc(p->dev, sizeof(int) * p->func[i]->pin_count, GFP_KERNEL);
1269 + for (j = 0; j < p->func[i]->pin_count; j++)
1270 + p->func[i]->pins[j] = p->func[i]->pin_first + j;
1271 +
1272 + pin = p->func[i]->pin_first + p->func[i]->pin_count;
1273 + if (pin > p->max_pins)
1274 + p->max_pins = pin;
1275 + }
1276 +
1277 + /* the buffer that tells us which pins are gpio */
1278 + p->gpio = devm_kzalloc(p->dev,sizeof(uint8_t) * p->max_pins,
1279 + GFP_KERNEL);
1280 + /* the pads needed to tell pinctrl about our pins */
1281 + p->pads = devm_kzalloc(p->dev,
1282 + sizeof(struct pinctrl_pin_desc) * p->max_pins,
1283 + GFP_KERNEL);
1284 + if (!p->pads || !p->gpio ) {
1285 + dev_err(p->dev, "Failed to allocate gpio data\n");
1286 + return -ENOMEM;
1287 + }
1288 +
1289 + memset(p->gpio, 1, sizeof(uint8_t) * p->max_pins);
1290 + for (i = 0; i < p->func_count; i++) {
1291 + if (!p->func[i]->pin_count)
1292 + continue;
1293 +
1294 + for (j = 0; j < p->func[i]->pin_count; j++)
1295 + p->gpio[p->func[i]->pins[j]] = 0;
1296 + }
1297 +
1298 + /* pin 0 is always a gpio */
1299 + p->gpio[0] = 1;
1300 +
1301 + /* set the pads */
1302 + for (i = 0; i < p->max_pins; i++) {
1303 + /* strlen("ioXY") + 1 = 5 */
1304 + char *name = devm_kzalloc(p->dev, 5, GFP_KERNEL);
1305 +
1306 + if (!name) {
1307 + dev_err(p->dev, "Failed to allocate pad name\n");
1308 + return -ENOMEM;
1309 + }
1310 + snprintf(name, 5, "io%d", i);
1311 + p->pads[i].number = i;
1312 + p->pads[i].name = name;
1313 + }
1314 + p->desc->pins = p->pads;
1315 + p->desc->npins = p->max_pins;
1316 +
1317 + return 0;
1318 +}
1319 +
1320 +static int rt2880_pinmux_probe(struct platform_device *pdev)
1321 +{
1322 + struct rt2880_priv *p;
1323 + struct pinctrl_dev *dev;
1324 + struct device_node *np;
1325 +
1326 + if (!rt2880_pinmux_data)
1327 + return -ENOSYS;
1328 +
1329 + /* setup the private data */
1330 + p = devm_kzalloc(&pdev->dev, sizeof(struct rt2880_priv), GFP_KERNEL);
1331 + if (!p)
1332 + return -ENOMEM;
1333 +
1334 + p->dev = &pdev->dev;
1335 + p->desc = &rt2880_pctrl_desc;
1336 + p->groups = rt2880_pinmux_data;
1337 + platform_set_drvdata(pdev, p);
1338 +
1339 + /* init the device */
1340 + if (rt2880_pinmux_index(p)) {
1341 + dev_err(&pdev->dev, "failed to load index\n");
1342 + return -EINVAL;
1343 + }
1344 + if (rt2880_pinmux_pins(p)) {
1345 + dev_err(&pdev->dev, "failed to load pins\n");
1346 + return -EINVAL;
1347 + }
1348 + dev = pinctrl_register(p->desc, &pdev->dev, p);
1349 + if (IS_ERR(dev))
1350 + return PTR_ERR(dev);
1351 +
1352 + /* finalize by adding gpio ranges for enables gpio controllers */
1353 + for_each_compatible_node(np, NULL, "ralink,rt2880-gpio") {
1354 + const __be32 *ngpio, *gpiobase;
1355 + struct pinctrl_gpio_range *range;
1356 + char *name;
1357 +
1358 + if (!of_device_is_available(np))
1359 + continue;
1360 +
1361 + ngpio = of_get_property(np, "ralink,num-gpios", NULL);
1362 + gpiobase = of_get_property(np, "ralink,gpio-base", NULL);
1363 + if (!ngpio || !gpiobase) {
1364 + dev_err(&pdev->dev, "failed to load chip info\n");
1365 + return -EINVAL;
1366 + }
1367 +
1368 + range = devm_kzalloc(p->dev, sizeof(struct pinctrl_gpio_range) + 4, GFP_KERNEL);
1369 + range->name = name = (char *) &range[1];
1370 + sprintf(name, "pio");
1371 + range->npins = __be32_to_cpu(*ngpio);
1372 + range->base = __be32_to_cpu(*gpiobase);
1373 + range->pin_base = range->base;
1374 + pinctrl_add_gpio_range(dev, range);
1375 + }
1376 +
1377 + return 0;
1378 +}
1379 +
1380 +static const struct of_device_id rt2880_pinmux_match[] = {
1381 + { .compatible = "ralink,rt2880-pinmux" },
1382 + {},
1383 +};
1384 +MODULE_DEVICE_TABLE(of, rt2880_pinmux_match);
1385 +
1386 +static struct platform_driver rt2880_pinmux_driver = {
1387 + .probe = rt2880_pinmux_probe,
1388 + .driver = {
1389 + .name = "rt2880-pinmux",
1390 + .owner = THIS_MODULE,
1391 + .of_match_table = rt2880_pinmux_match,
1392 + },
1393 +};
1394 +
1395 +int __init rt2880_pinmux_init(void)
1396 +{
1397 + return platform_driver_register(&rt2880_pinmux_driver);
1398 +}
1399 +
1400 +core_initcall_sync(rt2880_pinmux_init);
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