target/linux/ramips/patches-3.14/0048-GPIO-ralink-add-mt7621-gpio-controller.patch

   1 From 8481cdf6f96dc16cbcc129d046c021d17a891274 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Sun, 27 Jul 2014 11:00:32 +0100
   4 Subject: [PATCH 48/57] GPIO: ralink: add mt7621 gpio controller
   5
   6 Signed-off-by: John Crispin <blogic@openwrt.org>
   7 ---
   8  arch/mips/Kconfig          |    3 +
   9  drivers/gpio/Kconfig       |    6 ++
  10  drivers/gpio/Makefile      |    1 +
  11  drivers/gpio/gpio-mt7621.c |  177 ++++++++++++++++++++++++++++++++++++++++++++
  12  4 files changed, 187 insertions(+)
  13  create mode 100644 drivers/gpio/gpio-mt7621.c
  14
  15 --- a/arch/mips/Kconfig
  16 +++ b/arch/mips/Kconfig
  17 @@ -437,6 +437,9 @@ config RALINK
  18         select RESET_CONTROLLER
  19         select PINCTRL
  20         select PINCTRL_RT2880
  21 +       select ARCH_HAS_RESET_CONTROLLER
  22 +       select RESET_CONTROLLER
  23 +       select ARCH_REQUIRE_GPIOLIB
  24
  25  config SGI_IP22
  26         bool "SGI IP22 (Indy/Indigo2)"
  27 --- a/drivers/gpio/Kconfig
  28 +++ b/drivers/gpio/Kconfig
  29 @@ -827,6 +827,12 @@ config GPIO_BCM_KONA
  30         help
  31           Turn on GPIO support for Broadcom "Kona" chips.
  32
  33 +config GPIO_MT7621
  34 +       bool "Mediatek GPIO Support"
  35 +       depends on SOC_MT7620 || SOC_MT7621
  36 +       help
  37 +         Say yes here to support the Mediatek SoC GPIO device
  38 +
  39  comment "USB GPIO expanders:"
  40
  41  config GPIO_VIPERBOARD
  42 --- a/drivers/gpio/Makefile
  43 +++ b/drivers/gpio/Makefile
  44 @@ -100,3 +100,4 @@ obj-$(CONFIG_GPIO_WM8350)   += gpio-wm8350
  45  obj-$(CONFIG_GPIO_WM8994)      += gpio-wm8994.o
  46  obj-$(CONFIG_GPIO_XILINX)      += gpio-xilinx.o
  47  obj-$(CONFIG_GPIO_XTENSA)      += gpio-xtensa.o
  48 +obj-$(CONFIG_GPIO_MT7621)      += gpio-mt7621.o
  49 --- /dev/null
  50 +++ b/drivers/gpio/gpio-mt7621.c
  51 @@ -0,0 +1,177 @@
  52 +/*
  53 + * This program is free software; you can redistribute it and/or modify it
  54 + * under the terms of the GNU General Public License version 2 as published
  55 + * by the Free Software Foundation.
  56 + *
  57 + * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
  58 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
  59 + */
  60 +
  61 +#include <linux/io.h>
  62 +#include <linux/err.h>
  63 +#include <linux/gpio.h>
  64 +#include <linux/module.h>
  65 +#include <linux/of_irq.h>
  66 +#include <linux/spinlock.h>
  67 +#include <linux/irqdomain.h>
  68 +#include <linux/interrupt.h>
  69 +#include <linux/platform_device.h>
  70 +
  71 +#define MTK_BANK_WIDTH         32
  72 +
  73 +enum mediatek_gpio_reg {
  74 +       GPIO_REG_CTRL = 0,
  75 +       GPIO_REG_POL,
  76 +       GPIO_REG_DATA,
  77 +       GPIO_REG_DSET,
  78 +       GPIO_REG_DCLR,
  79 +};
  80 +
  81 +static void __iomem *mtk_gc_membase;
  82 +
  83 +struct mtk_gc {
  84 +       struct gpio_chip chip;
  85 +       spinlock_t lock;
  86 +       int bank;
  87 +};
  88 +
  89 +static inline struct mtk_gc
  90 +*to_mediatek_gpio(struct gpio_chip *chip)
  91 +{
  92 +       struct mtk_gc *mgc;
  93 +
  94 +       mgc = container_of(chip, struct mtk_gc, chip);
  95 +
  96 +       return mgc;
  97 +}
  98 +
  99 +static inline void
 100 +mtk_gpio_w32(struct mtk_gc *rg, u8 reg, u32 val)
 101 +{
 102 +       iowrite32(val, mtk_gc_membase + (reg * 0x10) + (rg->bank * 0x4));
 103 +}
 104 +
 105 +static inline u32
 106 +mtk_gpio_r32(struct mtk_gc *rg, u8 reg)
 107 +{
 108 +       return ioread32(mtk_gc_membase + (reg * 0x10) + (rg->bank * 0x4));
 109 +}
 110 +
 111 +static void
 112 +mediatek_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 113 +{
 114 +       struct mtk_gc *rg = to_mediatek_gpio(chip);
 115 +
 116 +       mtk_gpio_w32(rg, (value) ? GPIO_REG_DSET : GPIO_REG_DCLR, BIT(offset));
 117 +}
 118 +
 119 +static int
 120 +mediatek_gpio_get(struct gpio_chip *chip, unsigned offset)
 121 +{
 122 +       struct mtk_gc *rg = to_mediatek_gpio(chip);
 123 +
 124 +       return !!(mtk_gpio_r32(rg, GPIO_REG_DATA) & BIT(offset));
 125 +}
 126 +
 127 +static int
 128 +mediatek_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 129 +{
 130 +       struct mtk_gc *rg = to_mediatek_gpio(chip);
 131 +       unsigned long flags;
 132 +       u32 t;
 133 +
 134 +       spin_lock_irqsave(&rg->lock, flags);
 135 +       t = mtk_gpio_r32(rg, GPIO_REG_CTRL);
 136 +       t &= ~BIT(offset);
 137 +       mtk_gpio_w32(rg, GPIO_REG_CTRL, t);
 138 +       spin_unlock_irqrestore(&rg->lock, flags);
 139 +
 140 +       return 0;
 141 +}
 142 +
 143 +static int
 144 +mediatek_gpio_direction_output(struct gpio_chip *chip,
 145 +                                       unsigned offset, int value)
 146 +{
 147 +       struct mtk_gc *rg = to_mediatek_gpio(chip);
 148 +       unsigned long flags;
 149 +       u32 t;
 150 +
 151 +       spin_lock_irqsave(&rg->lock, flags);
 152 +       t = mtk_gpio_r32(rg, GPIO_REG_CTRL);
 153 +       t |= BIT(offset);
 154 +       mtk_gpio_w32(rg, GPIO_REG_CTRL, t);
 155 +       mediatek_gpio_set(chip, offset, value);
 156 +       spin_unlock_irqrestore(&rg->lock, flags);
 157 +
 158 +       return 0;
 159 +}
 160 +
 161 +static int
 162 +mediatek_gpio_bank_probe(struct platform_device *pdev, struct device_node *bank)
 163 +{
 164 +       const __be32 *id = of_get_property(bank, "reg", NULL);
 165 +       struct mtk_gc *rg = devm_kzalloc(&pdev->dev,
 166 +                               sizeof(struct mtk_gc), GFP_KERNEL);
 167 +       if (!rg || !id)
 168 +               return -ENOMEM;
 169 +
 170 +       spin_lock_init(&rg->lock);
 171 +
 172 +       rg->chip.dev = &pdev->dev;
 173 +       rg->chip.label = dev_name(&pdev->dev);
 174 +       rg->chip.of_node = bank;
 175 +       rg->chip.base = MTK_BANK_WIDTH * be32_to_cpu(*id);
 176 +       rg->chip.ngpio = MTK_BANK_WIDTH;
 177 +       rg->chip.direction_input = mediatek_gpio_direction_input;
 178 +       rg->chip.direction_output = mediatek_gpio_direction_output;
 179 +       rg->chip.get = mediatek_gpio_get;
 180 +       rg->chip.set = mediatek_gpio_set;
 181 +
 182 +       /* set polarity to low for all gpios */
 183 +       mtk_gpio_w32(rg, GPIO_REG_POL, 0);
 184 +
 185 +       dev_info(&pdev->dev, "registering %d gpios\n", rg->chip.ngpio);
 186 +
 187 +       return gpiochip_add(&rg->chip);
 188 +}
 189 +
 190 +static int
 191 +mediatek_gpio_probe(struct platform_device *pdev)
 192 +{
 193 +       struct device_node *bank, *np = pdev->dev.of_node;
 194 +       struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 195 +
 196 +       mtk_gc_membase = devm_request_and_ioremap(&pdev->dev, res);
 197 +       if (IS_ERR(mtk_gc_membase))
 198 +               return PTR_ERR(mtk_gc_membase);
 199 +
 200 +       for_each_child_of_node(np, bank)
 201 +               if (of_device_is_compatible(bank, "mtk,mt7621-gpio-bank"))
 202 +                       mediatek_gpio_bank_probe(pdev, bank);
 203 +
 204 +       return 0;
 205 +}
 206 +
 207 +static const struct of_device_id mediatek_gpio_match[] = {
 208 +       { .compatible = "mtk,mt7621-gpio" },
 209 +       {},
 210 +};
 211 +MODULE_DEVICE_TABLE(of, mediatek_gpio_match);
 212 +
 213 +static struct platform_driver mediatek_gpio_driver = {
 214 +       .probe = mediatek_gpio_probe,
 215 +       .driver = {
 216 +               .name = "mt7621_gpio",
 217 +               .owner = THIS_MODULE,
 218 +               .of_match_table = mediatek_gpio_match,
 219 +       },
 220 +};
 221 +
 222 +static int __init
 223 +mediatek_gpio_init(void)
 224 +{
 225 +       return platform_driver_register(&mediatek_gpio_driver);
 226 +}
 227 +
 228 +subsys_initcall(mediatek_gpio_init);