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[openwrt/openwrt.git] / target / linux / ramips / patches-3.14 / 0053-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch
1 From f954801c6f48fc291c39ca8a888dbdfda1021415 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Thu, 13 Nov 2014 19:08:40 +0100
4 Subject: [PATCH] mmc: MIPS: ralink: add sdhci for mt7620a SoC
5
6 Signed-off-by: John Crispin <blogic@openwrt.org>
7 ---
8 drivers/mmc/host/Kconfig | 2 +
9 drivers/mmc/host/Makefile | 1 +
10 drivers/mmc/host/mtk-mmc/Kconfig | 16 +
11 drivers/mmc/host/mtk-mmc/Makefile | 42 +
12 drivers/mmc/host/mtk-mmc/board.h | 137 ++
13 drivers/mmc/host/mtk-mmc/dbg.c | 347 ++++
14 drivers/mmc/host/mtk-mmc/dbg.h | 153 ++
15 drivers/mmc/host/mtk-mmc/mt6575_sd.h | 1001 +++++++++++
16 drivers/mmc/host/mtk-mmc/sd.c | 3041 ++++++++++++++++++++++++++++++++++
17 9 files changed, 4740 insertions(+)
18 create mode 100644 drivers/mmc/host/mtk-mmc/Kconfig
19 create mode 100644 drivers/mmc/host/mtk-mmc/Makefile
20 create mode 100644 drivers/mmc/host/mtk-mmc/board.h
21 create mode 100644 drivers/mmc/host/mtk-mmc/dbg.c
22 create mode 100644 drivers/mmc/host/mtk-mmc/dbg.h
23 create mode 100644 drivers/mmc/host/mtk-mmc/mt6575_sd.h
24 create mode 100644 drivers/mmc/host/mtk-mmc/sd.c
25
26 Index: linux-3.14.18/drivers/mmc/host/Kconfig
27 ===================================================================
28 --- linux-3.14.18.orig/drivers/mmc/host/Kconfig 2014-11-15 14:13:20.210278242 +0100
29 +++ linux-3.14.18/drivers/mmc/host/Kconfig 2014-11-15 14:13:20.998305852 +0100
30 @@ -714,3 +714,5 @@
31 help
32 Say Y here to include driver code to support SD/MMC card interface
33 of Realtek PCI-E card reader
34 +
35 +source "drivers/mmc/host/mtk-mmc/Kconfig"
36 Index: linux-3.14.18/drivers/mmc/host/Makefile
37 ===================================================================
38 --- linux-3.14.18.orig/drivers/mmc/host/Makefile 2014-11-15 14:13:20.210278242 +0100
39 +++ linux-3.14.18/drivers/mmc/host/Makefile 2014-11-15 14:13:20.998305852 +0100
40 @@ -2,6 +2,7 @@
41 # Makefile for MMC/SD host controller drivers
42 #
43
44 +obj-$(CONFIG_MTK_MMC) += mtk-mmc/
45 obj-$(CONFIG_MMC_ARMMMCI) += mmci.o
46 obj-$(CONFIG_MMC_PXA) += pxamci.o
47 obj-$(CONFIG_MMC_MXC) += mxcmmc.o
48 Index: linux-3.14.18/drivers/mmc/host/mtk-mmc/Kconfig
49 ===================================================================
50 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
51 +++ linux-3.14.18/drivers/mmc/host/mtk-mmc/Kconfig 2014-11-15 14:13:20.998305852 +0100
52 @@ -0,0 +1,16 @@
53 +config MTK_MMC
54 + tristate "MTK SD/MMC"
55 + depends on !MTD_NAND_RALINK
56 +
57 +config MTK_AEE_KDUMP
58 + bool "MTK AEE KDUMP"
59 + depends on MTK_MMC
60 +
61 +config MTK_MMC_CD_POLL
62 + bool "Card Detect with Polling"
63 + depends on MTK_MMC
64 +
65 +config MTK_MMC_EMMC_8BIT
66 + bool "eMMC 8-bit support"
67 + depends on MTK_MMC && RALINK_MT7628
68 +
69 Index: linux-3.14.18/drivers/mmc/host/mtk-mmc/Makefile
70 ===================================================================
71 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
72 +++ linux-3.14.18/drivers/mmc/host/mtk-mmc/Makefile 2014-11-15 14:13:20.998305852 +0100
73 @@ -0,0 +1,42 @@
74 +# Copyright Statement:
75 +#
76 +# This software/firmware and related documentation ("MediaTek Software") are
77 +# protected under relevant copyright laws. The information contained herein
78 +# is confidential and proprietary to MediaTek Inc. and/or its licensors.
79 +# Without the prior written permission of MediaTek inc. and/or its licensors,
80 +# any reproduction, modification, use or disclosure of MediaTek Software,
81 +# and information contained herein, in whole or in part, shall be strictly prohibited.
82 +#
83 +# MediaTek Inc. (C) 2010. All rights reserved.
84 +#
85 +# BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
86 +# THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
87 +# RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
88 +# AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
89 +# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
90 +# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
91 +# NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
92 +# SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
93 +# SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
94 +# THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
95 +# THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
96 +# CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
97 +# SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
98 +# STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
99 +# CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
100 +# AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
101 +# OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
102 +# MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
103 +#
104 +# The following software/firmware and/or related documentation ("MediaTek Software")
105 +# have been modified by MediaTek Inc. All revisions are subject to any receiver's
106 +# applicable license agreements with MediaTek Inc.
107 +
108 +obj-$(CONFIG_MTK_MMC) += mtk_sd.o
109 +mtk_sd-objs := sd.o dbg.o
110 +ifeq ($(CONFIG_MTK_AEE_KDUMP),y)
111 +EXTRA_CFLAGS += -DMT6575_SD_DEBUG
112 +endif
113 +
114 +clean:
115 + @rm -f *.o modules.order .*.cmd
116 Index: linux-3.14.18/drivers/mmc/host/mtk-mmc/board.h
117 ===================================================================
118 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
119 +++ linux-3.14.18/drivers/mmc/host/mtk-mmc/board.h 2014-11-15 14:13:20.998305852 +0100
120 @@ -0,0 +1,137 @@
121 +/* Copyright Statement:
122 + *
123 + * This software/firmware and related documentation ("MediaTek Software") are
124 + * protected under relevant copyright laws. The information contained herein
125 + * is confidential and proprietary to MediaTek Inc. and/or its licensors.
126 + * Without the prior written permission of MediaTek inc. and/or its licensors,
127 + * any reproduction, modification, use or disclosure of MediaTek Software,
128 + * and information contained herein, in whole or in part, shall be strictly prohibited.
129 + */
130 +/* MediaTek Inc. (C) 2010. All rights reserved.
131 + *
132 + * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
133 + * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
134 + * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
135 + * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
136 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
137 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
138 + * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
139 + * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
140 + * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
141 + * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
142 + * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
143 + * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
144 + * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
145 + * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
146 + * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
147 + * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
148 + * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
149 + * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
150 + *
151 + * The following software/firmware and/or related documentation ("MediaTek Software")
152 + * have been modified by MediaTek Inc. All revisions are subject to any receiver's
153 + * applicable license agreements with MediaTek Inc.
154 + */
155 +
156 +#ifndef __ARCH_ARM_MACH_BOARD_H
157 +#define __ARCH_ARM_MACH_BOARD_H
158 +
159 +#include <generated/autoconf.h>
160 +#include <linux/pm.h>
161 +/* --- chhung */
162 +// #include <mach/mt6575.h>
163 +// #include <board-custom.h>
164 +/* end of chhung */
165 +
166 +typedef void (*sdio_irq_handler_t)(void*); /* external irq handler */
167 +typedef void (*pm_callback_t)(pm_message_t state, void *data);
168 +
169 +#define MSDC_CD_PIN_EN (1 << 0) /* card detection pin is wired */
170 +#define MSDC_WP_PIN_EN (1 << 1) /* write protection pin is wired */
171 +#define MSDC_RST_PIN_EN (1 << 2) /* emmc reset pin is wired */
172 +#define MSDC_SDIO_IRQ (1 << 3) /* use internal sdio irq (bus) */
173 +#define MSDC_EXT_SDIO_IRQ (1 << 4) /* use external sdio irq */
174 +#define MSDC_REMOVABLE (1 << 5) /* removable slot */
175 +#define MSDC_SYS_SUSPEND (1 << 6) /* suspended by system */
176 +#define MSDC_HIGHSPEED (1 << 7) /* high-speed mode support */
177 +#define MSDC_UHS1 (1 << 8) /* uhs-1 mode support */
178 +#define MSDC_DDR (1 << 9) /* ddr mode support */
179 +
180 +
181 +#define MSDC_SMPL_RISING (0)
182 +#define MSDC_SMPL_FALLING (1)
183 +
184 +#define MSDC_CMD_PIN (0)
185 +#define MSDC_DAT_PIN (1)
186 +#define MSDC_CD_PIN (2)
187 +#define MSDC_WP_PIN (3)
188 +#define MSDC_RST_PIN (4)
189 +
190 +enum {
191 + MSDC_CLKSRC_48MHZ = 0,
192 +// MSDC_CLKSRC_26MHZ = 0,
193 +// MSDC_CLKSRC_197MHZ = 1,
194 +// MSDC_CLKSRC_208MHZ = 2
195 +};
196 +
197 +struct msdc_hw {
198 + unsigned char clk_src; /* host clock source */
199 + unsigned char cmd_edge; /* command latch edge */
200 + unsigned char data_edge; /* data latch edge */
201 + unsigned char clk_drv; /* clock pad driving */
202 + unsigned char cmd_drv; /* command pad driving */
203 + unsigned char dat_drv; /* data pad driving */
204 + unsigned long flags; /* hardware capability flags */
205 + unsigned long data_pins; /* data pins */
206 + unsigned long data_offset; /* data address offset */
207 +
208 + /* config gpio pull mode */
209 + void (*config_gpio_pin)(int type, int pull);
210 +
211 + /* external power control for card */
212 + void (*ext_power_on)(void);
213 + void (*ext_power_off)(void);
214 +
215 + /* external sdio irq operations */
216 + void (*request_sdio_eirq)(sdio_irq_handler_t sdio_irq_handler, void *data);
217 + void (*enable_sdio_eirq)(void);
218 + void (*disable_sdio_eirq)(void);
219 +
220 + /* external cd irq operations */
221 + void (*request_cd_eirq)(sdio_irq_handler_t cd_irq_handler, void *data);
222 + void (*enable_cd_eirq)(void);
223 + void (*disable_cd_eirq)(void);
224 + int (*get_cd_status)(void);
225 +
226 + /* power management callback for external module */
227 + void (*register_pm)(pm_callback_t pm_cb, void *data);
228 +};
229 +
230 +extern struct msdc_hw msdc0_hw;
231 +extern struct msdc_hw msdc1_hw;
232 +extern struct msdc_hw msdc2_hw;
233 +extern struct msdc_hw msdc3_hw;
234 +
235 +/*GPS driver*/
236 +#define GPS_FLAG_FORCE_OFF 0x0001
237 +struct mt3326_gps_hardware {
238 + int (*ext_power_on)(int);
239 + int (*ext_power_off)(int);
240 +};
241 +extern struct mt3326_gps_hardware mt3326_gps_hw;
242 +
243 +/* NAND driver */
244 +struct mt6575_nand_host_hw {
245 + unsigned int nfi_bus_width; /* NFI_BUS_WIDTH */
246 + unsigned int nfi_access_timing; /* NFI_ACCESS_TIMING */
247 + unsigned int nfi_cs_num; /* NFI_CS_NUM */
248 + unsigned int nand_sec_size; /* NAND_SECTOR_SIZE */
249 + unsigned int nand_sec_shift; /* NAND_SECTOR_SHIFT */
250 + unsigned int nand_ecc_size;
251 + unsigned int nand_ecc_bytes;
252 + unsigned int nand_ecc_mode;
253 +};
254 +extern struct mt6575_nand_host_hw mt6575_nand_hw;
255 +
256 +#endif /* __ARCH_ARM_MACH_BOARD_H */
257 +
258 Index: linux-3.14.18/drivers/mmc/host/mtk-mmc/dbg.c
259 ===================================================================
260 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
261 +++ linux-3.14.18/drivers/mmc/host/mtk-mmc/dbg.c 2014-11-15 14:13:20.998305852 +0100
262 @@ -0,0 +1,347 @@
263 +/* Copyright Statement:
264 + *
265 + * This software/firmware and related documentation ("MediaTek Software") are
266 + * protected under relevant copyright laws. The information contained herein
267 + * is confidential and proprietary to MediaTek Inc. and/or its licensors.
268 + * Without the prior written permission of MediaTek inc. and/or its licensors,
269 + * any reproduction, modification, use or disclosure of MediaTek Software,
270 + * and information contained herein, in whole or in part, shall be strictly prohibited.
271 + *
272 + * MediaTek Inc. (C) 2010. All rights reserved.
273 + *
274 + * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
275 + * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
276 + * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
277 + * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
278 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
279 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
280 + * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
281 + * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
282 + * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
283 + * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
284 + * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
285 + * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
286 + * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
287 + * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
288 + * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
289 + * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
290 + * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
291 + * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
292 + *
293 + * The following software/firmware and/or related documentation ("MediaTek Software")
294 + * have been modified by MediaTek Inc. All revisions are subject to any receiver's
295 + * applicable license agreements with MediaTek Inc.
296 + */
297 +
298 +#include <linux/version.h>
299 +#include <linux/kernel.h>
300 +#include <linux/sched.h>
301 +#include <linux/kthread.h>
302 +#include <linux/delay.h>
303 +#include <linux/module.h>
304 +#include <linux/init.h>
305 +#include <linux/proc_fs.h>
306 +#include <linux/string.h>
307 +#include <linux/uaccess.h>
308 +// #include <mach/mt6575_gpt.h> /* --- by chhung */
309 +#include "dbg.h"
310 +#include "mt6575_sd.h"
311 +#include <linux/seq_file.h>
312 +
313 +static char cmd_buf[256];
314 +
315 +/* for debug zone */
316 +unsigned int sd_debug_zone[4]={
317 + 0,
318 + 0,
319 + 0,
320 + 0
321 +};
322 +
323 +/* mode select */
324 +u32 dma_size[4]={
325 + 512,
326 + 512,
327 + 512,
328 + 512
329 +};
330 +msdc_mode drv_mode[4]={
331 + MODE_SIZE_DEP, /* using DMA or not depend on the size */
332 + MODE_SIZE_DEP,
333 + MODE_SIZE_DEP,
334 + MODE_SIZE_DEP
335 +};
336 +
337 +#if defined (MT6575_SD_DEBUG)
338 +/* for driver profile */
339 +#define TICKS_ONE_MS (13000)
340 +u32 gpt_enable = 0;
341 +u32 sdio_pro_enable = 0; /* make sure gpt is enabled */
342 +u32 sdio_pro_time = 0; /* no more than 30s */
343 +struct sdio_profile sdio_perfomance = {0};
344 +
345 +#if 0 /* --- chhung */
346 +void msdc_init_gpt(void)
347 +{
348 + GPT_CONFIG config;
349 +
350 + config.num = GPT6;
351 + config.mode = GPT_FREE_RUN;
352 + config.clkSrc = GPT_CLK_SRC_SYS;
353 + config.clkDiv = GPT_CLK_DIV_1; /* 13MHz GPT6 */
354 +
355 + if (GPT_Config(config) == FALSE )
356 + return;
357 +
358 + GPT_Start(GPT6);
359 +}
360 +#endif /* end of --- */
361 +
362 +u32 msdc_time_calc(u32 old_L32, u32 old_H32, u32 new_L32, u32 new_H32)
363 +{
364 + u32 ret = 0;
365 +
366 + if (new_H32 == old_H32) {
367 + ret = new_L32 - old_L32;
368 + } else if(new_H32 == (old_H32 + 1)) {
369 + if (new_L32 > old_L32) {
370 + printk("msdc old_L<0x%x> new_L<0x%x>\n", old_L32, new_L32);
371 + }
372 + ret = (0xffffffff - old_L32);
373 + ret += new_L32;
374 + } else {
375 + printk("msdc old_H<0x%x> new_H<0x%x>\n", old_H32, new_H32);
376 + }
377 +
378 + return ret;
379 +}
380 +
381 +void msdc_sdio_profile(struct sdio_profile* result)
382 +{
383 + struct cmd_profile* cmd;
384 + u32 i;
385 +
386 + printk("sdio === performance dump ===\n");
387 + printk("sdio === total execute tick<%d> time<%dms> Tx<%dB> Rx<%dB>\n",
388 + result->total_tc, result->total_tc / TICKS_ONE_MS,
389 + result->total_tx_bytes, result->total_rx_bytes);
390 +
391 + /* CMD52 Dump */
392 + cmd = &result->cmd52_rx;
393 + printk("sdio === CMD52 Rx <%d>times tick<%d> Max<%d> Min<%d> Aver<%d>\n", cmd->count, cmd->tot_tc,
394 + cmd->max_tc, cmd->min_tc, cmd->tot_tc/cmd->count);
395 + cmd = &result->cmd52_tx;
396 + printk("sdio === CMD52 Tx <%d>times tick<%d> Max<%d> Min<%d> Aver<%d>\n", cmd->count, cmd->tot_tc,
397 + cmd->max_tc, cmd->min_tc, cmd->tot_tc/cmd->count);
398 +
399 + /* CMD53 Rx bytes + block mode */
400 + for (i=0; i<512; i++) {
401 + cmd = &result->cmd53_rx_byte[i];
402 + if (cmd->count) {
403 + printk("sdio<%6d><%3dB>_Rx_<%9d><%9d><%6d><%6d>_<%9dB><%2dM>\n", cmd->count, i, cmd->tot_tc,
404 + cmd->max_tc, cmd->min_tc, cmd->tot_tc/cmd->count,
405 + cmd->tot_bytes, (cmd->tot_bytes/10)*13 / (cmd->tot_tc/10));
406 + }
407 + }
408 + for (i=0; i<100; i++) {
409 + cmd = &result->cmd53_rx_blk[i];
410 + if (cmd->count) {
411 + printk("sdio<%6d><%3d>B_Rx_<%9d><%9d><%6d><%6d>_<%9dB><%2dM>\n", cmd->count, i, cmd->tot_tc,
412 + cmd->max_tc, cmd->min_tc, cmd->tot_tc/cmd->count,
413 + cmd->tot_bytes, (cmd->tot_bytes/10)*13 / (cmd->tot_tc/10));
414 + }
415 + }
416 +
417 + /* CMD53 Tx bytes + block mode */
418 + for (i=0; i<512; i++) {
419 + cmd = &result->cmd53_tx_byte[i];
420 + if (cmd->count) {
421 + printk("sdio<%6d><%3dB>_Tx_<%9d><%9d><%6d><%6d>_<%9dB><%2dM>\n", cmd->count, i, cmd->tot_tc,
422 + cmd->max_tc, cmd->min_tc, cmd->tot_tc/cmd->count,
423 + cmd->tot_bytes, (cmd->tot_bytes/10)*13 / (cmd->tot_tc/10));
424 + }
425 + }
426 + for (i=0; i<100; i++) {
427 + cmd = &result->cmd53_tx_blk[i];
428 + if (cmd->count) {
429 + printk("sdio<%6d><%3d>B_Tx_<%9d><%9d><%6d><%6d>_<%9dB><%2dM>\n", cmd->count, i, cmd->tot_tc,
430 + cmd->max_tc, cmd->min_tc, cmd->tot_tc/cmd->count,
431 + cmd->tot_bytes, (cmd->tot_bytes/10)*13 / (cmd->tot_tc/10));
432 + }
433 + }
434 +
435 + printk("sdio === performance dump done ===\n");
436 +}
437 +
438 +//========= sdio command table ===========
439 +void msdc_performance(u32 opcode, u32 sizes, u32 bRx, u32 ticks)
440 +{
441 + struct sdio_profile* result = &sdio_perfomance;
442 + struct cmd_profile* cmd;
443 + u32 block;
444 +
445 + if (sdio_pro_enable == 0) {
446 + return;
447 + }
448 +
449 + if (opcode == 52) {
450 + cmd = bRx ? &result->cmd52_rx : &result->cmd52_tx;
451 + } else if (opcode == 53) {
452 + if (sizes < 512) {
453 + cmd = bRx ? &result->cmd53_rx_byte[sizes] : &result->cmd53_tx_byte[sizes];
454 + } else {
455 + block = sizes / 512;
456 + if (block >= 99) {
457 + printk("cmd53 error blocks\n");
458 + while(1);
459 + }
460 + cmd = bRx ? &result->cmd53_rx_blk[block] : &result->cmd53_tx_blk[block];
461 + }
462 + } else {
463 + return;
464 + }
465 +
466 + /* update the members */
467 + if (ticks > cmd->max_tc){
468 + cmd->max_tc = ticks;
469 + }
470 + if (cmd->min_tc == 0 || ticks < cmd->min_tc) {
471 + cmd->min_tc = ticks;
472 + }
473 + cmd->tot_tc += ticks;
474 + cmd->tot_bytes += sizes;
475 + cmd->count ++;
476 +
477 + if (bRx) {
478 + result->total_rx_bytes += sizes;
479 + } else {
480 + result->total_tx_bytes += sizes;
481 + }
482 + result->total_tc += ticks;
483 +
484 + /* dump when total_tc > 30s */
485 + if (result->total_tc >= sdio_pro_time * TICKS_ONE_MS * 1000) {
486 + msdc_sdio_profile(result);
487 + memset(result, 0 , sizeof(struct sdio_profile));
488 + }
489 +}
490 +
491 +//========== driver proc interface ===========
492 +static int msdc_debug_proc_read(struct seq_file *s, void *p)
493 +{
494 + seq_printf(s, "\n=========================================\n");
495 + seq_printf(s, "Index<0> + Id + Zone\n");
496 + seq_printf(s, "-> PWR<9> WRN<8> | FIO<7> OPS<6> FUN<5> CFG<4> | INT<3> RSP<2> CMD<1> DMA<0>\n");
497 + seq_printf(s, "-> echo 0 3 0x3ff >msdc_bebug -> host[3] debug zone set to 0x3ff\n");
498 + seq_printf(s, "-> MSDC[0] Zone: 0x%.8x\n", sd_debug_zone[0]);
499 + seq_printf(s, "-> MSDC[1] Zone: 0x%.8x\n", sd_debug_zone[1]);
500 + seq_printf(s, "-> MSDC[2] Zone: 0x%.8x\n", sd_debug_zone[2]);
501 + seq_printf(s, "-> MSDC[3] Zone: 0x%.8x\n", sd_debug_zone[3]);
502 +
503 + seq_printf(s, "Index<1> + ID:4|Mode:4 + DMA_SIZE\n");
504 + seq_printf(s, "-> 0)PIO 1)DMA 2)SIZE\n");
505 + seq_printf(s, "-> echo 1 22 0x200 >msdc_bebug -> host[2] size mode, dma when >= 512\n");
506 + seq_printf(s, "-> MSDC[0] mode<%d> size<%d>\n", drv_mode[0], dma_size[0]);
507 + seq_printf(s, "-> MSDC[1] mode<%d> size<%d>\n", drv_mode[1], dma_size[1]);
508 + seq_printf(s, "-> MSDC[2] mode<%d> size<%d>\n", drv_mode[2], dma_size[2]);
509 + seq_printf(s, "-> MSDC[3] mode<%d> size<%d>\n", drv_mode[3], dma_size[3]);
510 +
511 + seq_printf(s, "Index<3> + SDIO_PROFILE + TIME\n");
512 + seq_printf(s, "-> echo 3 1 0x1E >msdc_bebug -> enable sdio_profile, 30s\n");
513 + seq_printf(s, "-> SDIO_PROFILE<%d> TIME<%ds>\n", sdio_pro_enable, sdio_pro_time);
514 + seq_printf(s, "=========================================\n\n");
515 +
516 + return 0;
517 +}
518 +
519 +static ssize_t msdc_debug_proc_write(struct file *file,
520 + const char __user *buf, size_t count, loff_t *data)
521 +{
522 + int ret;
523 +
524 + int cmd, p1, p2;
525 + int id, zone;
526 + int mode, size;
527 +
528 + if (count == 0)return -1;
529 + if(count > 255)count = 255;
530 +
531 + ret = copy_from_user(cmd_buf, buf, count);
532 + if (ret < 0)return -1;
533 +
534 + cmd_buf[count] = '\0';
535 + printk("msdc Write %s\n", cmd_buf);
536 +
537 + sscanf(cmd_buf, "%x %x %x", &cmd, &p1, &p2);
538 +
539 + if(cmd == SD_TOOL_ZONE) {
540 + id = p1; zone = p2; zone &= 0x3ff;
541 + printk("msdc host_id<%d> zone<0x%.8x>\n", id, zone);
542 + if(id >=0 && id<=3){
543 + sd_debug_zone[id] = zone;
544 + }
545 + else if(id == 4){
546 + sd_debug_zone[0] = sd_debug_zone[1] = zone;
547 + sd_debug_zone[2] = sd_debug_zone[3] = zone;
548 + }
549 + else{
550 + printk("msdc host_id error when set debug zone\n");
551 + }
552 + } else if (cmd == SD_TOOL_DMA_SIZE) {
553 + id = p1>>4; mode = (p1&0xf); size = p2;
554 + if(id >=0 && id<=3){
555 + drv_mode[id] = mode;
556 + dma_size[id] = p2;
557 + }
558 + else if(id == 4){
559 + drv_mode[0] = drv_mode[1] = mode;
560 + drv_mode[2] = drv_mode[3] = mode;
561 + dma_size[0] = dma_size[1] = p2;
562 + dma_size[2] = dma_size[3] = p2;
563 + }
564 + else{
565 + printk("msdc host_id error when select mode\n");
566 + }
567 + } else if (cmd == SD_TOOL_SDIO_PROFILE) {
568 + if (p1 == 1) { /* enable profile */
569 + if (gpt_enable == 0) {
570 + // msdc_init_gpt(); /* --- by chhung */
571 + gpt_enable = 1;
572 + }
573 + sdio_pro_enable = 1;
574 + if (p2 == 0) p2 = 1; if (p2 >= 30) p2 = 30;
575 + sdio_pro_time = p2 ;
576 + } else if (p1 == 0) {
577 + /* todo */
578 + sdio_pro_enable = 0;
579 + }
580 + }
581 +
582 + return count;
583 +}
584 +
585 +static int msdc_debug_show(struct inode *inode, struct file *file)
586 +{
587 + return single_open(file, msdc_debug_proc_read, NULL);
588 +}
589 +
590 +static const struct file_operations msdc_debug_fops = {
591 + .owner = THIS_MODULE,
592 + .open = msdc_debug_show,
593 + .read = seq_read,
594 + .write = msdc_debug_proc_write,
595 + .llseek = seq_lseek,
596 + .release = single_release,
597 +};
598 +
599 +int msdc_debug_proc_init(void)
600 +{
601 + struct proc_dir_entry *de = proc_create("msdc_debug", 0667, NULL, &msdc_debug_fops);
602 +
603 + if (!de || IS_ERR(de))
604 + printk("!! Create MSDC debug PROC fail !!\n");
605 +
606 + return 0 ;
607 +}
608 +EXPORT_SYMBOL_GPL(msdc_debug_proc_init);
609 +#endif
610 Index: linux-3.14.18/drivers/mmc/host/mtk-mmc/dbg.h
611 ===================================================================
612 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
613 +++ linux-3.14.18/drivers/mmc/host/mtk-mmc/dbg.h 2014-11-15 14:13:20.998305852 +0100
614 @@ -0,0 +1,156 @@
615 +/* Copyright Statement:
616 + *
617 + * This software/firmware and related documentation ("MediaTek Software") are
618 + * protected under relevant copyright laws. The information contained herein
619 + * is confidential and proprietary to MediaTek Inc. and/or its licensors.
620 + * Without the prior written permission of MediaTek inc. and/or its licensors,
621 + * any reproduction, modification, use or disclosure of MediaTek Software,
622 + * and information contained herein, in whole or in part, shall be strictly prohibited.
623 + *
624 + * MediaTek Inc. (C) 2010. All rights reserved.
625 + *
626 + * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
627 + * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
628 + * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
629 + * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
630 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
631 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
632 + * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
633 + * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
634 + * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
635 + * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
636 + * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
637 + * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
638 + * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
639 + * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
640 + * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
641 + * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
642 + * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
643 + * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
644 + *
645 + * The following software/firmware and/or related documentation ("MediaTek Software")
646 + * have been modified by MediaTek Inc. All revisions are subject to any receiver's
647 + * applicable license agreements with MediaTek Inc.
648 + */
649 +#ifndef __MT_MSDC_DEUBG__
650 +#define __MT_MSDC_DEUBG__
651 +
652 +//==========================
653 +extern u32 sdio_pro_enable;
654 +/* for a type command, e.g. CMD53, 2 blocks */
655 +struct cmd_profile {
656 + u32 max_tc; /* Max tick count */
657 + u32 min_tc;
658 + u32 tot_tc; /* total tick count */
659 + u32 tot_bytes;
660 + u32 count; /* the counts of the command */
661 +};
662 +
663 +/* dump when total_tc and total_bytes */
664 +struct sdio_profile {
665 + u32 total_tc; /* total tick count of CMD52 and CMD53 */
666 + u32 total_tx_bytes; /* total bytes of CMD53 Tx */
667 + u32 total_rx_bytes; /* total bytes of CMD53 Rx */
668 +
669 + /*CMD52*/
670 + struct cmd_profile cmd52_tx;
671 + struct cmd_profile cmd52_rx;
672 +
673 + /*CMD53 in byte unit */
674 + struct cmd_profile cmd53_tx_byte[512];
675 + struct cmd_profile cmd53_rx_byte[512];
676 +
677 + /*CMD53 in block unit */
678 + struct cmd_profile cmd53_tx_blk[100];
679 + struct cmd_profile cmd53_rx_blk[100];
680 +};
681 +
682 +//==========================
683 +typedef enum {
684 + SD_TOOL_ZONE = 0,
685 + SD_TOOL_DMA_SIZE = 1,
686 + SD_TOOL_PM_ENABLE = 2,
687 + SD_TOOL_SDIO_PROFILE = 3,
688 +} msdc_dbg;
689 +
690 +typedef enum {
691 + MODE_PIO = 0,
692 + MODE_DMA = 1,
693 + MODE_SIZE_DEP = 2,
694 +} msdc_mode;
695 +extern msdc_mode drv_mode[4];
696 +extern u32 dma_size[4];
697 +
698 +/* Debug message event */
699 +#define DBG_EVT_NONE (0) /* No event */
700 +#define DBG_EVT_DMA (1 << 0) /* DMA related event */
701 +#define DBG_EVT_CMD (1 << 1) /* MSDC CMD related event */
702 +#define DBG_EVT_RSP (1 << 2) /* MSDC CMD RSP related event */
703 +#define DBG_EVT_INT (1 << 3) /* MSDC INT event */
704 +#define DBG_EVT_CFG (1 << 4) /* MSDC CFG event */
705 +#define DBG_EVT_FUC (1 << 5) /* Function event */
706 +#define DBG_EVT_OPS (1 << 6) /* Read/Write operation event */
707 +#define DBG_EVT_FIO (1 << 7) /* FIFO operation event */
708 +#define DBG_EVT_WRN (1 << 8) /* Warning event */
709 +#define DBG_EVT_PWR (1 << 9) /* Power event */
710 +#define DBG_EVT_ALL (0xffffffff)
711 +
712 +#define DBG_EVT_MASK (DBG_EVT_ALL)
713 +
714 +extern unsigned int sd_debug_zone[4];
715 +#define TAG "msdc"
716 +#if 0 /* +++ chhung */
717 +#define BUG_ON(x) \
718 +do { \
719 + if (x) { \
720 + printk("[BUG] %s LINE:%d FILE:%s\n", #x, __LINE__, __FILE__); \
721 + while(1); \
722 + } \
723 +}while(0)
724 +#endif /* end of +++ */
725 +
726 +#define N_MSG(evt, fmt, args...)
727 +/*
728 +do { \
729 + if ((DBG_EVT_##evt) & sd_debug_zone[host->id]) { \
730 + printk(KERN_ERR TAG"%d -> "fmt" <- %s() : L<%d> PID<%s><0x%x>\n", \
731 + host->id, ##args , __FUNCTION__, __LINE__, current->comm, current->pid); \
732 + } \
733 +} while(0)
734 +*/
735 +
736 +#define ERR_MSG(fmt, args...) \
737 +do { \
738 + printk(KERN_ERR TAG"%d -> "fmt" <- %s() : L<%d> PID<%s><0x%x>\n", \
739 + host->id, ##args , __FUNCTION__, __LINE__, current->comm, current->pid); \
740 +} while(0);
741 +
742 +#if 1
743 +//defined CONFIG_MTK_MMC_CD_POLL
744 +#define INIT_MSG(fmt, args...)
745 +#define IRQ_MSG(fmt, args...)
746 +#else
747 +#define INIT_MSG(fmt, args...) \
748 +do { \
749 + printk(KERN_ERR TAG"%d -> "fmt" <- %s() : L<%d> PID<%s><0x%x>\n", \
750 + host->id, ##args , __FUNCTION__, __LINE__, current->comm, current->pid); \
751 +} while(0);
752 +
753 +/* PID in ISR in not corrent */
754 +#define IRQ_MSG(fmt, args...) \
755 +do { \
756 + printk(KERN_ERR TAG"%d -> "fmt" <- %s() : L<%d>\n", \
757 + host->id, ##args , __FUNCTION__, __LINE__); \
758 +} while(0);
759 +#endif
760 +
761 +int msdc_debug_proc_init(void);
762 +
763 +#if 0 /* --- chhung */
764 +void msdc_init_gpt(void);
765 +extern void GPT_GetCounter64(UINT32 *cntL32, UINT32 *cntH32);
766 +#endif /* end of --- */
767 +u32 msdc_time_calc(u32 old_L32, u32 old_H32, u32 new_L32, u32 new_H32);
768 +void msdc_performance(u32 opcode, u32 sizes, u32 bRx, u32 ticks);
769 +
770 +#endif
771 Index: linux-3.14.18/drivers/mmc/host/mtk-mmc/mt6575_sd.h
772 ===================================================================
773 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
774 +++ linux-3.14.18/drivers/mmc/host/mtk-mmc/mt6575_sd.h 2014-11-15 14:13:20.998305852 +0100
775 @@ -0,0 +1,1001 @@
776 +/* Copyright Statement:
777 + *
778 + * This software/firmware and related documentation ("MediaTek Software") are
779 + * protected under relevant copyright laws. The information contained herein
780 + * is confidential and proprietary to MediaTek Inc. and/or its licensors.
781 + * Without the prior written permission of MediaTek inc. and/or its licensors,
782 + * any reproduction, modification, use or disclosure of MediaTek Software,
783 + * and information contained herein, in whole or in part, shall be strictly prohibited.
784 + */
785 +/* MediaTek Inc. (C) 2010. All rights reserved.
786 + *
787 + * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
788 + * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
789 + * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
790 + * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
791 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
792 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
793 + * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
794 + * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
795 + * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
796 + * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
797 + * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
798 + * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
799 + * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
800 + * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
801 + * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
802 + * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
803 + * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
804 + * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
805 + *
806 + * The following software/firmware and/or related documentation ("MediaTek Software")
807 + * have been modified by MediaTek Inc. All revisions are subject to any receiver's
808 + * applicable license agreements with MediaTek Inc.
809 + */
810 +
811 +#ifndef MT6575_SD_H
812 +#define MT6575_SD_H
813 +
814 +#include <linux/bitops.h>
815 +#include <linux/mmc/host.h>
816 +
817 +// #include <mach/mt6575_reg_base.h> /* --- by chhung */
818 +
819 +/*--------------------------------------------------------------------------*/
820 +/* Common Macro */
821 +/*--------------------------------------------------------------------------*/
822 +#define REG_ADDR(x) ((volatile u32*)(base + OFFSET_##x))
823 +
824 +/*--------------------------------------------------------------------------*/
825 +/* Common Definition */
826 +/*--------------------------------------------------------------------------*/
827 +#define MSDC_FIFO_SZ (128)
828 +#define MSDC_FIFO_THD (64) // (128)
829 +#define MSDC_NUM (4)
830 +
831 +#define MSDC_MS (0)
832 +#define MSDC_SDMMC (1)
833 +
834 +#define MSDC_MODE_UNKNOWN (0)
835 +#define MSDC_MODE_PIO (1)
836 +#define MSDC_MODE_DMA_BASIC (2)
837 +#define MSDC_MODE_DMA_DESC (3)
838 +#define MSDC_MODE_DMA_ENHANCED (4)
839 +#define MSDC_MODE_MMC_STREAM (5)
840 +
841 +#define MSDC_BUS_1BITS (0)
842 +#define MSDC_BUS_4BITS (1)
843 +#define MSDC_BUS_8BITS (2)
844 +
845 +#define MSDC_BRUST_8B (3)
846 +#define MSDC_BRUST_16B (4)
847 +#define MSDC_BRUST_32B (5)
848 +#define MSDC_BRUST_64B (6)
849 +
850 +#define MSDC_PIN_PULL_NONE (0)
851 +#define MSDC_PIN_PULL_DOWN (1)
852 +#define MSDC_PIN_PULL_UP (2)
853 +#define MSDC_PIN_KEEP (3)
854 +
855 +#define MSDC_MAX_SCLK (48000000) /* +/- by chhung */
856 +#define MSDC_MIN_SCLK (260000)
857 +
858 +#define MSDC_AUTOCMD12 (0x0001)
859 +#define MSDC_AUTOCMD23 (0x0002)
860 +#define MSDC_AUTOCMD19 (0x0003)
861 +
862 +#define MSDC_EMMC_BOOTMODE0 (0) /* Pull low CMD mode */
863 +#define MSDC_EMMC_BOOTMODE1 (1) /* Reset CMD mode */
864 +
865 +enum {
866 + RESP_NONE = 0,
867 + RESP_R1,
868 + RESP_R2,
869 + RESP_R3,
870 + RESP_R4,
871 + RESP_R5,
872 + RESP_R6,
873 + RESP_R7,
874 + RESP_R1B
875 +};
876 +
877 +/*--------------------------------------------------------------------------*/
878 +/* Register Offset */
879 +/*--------------------------------------------------------------------------*/
880 +#define OFFSET_MSDC_CFG (0x0)
881 +#define OFFSET_MSDC_IOCON (0x04)
882 +#define OFFSET_MSDC_PS (0x08)
883 +#define OFFSET_MSDC_INT (0x0c)
884 +#define OFFSET_MSDC_INTEN (0x10)
885 +#define OFFSET_MSDC_FIFOCS (0x14)
886 +#define OFFSET_MSDC_TXDATA (0x18)
887 +#define OFFSET_MSDC_RXDATA (0x1c)
888 +#define OFFSET_SDC_CFG (0x30)
889 +#define OFFSET_SDC_CMD (0x34)
890 +#define OFFSET_SDC_ARG (0x38)
891 +#define OFFSET_SDC_STS (0x3c)
892 +#define OFFSET_SDC_RESP0 (0x40)
893 +#define OFFSET_SDC_RESP1 (0x44)
894 +#define OFFSET_SDC_RESP2 (0x48)
895 +#define OFFSET_SDC_RESP3 (0x4c)
896 +#define OFFSET_SDC_BLK_NUM (0x50)
897 +#define OFFSET_SDC_CSTS (0x58)
898 +#define OFFSET_SDC_CSTS_EN (0x5c)
899 +#define OFFSET_SDC_DCRC_STS (0x60)
900 +#define OFFSET_EMMC_CFG0 (0x70)
901 +#define OFFSET_EMMC_CFG1 (0x74)
902 +#define OFFSET_EMMC_STS (0x78)
903 +#define OFFSET_EMMC_IOCON (0x7c)
904 +#define OFFSET_SDC_ACMD_RESP (0x80)
905 +#define OFFSET_SDC_ACMD19_TRG (0x84)
906 +#define OFFSET_SDC_ACMD19_STS (0x88)
907 +#define OFFSET_MSDC_DMA_SA (0x90)
908 +#define OFFSET_MSDC_DMA_CA (0x94)
909 +#define OFFSET_MSDC_DMA_CTRL (0x98)
910 +#define OFFSET_MSDC_DMA_CFG (0x9c)
911 +#define OFFSET_MSDC_DBG_SEL (0xa0)
912 +#define OFFSET_MSDC_DBG_OUT (0xa4)
913 +#define OFFSET_MSDC_PATCH_BIT (0xb0)
914 +#define OFFSET_MSDC_PATCH_BIT1 (0xb4)
915 +#define OFFSET_MSDC_PAD_CTL0 (0xe0)
916 +#define OFFSET_MSDC_PAD_CTL1 (0xe4)
917 +#define OFFSET_MSDC_PAD_CTL2 (0xe8)
918 +#define OFFSET_MSDC_PAD_TUNE (0xec)
919 +#define OFFSET_MSDC_DAT_RDDLY0 (0xf0)
920 +#define OFFSET_MSDC_DAT_RDDLY1 (0xf4)
921 +#define OFFSET_MSDC_HW_DBG (0xf8)
922 +#define OFFSET_MSDC_VERSION (0x100)
923 +#define OFFSET_MSDC_ECO_VER (0x104)
924 +
925 +/*--------------------------------------------------------------------------*/
926 +/* Register Address */
927 +/*--------------------------------------------------------------------------*/
928 +
929 +/* common register */
930 +#define MSDC_CFG REG_ADDR(MSDC_CFG)
931 +#define MSDC_IOCON REG_ADDR(MSDC_IOCON)
932 +#define MSDC_PS REG_ADDR(MSDC_PS)
933 +#define MSDC_INT REG_ADDR(MSDC_INT)
934 +#define MSDC_INTEN REG_ADDR(MSDC_INTEN)
935 +#define MSDC_FIFOCS REG_ADDR(MSDC_FIFOCS)
936 +#define MSDC_TXDATA REG_ADDR(MSDC_TXDATA)
937 +#define MSDC_RXDATA REG_ADDR(MSDC_RXDATA)
938 +#define MSDC_PATCH_BIT0 REG_ADDR(MSDC_PATCH_BIT)
939 +
940 +/* sdmmc register */
941 +#define SDC_CFG REG_ADDR(SDC_CFG)
942 +#define SDC_CMD REG_ADDR(SDC_CMD)
943 +#define SDC_ARG REG_ADDR(SDC_ARG)
944 +#define SDC_STS REG_ADDR(SDC_STS)
945 +#define SDC_RESP0 REG_ADDR(SDC_RESP0)
946 +#define SDC_RESP1 REG_ADDR(SDC_RESP1)
947 +#define SDC_RESP2 REG_ADDR(SDC_RESP2)
948 +#define SDC_RESP3 REG_ADDR(SDC_RESP3)
949 +#define SDC_BLK_NUM REG_ADDR(SDC_BLK_NUM)
950 +#define SDC_CSTS REG_ADDR(SDC_CSTS)
951 +#define SDC_CSTS_EN REG_ADDR(SDC_CSTS_EN)
952 +#define SDC_DCRC_STS REG_ADDR(SDC_DCRC_STS)
953 +
954 +/* emmc register*/
955 +#define EMMC_CFG0 REG_ADDR(EMMC_CFG0)
956 +#define EMMC_CFG1 REG_ADDR(EMMC_CFG1)
957 +#define EMMC_STS REG_ADDR(EMMC_STS)
958 +#define EMMC_IOCON REG_ADDR(EMMC_IOCON)
959 +
960 +/* auto command register */
961 +#define SDC_ACMD_RESP REG_ADDR(SDC_ACMD_RESP)
962 +#define SDC_ACMD19_TRG REG_ADDR(SDC_ACMD19_TRG)
963 +#define SDC_ACMD19_STS REG_ADDR(SDC_ACMD19_STS)
964 +
965 +/* dma register */
966 +#define MSDC_DMA_SA REG_ADDR(MSDC_DMA_SA)
967 +#define MSDC_DMA_CA REG_ADDR(MSDC_DMA_CA)
968 +#define MSDC_DMA_CTRL REG_ADDR(MSDC_DMA_CTRL)
969 +#define MSDC_DMA_CFG REG_ADDR(MSDC_DMA_CFG)
970 +
971 +/* pad ctrl register */
972 +#define MSDC_PAD_CTL0 REG_ADDR(MSDC_PAD_CTL0)
973 +#define MSDC_PAD_CTL1 REG_ADDR(MSDC_PAD_CTL1)
974 +#define MSDC_PAD_CTL2 REG_ADDR(MSDC_PAD_CTL2)
975 +
976 +/* data read delay */
977 +#define MSDC_DAT_RDDLY0 REG_ADDR(MSDC_DAT_RDDLY0)
978 +#define MSDC_DAT_RDDLY1 REG_ADDR(MSDC_DAT_RDDLY1)
979 +
980 +/* debug register */
981 +#define MSDC_DBG_SEL REG_ADDR(MSDC_DBG_SEL)
982 +#define MSDC_DBG_OUT REG_ADDR(MSDC_DBG_OUT)
983 +
984 +/* misc register */
985 +#define MSDC_PATCH_BIT REG_ADDR(MSDC_PATCH_BIT)
986 +#define MSDC_PATCH_BIT1 REG_ADDR(MSDC_PATCH_BIT1)
987 +#define MSDC_PAD_TUNE REG_ADDR(MSDC_PAD_TUNE)
988 +#define MSDC_HW_DBG REG_ADDR(MSDC_HW_DBG)
989 +#define MSDC_VERSION REG_ADDR(MSDC_VERSION)
990 +#define MSDC_ECO_VER REG_ADDR(MSDC_ECO_VER) /* ECO Version */
991 +
992 +/*--------------------------------------------------------------------------*/
993 +/* Register Mask */
994 +/*--------------------------------------------------------------------------*/
995 +
996 +/* MSDC_CFG mask */
997 +#define MSDC_CFG_MODE (0x1 << 0) /* RW */
998 +#define MSDC_CFG_CKPDN (0x1 << 1) /* RW */
999 +#define MSDC_CFG_RST (0x1 << 2) /* RW */
1000 +#define MSDC_CFG_PIO (0x1 << 3) /* RW */
1001 +#define MSDC_CFG_CKDRVEN (0x1 << 4) /* RW */
1002 +#define MSDC_CFG_BV18SDT (0x1 << 5) /* RW */
1003 +#define MSDC_CFG_BV18PSS (0x1 << 6) /* R */
1004 +#define MSDC_CFG_CKSTB (0x1 << 7) /* R */
1005 +#define MSDC_CFG_CKDIV (0xff << 8) /* RW */
1006 +#define MSDC_CFG_CKMOD (0x3 << 16) /* RW */
1007 +
1008 +/* MSDC_IOCON mask */
1009 +#define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */
1010 +#define MSDC_IOCON_RSPL (0x1 << 1) /* RW */
1011 +#define MSDC_IOCON_DSPL (0x1 << 2) /* RW */
1012 +#define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */
1013 +#define MSDC_IOCON_DDR50CKD (0x1 << 4) /* RW */
1014 +#define MSDC_IOCON_DSPLSEL (0x1 << 5) /* RW */
1015 +#define MSDC_IOCON_D0SPL (0x1 << 16) /* RW */
1016 +#define MSDC_IOCON_D1SPL (0x1 << 17) /* RW */
1017 +#define MSDC_IOCON_D2SPL (0x1 << 18) /* RW */
1018 +#define MSDC_IOCON_D3SPL (0x1 << 19) /* RW */
1019 +#define MSDC_IOCON_D4SPL (0x1 << 20) /* RW */
1020 +#define MSDC_IOCON_D5SPL (0x1 << 21) /* RW */
1021 +#define MSDC_IOCON_D6SPL (0x1 << 22) /* RW */
1022 +#define MSDC_IOCON_D7SPL (0x1 << 23) /* RW */
1023 +#define MSDC_IOCON_RISCSZ (0x3 << 24) /* RW */
1024 +
1025 +/* MSDC_PS mask */
1026 +#define MSDC_PS_CDEN (0x1 << 0) /* RW */
1027 +#define MSDC_PS_CDSTS (0x1 << 1) /* R */
1028 +#define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */
1029 +#define MSDC_PS_DAT (0xff << 16) /* R */
1030 +#define MSDC_PS_CMD (0x1 << 24) /* R */
1031 +#define MSDC_PS_WP (0x1UL<< 31) /* R */
1032 +
1033 +/* MSDC_INT mask */
1034 +#define MSDC_INT_MMCIRQ (0x1 << 0) /* W1C */
1035 +#define MSDC_INT_CDSC (0x1 << 1) /* W1C */
1036 +#define MSDC_INT_ACMDRDY (0x1 << 3) /* W1C */
1037 +#define MSDC_INT_ACMDTMO (0x1 << 4) /* W1C */
1038 +#define MSDC_INT_ACMDCRCERR (0x1 << 5) /* W1C */
1039 +#define MSDC_INT_DMAQ_EMPTY (0x1 << 6) /* W1C */
1040 +#define MSDC_INT_SDIOIRQ (0x1 << 7) /* W1C */
1041 +#define MSDC_INT_CMDRDY (0x1 << 8) /* W1C */
1042 +#define MSDC_INT_CMDTMO (0x1 << 9) /* W1C */
1043 +#define MSDC_INT_RSPCRCERR (0x1 << 10) /* W1C */
1044 +#define MSDC_INT_CSTA (0x1 << 11) /* R */
1045 +#define MSDC_INT_XFER_COMPL (0x1 << 12) /* W1C */
1046 +#define MSDC_INT_DXFER_DONE (0x1 << 13) /* W1C */
1047 +#define MSDC_INT_DATTMO (0x1 << 14) /* W1C */
1048 +#define MSDC_INT_DATCRCERR (0x1 << 15) /* W1C */
1049 +#define MSDC_INT_ACMD19_DONE (0x1 << 16) /* W1C */
1050 +
1051 +/* MSDC_INTEN mask */
1052 +#define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */
1053 +#define MSDC_INTEN_CDSC (0x1 << 1) /* RW */
1054 +#define MSDC_INTEN_ACMDRDY (0x1 << 3) /* RW */
1055 +#define MSDC_INTEN_ACMDTMO (0x1 << 4) /* RW */
1056 +#define MSDC_INTEN_ACMDCRCERR (0x1 << 5) /* RW */
1057 +#define MSDC_INTEN_DMAQ_EMPTY (0x1 << 6) /* RW */
1058 +#define MSDC_INTEN_SDIOIRQ (0x1 << 7) /* RW */
1059 +#define MSDC_INTEN_CMDRDY (0x1 << 8) /* RW */
1060 +#define MSDC_INTEN_CMDTMO (0x1 << 9) /* RW */
1061 +#define MSDC_INTEN_RSPCRCERR (0x1 << 10) /* RW */
1062 +#define MSDC_INTEN_CSTA (0x1 << 11) /* RW */
1063 +#define MSDC_INTEN_XFER_COMPL (0x1 << 12) /* RW */
1064 +#define MSDC_INTEN_DXFER_DONE (0x1 << 13) /* RW */
1065 +#define MSDC_INTEN_DATTMO (0x1 << 14) /* RW */
1066 +#define MSDC_INTEN_DATCRCERR (0x1 << 15) /* RW */
1067 +#define MSDC_INTEN_ACMD19_DONE (0x1 << 16) /* RW */
1068 +
1069 +/* MSDC_FIFOCS mask */
1070 +#define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */
1071 +#define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */
1072 +#define MSDC_FIFOCS_CLR (0x1UL<< 31) /* RW */
1073 +
1074 +/* SDC_CFG mask */
1075 +#define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */
1076 +#define SDC_CFG_INSWKUP (0x1 << 1) /* RW */
1077 +#define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */
1078 +#define SDC_CFG_SDIO (0x1 << 19) /* RW */
1079 +#define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */
1080 +#define SDC_CFG_INTATGAP (0x1 << 21) /* RW */
1081 +#define SDC_CFG_DTOC (0xffUL << 24) /* RW */
1082 +
1083 +/* SDC_CMD mask */
1084 +#define SDC_CMD_OPC (0x3f << 0) /* RW */
1085 +#define SDC_CMD_BRK (0x1 << 6) /* RW */
1086 +#define SDC_CMD_RSPTYP (0x7 << 7) /* RW */
1087 +#define SDC_CMD_DTYP (0x3 << 11) /* RW */
1088 +#define SDC_CMD_DTYP (0x3 << 11) /* RW */
1089 +#define SDC_CMD_RW (0x1 << 13) /* RW */
1090 +#define SDC_CMD_STOP (0x1 << 14) /* RW */
1091 +#define SDC_CMD_GOIRQ (0x1 << 15) /* RW */
1092 +#define SDC_CMD_BLKLEN (0xfff<< 16) /* RW */
1093 +#define SDC_CMD_AUTOCMD (0x3 << 28) /* RW */
1094 +#define SDC_CMD_VOLSWTH (0x1 << 30) /* RW */
1095 +
1096 +/* SDC_STS mask */
1097 +#define SDC_STS_SDCBUSY (0x1 << 0) /* RW */
1098 +#define SDC_STS_CMDBUSY (0x1 << 1) /* RW */
1099 +#define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */
1100 +
1101 +/* SDC_DCRC_STS mask */
1102 +#define SDC_DCRC_STS_NEG (0xf << 8) /* RO */
1103 +#define SDC_DCRC_STS_POS (0xff << 0) /* RO */
1104 +
1105 +/* EMMC_CFG0 mask */
1106 +#define EMMC_CFG0_BOOTSTART (0x1 << 0) /* W */
1107 +#define EMMC_CFG0_BOOTSTOP (0x1 << 1) /* W */
1108 +#define EMMC_CFG0_BOOTMODE (0x1 << 2) /* RW */
1109 +#define EMMC_CFG0_BOOTACKDIS (0x1 << 3) /* RW */
1110 +#define EMMC_CFG0_BOOTWDLY (0x7 << 12) /* RW */
1111 +#define EMMC_CFG0_BOOTSUPP (0x1 << 15) /* RW */
1112 +
1113 +/* EMMC_CFG1 mask */
1114 +#define EMMC_CFG1_BOOTDATTMC (0xfffff << 0) /* RW */
1115 +#define EMMC_CFG1_BOOTACKTMC (0xfffUL << 20) /* RW */
1116 +
1117 +/* EMMC_STS mask */
1118 +#define EMMC_STS_BOOTCRCERR (0x1 << 0) /* W1C */
1119 +#define EMMC_STS_BOOTACKERR (0x1 << 1) /* W1C */
1120 +#define EMMC_STS_BOOTDATTMO (0x1 << 2) /* W1C */
1121 +#define EMMC_STS_BOOTACKTMO (0x1 << 3) /* W1C */
1122 +#define EMMC_STS_BOOTUPSTATE (0x1 << 4) /* R */
1123 +#define EMMC_STS_BOOTACKRCV (0x1 << 5) /* W1C */
1124 +#define EMMC_STS_BOOTDATRCV (0x1 << 6) /* R */
1125 +
1126 +/* EMMC_IOCON mask */
1127 +#define EMMC_IOCON_BOOTRST (0x1 << 0) /* RW */
1128 +
1129 +/* SDC_ACMD19_TRG mask */
1130 +#define SDC_ACMD19_TRG_TUNESEL (0xf << 0) /* RW */
1131 +
1132 +/* MSDC_DMA_CTRL mask */
1133 +#define MSDC_DMA_CTRL_START (0x1 << 0) /* W */
1134 +#define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */
1135 +#define MSDC_DMA_CTRL_RESUME (0x1 << 2) /* W */
1136 +#define MSDC_DMA_CTRL_MODE (0x1 << 8) /* RW */
1137 +#define MSDC_DMA_CTRL_LASTBUF (0x1 << 10) /* RW */
1138 +#define MSDC_DMA_CTRL_BRUSTSZ (0x7 << 12) /* RW */
1139 +#define MSDC_DMA_CTRL_XFERSZ (0xffffUL << 16)/* RW */
1140 +
1141 +/* MSDC_DMA_CFG mask */
1142 +#define MSDC_DMA_CFG_STS (0x1 << 0) /* R */
1143 +#define MSDC_DMA_CFG_DECSEN (0x1 << 1) /* RW */
1144 +#define MSDC_DMA_CFG_BDCSERR (0x1 << 4) /* R */
1145 +#define MSDC_DMA_CFG_GPDCSERR (0x1 << 5) /* R */
1146 +
1147 +/* MSDC_PATCH_BIT mask */
1148 +#define MSDC_PATCH_BIT_WFLSMODE (0x1 << 0) /* RW */
1149 +#define MSDC_PATCH_BIT_ODDSUPP (0x1 << 1) /* RW */
1150 +#define MSDC_PATCH_BIT_CKGEN_CK (0x1 << 6) /* E2: Fixed to 1 */
1151 +#define MSDC_PATCH_BIT_IODSSEL (0x1 << 16) /* RW */
1152 +#define MSDC_PATCH_BIT_IOINTSEL (0x1 << 17) /* RW */
1153 +#define MSDC_PATCH_BIT_BUSYDLY (0xf << 18) /* RW */
1154 +#define MSDC_PATCH_BIT_WDOD (0xf << 22) /* RW */
1155 +#define MSDC_PATCH_BIT_IDRTSEL (0x1 << 26) /* RW */
1156 +#define MSDC_PATCH_BIT_CMDFSEL (0x1 << 27) /* RW */
1157 +#define MSDC_PATCH_BIT_INTDLSEL (0x1 << 28) /* RW */
1158 +#define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */
1159 +#define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */
1160 +
1161 +/* MSDC_PATCH_BIT1 mask */
1162 +#define MSDC_PATCH_BIT1_WRDAT_CRCS (0x7 << 3)
1163 +#define MSDC_PATCH_BIT1_CMD_RSP (0x7 << 0)
1164 +
1165 +/* MSDC_PAD_CTL0 mask */
1166 +#define MSDC_PAD_CTL0_CLKDRVN (0x7 << 0) /* RW */
1167 +#define MSDC_PAD_CTL0_CLKDRVP (0x7 << 4) /* RW */
1168 +#define MSDC_PAD_CTL0_CLKSR (0x1 << 8) /* RW */
1169 +#define MSDC_PAD_CTL0_CLKPD (0x1 << 16) /* RW */
1170 +#define MSDC_PAD_CTL0_CLKPU (0x1 << 17) /* RW */
1171 +#define MSDC_PAD_CTL0_CLKSMT (0x1 << 18) /* RW */
1172 +#define MSDC_PAD_CTL0_CLKIES (0x1 << 19) /* RW */
1173 +#define MSDC_PAD_CTL0_CLKTDSEL (0xf << 20) /* RW */
1174 +#define MSDC_PAD_CTL0_CLKRDSEL (0xffUL<< 24) /* RW */
1175 +
1176 +/* MSDC_PAD_CTL1 mask */
1177 +#define MSDC_PAD_CTL1_CMDDRVN (0x7 << 0) /* RW */
1178 +#define MSDC_PAD_CTL1_CMDDRVP (0x7 << 4) /* RW */
1179 +#define MSDC_PAD_CTL1_CMDSR (0x1 << 8) /* RW */
1180 +#define MSDC_PAD_CTL1_CMDPD (0x1 << 16) /* RW */
1181 +#define MSDC_PAD_CTL1_CMDPU (0x1 << 17) /* RW */
1182 +#define MSDC_PAD_CTL1_CMDSMT (0x1 << 18) /* RW */
1183 +#define MSDC_PAD_CTL1_CMDIES (0x1 << 19) /* RW */
1184 +#define MSDC_PAD_CTL1_CMDTDSEL (0xf << 20) /* RW */
1185 +#define MSDC_PAD_CTL1_CMDRDSEL (0xffUL<< 24) /* RW */
1186 +
1187 +/* MSDC_PAD_CTL2 mask */
1188 +#define MSDC_PAD_CTL2_DATDRVN (0x7 << 0) /* RW */
1189 +#define MSDC_PAD_CTL2_DATDRVP (0x7 << 4) /* RW */
1190 +#define MSDC_PAD_CTL2_DATSR (0x1 << 8) /* RW */
1191 +#define MSDC_PAD_CTL2_DATPD (0x1 << 16) /* RW */
1192 +#define MSDC_PAD_CTL2_DATPU (0x1 << 17) /* RW */
1193 +#define MSDC_PAD_CTL2_DATIES (0x1 << 19) /* RW */
1194 +#define MSDC_PAD_CTL2_DATSMT (0x1 << 18) /* RW */
1195 +#define MSDC_PAD_CTL2_DATTDSEL (0xf << 20) /* RW */
1196 +#define MSDC_PAD_CTL2_DATRDSEL (0xffUL<< 24) /* RW */
1197 +
1198 +/* MSDC_PAD_TUNE mask */
1199 +#define MSDC_PAD_TUNE_DATWRDLY (0x1F << 0) /* RW */
1200 +#define MSDC_PAD_TUNE_DATRRDLY (0x1F << 8) /* RW */
1201 +#define MSDC_PAD_TUNE_CMDRDLY (0x1F << 16) /* RW */
1202 +#define MSDC_PAD_TUNE_CMDRRDLY (0x1FUL << 22) /* RW */
1203 +#define MSDC_PAD_TUNE_CLKTXDLY (0x1FUL << 27) /* RW */
1204 +
1205 +/* MSDC_DAT_RDDLY0/1 mask */
1206 +#define MSDC_DAT_RDDLY0_D0 (0x1F << 0) /* RW */
1207 +#define MSDC_DAT_RDDLY0_D1 (0x1F << 8) /* RW */
1208 +#define MSDC_DAT_RDDLY0_D2 (0x1F << 16) /* RW */
1209 +#define MSDC_DAT_RDDLY0_D3 (0x1F << 24) /* RW */
1210 +
1211 +#define MSDC_DAT_RDDLY1_D4 (0x1F << 0) /* RW */
1212 +#define MSDC_DAT_RDDLY1_D5 (0x1F << 8) /* RW */
1213 +#define MSDC_DAT_RDDLY1_D6 (0x1F << 16) /* RW */
1214 +#define MSDC_DAT_RDDLY1_D7 (0x1F << 24) /* RW */
1215 +
1216 +#define MSDC_CKGEN_MSDC_DLY_SEL (0x1F<<10)
1217 +#define MSDC_INT_DAT_LATCH_CK_SEL (0x7<<7)
1218 +#define MSDC_CKGEN_MSDC_CK_SEL (0x1<<6)
1219 +#define CARD_READY_FOR_DATA (1<<8)
1220 +#define CARD_CURRENT_STATE(x) ((x&0x00001E00)>>9)
1221 +
1222 +/*--------------------------------------------------------------------------*/
1223 +/* Descriptor Structure */
1224 +/*--------------------------------------------------------------------------*/
1225 +typedef struct {
1226 + u32 hwo:1; /* could be changed by hw */
1227 + u32 bdp:1;
1228 + u32 rsv0:6;
1229 + u32 chksum:8;
1230 + u32 intr:1;
1231 + u32 rsv1:15;
1232 + void *next;
1233 + void *ptr;
1234 + u32 buflen:16;
1235 + u32 extlen:8;
1236 + u32 rsv2:8;
1237 + u32 arg;
1238 + u32 blknum;
1239 + u32 cmd;
1240 +} gpd_t;
1241 +
1242 +typedef struct {
1243 + u32 eol:1;
1244 + u32 rsv0:7;
1245 + u32 chksum:8;
1246 + u32 rsv1:1;
1247 + u32 blkpad:1;
1248 + u32 dwpad:1;
1249 + u32 rsv2:13;
1250 + void *next;
1251 + void *ptr;
1252 + u32 buflen:16;
1253 + u32 rsv3:16;
1254 +} bd_t;
1255 +
1256 +/*--------------------------------------------------------------------------*/
1257 +/* Register Debugging Structure */
1258 +/*--------------------------------------------------------------------------*/
1259 +
1260 +typedef struct {
1261 + u32 msdc:1;
1262 + u32 ckpwn:1;
1263 + u32 rst:1;
1264 + u32 pio:1;
1265 + u32 ckdrven:1;
1266 + u32 start18v:1;
1267 + u32 pass18v:1;
1268 + u32 ckstb:1;
1269 + u32 ckdiv:8;
1270 + u32 ckmod:2;
1271 + u32 pad:14;
1272 +} msdc_cfg_reg;
1273 +typedef struct {
1274 + u32 sdr104cksel:1;
1275 + u32 rsmpl:1;
1276 + u32 dsmpl:1;
1277 + u32 ddlysel:1;
1278 + u32 ddr50ckd:1;
1279 + u32 dsplsel:1;
1280 + u32 pad1:10;
1281 + u32 d0spl:1;
1282 + u32 d1spl:1;
1283 + u32 d2spl:1;
1284 + u32 d3spl:1;
1285 + u32 d4spl:1;
1286 + u32 d5spl:1;
1287 + u32 d6spl:1;
1288 + u32 d7spl:1;
1289 + u32 riscsz:1;
1290 + u32 pad2:7;
1291 +} msdc_iocon_reg;
1292 +typedef struct {
1293 + u32 cden:1;
1294 + u32 cdsts:1;
1295 + u32 pad1:10;
1296 + u32 cddebounce:4;
1297 + u32 dat:8;
1298 + u32 cmd:1;
1299 + u32 pad2:6;
1300 + u32 wp:1;
1301 +} msdc_ps_reg;
1302 +typedef struct {
1303 + u32 mmcirq:1;
1304 + u32 cdsc:1;
1305 + u32 pad1:1;
1306 + u32 atocmdrdy:1;
1307 + u32 atocmdtmo:1;
1308 + u32 atocmdcrc:1;
1309 + u32 dmaqempty:1;
1310 + u32 sdioirq:1;
1311 + u32 cmdrdy:1;
1312 + u32 cmdtmo:1;
1313 + u32 rspcrc:1;
1314 + u32 csta:1;
1315 + u32 xfercomp:1;
1316 + u32 dxferdone:1;
1317 + u32 dattmo:1;
1318 + u32 datcrc:1;
1319 + u32 atocmd19done:1;
1320 + u32 pad2:15;
1321 +} msdc_int_reg;
1322 +typedef struct {
1323 + u32 mmcirq:1;
1324 + u32 cdsc:1;
1325 + u32 pad1:1;
1326 + u32 atocmdrdy:1;
1327 + u32 atocmdtmo:1;
1328 + u32 atocmdcrc:1;
1329 + u32 dmaqempty:1;
1330 + u32 sdioirq:1;
1331 + u32 cmdrdy:1;
1332 + u32 cmdtmo:1;
1333 + u32 rspcrc:1;
1334 + u32 csta:1;
1335 + u32 xfercomp:1;
1336 + u32 dxferdone:1;
1337 + u32 dattmo:1;
1338 + u32 datcrc:1;
1339 + u32 atocmd19done:1;
1340 + u32 pad2:15;
1341 +} msdc_inten_reg;
1342 +typedef struct {
1343 + u32 rxcnt:8;
1344 + u32 pad1:8;
1345 + u32 txcnt:8;
1346 + u32 pad2:7;
1347 + u32 clr:1;
1348 +} msdc_fifocs_reg;
1349 +typedef struct {
1350 + u32 val;
1351 +} msdc_txdat_reg;
1352 +typedef struct {
1353 + u32 val;
1354 +} msdc_rxdat_reg;
1355 +typedef struct {
1356 + u32 sdiowkup:1;
1357 + u32 inswkup:1;
1358 + u32 pad1:14;
1359 + u32 buswidth:2;
1360 + u32 pad2:1;
1361 + u32 sdio:1;
1362 + u32 sdioide:1;
1363 + u32 intblkgap:1;
1364 + u32 pad4:2;
1365 + u32 dtoc:8;
1366 +} sdc_cfg_reg;
1367 +typedef struct {
1368 + u32 cmd:6;
1369 + u32 brk:1;
1370 + u32 rsptyp:3;
1371 + u32 pad1:1;
1372 + u32 dtype:2;
1373 + u32 rw:1;
1374 + u32 stop:1;
1375 + u32 goirq:1;
1376 + u32 blklen:12;
1377 + u32 atocmd:2;
1378 + u32 volswth:1;
1379 + u32 pad2:1;
1380 +} sdc_cmd_reg;
1381 +typedef struct {
1382 + u32 arg;
1383 +} sdc_arg_reg;
1384 +typedef struct {
1385 + u32 sdcbusy:1;
1386 + u32 cmdbusy:1;
1387 + u32 pad:29;
1388 + u32 swrcmpl:1;
1389 +} sdc_sts_reg;
1390 +typedef struct {
1391 + u32 val;
1392 +} sdc_resp0_reg;
1393 +typedef struct {
1394 + u32 val;
1395 +} sdc_resp1_reg;
1396 +typedef struct {
1397 + u32 val;
1398 +} sdc_resp2_reg;
1399 +typedef struct {
1400 + u32 val;
1401 +} sdc_resp3_reg;
1402 +typedef struct {
1403 + u32 num;
1404 +} sdc_blknum_reg;
1405 +typedef struct {
1406 + u32 sts;
1407 +} sdc_csts_reg;
1408 +typedef struct {
1409 + u32 sts;
1410 +} sdc_cstsen_reg;
1411 +typedef struct {
1412 + u32 datcrcsts:8;
1413 + u32 ddrcrcsts:4;
1414 + u32 pad:20;
1415 +} sdc_datcrcsts_reg;
1416 +typedef struct {
1417 + u32 bootstart:1;
1418 + u32 bootstop:1;
1419 + u32 bootmode:1;
1420 + u32 pad1:9;
1421 + u32 bootwaidly:3;
1422 + u32 bootsupp:1;
1423 + u32 pad2:16;
1424 +} emmc_cfg0_reg;
1425 +typedef struct {
1426 + u32 bootcrctmc:16;
1427 + u32 pad:4;
1428 + u32 bootacktmc:12;
1429 +} emmc_cfg1_reg;
1430 +typedef struct {
1431 + u32 bootcrcerr:1;
1432 + u32 bootackerr:1;
1433 + u32 bootdattmo:1;
1434 + u32 bootacktmo:1;
1435 + u32 bootupstate:1;
1436 + u32 bootackrcv:1;
1437 + u32 bootdatrcv:1;
1438 + u32 pad:25;
1439 +} emmc_sts_reg;
1440 +typedef struct {
1441 + u32 bootrst:1;
1442 + u32 pad:31;
1443 +} emmc_iocon_reg;
1444 +typedef struct {
1445 + u32 val;
1446 +} msdc_acmd_resp_reg;
1447 +typedef struct {
1448 + u32 tunesel:4;
1449 + u32 pad:28;
1450 +} msdc_acmd19_trg_reg;
1451 +typedef struct {
1452 + u32 val;
1453 +} msdc_acmd19_sts_reg;
1454 +typedef struct {
1455 + u32 addr;
1456 +} msdc_dma_sa_reg;
1457 +typedef struct {
1458 + u32 addr;
1459 +} msdc_dma_ca_reg;
1460 +typedef struct {
1461 + u32 start:1;
1462 + u32 stop:1;
1463 + u32 resume:1;
1464 + u32 pad1:5;
1465 + u32 mode:1;
1466 + u32 pad2:1;
1467 + u32 lastbuf:1;
1468 + u32 pad3:1;
1469 + u32 brustsz:3;
1470 + u32 pad4:1;
1471 + u32 xfersz:16;
1472 +} msdc_dma_ctrl_reg;
1473 +typedef struct {
1474 + u32 status:1;
1475 + u32 decsen:1;
1476 + u32 pad1:2;
1477 + u32 bdcsen:1;
1478 + u32 gpdcsen:1;
1479 + u32 pad2:26;
1480 +} msdc_dma_cfg_reg;
1481 +typedef struct {
1482 + u32 sel:16;
1483 + u32 pad2:16;
1484 +} msdc_dbg_sel_reg;
1485 +typedef struct {
1486 + u32 val;
1487 +} msdc_dbg_out_reg;
1488 +typedef struct {
1489 + u32 clkdrvn:3;
1490 + u32 rsv0:1;
1491 + u32 clkdrvp:3;
1492 + u32 rsv1:1;
1493 + u32 clksr:1;
1494 + u32 rsv2:7;
1495 + u32 clkpd:1;
1496 + u32 clkpu:1;
1497 + u32 clksmt:1;
1498 + u32 clkies:1;
1499 + u32 clktdsel:4;
1500 + u32 clkrdsel:8;
1501 +} msdc_pad_ctl0_reg;
1502 +typedef struct {
1503 + u32 cmddrvn:3;
1504 + u32 rsv0:1;
1505 + u32 cmddrvp:3;
1506 + u32 rsv1:1;
1507 + u32 cmdsr:1;
1508 + u32 rsv2:7;
1509 + u32 cmdpd:1;
1510 + u32 cmdpu:1;
1511 + u32 cmdsmt:1;
1512 + u32 cmdies:1;
1513 + u32 cmdtdsel:4;
1514 + u32 cmdrdsel:8;
1515 +} msdc_pad_ctl1_reg;
1516 +typedef struct {
1517 + u32 datdrvn:3;
1518 + u32 rsv0:1;
1519 + u32 datdrvp:3;
1520 + u32 rsv1:1;
1521 + u32 datsr:1;
1522 + u32 rsv2:7;
1523 + u32 datpd:1;
1524 + u32 datpu:1;
1525 + u32 datsmt:1;
1526 + u32 daties:1;
1527 + u32 dattdsel:4;
1528 + u32 datrdsel:8;
1529 +} msdc_pad_ctl2_reg;
1530 +typedef struct {
1531 + u32 wrrxdly:3;
1532 + u32 pad1:5;
1533 + u32 rdrxdly:8;
1534 + u32 pad2:16;
1535 +} msdc_pad_tune_reg;
1536 +typedef struct {
1537 + u32 dat0:5;
1538 + u32 rsv0:3;
1539 + u32 dat1:5;
1540 + u32 rsv1:3;
1541 + u32 dat2:5;
1542 + u32 rsv2:3;
1543 + u32 dat3:5;
1544 + u32 rsv3:3;
1545 +} msdc_dat_rddly0;
1546 +typedef struct {
1547 + u32 dat4:5;
1548 + u32 rsv4:3;
1549 + u32 dat5:5;
1550 + u32 rsv5:3;
1551 + u32 dat6:5;
1552 + u32 rsv6:3;
1553 + u32 dat7:5;
1554 + u32 rsv7:3;
1555 +} msdc_dat_rddly1;
1556 +typedef struct {
1557 + u32 dbg0sel:8;
1558 + u32 dbg1sel:6;
1559 + u32 pad1:2;
1560 + u32 dbg2sel:6;
1561 + u32 pad2:2;
1562 + u32 dbg3sel:6;
1563 + u32 pad3:2;
1564 +} msdc_hw_dbg_reg;
1565 +typedef struct {
1566 + u32 val;
1567 +} msdc_version_reg;
1568 +typedef struct {
1569 + u32 val;
1570 +} msdc_eco_ver_reg;
1571 +
1572 +struct msdc_regs {
1573 + msdc_cfg_reg msdc_cfg; /* base+0x00h */
1574 + msdc_iocon_reg msdc_iocon; /* base+0x04h */
1575 + msdc_ps_reg msdc_ps; /* base+0x08h */
1576 + msdc_int_reg msdc_int; /* base+0x0ch */
1577 + msdc_inten_reg msdc_inten; /* base+0x10h */
1578 + msdc_fifocs_reg msdc_fifocs; /* base+0x14h */
1579 + msdc_txdat_reg msdc_txdat; /* base+0x18h */
1580 + msdc_rxdat_reg msdc_rxdat; /* base+0x1ch */
1581 + u32 rsv1[4];
1582 + sdc_cfg_reg sdc_cfg; /* base+0x30h */
1583 + sdc_cmd_reg sdc_cmd; /* base+0x34h */
1584 + sdc_arg_reg sdc_arg; /* base+0x38h */
1585 + sdc_sts_reg sdc_sts; /* base+0x3ch */
1586 + sdc_resp0_reg sdc_resp0; /* base+0x40h */
1587 + sdc_resp1_reg sdc_resp1; /* base+0x44h */
1588 + sdc_resp2_reg sdc_resp2; /* base+0x48h */
1589 + sdc_resp3_reg sdc_resp3; /* base+0x4ch */
1590 + sdc_blknum_reg sdc_blknum; /* base+0x50h */
1591 + u32 rsv2[1];
1592 + sdc_csts_reg sdc_csts; /* base+0x58h */
1593 + sdc_cstsen_reg sdc_cstsen; /* base+0x5ch */
1594 + sdc_datcrcsts_reg sdc_dcrcsta; /* base+0x60h */
1595 + u32 rsv3[3];
1596 + emmc_cfg0_reg emmc_cfg0; /* base+0x70h */
1597 + emmc_cfg1_reg emmc_cfg1; /* base+0x74h */
1598 + emmc_sts_reg emmc_sts; /* base+0x78h */
1599 + emmc_iocon_reg emmc_iocon; /* base+0x7ch */
1600 + msdc_acmd_resp_reg acmd_resp; /* base+0x80h */
1601 + msdc_acmd19_trg_reg acmd19_trg; /* base+0x84h */
1602 + msdc_acmd19_sts_reg acmd19_sts; /* base+0x88h */
1603 + u32 rsv4[1];
1604 + msdc_dma_sa_reg dma_sa; /* base+0x90h */
1605 + msdc_dma_ca_reg dma_ca; /* base+0x94h */
1606 + msdc_dma_ctrl_reg dma_ctrl; /* base+0x98h */
1607 + msdc_dma_cfg_reg dma_cfg; /* base+0x9ch */
1608 + msdc_dbg_sel_reg dbg_sel; /* base+0xa0h */
1609 + msdc_dbg_out_reg dbg_out; /* base+0xa4h */
1610 + u32 rsv5[2];
1611 + u32 patch0; /* base+0xb0h */
1612 + u32 patch1; /* base+0xb4h */
1613 + u32 rsv6[10];
1614 + msdc_pad_ctl0_reg pad_ctl0; /* base+0xe0h */
1615 + msdc_pad_ctl1_reg pad_ctl1; /* base+0xe4h */
1616 + msdc_pad_ctl2_reg pad_ctl2; /* base+0xe8h */
1617 + msdc_pad_tune_reg pad_tune; /* base+0xech */
1618 + msdc_dat_rddly0 dat_rddly0; /* base+0xf0h */
1619 + msdc_dat_rddly1 dat_rddly1; /* base+0xf4h */
1620 + msdc_hw_dbg_reg hw_dbg; /* base+0xf8h */
1621 + u32 rsv7[1];
1622 + msdc_version_reg version; /* base+0x100h */
1623 + msdc_eco_ver_reg eco_ver; /* base+0x104h */
1624 +};
1625 +
1626 +struct scatterlist_ex {
1627 + u32 cmd;
1628 + u32 arg;
1629 + u32 sglen;
1630 + struct scatterlist *sg;
1631 +};
1632 +
1633 +#define DMA_FLAG_NONE (0x00000000)
1634 +#define DMA_FLAG_EN_CHKSUM (0x00000001)
1635 +#define DMA_FLAG_PAD_BLOCK (0x00000002)
1636 +#define DMA_FLAG_PAD_DWORD (0x00000004)
1637 +
1638 +struct msdc_dma {
1639 + u32 flags; /* flags */
1640 + u32 xfersz; /* xfer size in bytes */
1641 + u32 sglen; /* size of scatter list */
1642 + u32 blklen; /* block size */
1643 + struct scatterlist *sg; /* I/O scatter list */
1644 + struct scatterlist_ex *esg; /* extended I/O scatter list */
1645 + u8 mode; /* dma mode */
1646 + u8 burstsz; /* burst size */
1647 + u8 intr; /* dma done interrupt */
1648 + u8 padding; /* padding */
1649 + u32 cmd; /* enhanced mode command */
1650 + u32 arg; /* enhanced mode arg */
1651 + u32 rsp; /* enhanced mode command response */
1652 + u32 autorsp; /* auto command response */
1653 +
1654 + gpd_t *gpd; /* pointer to gpd array */
1655 + bd_t *bd; /* pointer to bd array */
1656 + dma_addr_t gpd_addr; /* the physical address of gpd array */
1657 + dma_addr_t bd_addr; /* the physical address of bd array */
1658 + u32 used_gpd; /* the number of used gpd elements */
1659 + u32 used_bd; /* the number of used bd elements */
1660 +};
1661 +
1662 +struct msdc_host
1663 +{
1664 + struct msdc_hw *hw;
1665 +
1666 + struct mmc_host *mmc; /* mmc structure */
1667 + struct mmc_command *cmd;
1668 + struct mmc_data *data;
1669 + struct mmc_request *mrq;
1670 + int cmd_rsp;
1671 + int cmd_rsp_done;
1672 + int cmd_r1b_done;
1673 +
1674 + int error;
1675 + spinlock_t lock; /* mutex */
1676 + struct semaphore sem;
1677 +
1678 + u32 blksz; /* host block size */
1679 + u32 base; /* host base address */
1680 + int id; /* host id */
1681 + int pwr_ref; /* core power reference count */
1682 +
1683 + u32 xfer_size; /* total transferred size */
1684 +
1685 + struct msdc_dma dma; /* dma channel */
1686 + u32 dma_addr; /* dma transfer address */
1687 + u32 dma_left_size; /* dma transfer left size */
1688 + u32 dma_xfer_size; /* dma transfer size in bytes */
1689 + int dma_xfer; /* dma transfer mode */
1690 +
1691 + u32 timeout_ns; /* data timeout ns */
1692 + u32 timeout_clks; /* data timeout clks */
1693 +
1694 + atomic_t abort; /* abort transfer */
1695 +
1696 + int irq; /* host interrupt */
1697 +
1698 + struct tasklet_struct card_tasklet;
1699 +#if 0
1700 + struct work_struct card_workqueue;
1701 +#else
1702 + struct delayed_work card_delaywork;
1703 +#endif
1704 +
1705 + struct completion cmd_done;
1706 + struct completion xfer_done;
1707 + struct pm_message pm_state;
1708 +
1709 + u32 mclk; /* mmc subsystem clock */
1710 + u32 hclk; /* host clock speed */
1711 + u32 sclk; /* SD/MS clock speed */
1712 + u8 core_clkon; /* Host core clock on ? */
1713 + u8 card_clkon; /* Card clock on ? */
1714 + u8 core_power; /* core power */
1715 + u8 power_mode; /* host power mode */
1716 + u8 card_inserted; /* card inserted ? */
1717 + u8 suspend; /* host suspended ? */
1718 + u8 reserved;
1719 + u8 app_cmd; /* for app command */
1720 + u32 app_cmd_arg;
1721 + u64 starttime;
1722 +};
1723 +
1724 +static inline unsigned int uffs(unsigned int x)
1725 +{
1726 + unsigned int r = 1;
1727 +
1728 + if (!x)
1729 + return 0;
1730 + if (!(x & 0xffff)) {
1731 + x >>= 16;
1732 + r += 16;
1733 + }
1734 + if (!(x & 0xff)) {
1735 + x >>= 8;
1736 + r += 8;
1737 + }
1738 + if (!(x & 0xf)) {
1739 + x >>= 4;
1740 + r += 4;
1741 + }
1742 + if (!(x & 3)) {
1743 + x >>= 2;
1744 + r += 2;
1745 + }
1746 + if (!(x & 1)) {
1747 + x >>= 1;
1748 + r += 1;
1749 + }
1750 + return r;
1751 +}
1752 +#define sdr_read8(reg) __raw_readb(reg)
1753 +#define sdr_read16(reg) __raw_readw(reg)
1754 +#define sdr_read32(reg) __raw_readl(reg)
1755 +#define sdr_write8(reg,val) __raw_writeb(val,reg)
1756 +#define sdr_write16(reg,val) __raw_writew(val,reg)
1757 +#define sdr_write32(reg,val) __raw_writel(val,reg)
1758 +
1759 +#define sdr_set_bits(reg,bs) ((*(volatile u32*)(reg)) |= (u32)(bs))
1760 +#define sdr_clr_bits(reg,bs) ((*(volatile u32*)(reg)) &= ~((u32)(bs)))
1761 +
1762 +#define sdr_set_field(reg,field,val) \
1763 + do { \
1764 + volatile unsigned int tv = sdr_read32(reg); \
1765 + tv &= ~(field); \
1766 + tv |= ((val) << (uffs((unsigned int)field) - 1)); \
1767 + sdr_write32(reg,tv); \
1768 + } while(0)
1769 +#define sdr_get_field(reg,field,val) \
1770 + do { \
1771 + volatile unsigned int tv = sdr_read32(reg); \
1772 + val = ((tv & (field)) >> (uffs((unsigned int)field) - 1)); \
1773 + } while(0)
1774 +
1775 +#endif
1776 +
1777 Index: linux-3.14.18/drivers/mmc/host/mtk-mmc/sd.c
1778 ===================================================================
1779 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
1780 +++ linux-3.14.18/drivers/mmc/host/mtk-mmc/sd.c 2014-11-15 14:41:50.334227875 +0100
1781 @@ -0,0 +1,3047 @@
1782 +/* Copyright Statement:
1783 + *
1784 + * This software/firmware and related documentation ("MediaTek Software") are
1785 + * protected under relevant copyright laws. The information contained herein
1786 + * is confidential and proprietary to MediaTek Inc. and/or its licensors.
1787 + * Without the prior written permission of MediaTek inc. and/or its licensors,
1788 + * any reproduction, modification, use or disclosure of MediaTek Software,
1789 + * and information contained herein, in whole or in part, shall be strictly prohibited.
1790 + *
1791 + * MediaTek Inc. (C) 2010. All rights reserved.
1792 + *
1793 + * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
1794 + * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
1795 + * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
1796 + * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
1797 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
1798 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
1799 + * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
1800 + * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
1801 + * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
1802 + * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
1803 + * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
1804 + * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
1805 + * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
1806 + * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
1807 + * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
1808 + * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
1809 + * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
1810 + * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
1811 + *
1812 + * The following software/firmware and/or related documentation ("MediaTek Software")
1813 + * have been modified by MediaTek Inc. All revisions are subject to any receiver's
1814 + * applicable license agreements with MediaTek Inc.
1815 + */
1816 +
1817 +#include <linux/module.h>
1818 +#include <linux/moduleparam.h>
1819 +#include <linux/init.h>
1820 +#include <linux/spinlock.h>
1821 +#include <linux/timer.h>
1822 +#include <linux/ioport.h>
1823 +#include <linux/device.h>
1824 +#include <linux/platform_device.h>
1825 +#include <linux/interrupt.h>
1826 +#include <linux/delay.h>
1827 +#include <linux/blkdev.h>
1828 +#include <linux/slab.h>
1829 +#include <linux/mmc/host.h>
1830 +#include <linux/mmc/card.h>
1831 +#include <linux/mmc/core.h>
1832 +#include <linux/mmc/mmc.h>
1833 +#include <linux/mmc/sd.h>
1834 +#include <linux/mmc/sdio.h>
1835 +#include <linux/dma-mapping.h>
1836 +
1837 +/* +++ by chhung */
1838 +#include <linux/types.h>
1839 +#include <linux/kernel.h>
1840 +#include <linux/version.h>
1841 +#include <linux/pm.h>
1842 +
1843 +#define MSDC_SMPL_FALLING (1)
1844 +#define MSDC_CD_PIN_EN (1 << 0) /* card detection pin is wired */
1845 +#define MSDC_WP_PIN_EN (1 << 1) /* write protection pin is wired */
1846 +#define MSDC_REMOVABLE (1 << 5) /* removable slot */
1847 +#define MSDC_SYS_SUSPEND (1 << 6) /* suspended by system */
1848 +#define MSDC_HIGHSPEED (1 << 7)
1849 +
1850 +//#define IRQ_SDC 14 //MT7620 /*FIXME*/
1851 +#ifdef CONFIG_SOC_MT7621
1852 +#define RALINK_SYSCTL_BASE 0xbe000000
1853 +#define RALINK_MSDC_BASE 0xbe130000
1854 +#else
1855 +#define RALINK_SYSCTL_BASE 0xb0000000
1856 +#define RALINK_MSDC_BASE 0xb0130000
1857 +#endif
1858 +#define IRQ_SDC 22 /*FIXME*/
1859 +
1860 +#include <asm/dma.h>
1861 +/* end of +++ */
1862 +
1863 +
1864 +#include <asm/mach-ralink/ralink_regs.h>
1865 +
1866 +#if 0 /* --- by chhung */
1867 +#include <mach/board.h>
1868 +#include <mach/mt6575_devs.h>
1869 +#include <mach/mt6575_typedefs.h>
1870 +#include <mach/mt6575_clock_manager.h>
1871 +#include <mach/mt6575_pm_ldo.h>
1872 +//#include <mach/mt6575_pll.h>
1873 +//#include <mach/mt6575_gpio.h>
1874 +//#include <mach/mt6575_gpt_sw.h>
1875 +#include <asm/tcm.h>
1876 +// #include <mach/mt6575_gpt.h>
1877 +#endif /* end of --- */
1878 +
1879 +#include "mt6575_sd.h"
1880 +#include "dbg.h"
1881 +
1882 +/* +++ by chhung */
1883 +#include "board.h"
1884 +/* end of +++ */
1885 +
1886 +#if 0 /* --- by chhung */
1887 +#define isb() __asm__ __volatile__ ("" : : : "memory")
1888 +#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
1889 + : : "r" (0) : "memory")
1890 +#define dmb() __asm__ __volatile__ ("" : : : "memory")
1891 +#endif /* end of --- */
1892 +
1893 +#define DRV_NAME "mtk-sd"
1894 +
1895 +#define HOST_MAX_NUM (1) /* +/- by chhung */
1896 +
1897 +#if defined (CONFIG_SOC_MT7620)
1898 +#define HOST_MAX_MCLK (48000000) /* +/- by chhung */
1899 +#elif defined (CONFIG_SOC_MT7621)
1900 +#define HOST_MAX_MCLK (50000000) /* +/- by chhung */
1901 +#endif
1902 +#define HOST_MIN_MCLK (260000)
1903 +
1904 +#define HOST_MAX_BLKSZ (2048)
1905 +
1906 +#define MSDC_OCR_AVAIL (MMC_VDD_28_29 | MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33)
1907 +
1908 +#define GPIO_PULL_DOWN (0)
1909 +#define GPIO_PULL_UP (1)
1910 +
1911 +#if 0 /* --- by chhung */
1912 +#define MSDC_CLKSRC_REG (0xf100000C)
1913 +#define PDN_REG (0xF1000010)
1914 +#endif /* end of --- */
1915 +
1916 +#define DEFAULT_DEBOUNCE (8) /* 8 cycles */
1917 +#define DEFAULT_DTOC (40) /* data timeout counter. 65536x40 sclk. */
1918 +
1919 +#define CMD_TIMEOUT (HZ/10) /* 100ms */
1920 +#define DAT_TIMEOUT (HZ/2 * 5) /* 500ms x5 */
1921 +
1922 +#define MAX_DMA_CNT (64 * 1024 - 512) /* a single transaction for WIFI may be 50K*/
1923 +
1924 +#define MAX_GPD_NUM (1 + 1) /* one null gpd */
1925 +#define MAX_BD_NUM (1024)
1926 +#define MAX_BD_PER_GPD (MAX_BD_NUM)
1927 +
1928 +#define MAX_HW_SGMTS (MAX_BD_NUM)
1929 +#define MAX_PHY_SGMTS (MAX_BD_NUM)
1930 +#define MAX_SGMT_SZ (MAX_DMA_CNT)
1931 +#define MAX_REQ_SZ (MAX_SGMT_SZ * 8)
1932 +
1933 +#ifdef MT6575_SD_DEBUG
1934 +static struct msdc_regs *msdc_reg[HOST_MAX_NUM];
1935 +#endif
1936 +
1937 +//=================================
1938 +#define PERI_MSDC0_PDN (15)
1939 +//#define PERI_MSDC1_PDN (16)
1940 +//#define PERI_MSDC2_PDN (17)
1941 +//#define PERI_MSDC3_PDN (18)
1942 +
1943 +struct msdc_host *msdc_6575_host[] = {NULL,NULL,NULL,NULL};
1944 +#if 0 /* --- by chhung */
1945 +/* gate means clock power down */
1946 +static int g_clk_gate = 0;
1947 +#define msdc_gate_clock(id) \
1948 + do { \
1949 + g_clk_gate &= ~(1 << ((id) + PERI_MSDC0_PDN)); \
1950 + } while(0)
1951 +/* not like power down register. 1 means clock on. */
1952 +#define msdc_ungate_clock(id) \
1953 + do { \
1954 + g_clk_gate |= 1 << ((id) + PERI_MSDC0_PDN); \
1955 + } while(0)
1956 +
1957 +// do we need sync object or not
1958 +void msdc_clk_status(int * status)
1959 +{
1960 + *status = g_clk_gate;
1961 +}
1962 +#endif /* end of --- */
1963 +
1964 +/* +++ by chhung */
1965 +struct msdc_hw msdc0_hw = {
1966 + .clk_src = 0,
1967 + .cmd_edge = MSDC_SMPL_FALLING,
1968 + .data_edge = MSDC_SMPL_FALLING,
1969 + .clk_drv = 4,
1970 + .cmd_drv = 4,
1971 + .dat_drv = 4,
1972 + .data_pins = 4,
1973 + .data_offset = 0,
1974 + .flags = MSDC_SYS_SUSPEND | MSDC_WP_PIN_EN | MSDC_CD_PIN_EN | MSDC_REMOVABLE | MSDC_HIGHSPEED,
1975 +// .flags = MSDC_SYS_SUSPEND | MSDC_WP_PIN_EN | MSDC_CD_PIN_EN | MSDC_REMOVABLE,
1976 +};
1977 +
1978 +static struct resource mtk_sd_resources[] = {
1979 + [0] = {
1980 + .start = RALINK_MSDC_BASE,
1981 + .end = RALINK_MSDC_BASE+0x3fff,
1982 + .flags = IORESOURCE_MEM,
1983 + },
1984 + [1] = {
1985 + .start = IRQ_SDC, /*FIXME*/
1986 + .end = IRQ_SDC, /*FIXME*/
1987 + .flags = IORESOURCE_IRQ,
1988 + },
1989 +};
1990 +
1991 +static struct platform_device mtk_sd_device = {
1992 + .name = "mtk-sd",
1993 + .id = 0,
1994 + .num_resources = ARRAY_SIZE(mtk_sd_resources),
1995 + .resource = mtk_sd_resources,
1996 +};
1997 +/* end of +++ */
1998 +
1999 +static int msdc_rsp[] = {
2000 + 0, /* RESP_NONE */
2001 + 1, /* RESP_R1 */
2002 + 2, /* RESP_R2 */
2003 + 3, /* RESP_R3 */
2004 + 4, /* RESP_R4 */
2005 + 1, /* RESP_R5 */
2006 + 1, /* RESP_R6 */
2007 + 1, /* RESP_R7 */
2008 + 7, /* RESP_R1b */
2009 +};
2010 +
2011 +/* For Inhanced DMA */
2012 +#define msdc_init_gpd_ex(gpd,extlen,cmd,arg,blknum) \
2013 + do { \
2014 + ((gpd_t*)gpd)->extlen = extlen; \
2015 + ((gpd_t*)gpd)->cmd = cmd; \
2016 + ((gpd_t*)gpd)->arg = arg; \
2017 + ((gpd_t*)gpd)->blknum = blknum; \
2018 + }while(0)
2019 +
2020 +#define msdc_init_bd(bd, blkpad, dwpad, dptr, dlen) \
2021 + do { \
2022 + BUG_ON(dlen > 0xFFFFUL); \
2023 + ((bd_t*)bd)->blkpad = blkpad; \
2024 + ((bd_t*)bd)->dwpad = dwpad; \
2025 + ((bd_t*)bd)->ptr = (void*)dptr; \
2026 + ((bd_t*)bd)->buflen = dlen; \
2027 + }while(0)
2028 +
2029 +#define msdc_txfifocnt() ((sdr_read32(MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16)
2030 +#define msdc_rxfifocnt() ((sdr_read32(MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) >> 0)
2031 +#define msdc_fifo_write32(v) sdr_write32(MSDC_TXDATA, (v))
2032 +#define msdc_fifo_write8(v) sdr_write8(MSDC_TXDATA, (v))
2033 +#define msdc_fifo_read32() sdr_read32(MSDC_RXDATA)
2034 +#define msdc_fifo_read8() sdr_read8(MSDC_RXDATA)
2035 +
2036 +
2037 +#define msdc_dma_on() sdr_clr_bits(MSDC_CFG, MSDC_CFG_PIO)
2038 +#define msdc_dma_off() sdr_set_bits(MSDC_CFG, MSDC_CFG_PIO)
2039 +
2040 +#define msdc_retry(expr,retry,cnt) \
2041 + do { \
2042 + int backup = cnt; \
2043 + while (retry) { \
2044 + if (!(expr)) break; \
2045 + if (cnt-- == 0) { \
2046 + retry--; mdelay(1); cnt = backup; \
2047 + } \
2048 + } \
2049 + WARN_ON(retry == 0); \
2050 + } while(0)
2051 +
2052 +#if 0 /* --- by chhung */
2053 +#define msdc_reset() \
2054 + do { \
2055 + int retry = 3, cnt = 1000; \
2056 + sdr_set_bits(MSDC_CFG, MSDC_CFG_RST); \
2057 + dsb(); \
2058 + msdc_retry(sdr_read32(MSDC_CFG) & MSDC_CFG_RST, retry, cnt); \
2059 + } while(0)
2060 +#else
2061 +#define msdc_reset() \
2062 + do { \
2063 + int retry = 3, cnt = 1000; \
2064 + sdr_set_bits(MSDC_CFG, MSDC_CFG_RST); \
2065 + msdc_retry(sdr_read32(MSDC_CFG) & MSDC_CFG_RST, retry, cnt); \
2066 + } while(0)
2067 +#endif /* end of +/- */
2068 +
2069 +#define msdc_clr_int() \
2070 + do { \
2071 + volatile u32 val = sdr_read32(MSDC_INT); \
2072 + sdr_write32(MSDC_INT, val); \
2073 + } while(0)
2074 +
2075 +#define msdc_clr_fifo() \
2076 + do { \
2077 + int retry = 3, cnt = 1000; \
2078 + sdr_set_bits(MSDC_FIFOCS, MSDC_FIFOCS_CLR); \
2079 + msdc_retry(sdr_read32(MSDC_FIFOCS) & MSDC_FIFOCS_CLR, retry, cnt); \
2080 + } while(0)
2081 +
2082 +#define msdc_irq_save(val) \
2083 + do { \
2084 + val = sdr_read32(MSDC_INTEN); \
2085 + sdr_clr_bits(MSDC_INTEN, val); \
2086 + } while(0)
2087 +
2088 +#define msdc_irq_restore(val) \
2089 + do { \
2090 + sdr_set_bits(MSDC_INTEN, val); \
2091 + } while(0)
2092 +
2093 +/* clock source for host: global */
2094 +#if defined (CONFIG_SOC_MT7620)
2095 +static u32 hclks[] = {48000000}; /* +/- by chhung */
2096 +#elif defined (CONFIG_SOC_MT7621)
2097 +static u32 hclks[] = {50000000}; /* +/- by chhung */
2098 +#endif
2099 +
2100 +//============================================
2101 +// the power for msdc host controller: global
2102 +// always keep the VMC on.
2103 +//============================================
2104 +#define msdc_vcore_on(host) \
2105 + do { \
2106 + INIT_MSG("[+]VMC ref. count<%d>", ++host->pwr_ref); \
2107 + (void)hwPowerOn(MT65XX_POWER_LDO_VMC, VOL_3300, "SD"); \
2108 + } while (0)
2109 +#define msdc_vcore_off(host) \
2110 + do { \
2111 + INIT_MSG("[-]VMC ref. count<%d>", --host->pwr_ref); \
2112 + (void)hwPowerDown(MT65XX_POWER_LDO_VMC, "SD"); \
2113 + } while (0)
2114 +
2115 +//====================================
2116 +// the vdd output for card: global
2117 +// always keep the VMCH on.
2118 +//====================================
2119 +#define msdc_vdd_on(host) \
2120 + do { \
2121 + (void)hwPowerOn(MT65XX_POWER_LDO_VMCH, VOL_3300, "SD"); \
2122 + } while (0)
2123 +#define msdc_vdd_off(host) \
2124 + do { \
2125 + (void)hwPowerDown(MT65XX_POWER_LDO_VMCH, "SD"); \
2126 + } while (0)
2127 +
2128 +#define sdc_is_busy() (sdr_read32(SDC_STS) & SDC_STS_SDCBUSY)
2129 +#define sdc_is_cmd_busy() (sdr_read32(SDC_STS) & SDC_STS_CMDBUSY)
2130 +
2131 +#define sdc_send_cmd(cmd,arg) \
2132 + do { \
2133 + sdr_write32(SDC_ARG, (arg)); \
2134 + sdr_write32(SDC_CMD, (cmd)); \
2135 + } while(0)
2136 +
2137 +// can modify to read h/w register.
2138 +//#define is_card_present(h) ((sdr_read32(MSDC_PS) & MSDC_PS_CDSTS) ? 0 : 1);
2139 +#define is_card_present(h) (((struct msdc_host*)(h))->card_inserted)
2140 +
2141 +/* +++ by chhung */
2142 +#ifndef __ASSEMBLY__
2143 +#define PHYSADDR(a) (((unsigned long)(a)) & 0x1fffffff)
2144 +#else
2145 +#define PHYSADDR(a) ((a) & 0x1fffffff)
2146 +#endif
2147 +/* end of +++ */
2148 +static unsigned int msdc_do_command(struct msdc_host *host,
2149 + struct mmc_command *cmd,
2150 + int tune,
2151 + unsigned long timeout);
2152 +
2153 +static int msdc_tune_cmdrsp(struct msdc_host*host,struct mmc_command *cmd);
2154 +
2155 +#ifdef MT6575_SD_DEBUG
2156 +static void msdc_dump_card_status(struct msdc_host *host, u32 status)
2157 +{
2158 + static char *state[] = {
2159 + "Idle", /* 0 */
2160 + "Ready", /* 1 */
2161 + "Ident", /* 2 */
2162 + "Stby", /* 3 */
2163 + "Tran", /* 4 */
2164 + "Data", /* 5 */
2165 + "Rcv", /* 6 */
2166 + "Prg", /* 7 */
2167 + "Dis", /* 8 */
2168 + "Reserved", /* 9 */
2169 + "Reserved", /* 10 */
2170 + "Reserved", /* 11 */
2171 + "Reserved", /* 12 */
2172 + "Reserved", /* 13 */
2173 + "Reserved", /* 14 */
2174 + "I/O mode", /* 15 */
2175 + };
2176 + if (status & R1_OUT_OF_RANGE)
2177 + N_MSG(RSP, "[CARD_STATUS] Out of Range");
2178 + if (status & R1_ADDRESS_ERROR)
2179 + N_MSG(RSP, "[CARD_STATUS] Address Error");
2180 + if (status & R1_BLOCK_LEN_ERROR)
2181 + N_MSG(RSP, "[CARD_STATUS] Block Len Error");
2182 + if (status & R1_ERASE_SEQ_ERROR)
2183 + N_MSG(RSP, "[CARD_STATUS] Erase Seq Error");
2184 + if (status & R1_ERASE_PARAM)
2185 + N_MSG(RSP, "[CARD_STATUS] Erase Param");
2186 + if (status & R1_WP_VIOLATION)
2187 + N_MSG(RSP, "[CARD_STATUS] WP Violation");
2188 + if (status & R1_CARD_IS_LOCKED)
2189 + N_MSG(RSP, "[CARD_STATUS] Card is Locked");
2190 + if (status & R1_LOCK_UNLOCK_FAILED)
2191 + N_MSG(RSP, "[CARD_STATUS] Lock/Unlock Failed");
2192 + if (status & R1_COM_CRC_ERROR)
2193 + N_MSG(RSP, "[CARD_STATUS] Command CRC Error");
2194 + if (status & R1_ILLEGAL_COMMAND)
2195 + N_MSG(RSP, "[CARD_STATUS] Illegal Command");
2196 + if (status & R1_CARD_ECC_FAILED)
2197 + N_MSG(RSP, "[CARD_STATUS] Card ECC Failed");
2198 + if (status & R1_CC_ERROR)
2199 + N_MSG(RSP, "[CARD_STATUS] CC Error");
2200 + if (status & R1_ERROR)
2201 + N_MSG(RSP, "[CARD_STATUS] Error");
2202 + if (status & R1_UNDERRUN)
2203 + N_MSG(RSP, "[CARD_STATUS] Underrun");
2204 + if (status & R1_OVERRUN)
2205 + N_MSG(RSP, "[CARD_STATUS] Overrun");
2206 + if (status & R1_CID_CSD_OVERWRITE)
2207 + N_MSG(RSP, "[CARD_STATUS] CID/CSD Overwrite");
2208 + if (status & R1_WP_ERASE_SKIP)
2209 + N_MSG(RSP, "[CARD_STATUS] WP Eraser Skip");
2210 + if (status & R1_CARD_ECC_DISABLED)
2211 + N_MSG(RSP, "[CARD_STATUS] Card ECC Disabled");
2212 + if (status & R1_ERASE_RESET)
2213 + N_MSG(RSP, "[CARD_STATUS] Erase Reset");
2214 + if (status & R1_READY_FOR_DATA)
2215 + N_MSG(RSP, "[CARD_STATUS] Ready for Data");
2216 + if (status & R1_SWITCH_ERROR)
2217 + N_MSG(RSP, "[CARD_STATUS] Switch error");
2218 + if (status & R1_APP_CMD)
2219 + N_MSG(RSP, "[CARD_STATUS] App Command");
2220 +
2221 + N_MSG(RSP, "[CARD_STATUS] '%s' State", state[R1_CURRENT_STATE(status)]);
2222 +}
2223 +
2224 +static void msdc_dump_ocr_reg(struct msdc_host *host, u32 resp)
2225 +{
2226 + if (resp & (1 << 7))
2227 + N_MSG(RSP, "[OCR] Low Voltage Range");
2228 + if (resp & (1 << 15))
2229 + N_MSG(RSP, "[OCR] 2.7-2.8 volt");
2230 + if (resp & (1 << 16))
2231 + N_MSG(RSP, "[OCR] 2.8-2.9 volt");
2232 + if (resp & (1 << 17))
2233 + N_MSG(RSP, "[OCR] 2.9-3.0 volt");
2234 + if (resp & (1 << 18))
2235 + N_MSG(RSP, "[OCR] 3.0-3.1 volt");
2236 + if (resp & (1 << 19))
2237 + N_MSG(RSP, "[OCR] 3.1-3.2 volt");
2238 + if (resp & (1 << 20))
2239 + N_MSG(RSP, "[OCR] 3.2-3.3 volt");
2240 + if (resp & (1 << 21))
2241 + N_MSG(RSP, "[OCR] 3.3-3.4 volt");
2242 + if (resp & (1 << 22))
2243 + N_MSG(RSP, "[OCR] 3.4-3.5 volt");
2244 + if (resp & (1 << 23))
2245 + N_MSG(RSP, "[OCR] 3.5-3.6 volt");
2246 + if (resp & (1 << 24))
2247 + N_MSG(RSP, "[OCR] Switching to 1.8V Accepted (S18A)");
2248 + if (resp & (1 << 30))
2249 + N_MSG(RSP, "[OCR] Card Capacity Status (CCS)");
2250 + if (resp & (1 << 31))
2251 + N_MSG(RSP, "[OCR] Card Power Up Status (Idle)");
2252 + else
2253 + N_MSG(RSP, "[OCR] Card Power Up Status (Busy)");
2254 +}
2255 +
2256 +static void msdc_dump_rca_resp(struct msdc_host *host, u32 resp)
2257 +{
2258 + u32 status = (((resp >> 15) & 0x1) << 23) |
2259 + (((resp >> 14) & 0x1) << 22) |
2260 + (((resp >> 13) & 0x1) << 19) |
2261 + (resp & 0x1fff);
2262 +
2263 + N_MSG(RSP, "[RCA] 0x%.4x", resp >> 16);
2264 + msdc_dump_card_status(host, status);
2265 +}
2266 +
2267 +static void msdc_dump_io_resp(struct msdc_host *host, u32 resp)
2268 +{
2269 + u32 flags = (resp >> 8) & 0xFF;
2270 + char *state[] = {"DIS", "CMD", "TRN", "RFU"};
2271 +
2272 + if (flags & (1 << 7))
2273 + N_MSG(RSP, "[IO] COM_CRC_ERR");
2274 + if (flags & (1 << 6))
2275 + N_MSG(RSP, "[IO] Illgal command");
2276 + if (flags & (1 << 3))
2277 + N_MSG(RSP, "[IO] Error");
2278 + if (flags & (1 << 2))
2279 + N_MSG(RSP, "[IO] RFU");
2280 + if (flags & (1 << 1))
2281 + N_MSG(RSP, "[IO] Function number error");
2282 + if (flags & (1 << 0))
2283 + N_MSG(RSP, "[IO] Out of range");
2284 +
2285 + N_MSG(RSP, "[IO] State: %s, Data:0x%x", state[(resp >> 12) & 0x3], resp & 0xFF);
2286 +}
2287 +#endif
2288 +
2289 +static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks)
2290 +{
2291 + u32 base = host->base;
2292 + u32 timeout, clk_ns;
2293 +
2294 + host->timeout_ns = ns;
2295 + host->timeout_clks = clks;
2296 +
2297 + clk_ns = 1000000000UL / host->sclk;
2298 + timeout = ns / clk_ns + clks;
2299 + timeout = timeout >> 16; /* in 65536 sclk cycle unit */
2300 + timeout = timeout > 1 ? timeout - 1 : 0;
2301 + timeout = timeout > 255 ? 255 : timeout;
2302 +
2303 + sdr_set_field(SDC_CFG, SDC_CFG_DTOC, timeout);
2304 +
2305 + N_MSG(OPS, "Set read data timeout: %dns %dclks -> %d x 65536 cycles",
2306 + ns, clks, timeout + 1);
2307 +}
2308 +
2309 +/* msdc_eirq_sdio() will be called when EIRQ(for WIFI) */
2310 +static void msdc_eirq_sdio(void *data)
2311 +{
2312 + struct msdc_host *host = (struct msdc_host *)data;
2313 +
2314 + N_MSG(INT, "SDIO EINT");
2315 +
2316 + mmc_signal_sdio_irq(host->mmc);
2317 +}
2318 +
2319 +/* msdc_eirq_cd will not be used! We not using EINT for card detection. */
2320 +static void msdc_eirq_cd(void *data)
2321 +{
2322 + struct msdc_host *host = (struct msdc_host *)data;
2323 +
2324 + N_MSG(INT, "CD EINT");
2325 +
2326 +#if 0
2327 + tasklet_hi_schedule(&host->card_tasklet);
2328 +#else
2329 + schedule_delayed_work(&host->card_delaywork, HZ);
2330 +#endif
2331 +}
2332 +
2333 +#if 0
2334 +static void msdc_tasklet_card(unsigned long arg)
2335 +{
2336 + struct msdc_host *host = (struct msdc_host *)arg;
2337 +#else
2338 +static void msdc_tasklet_card(struct work_struct *work)
2339 +{
2340 + struct msdc_host *host = (struct msdc_host *)container_of(work,
2341 + struct msdc_host, card_delaywork.work);
2342 +#endif
2343 + struct msdc_hw *hw = host->hw;
2344 + u32 base = host->base;
2345 + u32 inserted;
2346 + u32 status = 0;
2347 + //u32 change = 0;
2348 +
2349 + spin_lock(&host->lock);
2350 +
2351 + if (hw->get_cd_status) { // NULL
2352 + inserted = hw->get_cd_status();
2353 + } else {
2354 + status = sdr_read32(MSDC_PS);
2355 + inserted = (status & MSDC_PS_CDSTS) ? 0 : 1;
2356 + }
2357 +
2358 +#if 0
2359 + change = host->card_inserted ^ inserted;
2360 + host->card_inserted = inserted;
2361 +
2362 + if (change && !host->suspend) {
2363 + if (inserted) {
2364 + host->mmc->f_max = HOST_MAX_MCLK; // work around
2365 + }
2366 + mmc_detect_change(host->mmc, msecs_to_jiffies(20));
2367 + }
2368 +#else /* Make sure: handle the last interrupt */
2369 + host->card_inserted = inserted;
2370 +
2371 + if (!host->suspend) {
2372 + host->mmc->f_max = HOST_MAX_MCLK;
2373 + mmc_detect_change(host->mmc, msecs_to_jiffies(20));
2374 + }
2375 +
2376 + IRQ_MSG("card found<%s>", inserted ? "inserted" : "removed");
2377 +#endif
2378 +
2379 + spin_unlock(&host->lock);
2380 +}
2381 +
2382 +#if 0 /* --- by chhung */
2383 +/* For E2 only */
2384 +static u8 clk_src_bit[4] = {
2385 + 0, 3, 5, 7
2386 +};
2387 +
2388 +static void msdc_select_clksrc(struct msdc_host* host, unsigned char clksrc)
2389 +{
2390 + u32 val;
2391 + u32 base = host->base;
2392 +
2393 + BUG_ON(clksrc > 3);
2394 + INIT_MSG("set clock source to <%d>", clksrc);
2395 +
2396 + val = sdr_read32(MSDC_CLKSRC_REG);
2397 + if (sdr_read32(MSDC_ECO_VER) >= 4) {
2398 + val &= ~(0x3 << clk_src_bit[host->id]);
2399 + val |= clksrc << clk_src_bit[host->id];
2400 + } else {
2401 + val &= ~0x3; val |= clksrc;
2402 + }
2403 + sdr_write32(MSDC_CLKSRC_REG, val);
2404 +
2405 + host->hclk = hclks[clksrc];
2406 + host->hw->clk_src = clksrc;
2407 +}
2408 +#endif /* end of --- */
2409 +
2410 +static void msdc_set_mclk(struct msdc_host *host, int ddr, unsigned int hz)
2411 +{
2412 + //struct msdc_hw *hw = host->hw;
2413 + u32 base = host->base;
2414 + u32 mode;
2415 + u32 flags;
2416 + u32 div;
2417 + u32 sclk;
2418 + u32 hclk = host->hclk;
2419 + //u8 clksrc = hw->clk_src;
2420 +
2421 + if (!hz) { // set mmc system clock to 0 ?
2422 + ERR_MSG("set mclk to 0!!!");
2423 + msdc_reset();
2424 + return;
2425 + }
2426 +
2427 + msdc_irq_save(flags);
2428 +
2429 +#if defined (CONFIG_MT7621_FPGA) || defined (CONFIG_MT7628_FPGA)
2430 + mode = 0x0; /* use divisor */
2431 + if (hz >= (hclk >> 1)) {
2432 + div = 0; /* mean div = 1/2 */
2433 + sclk = hclk >> 1; /* sclk = clk / 2 */
2434 + } else {
2435 + div = (hclk + ((hz << 2) - 1)) / (hz << 2);
2436 + sclk = (hclk >> 2) / div;
2437 + }
2438 +#else
2439 + if (ddr) {
2440 + mode = 0x2; /* ddr mode and use divisor */
2441 + if (hz >= (hclk >> 2)) {
2442 + div = 1; /* mean div = 1/4 */
2443 + sclk = hclk >> 2; /* sclk = clk / 4 */
2444 + } else {
2445 + div = (hclk + ((hz << 2) - 1)) / (hz << 2);
2446 + sclk = (hclk >> 2) / div;
2447 + }
2448 + } else if (hz >= hclk) { /* bug fix */
2449 + mode = 0x1; /* no divisor and divisor is ignored */
2450 + div = 0;
2451 + sclk = hclk;
2452 + } else {
2453 + mode = 0x0; /* use divisor */
2454 + if (hz >= (hclk >> 1)) {
2455 + div = 0; /* mean div = 1/2 */
2456 + sclk = hclk >> 1; /* sclk = clk / 2 */
2457 + } else {
2458 + div = (hclk + ((hz << 2) - 1)) / (hz << 2);
2459 + sclk = (hclk >> 2) / div;
2460 + }
2461 + }
2462 +#endif
2463 + /* set clock mode and divisor */
2464 + sdr_set_field(MSDC_CFG, MSDC_CFG_CKMOD, mode);
2465 + sdr_set_field(MSDC_CFG, MSDC_CFG_CKDIV, div);
2466 +
2467 + /* wait clock stable */
2468 + while (!(sdr_read32(MSDC_CFG) & MSDC_CFG_CKSTB));
2469 +
2470 + host->sclk = sclk;
2471 + host->mclk = hz;
2472 + msdc_set_timeout(host, host->timeout_ns, host->timeout_clks); // need?
2473 +
2474 + INIT_MSG("================");
2475 + INIT_MSG("!!! Set<%dKHz> Source<%dKHz> -> sclk<%dKHz>", hz/1000, hclk/1000, sclk/1000);
2476 + INIT_MSG("================");
2477 +
2478 + msdc_irq_restore(flags);
2479 +}
2480 +
2481 +/* Fix me. when need to abort */
2482 +static void msdc_abort_data(struct msdc_host *host)
2483 +{
2484 + u32 base = host->base;
2485 + struct mmc_command *stop = host->mrq->stop;
2486 +
2487 + ERR_MSG("Need to Abort. dma<%d>", host->dma_xfer);
2488 +
2489 + msdc_reset();
2490 + msdc_clr_fifo();
2491 + msdc_clr_int();
2492 +
2493 + // need to check FIFO count 0 ?
2494 +
2495 + if (stop) { /* try to stop, but may not success */
2496 + ERR_MSG("stop when abort CMD<%d>", stop->opcode);
2497 + (void)msdc_do_command(host, stop, 0, CMD_TIMEOUT);
2498 + }
2499 +
2500 + //if (host->mclk >= 25000000) {
2501 + // msdc_set_mclk(host, 0, host->mclk >> 1);
2502 + //}
2503 +}
2504 +
2505 +#if 0 /* --- by chhung */
2506 +static void msdc_pin_config(struct msdc_host *host, int mode)
2507 +{
2508 + struct msdc_hw *hw = host->hw;
2509 + u32 base = host->base;
2510 + int pull = (mode == MSDC_PIN_PULL_UP) ? GPIO_PULL_UP : GPIO_PULL_DOWN;
2511 +
2512 + /* Config WP pin */
2513 + if (hw->flags & MSDC_WP_PIN_EN) {
2514 + if (hw->config_gpio_pin) /* NULL */
2515 + hw->config_gpio_pin(MSDC_WP_PIN, pull);
2516 + }
2517 +
2518 + switch (mode) {
2519 + case MSDC_PIN_PULL_UP:
2520 + //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPU, 1); /* Check & FIXME */
2521 + //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPD, 0); /* Check & FIXME */
2522 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPU, 1);
2523 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPD, 0);
2524 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPU, 1);
2525 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPD, 0);
2526 + break;
2527 + case MSDC_PIN_PULL_DOWN:
2528 + //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPU, 0); /* Check & FIXME */
2529 + //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPD, 1); /* Check & FIXME */
2530 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPU, 0);
2531 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPD, 1);
2532 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPU, 0);
2533 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPD, 1);
2534 + break;
2535 + case MSDC_PIN_PULL_NONE:
2536 + default:
2537 + //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPU, 0); /* Check & FIXME */
2538 + //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPD, 0); /* Check & FIXME */
2539 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPU, 0);
2540 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPD, 0);
2541 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPU, 0);
2542 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPD, 0);
2543 + break;
2544 + }
2545 +
2546 + N_MSG(CFG, "Pins mode(%d), down(%d), up(%d)",
2547 + mode, MSDC_PIN_PULL_DOWN, MSDC_PIN_PULL_UP);
2548 +}
2549 +
2550 +void msdc_pin_reset(struct msdc_host *host, int mode)
2551 +{
2552 + struct msdc_hw *hw = (struct msdc_hw *)host->hw;
2553 + u32 base = host->base;
2554 + int pull = (mode == MSDC_PIN_PULL_UP) ? GPIO_PULL_UP : GPIO_PULL_DOWN;
2555 +
2556 + /* Config reset pin */
2557 + if (hw->flags & MSDC_RST_PIN_EN) {
2558 + if (hw->config_gpio_pin) /* NULL */
2559 + hw->config_gpio_pin(MSDC_RST_PIN, pull);
2560 +
2561 + if (mode == MSDC_PIN_PULL_UP) {
2562 + sdr_clr_bits(EMMC_IOCON, EMMC_IOCON_BOOTRST);
2563 + } else {
2564 + sdr_set_bits(EMMC_IOCON, EMMC_IOCON_BOOTRST);
2565 + }
2566 + }
2567 +}
2568 +
2569 +static void msdc_core_power(struct msdc_host *host, int on)
2570 +{
2571 + N_MSG(CFG, "Turn %s %s power (copower: %d -> %d)",
2572 + on ? "on" : "off", "core", host->core_power, on);
2573 +
2574 + if (on && host->core_power == 0) {
2575 + msdc_vcore_on(host);
2576 + host->core_power = 1;
2577 + msleep(1);
2578 + } else if (!on && host->core_power == 1) {
2579 + msdc_vcore_off(host);
2580 + host->core_power = 0;
2581 + msleep(1);
2582 + }
2583 +}
2584 +
2585 +static void msdc_host_power(struct msdc_host *host, int on)
2586 +{
2587 + N_MSG(CFG, "Turn %s %s power ", on ? "on" : "off", "host");
2588 +
2589 + if (on) {
2590 + //msdc_core_power(host, 1); // need do card detection.
2591 + msdc_pin_reset(host, MSDC_PIN_PULL_UP);
2592 + } else {
2593 + msdc_pin_reset(host, MSDC_PIN_PULL_DOWN);
2594 + //msdc_core_power(host, 0);
2595 + }
2596 +}
2597 +
2598 +static void msdc_card_power(struct msdc_host *host, int on)
2599 +{
2600 + N_MSG(CFG, "Turn %s %s power ", on ? "on" : "off", "card");
2601 +
2602 + if (on) {
2603 + msdc_pin_config(host, MSDC_PIN_PULL_UP);
2604 + if (host->hw->ext_power_on) {
2605 + host->hw->ext_power_on();
2606 + } else {
2607 + //msdc_vdd_on(host); // need todo card detection.
2608 + }
2609 + msleep(1);
2610 + } else {
2611 + if (host->hw->ext_power_off) {
2612 + host->hw->ext_power_off();
2613 + } else {
2614 + //msdc_vdd_off(host);
2615 + }
2616 + msdc_pin_config(host, MSDC_PIN_PULL_DOWN);
2617 + msleep(1);
2618 + }
2619 +}
2620 +
2621 +static void msdc_set_power_mode(struct msdc_host *host, u8 mode)
2622 +{
2623 + N_MSG(CFG, "Set power mode(%d)", mode);
2624 +
2625 + if (host->power_mode == MMC_POWER_OFF && mode != MMC_POWER_OFF) {
2626 + msdc_host_power(host, 1);
2627 + msdc_card_power(host, 1);
2628 + } else if (host->power_mode != MMC_POWER_OFF && mode == MMC_POWER_OFF) {
2629 + msdc_card_power(host, 0);
2630 + msdc_host_power(host, 0);
2631 + }
2632 + host->power_mode = mode;
2633 +}
2634 +#endif /* end of --- */
2635 +
2636 +#ifdef CONFIG_PM
2637 +/*
2638 + register as callback function of WIFI(combo_sdio_register_pm) .
2639 + can called by msdc_drv_suspend/resume too.
2640 +*/
2641 +static void msdc_pm(pm_message_t state, void *data)
2642 +{
2643 + struct msdc_host *host = (struct msdc_host *)data;
2644 + int evt = state.event;
2645 +
2646 + if (evt == PM_EVENT_USER_RESUME || evt == PM_EVENT_USER_SUSPEND) {
2647 + INIT_MSG("USR_%s: suspend<%d> power<%d>",
2648 + evt == PM_EVENT_USER_RESUME ? "EVENT_USER_RESUME" : "EVENT_USER_SUSPEND",
2649 + host->suspend, host->power_mode);
2650 + }
2651 +
2652 + if (evt == PM_EVENT_SUSPEND || evt == PM_EVENT_USER_SUSPEND) {
2653 + if (host->suspend) /* already suspend */ /* default 0*/
2654 + return;
2655 +
2656 + /* for memory card. already power off by mmc */
2657 + if (evt == PM_EVENT_SUSPEND && host->power_mode == MMC_POWER_OFF)
2658 + return;
2659 +
2660 + host->suspend = 1;
2661 + host->pm_state = state; /* default PMSG_RESUME */
2662 +
2663 + INIT_MSG("%s Suspend", evt == PM_EVENT_SUSPEND ? "PM" : "USR");
2664 + if(host->hw->flags & MSDC_SYS_SUSPEND) /* set for card */
2665 + (void)mmc_suspend_host(host->mmc);
2666 + else {
2667 + // host->mmc->pm_flags |= MMC_PM_IGNORE_PM_NOTIFY; /* just for double confirm */ /* --- by chhung */
2668 + mmc_remove_host(host->mmc);
2669 + }
2670 + } else if (evt == PM_EVENT_RESUME || evt == PM_EVENT_USER_RESUME) {
2671 + if (!host->suspend){
2672 + //ERR_MSG("warning: already resume");
2673 + return;
2674 + }
2675 +
2676 + /* No PM resume when USR suspend */
2677 + if (evt == PM_EVENT_RESUME && host->pm_state.event == PM_EVENT_USER_SUSPEND) {
2678 + ERR_MSG("PM Resume when in USR Suspend"); /* won't happen. */
2679 + return;
2680 + }
2681 +
2682 + host->suspend = 0;
2683 + host->pm_state = state;
2684 +
2685 + INIT_MSG("%s Resume", evt == PM_EVENT_RESUME ? "PM" : "USR");
2686 + if(host->hw->flags & MSDC_SYS_SUSPEND) { /* will not set for WIFI */
2687 + (void)mmc_resume_host(host->mmc);
2688 + }
2689 + else {
2690 + // host->mmc->pm_flags |= MMC_PM_IGNORE_PM_NOTIFY; /* --- by chhung */
2691 + mmc_add_host(host->mmc);
2692 + }
2693 + }
2694 +}
2695 +#endif
2696 +
2697 +/*--------------------------------------------------------------------------*/
2698 +/* mmc_host_ops members */
2699 +/*--------------------------------------------------------------------------*/
2700 +static unsigned int msdc_command_start(struct msdc_host *host,
2701 + struct mmc_command *cmd,
2702 + int tune, /* not used */
2703 + unsigned long timeout)
2704 +{
2705 + u32 base = host->base;
2706 + u32 opcode = cmd->opcode;
2707 + u32 rawcmd;
2708 + u32 wints = MSDC_INT_CMDRDY | MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO |
2709 + MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR | MSDC_INT_ACMDTMO |
2710 + MSDC_INT_ACMD19_DONE;
2711 +
2712 + u32 resp;
2713 + unsigned long tmo;
2714 +
2715 + /* Protocol layer does not provide response type, but our hardware needs
2716 + * to know exact type, not just size!
2717 + */
2718 + if (opcode == MMC_SEND_OP_COND || opcode == SD_APP_OP_COND)
2719 + resp = RESP_R3;
2720 + else if (opcode == MMC_SET_RELATIVE_ADDR || opcode == SD_SEND_RELATIVE_ADDR)
2721 + resp = (mmc_cmd_type(cmd) == MMC_CMD_BCR) ? RESP_R6 : RESP_R1;
2722 + else if (opcode == MMC_FAST_IO)
2723 + resp = RESP_R4;
2724 + else if (opcode == MMC_GO_IRQ_STATE)
2725 + resp = RESP_R5;
2726 + else if (opcode == MMC_SELECT_CARD)
2727 + resp = (cmd->arg != 0) ? RESP_R1B : RESP_NONE;
2728 + else if (opcode == SD_IO_RW_DIRECT || opcode == SD_IO_RW_EXTENDED)
2729 + resp = RESP_R1; /* SDIO workaround. */
2730 + else if (opcode == SD_SEND_IF_COND && (mmc_cmd_type(cmd) == MMC_CMD_BCR))
2731 + resp = RESP_R1;
2732 + else {
2733 + switch (mmc_resp_type(cmd)) {
2734 + case MMC_RSP_R1:
2735 + resp = RESP_R1;
2736 + break;
2737 + case MMC_RSP_R1B:
2738 + resp = RESP_R1B;
2739 + break;
2740 + case MMC_RSP_R2:
2741 + resp = RESP_R2;
2742 + break;
2743 + case MMC_RSP_R3:
2744 + resp = RESP_R3;
2745 + break;
2746 + case MMC_RSP_NONE:
2747 + default:
2748 + resp = RESP_NONE;
2749 + break;
2750 + }
2751 + }
2752 +
2753 + cmd->error = 0;
2754 + /* rawcmd :
2755 + * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 |
2756 + * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode
2757 + */
2758 + rawcmd = opcode | msdc_rsp[resp] << 7 | host->blksz << 16;
2759 +
2760 + if (opcode == MMC_READ_MULTIPLE_BLOCK) {
2761 + rawcmd |= (2 << 11);
2762 + } else if (opcode == MMC_READ_SINGLE_BLOCK) {
2763 + rawcmd |= (1 << 11);
2764 + } else if (opcode == MMC_WRITE_MULTIPLE_BLOCK) {
2765 + rawcmd |= ((2 << 11) | (1 << 13));
2766 + } else if (opcode == MMC_WRITE_BLOCK) {
2767 + rawcmd |= ((1 << 11) | (1 << 13));
2768 + } else if (opcode == SD_IO_RW_EXTENDED) {
2769 + if (cmd->data->flags & MMC_DATA_WRITE)
2770 + rawcmd |= (1 << 13);
2771 + if (cmd->data->blocks > 1)
2772 + rawcmd |= (2 << 11);
2773 + else
2774 + rawcmd |= (1 << 11);
2775 + } else if (opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int)-1) {
2776 + rawcmd |= (1 << 14);
2777 + } else if ((opcode == SD_APP_SEND_SCR) ||
2778 + (opcode == SD_APP_SEND_NUM_WR_BLKS) ||
2779 + (opcode == SD_SWITCH && (mmc_cmd_type(cmd) == MMC_CMD_ADTC)) ||
2780 + (opcode == SD_APP_SD_STATUS && (mmc_cmd_type(cmd) == MMC_CMD_ADTC)) ||
2781 + (opcode == MMC_SEND_EXT_CSD && (mmc_cmd_type(cmd) == MMC_CMD_ADTC))) {
2782 + rawcmd |= (1 << 11);
2783 + } else if (opcode == MMC_STOP_TRANSMISSION) {
2784 + rawcmd |= (1 << 14);
2785 + rawcmd &= ~(0x0FFF << 16);
2786 + }
2787 +
2788 + N_MSG(CMD, "CMD<%d><0x%.8x> Arg<0x%.8x>", opcode , rawcmd, cmd->arg);
2789 +
2790 + tmo = jiffies + timeout;
2791 +
2792 + if (opcode == MMC_SEND_STATUS) {
2793 + for (;;) {
2794 + if (!sdc_is_cmd_busy())
2795 + break;
2796 +
2797 + if (time_after(jiffies, tmo)) {
2798 + ERR_MSG("XXX cmd_busy timeout: before CMD<%d>", opcode);
2799 + cmd->error = (unsigned int)-ETIMEDOUT;
2800 + msdc_reset();
2801 + goto end;
2802 + }
2803 + }
2804 + }else {
2805 + for (;;) {
2806 + if (!sdc_is_busy())
2807 + break;
2808 + if (time_after(jiffies, tmo)) {
2809 + ERR_MSG("XXX sdc_busy timeout: before CMD<%d>", opcode);
2810 + cmd->error = (unsigned int)-ETIMEDOUT;
2811 + msdc_reset();
2812 + goto end;
2813 + }
2814 + }
2815 + }
2816 +
2817 + //BUG_ON(in_interrupt());
2818 + host->cmd = cmd;
2819 + host->cmd_rsp = resp;
2820 +
2821 + init_completion(&host->cmd_done);
2822 +
2823 + sdr_set_bits(MSDC_INTEN, wints);
2824 + sdc_send_cmd(rawcmd, cmd->arg);
2825 +
2826 +end:
2827 + return cmd->error;
2828 +}
2829 +
2830 +static unsigned int msdc_command_resp(struct msdc_host *host,
2831 + struct mmc_command *cmd,
2832 + int tune,
2833 + unsigned long timeout)
2834 +{
2835 + u32 base = host->base;
2836 + u32 opcode = cmd->opcode;
2837 + //u32 rawcmd;
2838 + u32 resp;
2839 + u32 wints = MSDC_INT_CMDRDY | MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO |
2840 + MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR | MSDC_INT_ACMDTMO |
2841 + MSDC_INT_ACMD19_DONE;
2842 +
2843 + resp = host->cmd_rsp;
2844 +
2845 + BUG_ON(in_interrupt());
2846 + //init_completion(&host->cmd_done);
2847 + //sdr_set_bits(MSDC_INTEN, wints);
2848 +
2849 + spin_unlock(&host->lock);
2850 + if(!wait_for_completion_timeout(&host->cmd_done, 10*timeout)){
2851 + ERR_MSG("XXX CMD<%d> wait_for_completion timeout ARG<0x%.8x>", opcode, cmd->arg);
2852 + cmd->error = (unsigned int)-ETIMEDOUT;
2853 + msdc_reset();
2854 + }
2855 + spin_lock(&host->lock);
2856 +
2857 + sdr_clr_bits(MSDC_INTEN, wints);
2858 + host->cmd = NULL;
2859 +
2860 +//end:
2861 +#ifdef MT6575_SD_DEBUG
2862 + switch (resp) {
2863 + case RESP_NONE:
2864 + N_MSG(RSP, "CMD_RSP(%d): %d RSP(%d)", opcode, cmd->error, resp);
2865 + break;
2866 + case RESP_R2:
2867 + N_MSG(RSP, "CMD_RSP(%d): %d RSP(%d)= %.8x %.8x %.8x %.8x",
2868 + opcode, cmd->error, resp, cmd->resp[0], cmd->resp[1],
2869 + cmd->resp[2], cmd->resp[3]);
2870 + break;
2871 + default: /* Response types 1, 3, 4, 5, 6, 7(1b) */
2872 + N_MSG(RSP, "CMD_RSP(%d): %d RSP(%d)= 0x%.8x",
2873 + opcode, cmd->error, resp, cmd->resp[0]);
2874 + if (cmd->error == 0) {
2875 + switch (resp) {
2876 + case RESP_R1:
2877 + case RESP_R1B:
2878 + msdc_dump_card_status(host, cmd->resp[0]);
2879 + break;
2880 + case RESP_R3:
2881 + msdc_dump_ocr_reg(host, cmd->resp[0]);
2882 + break;
2883 + case RESP_R5:
2884 + msdc_dump_io_resp(host, cmd->resp[0]);
2885 + break;
2886 + case RESP_R6:
2887 + msdc_dump_rca_resp(host, cmd->resp[0]);
2888 + break;
2889 + }
2890 + }
2891 + break;
2892 + }
2893 +#endif
2894 +
2895 + /* do we need to save card's RCA when SD_SEND_RELATIVE_ADDR */
2896 +
2897 + if (!tune) {
2898 + return cmd->error;
2899 + }
2900 +
2901 + /* memory card CRC */
2902 + if(host->hw->flags & MSDC_REMOVABLE && cmd->error == (unsigned int)(-EIO) ) {
2903 + if (sdr_read32(SDC_CMD) & 0x1800) { /* check if has data phase */
2904 + msdc_abort_data(host);
2905 + } else {
2906 + /* do basic: reset*/
2907 + msdc_reset();
2908 + msdc_clr_fifo();
2909 + msdc_clr_int();
2910 + }
2911 + cmd->error = msdc_tune_cmdrsp(host,cmd);
2912 + }
2913 +
2914 + // check DAT0
2915 + /* if (resp == RESP_R1B) {
2916 + while ((sdr_read32(MSDC_PS) & 0x10000) != 0x10000);
2917 + } */
2918 + /* CMD12 Error Handle */
2919 +
2920 + return cmd->error;
2921 +}
2922 +
2923 +static unsigned int msdc_do_command(struct msdc_host *host,
2924 + struct mmc_command *cmd,
2925 + int tune,
2926 + unsigned long timeout)
2927 +{
2928 + if (msdc_command_start(host, cmd, tune, timeout))
2929 + goto end;
2930 +
2931 + if (msdc_command_resp(host, cmd, tune, timeout))
2932 + goto end;
2933 +
2934 +end:
2935 +
2936 + N_MSG(CMD, " return<%d> resp<0x%.8x>", cmd->error, cmd->resp[0]);
2937 + return cmd->error;
2938 +}
2939 +
2940 +/* The abort condition when PIO read/write
2941 + tmo:
2942 +*/
2943 +static int msdc_pio_abort(struct msdc_host *host, struct mmc_data *data, unsigned long tmo)
2944 +{
2945 + int ret = 0;
2946 + u32 base = host->base;
2947 +
2948 + if (atomic_read(&host->abort)) {
2949 + ret = 1;
2950 + }
2951 +
2952 + if (time_after(jiffies, tmo)) {
2953 + data->error = (unsigned int)-ETIMEDOUT;
2954 + ERR_MSG("XXX PIO Data Timeout: CMD<%d>", host->mrq->cmd->opcode);
2955 + ret = 1;
2956 + }
2957 +
2958 + if(ret) {
2959 + msdc_reset();
2960 + msdc_clr_fifo();
2961 + msdc_clr_int();
2962 + ERR_MSG("msdc pio find abort");
2963 + }
2964 + return ret;
2965 +}
2966 +
2967 +/*
2968 + Need to add a timeout, or WDT timeout, system reboot.
2969 +*/
2970 +// pio mode data read/write
2971 +static int msdc_pio_read(struct msdc_host *host, struct mmc_data *data)
2972 +{
2973 + struct scatterlist *sg = data->sg;
2974 + u32 base = host->base;
2975 + u32 num = data->sg_len;
2976 + u32 *ptr;
2977 + u8 *u8ptr;
2978 + u32 left = 0;
2979 + u32 count, size = 0;
2980 + u32 wints = MSDC_INTEN_DATTMO | MSDC_INTEN_DATCRCERR ;
2981 + unsigned long tmo = jiffies + DAT_TIMEOUT;
2982 +
2983 + sdr_set_bits(MSDC_INTEN, wints);
2984 + while (num) {
2985 + left = sg_dma_len(sg);
2986 + ptr = sg_virt(sg);
2987 + while (left) {
2988 + if ((left >= MSDC_FIFO_THD) && (msdc_rxfifocnt() >= MSDC_FIFO_THD)) {
2989 + count = MSDC_FIFO_THD >> 2;
2990 + do {
2991 + *ptr++ = msdc_fifo_read32();
2992 + } while (--count);
2993 + left -= MSDC_FIFO_THD;
2994 + } else if ((left < MSDC_FIFO_THD) && msdc_rxfifocnt() >= left) {
2995 + while (left > 3) {
2996 + *ptr++ = msdc_fifo_read32();
2997 + left -= 4;
2998 + }
2999 +
3000 + u8ptr = (u8 *)ptr;
3001 + while(left) {
3002 + * u8ptr++ = msdc_fifo_read8();
3003 + left--;
3004 + }
3005 + }
3006 +
3007 + if (msdc_pio_abort(host, data, tmo)) {
3008 + goto end;
3009 + }
3010 + }
3011 + size += sg_dma_len(sg);
3012 + sg = sg_next(sg); num--;
3013 + }
3014 +end:
3015 + data->bytes_xfered += size;
3016 + N_MSG(FIO, " PIO Read<%d>bytes", size);
3017 +
3018 + sdr_clr_bits(MSDC_INTEN, wints);
3019 + if(data->error) ERR_MSG("read pio data->error<%d> left<%d> size<%d>", data->error, left, size);
3020 + return data->error;
3021 +}
3022 +
3023 +/* please make sure won't using PIO when size >= 512
3024 + which means, memory card block read/write won't using pio
3025 + then don't need to handle the CMD12 when data error.
3026 +*/
3027 +static int msdc_pio_write(struct msdc_host* host, struct mmc_data *data)
3028 +{
3029 + u32 base = host->base;
3030 + struct scatterlist *sg = data->sg;
3031 + u32 num = data->sg_len;
3032 + u32 *ptr;
3033 + u8 *u8ptr;
3034 + u32 left;
3035 + u32 count, size = 0;
3036 + u32 wints = MSDC_INTEN_DATTMO | MSDC_INTEN_DATCRCERR ;
3037 + unsigned long tmo = jiffies + DAT_TIMEOUT;
3038 +
3039 + sdr_set_bits(MSDC_INTEN, wints);
3040 + while (num) {
3041 + left = sg_dma_len(sg);
3042 + ptr = sg_virt(sg);
3043 +
3044 + while (left) {
3045 + if (left >= MSDC_FIFO_SZ && msdc_txfifocnt() == 0) {
3046 + count = MSDC_FIFO_SZ >> 2;
3047 + do {
3048 + msdc_fifo_write32(*ptr); ptr++;
3049 + } while (--count);
3050 + left -= MSDC_FIFO_SZ;
3051 + } else if (left < MSDC_FIFO_SZ && msdc_txfifocnt() == 0) {
3052 + while (left > 3) {
3053 + msdc_fifo_write32(*ptr); ptr++;
3054 + left -= 4;
3055 + }
3056 +
3057 + u8ptr = (u8*)ptr;
3058 + while(left){
3059 + msdc_fifo_write8(*u8ptr); u8ptr++;
3060 + left--;
3061 + }
3062 + }
3063 +
3064 + if (msdc_pio_abort(host, data, tmo)) {
3065 + goto end;
3066 + }
3067 + }
3068 + size += sg_dma_len(sg);
3069 + sg = sg_next(sg); num--;
3070 + }
3071 +end:
3072 + data->bytes_xfered += size;
3073 + N_MSG(FIO, " PIO Write<%d>bytes", size);
3074 + if(data->error) ERR_MSG("write pio data->error<%d>", data->error);
3075 +
3076 + sdr_clr_bits(MSDC_INTEN, wints);
3077 + return data->error;
3078 +}
3079 +
3080 +#if 0 /* --- by chhung */
3081 +// DMA resume / start / stop
3082 +static void msdc_dma_resume(struct msdc_host *host)
3083 +{
3084 + u32 base = host->base;
3085 +
3086 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_RESUME, 1);
3087 +
3088 + N_MSG(DMA, "DMA resume");
3089 +}
3090 +#endif /* end of --- */
3091 +
3092 +static void msdc_dma_start(struct msdc_host *host)
3093 +{
3094 + u32 base = host->base;
3095 + u32 wints = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | MSDC_INTEN_DATCRCERR ;
3096 +
3097 + sdr_set_bits(MSDC_INTEN, wints);
3098 + //dsb(); /* --- by chhung */
3099 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1);
3100 +
3101 + N_MSG(DMA, "DMA start");
3102 +}
3103 +
3104 +static void msdc_dma_stop(struct msdc_host *host)
3105 +{
3106 + u32 base = host->base;
3107 + //u32 retries=500;
3108 + u32 wints = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | MSDC_INTEN_DATCRCERR ;
3109 +
3110 + N_MSG(DMA, "DMA status: 0x%.8x",sdr_read32(MSDC_DMA_CFG));
3111 + //while (sdr_read32(MSDC_DMA_CFG) & MSDC_DMA_CFG_STS);
3112 +
3113 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, 1);
3114 + while (sdr_read32(MSDC_DMA_CFG) & MSDC_DMA_CFG_STS);
3115 +
3116 + //dsb(); /* --- by chhung */
3117 + sdr_clr_bits(MSDC_INTEN, wints); /* Not just xfer_comp */
3118 +
3119 + N_MSG(DMA, "DMA stop");
3120 +}
3121 +
3122 +#if 0 /* --- by chhung */
3123 +/* dump a gpd list */
3124 +static void msdc_dma_dump(struct msdc_host *host, struct msdc_dma *dma)
3125 +{
3126 + gpd_t *gpd = dma->gpd;
3127 + bd_t *bd = dma->bd;
3128 + bd_t *ptr;
3129 + int i = 0;
3130 + int p_to_v;
3131 +
3132 + if (dma->mode != MSDC_MODE_DMA_DESC) {
3133 + return;
3134 + }
3135 +
3136 + ERR_MSG("try to dump gpd and bd");
3137 +
3138 + /* dump gpd */
3139 + ERR_MSG(".gpd<0x%.8x> gpd_phy<0x%.8x>", (int)gpd, (int)dma->gpd_addr);
3140 + ERR_MSG("...hwo <%d>", gpd->hwo );
3141 + ERR_MSG("...bdp <%d>", gpd->bdp );
3142 + ERR_MSG("...chksum<0x%.8x>", gpd->chksum );
3143 + //ERR_MSG("...intr <0x%.8x>", gpd->intr );
3144 + ERR_MSG("...next <0x%.8x>", (int)gpd->next );
3145 + ERR_MSG("...ptr <0x%.8x>", (int)gpd->ptr );
3146 + ERR_MSG("...buflen<0x%.8x>", gpd->buflen );
3147 + //ERR_MSG("...extlen<0x%.8x>", gpd->extlen );
3148 + //ERR_MSG("...arg <0x%.8x>", gpd->arg );
3149 + //ERR_MSG("...blknum<0x%.8x>", gpd->blknum );
3150 + //ERR_MSG("...cmd <0x%.8x>", gpd->cmd );
3151 +
3152 + /* dump bd */
3153 + ERR_MSG(".bd<0x%.8x> bd_phy<0x%.8x> gpd_ptr<0x%.8x>", (int)bd, (int)dma->bd_addr, (int)gpd->ptr);
3154 + ptr = bd;
3155 + p_to_v = ((u32)bd - (u32)dma->bd_addr);
3156 + while (1) {
3157 + ERR_MSG(".bd[%d]", i); i++;
3158 + ERR_MSG("...eol <%d>", ptr->eol );
3159 + ERR_MSG("...chksum<0x%.8x>", ptr->chksum );
3160 + //ERR_MSG("...blkpad<0x%.8x>", ptr->blkpad );
3161 + //ERR_MSG("...dwpad <0x%.8x>", ptr->dwpad );
3162 + ERR_MSG("...next <0x%.8x>", (int)ptr->next );
3163 + ERR_MSG("...ptr <0x%.8x>", (int)ptr->ptr );
3164 + ERR_MSG("...buflen<0x%.8x>", (int)ptr->buflen );
3165 +
3166 + if (ptr->eol == 1) {
3167 + break;
3168 + }
3169 +
3170 + /* find the next bd, virtual address of ptr->next */
3171 + /* don't need to enable when use malloc */
3172 + //BUG_ON( (ptr->next + p_to_v)!=(ptr+1) );
3173 + //ERR_MSG(".next bd<0x%.8x><0x%.8x>", (ptr->next + p_to_v), (ptr+1));
3174 + ptr++;
3175 + }
3176 +
3177 + ERR_MSG("dump gpd and bd finished");
3178 +}
3179 +#endif /* end of --- */
3180 +
3181 +/* calc checksum */
3182 +static u8 msdc_dma_calcs(u8 *buf, u32 len)
3183 +{
3184 + u32 i, sum = 0;
3185 + for (i = 0; i < len; i++) {
3186 + sum += buf[i];
3187 + }
3188 + return 0xFF - (u8)sum;
3189 +}
3190 +
3191 +/* gpd bd setup + dma registers */
3192 +static int msdc_dma_config(struct msdc_host *host, struct msdc_dma *dma)
3193 +{
3194 + u32 base = host->base;
3195 + u32 sglen = dma->sglen;
3196 + //u32 i, j, num, bdlen, arg, xfersz;
3197 + u32 j, num, bdlen;
3198 + u8 blkpad, dwpad, chksum;
3199 + struct scatterlist *sg = dma->sg;
3200 + gpd_t *gpd;
3201 + bd_t *bd;
3202 +
3203 + switch (dma->mode) {
3204 + case MSDC_MODE_DMA_BASIC:
3205 + BUG_ON(dma->xfersz > 65535);
3206 + BUG_ON(dma->sglen != 1);
3207 + sdr_write32(MSDC_DMA_SA, PHYSADDR(sg_dma_address(sg)));
3208 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_LASTBUF, 1);
3209 +//#if defined (CONFIG_RALINK_MT7620)
3210 + if (ralink_soc == MT762X_SOC_MT7620A)
3211 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_XFERSZ, sg_dma_len(sg));
3212 +//#elif defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628)
3213 + else
3214 + sdr_write32((volatile u32*)(RALINK_MSDC_BASE+0xa8), sg_dma_len(sg));
3215 +//#endif
3216 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_BRUSTSZ, dma->burstsz);
3217 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_MODE, 0);
3218 + break;
3219 + case MSDC_MODE_DMA_DESC:
3220 + blkpad = (dma->flags & DMA_FLAG_PAD_BLOCK) ? 1 : 0;
3221 + dwpad = (dma->flags & DMA_FLAG_PAD_DWORD) ? 1 : 0;
3222 + chksum = (dma->flags & DMA_FLAG_EN_CHKSUM) ? 1 : 0;
3223 +
3224 + /* calculate the required number of gpd */
3225 + num = (sglen + MAX_BD_PER_GPD - 1) / MAX_BD_PER_GPD;
3226 + BUG_ON(num !=1 );
3227 +
3228 + gpd = dma->gpd;
3229 + bd = dma->bd;
3230 + bdlen = sglen;
3231 +
3232 + /* modify gpd*/
3233 + //gpd->intr = 0;
3234 + gpd->hwo = 1; /* hw will clear it */
3235 + gpd->bdp = 1;
3236 + gpd->chksum = 0; /* need to clear first. */
3237 + gpd->chksum = (chksum ? msdc_dma_calcs((u8 *)gpd, 16) : 0);
3238 +
3239 + /* modify bd*/
3240 + for (j = 0; j < bdlen; j++) {
3241 + msdc_init_bd(&bd[j], blkpad, dwpad, sg_dma_address(sg), sg_dma_len(sg));
3242 + if(j == bdlen - 1) {
3243 + bd[j].eol = 1; /* the last bd */
3244 + } else {
3245 + bd[j].eol = 0;
3246 + }
3247 + bd[j].chksum = 0; /* checksume need to clear first */
3248 + bd[j].chksum = (chksum ? msdc_dma_calcs((u8 *)(&bd[j]), 16) : 0);
3249 + sg++;
3250 + }
3251 +
3252 + dma->used_gpd += 2;
3253 + dma->used_bd += bdlen;
3254 +
3255 + sdr_set_field(MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, chksum);
3256 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_BRUSTSZ, dma->burstsz);
3257 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_MODE, 1);
3258 +
3259 + sdr_write32(MSDC_DMA_SA, PHYSADDR((u32)dma->gpd_addr));
3260 + break;
3261 +
3262 + default:
3263 + break;
3264 + }
3265 +
3266 + N_MSG(DMA, "DMA_CTRL = 0x%x", sdr_read32(MSDC_DMA_CTRL));
3267 + N_MSG(DMA, "DMA_CFG = 0x%x", sdr_read32(MSDC_DMA_CFG));
3268 + N_MSG(DMA, "DMA_SA = 0x%x", sdr_read32(MSDC_DMA_SA));
3269 +
3270 + return 0;
3271 +}
3272 +
3273 +static void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma,
3274 + struct scatterlist *sg, unsigned int sglen)
3275 +{
3276 + BUG_ON(sglen > MAX_BD_NUM); /* not support currently */
3277 +
3278 + dma->sg = sg;
3279 + dma->flags = DMA_FLAG_EN_CHKSUM;
3280 + //dma->flags = DMA_FLAG_NONE; /* CHECKME */
3281 + dma->sglen = sglen;
3282 + dma->xfersz = host->xfer_size;
3283 + dma->burstsz = MSDC_BRUST_64B;
3284 +
3285 + if (sglen == 1 && sg_dma_len(sg) <= MAX_DMA_CNT)
3286 + dma->mode = MSDC_MODE_DMA_BASIC;
3287 + else
3288 + dma->mode = MSDC_MODE_DMA_DESC;
3289 +
3290 + N_MSG(DMA, "DMA mode<%d> sglen<%d> xfersz<%d>", dma->mode, dma->sglen, dma->xfersz);
3291 +
3292 + msdc_dma_config(host, dma);
3293 +
3294 + /*if (dma->mode == MSDC_MODE_DMA_DESC) {
3295 + //msdc_dma_dump(host, dma);
3296 + } */
3297 +}
3298 +
3299 +/* set block number before send command */
3300 +static void msdc_set_blknum(struct msdc_host *host, u32 blknum)
3301 +{
3302 + u32 base = host->base;
3303 +
3304 + sdr_write32(SDC_BLK_NUM, blknum);
3305 +}
3306 +
3307 +static int msdc_do_request(struct mmc_host*mmc, struct mmc_request*mrq)
3308 +{
3309 + struct msdc_host *host = mmc_priv(mmc);
3310 + struct mmc_command *cmd;
3311 + struct mmc_data *data;
3312 + u32 base = host->base;
3313 + //u32 intsts = 0;
3314 + unsigned int left=0;
3315 + int dma = 0, read = 1, dir = DMA_FROM_DEVICE, send_type=0;
3316 +
3317 + #define SND_DAT 0
3318 + #define SND_CMD 1
3319 +
3320 + BUG_ON(mmc == NULL);
3321 + BUG_ON(mrq == NULL);
3322 +
3323 + host->error = 0;
3324 + atomic_set(&host->abort, 0);
3325 +
3326 + cmd = mrq->cmd;
3327 + data = mrq->cmd->data;
3328 +
3329 +#if 0 /* --- by chhung */
3330 + //if(host->id ==1){
3331 + N_MSG(OPS, "enable clock!");
3332 + msdc_ungate_clock(host->id);
3333 + //}
3334 +#endif /* end of --- */
3335 +
3336 + if (!data) {
3337 + send_type=SND_CMD;
3338 + if (msdc_do_command(host, cmd, 1, CMD_TIMEOUT) != 0) {
3339 + goto done;
3340 + }
3341 + } else {
3342 + BUG_ON(data->blksz > HOST_MAX_BLKSZ);
3343 + send_type=SND_DAT;
3344 +
3345 + data->error = 0;
3346 + read = data->flags & MMC_DATA_READ ? 1 : 0;
3347 + host->data = data;
3348 + host->xfer_size = data->blocks * data->blksz;
3349 + host->blksz = data->blksz;
3350 +
3351 + /* deside the transfer mode */
3352 + if (drv_mode[host->id] == MODE_PIO) {
3353 + host->dma_xfer = dma = 0;
3354 + } else if (drv_mode[host->id] == MODE_DMA) {
3355 + host->dma_xfer = dma = 1;
3356 + } else if (drv_mode[host->id] == MODE_SIZE_DEP) {
3357 + host->dma_xfer = dma = ((host->xfer_size >= dma_size[host->id]) ? 1 : 0);
3358 + }
3359 +
3360 + if (read) {
3361 + if ((host->timeout_ns != data->timeout_ns) ||
3362 + (host->timeout_clks != data->timeout_clks)) {
3363 + msdc_set_timeout(host, data->timeout_ns, data->timeout_clks);
3364 + }
3365 + }
3366 +
3367 + msdc_set_blknum(host, data->blocks);
3368 + //msdc_clr_fifo(); /* no need */
3369 +
3370 + if (dma) {
3371 + msdc_dma_on(); /* enable DMA mode first!! */
3372 + init_completion(&host->xfer_done);
3373 +
3374 + /* start the command first*/
3375 + if (msdc_command_start(host, cmd, 1, CMD_TIMEOUT) != 0)
3376 + goto done;
3377 +
3378 + dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
3379 + (void)dma_map_sg(mmc_dev(mmc), data->sg, data->sg_len, dir);
3380 + msdc_dma_setup(host, &host->dma, data->sg, data->sg_len);
3381 +
3382 + /* then wait command done */
3383 + if (msdc_command_resp(host, cmd, 1, CMD_TIMEOUT) != 0)
3384 + goto done;
3385 +
3386 + /* for read, the data coming too fast, then CRC error
3387 + start DMA no business with CRC. */
3388 + //init_completion(&host->xfer_done);
3389 + msdc_dma_start(host);
3390 +
3391 + spin_unlock(&host->lock);
3392 + if(!wait_for_completion_timeout(&host->xfer_done, DAT_TIMEOUT)){
3393 + ERR_MSG("XXX CMD<%d> wait xfer_done<%d> timeout!!", cmd->opcode, data->blocks * data->blksz);
3394 + ERR_MSG(" DMA_SA = 0x%x", sdr_read32(MSDC_DMA_SA));
3395 + ERR_MSG(" DMA_CA = 0x%x", sdr_read32(MSDC_DMA_CA));
3396 + ERR_MSG(" DMA_CTRL = 0x%x", sdr_read32(MSDC_DMA_CTRL));
3397 + ERR_MSG(" DMA_CFG = 0x%x", sdr_read32(MSDC_DMA_CFG));
3398 + data->error = (unsigned int)-ETIMEDOUT;
3399 +
3400 + msdc_reset();
3401 + msdc_clr_fifo();
3402 + msdc_clr_int();
3403 + }
3404 + spin_lock(&host->lock);
3405 + msdc_dma_stop(host);
3406 + } else {
3407 + /* Firstly: send command */
3408 + if (msdc_do_command(host, cmd, 1, CMD_TIMEOUT) != 0) {
3409 + goto done;
3410 + }
3411 +
3412 + /* Secondly: pio data phase */
3413 + if (read) {
3414 + if (msdc_pio_read(host, data)){
3415 + goto done;
3416 + }
3417 + } else {
3418 + if (msdc_pio_write(host, data)) {
3419 + goto done;
3420 + }
3421 + }
3422 +
3423 + /* For write case: make sure contents in fifo flushed to device */
3424 + if (!read) {
3425 + while (1) {
3426 + left=msdc_txfifocnt();
3427 + if (left == 0) {
3428 + break;
3429 + }
3430 + if (msdc_pio_abort(host, data, jiffies + DAT_TIMEOUT)) {
3431 + break;
3432 + /* Fix me: what about if data error, when stop ? how to? */
3433 + }
3434 + }
3435 + } else {
3436 + /* Fix me: read case: need to check CRC error */
3437 + }
3438 +
3439 + /* For write case: SDCBUSY and Xfer_Comp will assert when DAT0 not busy.
3440 + For read case : SDCBUSY and Xfer_Comp will assert when last byte read out from FIFO.
3441 + */
3442 +
3443 + /* try not to wait xfer_comp interrupt.
3444 + the next command will check SDC_BUSY.
3445 + SDC_BUSY means xfer_comp assert
3446 + */
3447 +
3448 + } // PIO mode
3449 +
3450 + /* Last: stop transfer */
3451 + if (data->stop){
3452 + if (msdc_do_command(host, data->stop, 0, CMD_TIMEOUT) != 0) {
3453 + goto done;
3454 + }
3455 + }
3456 + }
3457 +
3458 +done:
3459 + if (data != NULL) {
3460 + host->data = NULL;
3461 + host->dma_xfer = 0;
3462 + if (dma != 0) {
3463 + msdc_dma_off();
3464 + host->dma.used_bd = 0;
3465 + host->dma.used_gpd = 0;
3466 + dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len, dir);
3467 + }
3468 + host->blksz = 0;
3469 +
3470 +#if 0 // don't stop twice!
3471 + if(host->hw->flags & MSDC_REMOVABLE && data->error) {
3472 + msdc_abort_data(host);
3473 + /* reset in IRQ, stop command has issued. -> No need */
3474 + }
3475 +#endif
3476 +
3477 + N_MSG(OPS, "CMD<%d> data<%s %s> blksz<%d> block<%d> error<%d>",cmd->opcode, (dma? "dma":"pio"),
3478 + (read ? "read ":"write") ,data->blksz, data->blocks, data->error);
3479 + }
3480 +
3481 +#if 0 /* --- by chhung */
3482 +#if 1
3483 + //if(host->id==1) {
3484 + if(send_type==SND_CMD) {
3485 + if(cmd->opcode == MMC_SEND_STATUS) {
3486 + if((cmd->resp[0] & CARD_READY_FOR_DATA) ||(CARD_CURRENT_STATE(cmd->resp[0]) != 7)){
3487 + N_MSG(OPS,"disable clock, CMD13 IDLE");
3488 + msdc_gate_clock(host->id);
3489 + }
3490 + } else {
3491 + N_MSG(OPS,"disable clock, CMD<%d>", cmd->opcode);
3492 + msdc_gate_clock(host->id);
3493 + }
3494 + } else {
3495 + if(read) {
3496 + N_MSG(OPS,"disable clock!!! Read CMD<%d>",cmd->opcode);
3497 + msdc_gate_clock(host->id);
3498 + }
3499 + }
3500 + //}
3501 +#else
3502 + msdc_gate_clock(host->id);
3503 +#endif
3504 +#endif /* end of --- */
3505 +
3506 + if (mrq->cmd->error) host->error = 0x001;
3507 + if (mrq->data && mrq->data->error) host->error |= 0x010;
3508 + if (mrq->stop && mrq->stop->error) host->error |= 0x100;
3509 +
3510 + //if (host->error) ERR_MSG("host->error<%d>", host->error);
3511 +
3512 + return host->error;
3513 +}
3514 +
3515 +static int msdc_app_cmd(struct mmc_host *mmc, struct msdc_host *host)
3516 +{
3517 + struct mmc_command cmd;
3518 + struct mmc_request mrq;
3519 + u32 err;
3520 +
3521 + memset(&cmd, 0, sizeof(struct mmc_command));
3522 + cmd.opcode = MMC_APP_CMD;
3523 +#if 0 /* bug: we meet mmc->card is null when ACMD6 */
3524 + cmd.arg = mmc->card->rca << 16;
3525 +#else
3526 + cmd.arg = host->app_cmd_arg;
3527 +#endif
3528 + cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_R1 | MMC_CMD_AC;
3529 +
3530 + memset(&mrq, 0, sizeof(struct mmc_request));
3531 + mrq.cmd = &cmd; cmd.mrq = &mrq;
3532 + cmd.data = NULL;
3533 +
3534 + err = msdc_do_command(host, &cmd, 0, CMD_TIMEOUT);
3535 + return err;
3536 +}
3537 +
3538 +static int msdc_tune_cmdrsp(struct msdc_host*host, struct mmc_command *cmd)
3539 +{
3540 + int result = -1;
3541 + u32 base = host->base;
3542 + u32 rsmpl, cur_rsmpl, orig_rsmpl;
3543 + u32 rrdly, cur_rrdly = 0xffffffff, orig_rrdly;
3544 + u32 skip = 1;
3545 +
3546 + /* ==== don't support 3.0 now ====
3547 + 1: R_SMPL[1]
3548 + 2: PAD_CMD_RESP_RXDLY[26:22]
3549 + ==========================*/
3550 +
3551 + // save the previous tune result
3552 + sdr_get_field(MSDC_IOCON, MSDC_IOCON_RSPL, orig_rsmpl);
3553 + sdr_get_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRRDLY, orig_rrdly);
3554 +
3555 + rrdly = 0;
3556 + do {
3557 + for (rsmpl = 0; rsmpl < 2; rsmpl++) {
3558 + /* Lv1: R_SMPL[1] */
3559 + cur_rsmpl = (orig_rsmpl + rsmpl) % 2;
3560 + if (skip == 1) {
3561 + skip = 0;
3562 + continue;
3563 + }
3564 + sdr_set_field(MSDC_IOCON, MSDC_IOCON_RSPL, cur_rsmpl);
3565 +
3566 + if (host->app_cmd) {
3567 + result = msdc_app_cmd(host->mmc, host);
3568 + if (result) {
3569 + ERR_MSG("TUNE_CMD app_cmd<%d> failed: RESP_RXDLY<%d>,R_SMPL<%d>",
3570 + host->mrq->cmd->opcode, cur_rrdly, cur_rsmpl);
3571 + continue;
3572 + }
3573 + }
3574 + result = msdc_do_command(host, cmd, 0, CMD_TIMEOUT); // not tune.
3575 + ERR_MSG("TUNE_CMD<%d> %s PAD_CMD_RESP_RXDLY[26:22]<%d> R_SMPL[1]<%d>", cmd->opcode,
3576 + (result == 0) ? "PASS" : "FAIL", cur_rrdly, cur_rsmpl);
3577 +
3578 + if (result == 0) {
3579 + return 0;
3580 + }
3581 + if (result != (unsigned int)(-EIO)) {
3582 + ERR_MSG("TUNE_CMD<%d> Error<%d> not -EIO", cmd->opcode, result);
3583 + return result;
3584 + }
3585 +
3586 + /* should be EIO */
3587 + if (sdr_read32(SDC_CMD) & 0x1800) { /* check if has data phase */
3588 + msdc_abort_data(host);
3589 + }
3590 + }
3591 +
3592 + /* Lv2: PAD_CMD_RESP_RXDLY[26:22] */
3593 + cur_rrdly = (orig_rrdly + rrdly + 1) % 32;
3594 + sdr_set_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRRDLY, cur_rrdly);
3595 + }while (++rrdly < 32);
3596 +
3597 + return result;
3598 +}
3599 +
3600 +/* Support SD2.0 Only */
3601 +static int msdc_tune_bread(struct mmc_host *mmc, struct mmc_request *mrq)
3602 +{
3603 + struct msdc_host *host = mmc_priv(mmc);
3604 + u32 base = host->base;
3605 + u32 ddr=0;
3606 + u32 dcrc=0;
3607 + u32 rxdly, cur_rxdly0, cur_rxdly1;
3608 + u32 dsmpl, cur_dsmpl, orig_dsmpl;
3609 + u32 cur_dat0, cur_dat1, cur_dat2, cur_dat3;
3610 + u32 cur_dat4, cur_dat5, cur_dat6, cur_dat7;
3611 + u32 orig_dat0, orig_dat1, orig_dat2, orig_dat3;
3612 + u32 orig_dat4, orig_dat5, orig_dat6, orig_dat7;
3613 + int result = -1;
3614 + u32 skip = 1;
3615 +
3616 + sdr_get_field(MSDC_IOCON, MSDC_IOCON_DSPL, orig_dsmpl);
3617 +
3618 + /* Tune Method 2. */
3619 + sdr_set_field(MSDC_IOCON, MSDC_IOCON_DDLSEL, 1);
3620 +
3621 + rxdly = 0;
3622 + do {
3623 + for (dsmpl = 0; dsmpl < 2; dsmpl++) {
3624 + cur_dsmpl = (orig_dsmpl + dsmpl) % 2;
3625 + if (skip == 1) {
3626 + skip = 0;
3627 + continue;
3628 + }
3629 + sdr_set_field(MSDC_IOCON, MSDC_IOCON_DSPL, cur_dsmpl);
3630 +
3631 + if (host->app_cmd) {
3632 + result = msdc_app_cmd(host->mmc, host);
3633 + if (result) {
3634 + ERR_MSG("TUNE_BREAD app_cmd<%d> failed", host->mrq->cmd->opcode);
3635 + continue;
3636 + }
3637 + }
3638 + result = msdc_do_request(mmc,mrq);
3639 +
3640 + sdr_get_field(SDC_DCRC_STS, SDC_DCRC_STS_POS|SDC_DCRC_STS_NEG, dcrc); /* RO */
3641 + if (!ddr) dcrc &= ~SDC_DCRC_STS_NEG;
3642 + ERR_MSG("TUNE_BREAD<%s> dcrc<0x%x> DATRDDLY0/1<0x%x><0x%x> dsmpl<0x%x>",
3643 + (result == 0 && dcrc == 0) ? "PASS" : "FAIL", dcrc,
3644 + sdr_read32(MSDC_DAT_RDDLY0), sdr_read32(MSDC_DAT_RDDLY1), cur_dsmpl);
3645 +
3646 + /* Fix me: result is 0, but dcrc is still exist */
3647 + if (result == 0 && dcrc == 0) {
3648 + goto done;
3649 + } else {
3650 + /* there is a case: command timeout, and data phase not processed */
3651 + if (mrq->data->error != 0 && mrq->data->error != (unsigned int)(-EIO)) {
3652 + ERR_MSG("TUNE_READ: result<0x%x> cmd_error<%d> data_error<%d>",
3653 + result, mrq->cmd->error, mrq->data->error);
3654 + goto done;
3655 + }
3656 + }
3657 + }
3658 +
3659 + cur_rxdly0 = sdr_read32(MSDC_DAT_RDDLY0);
3660 + cur_rxdly1 = sdr_read32(MSDC_DAT_RDDLY1);
3661 +
3662 + /* E1 ECO. YD: Reverse */
3663 + if (sdr_read32(MSDC_ECO_VER) >= 4) {
3664 + orig_dat0 = (cur_rxdly0 >> 24) & 0x1F;
3665 + orig_dat1 = (cur_rxdly0 >> 16) & 0x1F;
3666 + orig_dat2 = (cur_rxdly0 >> 8) & 0x1F;
3667 + orig_dat3 = (cur_rxdly0 >> 0) & 0x1F;
3668 + orig_dat4 = (cur_rxdly1 >> 24) & 0x1F;
3669 + orig_dat5 = (cur_rxdly1 >> 16) & 0x1F;
3670 + orig_dat6 = (cur_rxdly1 >> 8) & 0x1F;
3671 + orig_dat7 = (cur_rxdly1 >> 0) & 0x1F;
3672 + } else {
3673 + orig_dat0 = (cur_rxdly0 >> 0) & 0x1F;
3674 + orig_dat1 = (cur_rxdly0 >> 8) & 0x1F;
3675 + orig_dat2 = (cur_rxdly0 >> 16) & 0x1F;
3676 + orig_dat3 = (cur_rxdly0 >> 24) & 0x1F;
3677 + orig_dat4 = (cur_rxdly1 >> 0) & 0x1F;
3678 + orig_dat5 = (cur_rxdly1 >> 8) & 0x1F;
3679 + orig_dat6 = (cur_rxdly1 >> 16) & 0x1F;
3680 + orig_dat7 = (cur_rxdly1 >> 24) & 0x1F;
3681 + }
3682 +
3683 + if (ddr) {
3684 + cur_dat0 = (dcrc & (1 << 0) || dcrc & (1 << 8)) ? ((orig_dat0 + 1) % 32) : orig_dat0;
3685 + cur_dat1 = (dcrc & (1 << 1) || dcrc & (1 << 9)) ? ((orig_dat1 + 1) % 32) : orig_dat1;
3686 + cur_dat2 = (dcrc & (1 << 2) || dcrc & (1 << 10)) ? ((orig_dat2 + 1) % 32) : orig_dat2;
3687 + cur_dat3 = (dcrc & (1 << 3) || dcrc & (1 << 11)) ? ((orig_dat3 + 1) % 32) : orig_dat3;
3688 + } else {
3689 + cur_dat0 = (dcrc & (1 << 0)) ? ((orig_dat0 + 1) % 32) : orig_dat0;
3690 + cur_dat1 = (dcrc & (1 << 1)) ? ((orig_dat1 + 1) % 32) : orig_dat1;
3691 + cur_dat2 = (dcrc & (1 << 2)) ? ((orig_dat2 + 1) % 32) : orig_dat2;
3692 + cur_dat3 = (dcrc & (1 << 3)) ? ((orig_dat3 + 1) % 32) : orig_dat3;
3693 + }
3694 + cur_dat4 = (dcrc & (1 << 4)) ? ((orig_dat4 + 1) % 32) : orig_dat4;
3695 + cur_dat5 = (dcrc & (1 << 5)) ? ((orig_dat5 + 1) % 32) : orig_dat5;
3696 + cur_dat6 = (dcrc & (1 << 6)) ? ((orig_dat6 + 1) % 32) : orig_dat6;
3697 + cur_dat7 = (dcrc & (1 << 7)) ? ((orig_dat7 + 1) % 32) : orig_dat7;
3698 +
3699 + cur_rxdly0 = (cur_dat0 << 24) | (cur_dat1 << 16) | (cur_dat2 << 8) | (cur_dat3 << 0);
3700 + cur_rxdly1 = (cur_dat4 << 24) | (cur_dat5 << 16) | (cur_dat6 << 8) | (cur_dat7 << 0);
3701 +
3702 + sdr_write32(MSDC_DAT_RDDLY0, cur_rxdly0);
3703 + sdr_write32(MSDC_DAT_RDDLY1, cur_rxdly1);
3704 +
3705 + } while (++rxdly < 32);
3706 +
3707 +done:
3708 + return result;
3709 +}
3710 +
3711 +static int msdc_tune_bwrite(struct mmc_host *mmc,struct mmc_request *mrq)
3712 +{
3713 + struct msdc_host *host = mmc_priv(mmc);
3714 + u32 base = host->base;
3715 +
3716 + u32 wrrdly, cur_wrrdly = 0xffffffff, orig_wrrdly;
3717 + u32 dsmpl, cur_dsmpl, orig_dsmpl;
3718 + u32 rxdly, cur_rxdly0;
3719 + u32 orig_dat0, orig_dat1, orig_dat2, orig_dat3;
3720 + u32 cur_dat0, cur_dat1, cur_dat2, cur_dat3;
3721 + int result = -1;
3722 + u32 skip = 1;
3723 +
3724 + // MSDC_IOCON_DDR50CKD need to check. [Fix me]
3725 +
3726 + sdr_get_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_DATWRDLY, orig_wrrdly);
3727 + sdr_get_field(MSDC_IOCON, MSDC_IOCON_DSPL, orig_dsmpl );
3728 +
3729 + /* Tune Method 2. just DAT0 */
3730 + sdr_set_field(MSDC_IOCON, MSDC_IOCON_DDLSEL, 1);
3731 + cur_rxdly0 = sdr_read32(MSDC_DAT_RDDLY0);
3732 +
3733 + /* E1 ECO. YD: Reverse */
3734 + if (sdr_read32(MSDC_ECO_VER) >= 4) {
3735 + orig_dat0 = (cur_rxdly0 >> 24) & 0x1F;
3736 + orig_dat1 = (cur_rxdly0 >> 16) & 0x1F;
3737 + orig_dat2 = (cur_rxdly0 >> 8) & 0x1F;
3738 + orig_dat3 = (cur_rxdly0 >> 0) & 0x1F;
3739 + } else {
3740 + orig_dat0 = (cur_rxdly0 >> 0) & 0x1F;
3741 + orig_dat1 = (cur_rxdly0 >> 8) & 0x1F;
3742 + orig_dat2 = (cur_rxdly0 >> 16) & 0x1F;
3743 + orig_dat3 = (cur_rxdly0 >> 24) & 0x1F;
3744 + }
3745 +
3746 + rxdly = 0;
3747 + do {
3748 + wrrdly = 0;
3749 + do {
3750 + for (dsmpl = 0; dsmpl < 2; dsmpl++) {
3751 + cur_dsmpl = (orig_dsmpl + dsmpl) % 2;
3752 + if (skip == 1) {
3753 + skip = 0;
3754 + continue;
3755 + }
3756 + sdr_set_field(MSDC_IOCON, MSDC_IOCON_DSPL, cur_dsmpl);
3757 +
3758 + if (host->app_cmd) {
3759 + result = msdc_app_cmd(host->mmc, host);
3760 + if (result) {
3761 + ERR_MSG("TUNE_BWRITE app_cmd<%d> failed", host->mrq->cmd->opcode);
3762 + continue;
3763 + }
3764 + }
3765 + result = msdc_do_request(mmc,mrq);
3766 +
3767 + ERR_MSG("TUNE_BWRITE<%s> DSPL<%d> DATWRDLY<%d> MSDC_DAT_RDDLY0<0x%x>",
3768 + result == 0 ? "PASS" : "FAIL",
3769 + cur_dsmpl, cur_wrrdly, cur_rxdly0);
3770 +
3771 + if (result == 0) {
3772 + goto done;
3773 + }
3774 + else {
3775 + /* there is a case: command timeout, and data phase not processed */
3776 + if (mrq->data->error != (unsigned int)(-EIO)) {
3777 + ERR_MSG("TUNE_READ: result<0x%x> cmd_error<%d> data_error<%d>",
3778 + result, mrq->cmd->error, mrq->data->error);
3779 + goto done;
3780 + }
3781 + }
3782 + }
3783 + cur_wrrdly = (orig_wrrdly + wrrdly + 1) % 32;
3784 + sdr_set_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_DATWRDLY, cur_wrrdly);
3785 + } while (++wrrdly < 32);
3786 +
3787 + cur_dat0 = (orig_dat0 + rxdly) % 32; /* only adjust bit-1 for crc */
3788 + cur_dat1 = orig_dat1;
3789 + cur_dat2 = orig_dat2;
3790 + cur_dat3 = orig_dat3;
3791 +
3792 + cur_rxdly0 = (cur_dat0 << 24) | (cur_dat1 << 16) | (cur_dat2 << 8) | (cur_dat3 << 0);
3793 + sdr_write32(MSDC_DAT_RDDLY0, cur_rxdly0);
3794 + } while (++rxdly < 32);
3795 +
3796 +done:
3797 + return result;
3798 +}
3799 +
3800 +static int msdc_get_card_status(struct mmc_host *mmc, struct msdc_host *host, u32 *status)
3801 +{
3802 + struct mmc_command cmd;
3803 + struct mmc_request mrq;
3804 + u32 err;
3805 +
3806 + memset(&cmd, 0, sizeof(struct mmc_command));
3807 + cmd.opcode = MMC_SEND_STATUS;
3808 + if (mmc->card) {
3809 + cmd.arg = mmc->card->rca << 16;
3810 + } else {
3811 + ERR_MSG("cmd13 mmc card is null");
3812 + cmd.arg = host->app_cmd_arg;
3813 + }
3814 + cmd.flags = MMC_RSP_SPI_R2 | MMC_RSP_R1 | MMC_CMD_AC;
3815 +
3816 + memset(&mrq, 0, sizeof(struct mmc_request));
3817 + mrq.cmd = &cmd; cmd.mrq = &mrq;
3818 + cmd.data = NULL;
3819 +
3820 + err = msdc_do_command(host, &cmd, 1, CMD_TIMEOUT);
3821 +
3822 + if (status) {
3823 + *status = cmd.resp[0];
3824 + }
3825 +
3826 + return err;
3827 +}
3828 +
3829 +static int msdc_check_busy(struct mmc_host *mmc, struct msdc_host *host)
3830 +{
3831 + u32 err = 0;
3832 + u32 status = 0;
3833 +
3834 + do {
3835 + err = msdc_get_card_status(mmc, host, &status);
3836 + if (err) return err;
3837 + /* need cmd12? */
3838 + ERR_MSG("cmd<13> resp<0x%x>", status);
3839 + } while (R1_CURRENT_STATE(status) == 7);
3840 +
3841 + return err;
3842 +}
3843 +
3844 +/* failed when msdc_do_request */
3845 +static int msdc_tune_request(struct mmc_host *mmc, struct mmc_request *mrq)
3846 +{
3847 + struct msdc_host *host = mmc_priv(mmc);
3848 + struct mmc_command *cmd;
3849 + struct mmc_data *data;
3850 + //u32 base = host->base;
3851 + int ret=0, read;
3852 +
3853 + cmd = mrq->cmd;
3854 + data = mrq->cmd->data;
3855 +
3856 + read = data->flags & MMC_DATA_READ ? 1 : 0;
3857 +
3858 + if (read) {
3859 + if (data->error == (unsigned int)(-EIO)) {
3860 + ret = msdc_tune_bread(mmc,mrq);
3861 + }
3862 + } else {
3863 + ret = msdc_check_busy(mmc, host);
3864 + if (ret){
3865 + ERR_MSG("XXX cmd13 wait program done failed");
3866 + return ret;
3867 + }
3868 + /* CRC and TO */
3869 + /* Fix me: don't care card status? */
3870 + ret = msdc_tune_bwrite(mmc,mrq);
3871 + }
3872 +
3873 + return ret;
3874 +}
3875 +
3876 +/* ops.request */
3877 +static void msdc_ops_request(struct mmc_host *mmc,struct mmc_request *mrq)
3878 +{
3879 + struct msdc_host *host = mmc_priv(mmc);
3880 +
3881 + //=== for sdio profile ===
3882 +#if 0 /* --- by chhung */
3883 + u32 old_H32, old_L32, new_H32, new_L32;
3884 + u32 ticks = 0, opcode = 0, sizes = 0, bRx = 0;
3885 +#endif /* end of --- */
3886 +
3887 + if(host->mrq){
3888 + ERR_MSG("XXX host->mrq<0x%.8x>", (int)host->mrq);
3889 + BUG();
3890 + }
3891 +
3892 + if (!is_card_present(host) || host->power_mode == MMC_POWER_OFF) {
3893 + ERR_MSG("cmd<%d> card<%d> power<%d>", mrq->cmd->opcode, is_card_present(host), host->power_mode);
3894 + mrq->cmd->error = (unsigned int)-ENOMEDIUM;
3895 +
3896 +#if 1
3897 + mrq->done(mrq); // call done directly.
3898 +#else
3899 + mrq->cmd->retries = 0; // please don't retry.
3900 + mmc_request_done(mmc, mrq);
3901 +#endif
3902 +
3903 + return;
3904 + }
3905 +
3906 + /* start to process */
3907 + spin_lock(&host->lock);
3908 +#if 0 /* --- by chhung */
3909 + if (sdio_pro_enable) { //=== for sdio profile ===
3910 + if (mrq->cmd->opcode == 52 || mrq->cmd->opcode == 53) {
3911 + GPT_GetCounter64(&old_L32, &old_H32);
3912 + }
3913 + }
3914 +#endif /* end of --- */
3915 +
3916 + host->mrq = mrq;
3917 +
3918 + if (msdc_do_request(mmc,mrq)) {
3919 + if(host->hw->flags & MSDC_REMOVABLE && mrq->data && mrq->data->error) {
3920 + msdc_tune_request(mmc,mrq);
3921 + }
3922 + }
3923 +
3924 + /* ==== when request done, check if app_cmd ==== */
3925 + if (mrq->cmd->opcode == MMC_APP_CMD) {
3926 + host->app_cmd = 1;
3927 + host->app_cmd_arg = mrq->cmd->arg; /* save the RCA */
3928 + } else {
3929 + host->app_cmd = 0;
3930 + //host->app_cmd_arg = 0;
3931 + }
3932 +
3933 + host->mrq = NULL;
3934 +
3935 +#if 0 /* --- by chhung */
3936 + //=== for sdio profile ===
3937 + if (sdio_pro_enable) {
3938 + if (mrq->cmd->opcode == 52 || mrq->cmd->opcode == 53) {
3939 + GPT_GetCounter64(&new_L32, &new_H32);
3940 + ticks = msdc_time_calc(old_L32, old_H32, new_L32, new_H32);
3941 +
3942 + opcode = mrq->cmd->opcode;
3943 + if (mrq->cmd->data) {
3944 + sizes = mrq->cmd->data->blocks * mrq->cmd->data->blksz;
3945 + bRx = mrq->cmd->data->flags & MMC_DATA_READ ? 1 : 0 ;
3946 + } else {
3947 + bRx = mrq->cmd->arg & 0x80000000 ? 1 : 0;
3948 + }
3949 +
3950 + if (!mrq->cmd->error) {
3951 + msdc_performance(opcode, sizes, bRx, ticks);
3952 + }
3953 + }
3954 + }
3955 +#endif /* end of --- */
3956 + spin_unlock(&host->lock);
3957 +
3958 + mmc_request_done(mmc, mrq);
3959 +
3960 + return;
3961 +}
3962 +
3963 +/* called by ops.set_ios */
3964 +static void msdc_set_buswidth(struct msdc_host *host, u32 width)
3965 +{
3966 + u32 base = host->base;
3967 + u32 val = sdr_read32(SDC_CFG);
3968 +
3969 + val &= ~SDC_CFG_BUSWIDTH;
3970 +
3971 + switch (width) {
3972 + default:
3973 + case MMC_BUS_WIDTH_1:
3974 + width = 1;
3975 + val |= (MSDC_BUS_1BITS << 16);
3976 + break;
3977 + case MMC_BUS_WIDTH_4:
3978 + val |= (MSDC_BUS_4BITS << 16);
3979 + break;
3980 + case MMC_BUS_WIDTH_8:
3981 + val |= (MSDC_BUS_8BITS << 16);
3982 + break;
3983 + }
3984 +
3985 + sdr_write32(SDC_CFG, val);
3986 +
3987 + N_MSG(CFG, "Bus Width = %d", width);
3988 +}
3989 +
3990 +/* ops.set_ios */
3991 +static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
3992 +{
3993 + struct msdc_host *host = mmc_priv(mmc);
3994 + struct msdc_hw *hw=host->hw;
3995 + u32 base = host->base;
3996 + u32 ddr = 0;
3997 +
3998 +#ifdef MT6575_SD_DEBUG
3999 + static char *vdd[] = {
4000 + "1.50v", "1.55v", "1.60v", "1.65v", "1.70v", "1.80v", "1.90v",
4001 + "2.00v", "2.10v", "2.20v", "2.30v", "2.40v", "2.50v", "2.60v",
4002 + "2.70v", "2.80v", "2.90v", "3.00v", "3.10v", "3.20v", "3.30v",
4003 + "3.40v", "3.50v", "3.60v"
4004 + };
4005 + static char *power_mode[] = {
4006 + "OFF", "UP", "ON"
4007 + };
4008 + static char *bus_mode[] = {
4009 + "UNKNOWN", "OPENDRAIN", "PUSHPULL"
4010 + };
4011 + static char *timing[] = {
4012 + "LEGACY", "MMC_HS", "SD_HS"
4013 + };
4014 +
4015 + printk("SET_IOS: CLK(%dkHz), BUS(%s), BW(%u), PWR(%s), VDD(%s), TIMING(%s)",
4016 + ios->clock / 1000, bus_mode[ios->bus_mode],
4017 + (ios->bus_width == MMC_BUS_WIDTH_4) ? 4 : 1,
4018 + power_mode[ios->power_mode], vdd[ios->vdd], timing[ios->timing]);
4019 +#endif
4020 +
4021 + msdc_set_buswidth(host, ios->bus_width);
4022 +
4023 + /* Power control ??? */
4024 + switch (ios->power_mode) {
4025 + case MMC_POWER_OFF:
4026 + case MMC_POWER_UP:
4027 + // msdc_set_power_mode(host, ios->power_mode); /* --- by chhung */
4028 + break;
4029 + case MMC_POWER_ON:
4030 + host->power_mode = MMC_POWER_ON;
4031 + break;
4032 + default:
4033 + break;
4034 + }
4035 +
4036 + /* Clock control */
4037 + if (host->mclk != ios->clock) {
4038 + if(ios->clock > 25000000) {
4039 + //if (!(host->hw->flags & MSDC_REMOVABLE)) {
4040 + INIT_MSG("SD data latch edge<%d>", hw->data_edge);
4041 + sdr_set_field(MSDC_IOCON, MSDC_IOCON_RSPL, hw->cmd_edge);
4042 + sdr_set_field(MSDC_IOCON, MSDC_IOCON_DSPL, hw->data_edge);
4043 + //} /* for tuning debug */
4044 + } else { /* default value */
4045 + sdr_write32(MSDC_IOCON, 0x00000000);
4046 + // sdr_write32(MSDC_DAT_RDDLY0, 0x00000000);
4047 + sdr_write32(MSDC_DAT_RDDLY0, 0x10101010); // for MT7620 E2 and afterward
4048 + sdr_write32(MSDC_DAT_RDDLY1, 0x00000000);
4049 + // sdr_write32(MSDC_PAD_TUNE, 0x00000000);
4050 + sdr_write32(MSDC_PAD_TUNE, 0x84101010); // for MT7620 E2 and afterward
4051 + }
4052 + msdc_set_mclk(host, ddr, ios->clock);
4053 + }
4054 +}
4055 +
4056 +/* ops.get_ro */
4057 +static int msdc_ops_get_ro(struct mmc_host *mmc)
4058 +{
4059 + struct msdc_host *host = mmc_priv(mmc);
4060 + u32 base = host->base;
4061 + unsigned long flags;
4062 + int ro = 0;
4063 +
4064 + if (host->hw->flags & MSDC_WP_PIN_EN) { /* set for card */
4065 + spin_lock_irqsave(&host->lock, flags);
4066 + ro = (sdr_read32(MSDC_PS) >> 31);
4067 + spin_unlock_irqrestore(&host->lock, flags);
4068 + }
4069 + return ro;
4070 +}
4071 +
4072 +/* ops.get_cd */
4073 +static int msdc_ops_get_cd(struct mmc_host *mmc)
4074 +{
4075 + struct msdc_host *host = mmc_priv(mmc);
4076 + u32 base = host->base;
4077 + unsigned long flags;
4078 + int present = 1;
4079 +
4080 + /* for sdio, MSDC_REMOVABLE not set, always return 1 */
4081 + if (!(host->hw->flags & MSDC_REMOVABLE)) {
4082 + /* For sdio, read H/W always get<1>, but may timeout some times */
4083 +#if 1
4084 + host->card_inserted = 1;
4085 + return 1;
4086 +#else
4087 + host->card_inserted = (host->pm_state.event == PM_EVENT_USER_RESUME) ? 1 : 0;
4088 + INIT_MSG("sdio ops_get_cd<%d>", host->card_inserted);
4089 + return host->card_inserted;
4090 +#endif
4091 + }
4092 +
4093 + /* MSDC_CD_PIN_EN set for card */
4094 + if (host->hw->flags & MSDC_CD_PIN_EN) {
4095 + spin_lock_irqsave(&host->lock, flags);
4096 +#if 0
4097 + present = host->card_inserted; /* why not read from H/W: Fix me*/
4098 +#else
4099 + present = (sdr_read32(MSDC_PS) & MSDC_PS_CDSTS) ? 0 : 1;
4100 + host->card_inserted = present;
4101 +#endif
4102 + spin_unlock_irqrestore(&host->lock, flags);
4103 + } else {
4104 + present = 0; /* TODO? Check DAT3 pins for card detection */
4105 + }
4106 +
4107 + INIT_MSG("ops_get_cd return<%d>", present);
4108 + return present;
4109 +}
4110 +
4111 +/* ops.enable_sdio_irq */
4112 +static void msdc_ops_enable_sdio_irq(struct mmc_host *mmc, int enable)
4113 +{
4114 + struct msdc_host *host = mmc_priv(mmc);
4115 + struct msdc_hw *hw = host->hw;
4116 + u32 base = host->base;
4117 + u32 tmp;
4118 +
4119 + if (hw->flags & MSDC_EXT_SDIO_IRQ) { /* yes for sdio */
4120 + if (enable) {
4121 + hw->enable_sdio_eirq(); /* combo_sdio_enable_eirq */
4122 + } else {
4123 + hw->disable_sdio_eirq(); /* combo_sdio_disable_eirq */
4124 + }
4125 + } else {
4126 + ERR_MSG("XXX "); /* so never enter here */
4127 + tmp = sdr_read32(SDC_CFG);
4128 + /* FIXME. Need to interrupt gap detection */
4129 + if (enable) {
4130 + tmp |= (SDC_CFG_SDIOIDE | SDC_CFG_SDIOINTWKUP);
4131 + } else {
4132 + tmp &= ~(SDC_CFG_SDIOIDE | SDC_CFG_SDIOINTWKUP);
4133 + }
4134 + sdr_write32(SDC_CFG, tmp);
4135 + }
4136 +}
4137 +
4138 +static struct mmc_host_ops mt_msdc_ops = {
4139 + .request = msdc_ops_request,
4140 + .set_ios = msdc_ops_set_ios,
4141 + .get_ro = msdc_ops_get_ro,
4142 + .get_cd = msdc_ops_get_cd,
4143 + .enable_sdio_irq = msdc_ops_enable_sdio_irq,
4144 +};
4145 +
4146 +/*--------------------------------------------------------------------------*/
4147 +/* interrupt handler */
4148 +/*--------------------------------------------------------------------------*/
4149 +static irqreturn_t msdc_irq(int irq, void *dev_id)
4150 +{
4151 + struct msdc_host *host = (struct msdc_host *)dev_id;
4152 + struct mmc_data *data = host->data;
4153 + struct mmc_command *cmd = host->cmd;
4154 + u32 base = host->base;
4155 +
4156 + u32 cmdsts = MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO | MSDC_INT_CMDRDY |
4157 + MSDC_INT_ACMDCRCERR | MSDC_INT_ACMDTMO | MSDC_INT_ACMDRDY |
4158 + MSDC_INT_ACMD19_DONE;
4159 + u32 datsts = MSDC_INT_DATCRCERR |MSDC_INT_DATTMO;
4160 +
4161 + u32 intsts = sdr_read32(MSDC_INT);
4162 + u32 inten = sdr_read32(MSDC_INTEN); inten &= intsts;
4163 +
4164 + sdr_write32(MSDC_INT, intsts); /* clear interrupts */
4165 + /* MSG will cause fatal error */
4166 +
4167 + /* card change interrupt */
4168 + if (intsts & MSDC_INT_CDSC){
4169 +#if defined CONFIG_MTK_MMC_CD_POLL
4170 + return IRQ_HANDLED;
4171 +#endif
4172 + IRQ_MSG("MSDC_INT_CDSC irq<0x%.8x>", intsts);
4173 +#if 0 /* ---/+++ by chhung: fix slot mechanical bounce issue */
4174 + tasklet_hi_schedule(&host->card_tasklet);
4175 +#else
4176 + schedule_delayed_work(&host->card_delaywork, HZ);
4177 +#endif
4178 + /* tuning when plug card ? */
4179 + }
4180 +
4181 + /* sdio interrupt */
4182 + if (intsts & MSDC_INT_SDIOIRQ){
4183 + IRQ_MSG("XXX MSDC_INT_SDIOIRQ"); /* seems not sdio irq */
4184 + //mmc_signal_sdio_irq(host->mmc);
4185 + }
4186 +
4187 + /* transfer complete interrupt */
4188 + if (data != NULL) {
4189 + if (inten & MSDC_INT_XFER_COMPL) {
4190 + data->bytes_xfered = host->dma.xfersz;
4191 + complete(&host->xfer_done);
4192 + }
4193 +
4194 + if (intsts & datsts) {
4195 + /* do basic reset, or stop command will sdc_busy */
4196 + msdc_reset();
4197 + msdc_clr_fifo();
4198 + msdc_clr_int();
4199 + atomic_set(&host->abort, 1); /* For PIO mode exit */
4200 +
4201 + if (intsts & MSDC_INT_DATTMO){
4202 + IRQ_MSG("XXX CMD<%d> MSDC_INT_DATTMO", host->mrq->cmd->opcode);
4203 + data->error = (unsigned int)-ETIMEDOUT;
4204 + }
4205 + else if (intsts & MSDC_INT_DATCRCERR){
4206 + IRQ_MSG("XXX CMD<%d> MSDC_INT_DATCRCERR, SDC_DCRC_STS<0x%x>", host->mrq->cmd->opcode, sdr_read32(SDC_DCRC_STS));
4207 + data->error = (unsigned int)-EIO;
4208 + }
4209 +
4210 + //if(sdr_read32(MSDC_INTEN) & MSDC_INT_XFER_COMPL) {
4211 + if (host->dma_xfer) {
4212 + complete(&host->xfer_done); /* Read CRC come fast, XFER_COMPL not enabled */
4213 + } /* PIO mode can't do complete, because not init */
4214 + }
4215 + }
4216 +
4217 + /* command interrupts */
4218 + if ((cmd != NULL) && (intsts & cmdsts)) {
4219 + if ((intsts & MSDC_INT_CMDRDY) || (intsts & MSDC_INT_ACMDRDY) ||
4220 + (intsts & MSDC_INT_ACMD19_DONE)) {
4221 + u32 *rsp = &cmd->resp[0];
4222 +
4223 + switch (host->cmd_rsp) {
4224 + case RESP_NONE:
4225 + break;
4226 + case RESP_R2:
4227 + *rsp++ = sdr_read32(SDC_RESP3); *rsp++ = sdr_read32(SDC_RESP2);
4228 + *rsp++ = sdr_read32(SDC_RESP1); *rsp++ = sdr_read32(SDC_RESP0);
4229 + break;
4230 + default: /* Response types 1, 3, 4, 5, 6, 7(1b) */
4231 + if ((intsts & MSDC_INT_ACMDRDY) || (intsts & MSDC_INT_ACMD19_DONE)) {
4232 + *rsp = sdr_read32(SDC_ACMD_RESP);
4233 + } else {
4234 + *rsp = sdr_read32(SDC_RESP0);
4235 + }
4236 + break;
4237 + }
4238 + } else if ((intsts & MSDC_INT_RSPCRCERR) || (intsts & MSDC_INT_ACMDCRCERR)) {
4239 + if(intsts & MSDC_INT_ACMDCRCERR){
4240 + IRQ_MSG("XXX CMD<%d> MSDC_INT_ACMDCRCERR",cmd->opcode);
4241 + }
4242 + else {
4243 + IRQ_MSG("XXX CMD<%d> MSDC_INT_RSPCRCERR",cmd->opcode);
4244 + }
4245 + cmd->error = (unsigned int)-EIO;
4246 + } else if ((intsts & MSDC_INT_CMDTMO) || (intsts & MSDC_INT_ACMDTMO)) {
4247 + if(intsts & MSDC_INT_ACMDTMO){
4248 + IRQ_MSG("XXX CMD<%d> MSDC_INT_ACMDTMO",cmd->opcode);
4249 + }
4250 + else {
4251 + IRQ_MSG("XXX CMD<%d> MSDC_INT_CMDTMO",cmd->opcode);
4252 + }
4253 + cmd->error = (unsigned int)-ETIMEDOUT;
4254 + msdc_reset();
4255 + msdc_clr_fifo();
4256 + msdc_clr_int();
4257 + }
4258 + complete(&host->cmd_done);
4259 + }
4260 +
4261 + /* mmc irq interrupts */
4262 + if (intsts & MSDC_INT_MMCIRQ) {
4263 + printk(KERN_INFO "msdc[%d] MMCIRQ: SDC_CSTS=0x%.8x\r\n", host->id, sdr_read32(SDC_CSTS));
4264 + }
4265 +
4266 +#ifdef MT6575_SD_DEBUG
4267 + {
4268 + msdc_int_reg *int_reg = (msdc_int_reg*)&intsts;
4269 + N_MSG(INT, "IRQ_EVT(0x%x): MMCIRQ(%d) CDSC(%d), ACRDY(%d), ACTMO(%d), ACCRE(%d) AC19DN(%d)",
4270 + intsts,
4271 + int_reg->mmcirq,
4272 + int_reg->cdsc,
4273 + int_reg->atocmdrdy,
4274 + int_reg->atocmdtmo,
4275 + int_reg->atocmdcrc,
4276 + int_reg->atocmd19done);
4277 + N_MSG(INT, "IRQ_EVT(0x%x): SDIO(%d) CMDRDY(%d), CMDTMO(%d), RSPCRC(%d), CSTA(%d)",
4278 + intsts,
4279 + int_reg->sdioirq,
4280 + int_reg->cmdrdy,
4281 + int_reg->cmdtmo,
4282 + int_reg->rspcrc,
4283 + int_reg->csta);
4284 + N_MSG(INT, "IRQ_EVT(0x%x): XFCMP(%d) DXDONE(%d), DATTMO(%d), DATCRC(%d), DMAEMP(%d)",
4285 + intsts,
4286 + int_reg->xfercomp,
4287 + int_reg->dxferdone,
4288 + int_reg->dattmo,
4289 + int_reg->datcrc,
4290 + int_reg->dmaqempty);
4291 +
4292 + }
4293 +#endif
4294 +
4295 + return IRQ_HANDLED;
4296 +}
4297 +
4298 +/*--------------------------------------------------------------------------*/
4299 +/* platform_driver members */
4300 +/*--------------------------------------------------------------------------*/
4301 +/* called by msdc_drv_probe/remove */
4302 +static void msdc_enable_cd_irq(struct msdc_host *host, int enable)
4303 +{
4304 + struct msdc_hw *hw = host->hw;
4305 + u32 base = host->base;
4306 +
4307 + /* for sdio, not set */
4308 + if ((hw->flags & MSDC_CD_PIN_EN) == 0) {
4309 + /* Pull down card detection pin since it is not avaiable */
4310 + /*
4311 + if (hw->config_gpio_pin)
4312 + hw->config_gpio_pin(MSDC_CD_PIN, GPIO_PULL_DOWN);
4313 + */
4314 + sdr_clr_bits(MSDC_PS, MSDC_PS_CDEN);
4315 + sdr_clr_bits(MSDC_INTEN, MSDC_INTEN_CDSC);
4316 + sdr_clr_bits(SDC_CFG, SDC_CFG_INSWKUP);
4317 + return;
4318 + }
4319 +
4320 + N_MSG(CFG, "CD IRQ Eanable(%d)", enable);
4321 +
4322 + if (enable) {
4323 + if (hw->enable_cd_eirq) { /* not set, never enter */
4324 + hw->enable_cd_eirq();
4325 + } else {
4326 + /* card detection circuit relies on the core power so that the core power
4327 + * shouldn't be turned off. Here adds a reference count to keep
4328 + * the core power alive.
4329 + */
4330 + //msdc_vcore_on(host); //did in msdc_init_hw()
4331 +
4332 + if (hw->config_gpio_pin) /* NULL */
4333 + hw->config_gpio_pin(MSDC_CD_PIN, GPIO_PULL_UP);
4334 +
4335 + sdr_set_field(MSDC_PS, MSDC_PS_CDDEBOUNCE, DEFAULT_DEBOUNCE);
4336 + sdr_set_bits(MSDC_PS, MSDC_PS_CDEN);
4337 + sdr_set_bits(MSDC_INTEN, MSDC_INTEN_CDSC);
4338 + sdr_set_bits(SDC_CFG, SDC_CFG_INSWKUP); /* not in document! Fix me */
4339 + }
4340 + } else {
4341 + if (hw->disable_cd_eirq) {
4342 + hw->disable_cd_eirq();
4343 + } else {
4344 + if (hw->config_gpio_pin) /* NULL */
4345 + hw->config_gpio_pin(MSDC_CD_PIN, GPIO_PULL_DOWN);
4346 +
4347 + sdr_clr_bits(SDC_CFG, SDC_CFG_INSWKUP);
4348 + sdr_clr_bits(MSDC_PS, MSDC_PS_CDEN);
4349 + sdr_clr_bits(MSDC_INTEN, MSDC_INTEN_CDSC);
4350 +
4351 + /* Here decreases a reference count to core power since card
4352 + * detection circuit is shutdown.
4353 + */
4354 + //msdc_vcore_off(host);
4355 + }
4356 + }
4357 +}
4358 +
4359 +/* called by msdc_drv_probe */
4360 +static void msdc_init_hw(struct msdc_host *host)
4361 +{
4362 + u32 base = host->base;
4363 + struct msdc_hw *hw = host->hw;
4364 +
4365 +#ifdef MT6575_SD_DEBUG
4366 + msdc_reg[host->id] = (struct msdc_regs *)host->base;
4367 +#endif
4368 +
4369 + /* Power on */
4370 +#if 0 /* --- by chhung */
4371 + msdc_vcore_on(host);
4372 + msdc_pin_reset(host, MSDC_PIN_PULL_UP);
4373 + msdc_select_clksrc(host, hw->clk_src);
4374 + enable_clock(PERI_MSDC0_PDN + host->id, "SD");
4375 + msdc_vdd_on(host);
4376 +#endif /* end of --- */
4377 + /* Configure to MMC/SD mode */
4378 + sdr_set_field(MSDC_CFG, MSDC_CFG_MODE, MSDC_SDMMC);
4379 +
4380 + /* Reset */
4381 + msdc_reset();
4382 + msdc_clr_fifo();
4383 +
4384 + /* Disable card detection */
4385 + sdr_clr_bits(MSDC_PS, MSDC_PS_CDEN);
4386 +
4387 + /* Disable and clear all interrupts */
4388 + sdr_clr_bits(MSDC_INTEN, sdr_read32(MSDC_INTEN));
4389 + sdr_write32(MSDC_INT, sdr_read32(MSDC_INT));
4390 +
4391 +#if 1
4392 + /* reset tuning parameter */
4393 + sdr_write32(MSDC_PAD_CTL0, 0x00090000);
4394 + sdr_write32(MSDC_PAD_CTL1, 0x000A0000);
4395 + sdr_write32(MSDC_PAD_CTL2, 0x000A0000);
4396 + // sdr_write32(MSDC_PAD_TUNE, 0x00000000);
4397 + sdr_write32(MSDC_PAD_TUNE, 0x84101010); // for MT7620 E2 and afterward
4398 + // sdr_write32(MSDC_DAT_RDDLY0, 0x00000000);
4399 + sdr_write32(MSDC_DAT_RDDLY0, 0x10101010); // for MT7620 E2 and afterward
4400 + sdr_write32(MSDC_DAT_RDDLY1, 0x00000000);
4401 + sdr_write32(MSDC_IOCON, 0x00000000);
4402 +#if 0 // use MT7620 default value: 0x403c004f
4403 + sdr_write32(MSDC_PATCH_BIT0, 0x003C000F); /* bit0 modified: Rx Data Clock Source: 1 -> 2.0*/
4404 +#endif
4405 +
4406 + if (sdr_read32(MSDC_ECO_VER) >= 4) {
4407 + if (host->id == 1) {
4408 + sdr_set_field(MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_WRDAT_CRCS, 1);
4409 + sdr_set_field(MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMD_RSP, 1);
4410 +
4411 + /* internal clock: latch read data */
4412 + sdr_set_bits(MSDC_PATCH_BIT0, MSDC_PATCH_BIT_CKGEN_CK);
4413 + }
4414 + }
4415 +#endif
4416 +
4417 + /* for safety, should clear SDC_CFG.SDIO_INT_DET_EN & set SDC_CFG.SDIO in
4418 + pre-loader,uboot,kernel drivers. and SDC_CFG.SDIO_INT_DET_EN will be only
4419 + set when kernel driver wants to use SDIO bus interrupt */
4420 + /* Configure to enable SDIO mode. it's must otherwise sdio cmd5 failed */
4421 + sdr_set_bits(SDC_CFG, SDC_CFG_SDIO);
4422 +
4423 + /* disable detect SDIO device interupt function */
4424 + sdr_clr_bits(SDC_CFG, SDC_CFG_SDIOIDE);
4425 +
4426 + /* eneable SMT for glitch filter */
4427 + sdr_set_bits(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKSMT);
4428 + sdr_set_bits(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDSMT);
4429 + sdr_set_bits(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATSMT);
4430 +
4431 +#if 1
4432 + /* set clk, cmd, dat pad driving */
4433 + sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVN, hw->clk_drv);
4434 + sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVP, hw->clk_drv);
4435 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVN, hw->cmd_drv);
4436 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVP, hw->cmd_drv);
4437 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVN, hw->dat_drv);
4438 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVP, hw->dat_drv);
4439 +#else
4440 + sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVN, 0);
4441 + sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVP, 0);
4442 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVN, 0);
4443 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVP, 0);
4444 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVN, 0);
4445 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVP, 0);
4446 +#endif
4447 +
4448 + /* set sampling edge */
4449 +
4450 + /* write crc timeout detection */
4451 + sdr_set_field(MSDC_PATCH_BIT0, 1 << 30, 1);
4452 +
4453 + /* Configure to default data timeout */
4454 + sdr_set_field(SDC_CFG, SDC_CFG_DTOC, DEFAULT_DTOC);
4455 +
4456 + msdc_set_buswidth(host, MMC_BUS_WIDTH_1);
4457 +
4458 + N_MSG(FUC, "init hardware done!");
4459 +}
4460 +
4461 +/* called by msdc_drv_remove */
4462 +static void msdc_deinit_hw(struct msdc_host *host)
4463 +{
4464 + u32 base = host->base;
4465 +
4466 + /* Disable and clear all interrupts */
4467 + sdr_clr_bits(MSDC_INTEN, sdr_read32(MSDC_INTEN));
4468 + sdr_write32(MSDC_INT, sdr_read32(MSDC_INT));
4469 +
4470 + /* Disable card detection */
4471 + msdc_enable_cd_irq(host, 0);
4472 + // msdc_set_power_mode(host, MMC_POWER_OFF); /* make sure power down */ /* --- by chhung */
4473 +}
4474 +
4475 +/* init gpd and bd list in msdc_drv_probe */
4476 +static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma)
4477 +{
4478 + gpd_t *gpd = dma->gpd;
4479 + bd_t *bd = dma->bd;
4480 + bd_t *ptr, *prev;
4481 +
4482 + /* we just support one gpd */
4483 + int bdlen = MAX_BD_PER_GPD;
4484 +
4485 + /* init the 2 gpd */
4486 + memset(gpd, 0, sizeof(gpd_t) * 2);
4487 + //gpd->next = (void *)virt_to_phys(gpd + 1); /* pointer to a null gpd, bug! kmalloc <-> virt_to_phys */
4488 + //gpd->next = (dma->gpd_addr + 1); /* bug */
4489 + gpd->next = (void *)((u32)dma->gpd_addr + sizeof(gpd_t));
4490 +
4491 + //gpd->intr = 0;
4492 + gpd->bdp = 1; /* hwo, cs, bd pointer */
4493 + //gpd->ptr = (void*)virt_to_phys(bd);
4494 + gpd->ptr = (void *)dma->bd_addr; /* physical address */
4495 +
4496 + memset(bd, 0, sizeof(bd_t) * bdlen);
4497 + ptr = bd + bdlen - 1;
4498 + //ptr->eol = 1; /* 0 or 1 [Fix me]*/
4499 + //ptr->next = 0;
4500 +
4501 + while (ptr != bd) {
4502 + prev = ptr - 1;
4503 + prev->next = (void *)(dma->bd_addr + sizeof(bd_t) *(ptr - bd));
4504 + ptr = prev;
4505 + }
4506 +}
4507 +
4508 +static int msdc_drv_probe(struct platform_device *pdev)
4509 +{
4510 + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4511 + __iomem void *base;
4512 + struct mmc_host *mmc;
4513 + struct resource *mem;
4514 + struct msdc_host *host;
4515 + struct msdc_hw *hw;
4516 + int ret, irq;
4517 +
4518 + pdev->dev.platform_data = &msdc0_hw;
4519 +
4520 + /* Allocate MMC host for this device */
4521 + mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev);
4522 + if (!mmc) return -ENOMEM;
4523 +
4524 + hw = (struct msdc_hw*)pdev->dev.platform_data;
4525 + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4526 + irq = platform_get_irq(pdev, 0);
4527 +
4528 + //BUG_ON((!hw) || (!mem) || (irq < 0)); /* --- by chhung */
4529 +
4530 + base = devm_request_and_ioremap(&pdev->dev, res);
4531 + if (IS_ERR(base))
4532 + return PTR_ERR(base);
4533 +
4534 + /* Set host parameters to mmc */
4535 + mmc->ops = &mt_msdc_ops;
4536 + mmc->f_min = HOST_MIN_MCLK;
4537 + mmc->f_max = HOST_MAX_MCLK;
4538 + mmc->ocr_avail = MSDC_OCR_AVAIL;
4539 +
4540 + /* For sd card: MSDC_SYS_SUSPEND | MSDC_WP_PIN_EN | MSDC_CD_PIN_EN | MSDC_REMOVABLE | MSDC_HIGHSPEED,
4541 + For sdio : MSDC_EXT_SDIO_IRQ | MSDC_HIGHSPEED */
4542 + if (hw->flags & MSDC_HIGHSPEED) {
4543 + mmc->caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
4544 + }
4545 + if (hw->data_pins == 4) { /* current data_pins are all 4*/
4546 + mmc->caps |= MMC_CAP_4_BIT_DATA;
4547 + } else if (hw->data_pins == 8) {
4548 + mmc->caps |= MMC_CAP_8_BIT_DATA;
4549 + }
4550 + if ((hw->flags & MSDC_SDIO_IRQ) || (hw->flags & MSDC_EXT_SDIO_IRQ))
4551 + mmc->caps |= MMC_CAP_SDIO_IRQ; /* yes for sdio */
4552 +
4553 +#if defined CONFIG_MTK_MMC_CD_POLL
4554 + mmc->caps |= MMC_CAP_NEEDS_POLL;
4555 +#endif
4556 +
4557 + /* MMC core transfer sizes tunable parameters */
4558 +#if LINUX_VERSION_CODE > KERNEL_VERSION(3,10,0)
4559 + mmc->max_segs = MAX_HW_SGMTS;
4560 +#else
4561 + mmc->max_hw_segs = MAX_HW_SGMTS;
4562 + mmc->max_phys_segs = MAX_PHY_SGMTS;
4563 +#endif
4564 + mmc->max_seg_size = MAX_SGMT_SZ;
4565 + mmc->max_blk_size = HOST_MAX_BLKSZ;
4566 + mmc->max_req_size = MAX_REQ_SZ;
4567 + mmc->max_blk_count = mmc->max_req_size;
4568 +
4569 + host = mmc_priv(mmc);
4570 + host->hw = hw;
4571 + host->mmc = mmc;
4572 + host->id = pdev->id;
4573 + host->error = 0;
4574 + host->irq = irq;
4575 + host->base = (unsigned long) base;
4576 + host->mclk = 0; /* mclk: the request clock of mmc sub-system */
4577 + host->hclk = hclks[hw->clk_src]; /* hclk: clock of clock source to msdc controller */
4578 + host->sclk = 0; /* sclk: the really clock after divition */
4579 + host->pm_state = PMSG_RESUME;
4580 + host->suspend = 0;
4581 + host->core_clkon = 0;
4582 + host->card_clkon = 0;
4583 + host->core_power = 0;
4584 + host->power_mode = MMC_POWER_OFF;
4585 +// host->card_inserted = hw->flags & MSDC_REMOVABLE ? 0 : 1;
4586 + host->timeout_ns = 0;
4587 + host->timeout_clks = DEFAULT_DTOC * 65536;
4588 +
4589 + host->mrq = NULL;
4590 + //init_MUTEX(&host->sem); /* we don't need to support multiple threads access */
4591 +
4592 + host->dma.used_gpd = 0;
4593 + host->dma.used_bd = 0;
4594 +
4595 + /* using dma_alloc_coherent*/ /* todo: using 1, for all 4 slots */
4596 + host->dma.gpd = dma_alloc_coherent(NULL, MAX_GPD_NUM * sizeof(gpd_t), &host->dma.gpd_addr, GFP_KERNEL);
4597 + host->dma.bd = dma_alloc_coherent(NULL, MAX_BD_NUM * sizeof(bd_t), &host->dma.bd_addr, GFP_KERNEL);
4598 + BUG_ON((!host->dma.gpd) || (!host->dma.bd));
4599 + msdc_init_gpd_bd(host, &host->dma);
4600 + /*for emmc*/
4601 + msdc_6575_host[pdev->id] = host;
4602 +
4603 +#if 0
4604 + tasklet_init(&host->card_tasklet, msdc_tasklet_card, (ulong)host);
4605 +#else
4606 + INIT_DELAYED_WORK(&host->card_delaywork, msdc_tasklet_card);
4607 +#endif
4608 + spin_lock_init(&host->lock);
4609 + msdc_init_hw(host);
4610 +
4611 + ret = request_irq((unsigned int)irq, msdc_irq, IRQF_TRIGGER_LOW, dev_name(&pdev->dev), host);
4612 + if (ret) goto release;
4613 + // mt65xx_irq_unmask(irq); /* --- by chhung */
4614 +
4615 + if (hw->flags & MSDC_CD_PIN_EN) { /* not set for sdio */
4616 + if (hw->request_cd_eirq) { /* not set for MT6575 */
4617 + hw->request_cd_eirq(msdc_eirq_cd, (void*)host); /* msdc_eirq_cd will not be used! */
4618 + }
4619 + }
4620 +
4621 + if (hw->request_sdio_eirq) /* set to combo_sdio_request_eirq() for WIFI */
4622 + hw->request_sdio_eirq(msdc_eirq_sdio, (void*)host); /* msdc_eirq_sdio() will be called when EIRQ */
4623 +
4624 + if (hw->register_pm) {/* yes for sdio */
4625 +#ifdef CONFIG_PM
4626 + hw->register_pm(msdc_pm, (void*)host); /* combo_sdio_register_pm() */
4627 +#endif
4628 + if(hw->flags & MSDC_SYS_SUSPEND) { /* will not set for WIFI */
4629 + ERR_MSG("MSDC_SYS_SUSPEND and register_pm both set");
4630 + }
4631 + //mmc->pm_flags |= MMC_PM_IGNORE_PM_NOTIFY; /* pm not controlled by system but by client. */ /* --- by chhung */
4632 + }
4633 +
4634 + platform_set_drvdata(pdev, mmc);
4635 +
4636 + ret = mmc_add_host(mmc);
4637 + if (ret) goto free_irq;
4638 +
4639 + /* Config card detection pin and enable interrupts */
4640 + if (hw->flags & MSDC_CD_PIN_EN) { /* set for card */
4641 + msdc_enable_cd_irq(host, 1);
4642 + } else {
4643 + msdc_enable_cd_irq(host, 0);
4644 + }
4645 +
4646 + return 0;
4647 +
4648 +free_irq:
4649 + free_irq(irq, host);
4650 +release:
4651 + platform_set_drvdata(pdev, NULL);
4652 + msdc_deinit_hw(host);
4653 +
4654 +#if 0
4655 + tasklet_kill(&host->card_tasklet);
4656 +#else
4657 + cancel_delayed_work_sync(&host->card_delaywork);
4658 +#endif
4659 +
4660 + if (mem)
4661 + release_mem_region(mem->start, mem->end - mem->start + 1);
4662 +
4663 + mmc_free_host(mmc);
4664 +
4665 + return ret;
4666 +}
4667 +
4668 +/* 4 device share one driver, using "drvdata" to show difference */
4669 +static int msdc_drv_remove(struct platform_device *pdev)
4670 +{
4671 + struct mmc_host *mmc;
4672 + struct msdc_host *host;
4673 + struct resource *mem;
4674 +
4675 + mmc = platform_get_drvdata(pdev);
4676 + BUG_ON(!mmc);
4677 +
4678 + host = mmc_priv(mmc);
4679 + BUG_ON(!host);
4680 +
4681 + ERR_MSG("removed !!!");
4682 +
4683 + platform_set_drvdata(pdev, NULL);
4684 + mmc_remove_host(host->mmc);
4685 + msdc_deinit_hw(host);
4686 +
4687 +#if 0
4688 + tasklet_kill(&host->card_tasklet);
4689 +#else
4690 + cancel_delayed_work_sync(&host->card_delaywork);
4691 +#endif
4692 + free_irq(host->irq, host);
4693 +
4694 + dma_free_coherent(NULL, MAX_GPD_NUM * sizeof(gpd_t), host->dma.gpd, host->dma.gpd_addr);
4695 + dma_free_coherent(NULL, MAX_BD_NUM * sizeof(bd_t), host->dma.bd, host->dma.bd_addr);
4696 +
4697 + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4698 +
4699 + if (mem)
4700 + release_mem_region(mem->start, mem->end - mem->start + 1);
4701 +
4702 + mmc_free_host(host->mmc);
4703 +
4704 + return 0;
4705 +}
4706 +
4707 +/* Fix me: Power Flow */
4708 +#ifdef CONFIG_PM
4709 +static int msdc_drv_suspend(struct platform_device *pdev, pm_message_t state)
4710 +{
4711 + int ret = 0;
4712 + struct mmc_host *mmc = platform_get_drvdata(pdev);
4713 + struct msdc_host *host = mmc_priv(mmc);
4714 +
4715 + if (mmc && state.event == PM_EVENT_SUSPEND && (host->hw->flags & MSDC_SYS_SUSPEND)) { /* will set for card */
4716 + msdc_pm(state, (void*)host);
4717 + }
4718 +
4719 + return ret;
4720 +}
4721 +
4722 +static int msdc_drv_resume(struct platform_device *pdev)
4723 +{
4724 + int ret = 0;
4725 + struct mmc_host *mmc = platform_get_drvdata(pdev);
4726 + struct msdc_host *host = mmc_priv(mmc);
4727 + struct pm_message state;
4728 +
4729 + state.event = PM_EVENT_RESUME;
4730 + if (mmc && (host->hw->flags & MSDC_SYS_SUSPEND)) {/* will set for card */
4731 + msdc_pm(state, (void*)host);
4732 + }
4733 +
4734 + /* This mean WIFI not controller by PM */
4735 +
4736 + return ret;
4737 +}
4738 +#endif
4739 +
4740 +static const struct of_device_id mt7620_sdhci_match[] = {
4741 + { .compatible = "ralink,mt7620-sdhci" },
4742 + {},
4743 +};
4744 +MODULE_DEVICE_TABLE(of, rt288x_wdt_match);
4745 +
4746 +static struct platform_driver mt_msdc_driver = {
4747 + .probe = msdc_drv_probe,
4748 + .remove = msdc_drv_remove,
4749 +#ifdef CONFIG_PM
4750 + .suspend = msdc_drv_suspend,
4751 + .resume = msdc_drv_resume,
4752 +#endif
4753 + .driver = {
4754 + .name = DRV_NAME,
4755 + .owner = THIS_MODULE,
4756 + .of_match_table = mt7620_sdhci_match,
4757 + },
4758 +};
4759 +
4760 +/*--------------------------------------------------------------------------*/
4761 +/* module init/exit */
4762 +/*--------------------------------------------------------------------------*/
4763 +static int __init mt_msdc_init(void)
4764 +{
4765 + int ret;
4766 +/* +++ by chhung */
4767 + u32 reg;
4768 +
4769 +#if defined (CONFIG_MTD_ANY_RALINK)
4770 + extern int ra_check_flash_type(void);
4771 + if(ra_check_flash_type() == 2) { /* NAND */
4772 + printk("%s: !!!!! SDXC Module Initialize Fail !!!!!", __func__);
4773 + return 0;
4774 + }
4775 +#endif
4776 + printk("MTK MSDC device init.\n");
4777 + mtk_sd_device.dev.platform_data = &msdc0_hw;
4778 +if (ralink_soc == MT762X_SOC_MT7620A || ralink_soc == MT762X_SOC_MT7621AT) {
4779 +//#if defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621)
4780 + reg = sdr_read32((volatile u32*)(RALINK_SYSCTL_BASE + 0x60)) & ~(0x3<<18);
4781 +//#if defined (CONFIG_RALINK_MT7620)
4782 + if (ralink_soc == MT762X_SOC_MT7620A)
4783 + reg |= 0x1<<18;
4784 +//#endif
4785 +} else {
4786 +//#elif defined (CONFIG_RALINK_MT7628)
4787 + /* TODO: maybe omitted when RAether already toggle AGPIO_CFG */
4788 + reg = sdr_read32((volatile u32*)(RALINK_SYSCTL_BASE + 0x3c));
4789 + reg |= 0x1e << 16;
4790 + sdr_write32((volatile u32*)(RALINK_SYSCTL_BASE + 0x3c), reg);
4791 +
4792 + reg = sdr_read32((volatile u32*)(RALINK_SYSCTL_BASE + 0x60)) & ~(0x3<<10);
4793 +#if defined (CONFIG_MTK_MMC_EMMC_8BIT)
4794 + reg |= 0x3<<26 | 0x3<<28 | 0x3<<30;
4795 + msdc0_hw.data_pins = 8,
4796 +#endif
4797 +//#endif
4798 +}
4799 + sdr_write32((volatile u32*)(RALINK_SYSCTL_BASE + 0x60), reg);
4800 + //platform_device_register(&mtk_sd_device);
4801 +/* end of +++ */
4802 +
4803 + ret = platform_driver_register(&mt_msdc_driver);
4804 + if (ret) {
4805 + printk(KERN_ERR DRV_NAME ": Can't register driver");
4806 + return ret;
4807 + }
4808 + printk(KERN_INFO DRV_NAME ": MediaTek MT6575 MSDC Driver\n");
4809 +
4810 +#if defined (MT6575_SD_DEBUG)
4811 + msdc_debug_proc_init();
4812 +#endif
4813 + return 0;
4814 +}
4815 +
4816 +static void __exit mt_msdc_exit(void)
4817 +{
4818 +// platform_device_unregister(&mtk_sd_device);
4819 + platform_driver_unregister(&mt_msdc_driver);
4820 +}
4821 +
4822 +module_init(mt_msdc_init);
4823 +module_exit(mt_msdc_exit);
4824 +MODULE_LICENSE("GPL");
4825 +MODULE_DESCRIPTION("MediaTek MT6575 SD/MMC Card Driver");
4826 +MODULE_AUTHOR("Infinity Chen <infinity.chen@mediatek.com>");
4827 +
4828 +EXPORT_SYMBOL(msdc_6575_host);
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