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[openwrt/openwrt.git] / target / linux / ramips / patches-3.14 / 0060-soc_type.patch
1 Index: linux-3.14.18/arch/mips/include/asm/mach-ralink/mt7620.h
2 ===================================================================
3 --- linux-3.14.18.orig/arch/mips/include/asm/mach-ralink/mt7620.h 2014-11-17 19:54:59.683128174 +0100
4 +++ linux-3.14.18/arch/mips/include/asm/mach-ralink/mt7620.h 2014-11-17 19:54:59.975139185 +0100
5 @@ -13,14 +13,6 @@
6 #ifndef _MT7620_REGS_H_
7 #define _MT7620_REGS_H_
8
9 -enum mt762x_soc_type {
10 - MT762X_SOC_UNKNOWN = 0,
11 - MT762X_SOC_MT7620A,
12 - MT762X_SOC_MT7620N,
13 - MT762X_SOC_MT7628AN,
14 -};
15 -extern enum mt762x_soc_type mt762x_soc;
16 -
17 #define MT7620_SYSC_BASE 0x10000000
18
19 #define SYSC_REG_CHIP_NAME0 0x00
20 Index: linux-3.14.18/arch/mips/include/asm/mach-ralink/ralink_regs.h
21 ===================================================================
22 --- linux-3.14.18.orig/arch/mips/include/asm/mach-ralink/ralink_regs.h 2014-11-17 19:54:59.379116714 +0100
23 +++ linux-3.14.18/arch/mips/include/asm/mach-ralink/ralink_regs.h 2014-11-17 19:54:59.975139185 +0100
24 @@ -13,6 +13,20 @@
25 #ifndef _RALINK_REGS_H_
26 #define _RALINK_REGS_H_
27
28 +enum ralink_soc_type {
29 + RALINK_UNKNOWN = 0,
30 + RT305X_SOC_RT3050,
31 + RT305X_SOC_RT3052,
32 + RT305X_SOC_RT3350,
33 + RT305X_SOC_RT3352,
34 + RT305X_SOC_RT5350,
35 + MT762X_SOC_MT7620A,
36 + MT762X_SOC_MT7620N,
37 + MT762X_SOC_MT7621AT,
38 + MT762X_SOC_MT7628AN,
39 +};
40 +extern enum ralink_soc_type ralink_soc;
41 +
42 extern __iomem void *rt_sysc_membase;
43 extern __iomem void *rt_memc_membase;
44
45 Index: linux-3.14.18/arch/mips/include/asm/mach-ralink/rt305x.h
46 ===================================================================
47 --- linux-3.14.18.orig/arch/mips/include/asm/mach-ralink/rt305x.h 2014-11-17 19:54:59.663127421 +0100
48 +++ linux-3.14.18/arch/mips/include/asm/mach-ralink/rt305x.h 2014-11-17 19:54:59.975139185 +0100
49 @@ -13,25 +13,16 @@
50 #ifndef _RT305X_REGS_H_
51 #define _RT305X_REGS_H_
52
53 -enum rt305x_soc_type {
54 - RT305X_SOC_UNKNOWN = 0,
55 - RT305X_SOC_RT3050,
56 - RT305X_SOC_RT3052,
57 - RT305X_SOC_RT3350,
58 - RT305X_SOC_RT3352,
59 - RT305X_SOC_RT5350,
60 -};
61 -
62 -extern enum rt305x_soc_type rt305x_soc;
63 +extern enum ralink_soc_type ralink_soc;
64
65 static inline int soc_is_rt3050(void)
66 {
67 - return rt305x_soc == RT305X_SOC_RT3050;
68 + return ralink_soc == RT305X_SOC_RT3050;
69 }
70
71 static inline int soc_is_rt3052(void)
72 {
73 - return rt305x_soc == RT305X_SOC_RT3052;
74 + return ralink_soc == RT305X_SOC_RT3052;
75 }
76
77 static inline int soc_is_rt305x(void)
78 @@ -41,17 +32,17 @@
79
80 static inline int soc_is_rt3350(void)
81 {
82 - return rt305x_soc == RT305X_SOC_RT3350;
83 + return ralink_soc == RT305X_SOC_RT3350;
84 }
85
86 static inline int soc_is_rt3352(void)
87 {
88 - return rt305x_soc == RT305X_SOC_RT3352;
89 + return ralink_soc == RT305X_SOC_RT3352;
90 }
91
92 static inline int soc_is_rt5350(void)
93 {
94 - return rt305x_soc == RT305X_SOC_RT5350;
95 + return ralink_soc == RT305X_SOC_RT5350;
96 }
97
98 #define RT305X_SYSC_BASE 0x10000000
99 Index: linux-3.14.18/arch/mips/ralink/mt7620.c
100 ===================================================================
101 --- linux-3.14.18.orig/arch/mips/ralink/mt7620.c 2014-11-17 19:54:59.663127421 +0100
102 +++ linux-3.14.18/arch/mips/ralink/mt7620.c 2014-11-17 19:54:59.975139185 +0100
103 @@ -43,8 +43,6 @@
104 #define CLKCFG_FFRAC_MASK 0x001f
105 #define CLKCFG_FFRAC_USB_VAL 0x0003
106
107 -enum mt762x_soc_type mt762x_soc;
108 -
109 /* does the board have sdram or ddram */
110 static int dram_type;
111
112 @@ -375,7 +373,7 @@
113 #define RINT(x) ((x) / 1000000)
114 #define RFRAC(x) (((x) / 1000) % 1000)
115
116 - if (mt762x_soc == MT762X_SOC_MT7628AN) {
117 + if (ralink_soc == MT762X_SOC_MT7628AN) {
118 if (xtal_rate == MHZ(40))
119 cpu_rate = MHZ(580);
120 else
121 @@ -418,7 +416,7 @@
122 ralink_clk_add("10000c00.uartlite", periph_rate);
123 ralink_clk_add("10180000.wmac", xtal_rate);
124
125 - if (IS_ENABLED(CONFIG_USB) && mt762x_soc != MT762X_SOC_MT7628AN) {
126 + if (IS_ENABLED(CONFIG_USB) && ralink_soc != MT762X_SOC_MT7628AN) {
127 /*
128 * When the CPU goes into sleep mode, the BUS clock will be too low for
129 * USB to function properly
130 @@ -506,11 +504,11 @@
131
132 if (n0 == MT7620_CHIP_NAME0 && n1 == MT7620_CHIP_NAME1) {
133 if (bga) {
134 - mt762x_soc = MT762X_SOC_MT7620A;
135 + ralink_soc = MT762X_SOC_MT7620A;
136 name = "MT7620A";
137 soc_info->compatible = "ralink,mt7620a-soc";
138 } else {
139 - mt762x_soc = MT762X_SOC_MT7620N;
140 + ralink_soc = MT762X_SOC_MT7620N;
141 name = "MT7620N";
142 soc_info->compatible = "ralink,mt7620n-soc";
143 #ifdef CONFIG_PCI
144 @@ -518,7 +516,7 @@
145 #endif
146 }
147 } else if (n0 == MT7620_CHIP_NAME0 && n1 == MT7628_CHIP_NAME1) {
148 - mt762x_soc = MT762X_SOC_MT7628AN;
149 + ralink_soc = MT762X_SOC_MT7628AN;
150 name = "MT7628AN";
151 soc_info->compatible = "ralink,mt7628an-soc";
152 } else {
153 @@ -535,7 +533,7 @@
154 dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & SYSCFG0_DRAM_TYPE_MASK;
155
156 soc_info->mem_base = MT7620_DRAM_BASE;
157 - if (mt762x_soc == MT762X_SOC_MT7628AN)
158 + if (ralink_soc == MT762X_SOC_MT7628AN)
159 mt7628_dram_init(soc_info);
160 else
161 mt7620_dram_init(soc_info);
162 @@ -548,7 +546,7 @@
163 pr_info("Digital PMU set to %s control\n",
164 (pmu1 & DIG_SW_SEL) ? ("sw") : ("hw"));
165
166 - if (mt762x_soc == MT762X_SOC_MT7628AN)
167 + if (ralink_soc == MT762X_SOC_MT7628AN)
168 rt2880_pinmux_data = mt7628an_pinmux_data;
169 else
170 rt2880_pinmux_data = mt7620a_pinmux_data;
171 Index: linux-3.14.18/arch/mips/ralink/rt305x.c
172 ===================================================================
173 --- linux-3.14.18.orig/arch/mips/ralink/rt305x.c 2014-11-17 19:54:59.715129381 +0100
174 +++ linux-3.14.18/arch/mips/ralink/rt305x.c 2014-11-17 19:54:59.975139185 +0100
175 @@ -21,8 +21,6 @@
176
177 #include "common.h"
178
179 -enum rt305x_soc_type rt305x_soc;
180 -
181 static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) };
182 static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
183 static struct rt2880_pmx_func uartf_func[] = {
184 @@ -234,24 +232,24 @@
185
186 icache_sets = (read_c0_config1() >> 22) & 7;
187 if (icache_sets == 1) {
188 - rt305x_soc = RT305X_SOC_RT3050;
189 + ralink_soc = RT305X_SOC_RT3050;
190 name = "RT3050";
191 soc_info->compatible = "ralink,rt3050-soc";
192 } else {
193 - rt305x_soc = RT305X_SOC_RT3052;
194 + ralink_soc = RT305X_SOC_RT3052;
195 name = "RT3052";
196 soc_info->compatible = "ralink,rt3052-soc";
197 }
198 } else if (n0 == RT3350_CHIP_NAME0 && n1 == RT3350_CHIP_NAME1) {
199 - rt305x_soc = RT305X_SOC_RT3350;
200 + ralink_soc = RT305X_SOC_RT3350;
201 name = "RT3350";
202 soc_info->compatible = "ralink,rt3350-soc";
203 } else if (n0 == RT3352_CHIP_NAME0 && n1 == RT3352_CHIP_NAME1) {
204 - rt305x_soc = RT305X_SOC_RT3352;
205 + ralink_soc = RT305X_SOC_RT3352;
206 name = "RT3352";
207 soc_info->compatible = "ralink,rt3352-soc";
208 } else if (n0 == RT5350_CHIP_NAME0 && n1 == RT5350_CHIP_NAME1) {
209 - rt305x_soc = RT305X_SOC_RT5350;
210 + ralink_soc = RT305X_SOC_RT5350;
211 name = "RT5350";
212 soc_info->compatible = "ralink,rt5350-soc";
213 } else {
214 Index: linux-3.14.18/arch/mips/ralink/prom.c
215 ===================================================================
216 --- linux-3.14.18.orig/arch/mips/ralink/prom.c 2014-09-06 01:34:59.000000000 +0200
217 +++ linux-3.14.18/arch/mips/ralink/prom.c 2014-11-17 19:54:59.975139185 +0100
218 @@ -15,9 +15,13 @@
219 #include <asm/bootinfo.h>
220 #include <asm/addrspace.h>
221
222 +#include <asm/mach-ralink/ralink_regs.h>
223 +
224 #include "common.h"
225
226 struct ralink_soc_info soc_info;
227 +enum ralink_soc_type ralink_soc;
228 +EXPORT_SYMBOL_GPL(ralink_soc);
229
230 const char *get_system_type(void)
231 {
232 Index: linux-3.14.18/arch/mips/ralink/mt7621.c
233 ===================================================================
234 --- linux-3.14.18.orig/arch/mips/ralink/mt7621.c 2014-11-17 19:54:59.471120181 +0100
235 +++ linux-3.14.18/arch/mips/ralink/mt7621.c 2014-11-17 19:58:52.667916008 +0100
236 @@ -175,6 +175,7 @@
237 soc_info->mem_size_min = MT7621_DDR2_SIZE_MIN;
238 soc_info->mem_size_max = MT7621_DDR2_SIZE_MAX;
239 soc_info->mem_base = MT7621_DRAM_BASE;
240 + ralink_soc = MT762X_SOC_MT7621AT;
241
242 rt2880_pinmux_data = mt7621_pinmux_data;
243
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