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[openwrt/openwrt.git] / target / linux / ramips / patches-3.18 / 0050-SPI-ralink-add-Ralink-SoC-spi-driver.patch
1 From fc006d0622ab8c43086b2c9018c03012db332033 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sun, 27 Jul 2014 11:15:12 +0100
4 Subject: [PATCH 50/57] SPI: ralink: add Ralink SoC spi driver
5
6 Add the driver needed to make SPI work on Ralink SoC.
7
8 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
9 Acked-by: John Crispin <blogic@openwrt.org>
10 ---
11 drivers/spi/Kconfig | 6 +
12 drivers/spi/Makefile | 1 +
13 drivers/spi/spi-rt2880.c | 432 ++++++++++++++++++++++++++++++++++++++++++++++
14 3 files changed, 439 insertions(+)
15 create mode 100644 drivers/spi/spi-rt2880.c
16
17 --- a/drivers/spi/Kconfig
18 +++ b/drivers/spi/Kconfig
19 @@ -433,6 +433,12 @@ config SPI_QUP
20 This driver can also be built as a module. If so, the module
21 will be called spi_qup.
22
23 +config SPI_RT2880
24 + tristate "Ralink RT288x SPI Controller"
25 + depends on RALINK
26 + help
27 + This selects a driver for the Ralink RT288x/RT305x SPI Controller.
28 +
29 config SPI_S3C24XX
30 tristate "Samsung S3C24XX series SPI"
31 depends on ARCH_S3C24XX
32 --- a/drivers/spi/Makefile
33 +++ b/drivers/spi/Makefile
34 @@ -65,6 +65,7 @@ obj-$(CONFIG_SPI_PXA2XX_PCI) += spi-pxa
35 obj-$(CONFIG_SPI_QUP) += spi-qup.o
36 obj-$(CONFIG_SPI_ROCKCHIP) += spi-rockchip.o
37 obj-$(CONFIG_SPI_RSPI) += spi-rspi.o
38 +obj-$(CONFIG_SPI_RT2880) += spi-rt2880.o
39 obj-$(CONFIG_SPI_S3C24XX) += spi-s3c24xx-hw.o
40 spi-s3c24xx-hw-y := spi-s3c24xx.o
41 spi-s3c24xx-hw-$(CONFIG_SPI_S3C24XX_FIQ) += spi-s3c24xx-fiq.o
42 --- /dev/null
43 +++ b/drivers/spi/spi-rt2880.c
44 @@ -0,0 +1,493 @@
45 +/*
46 + * spi-rt2880.c -- Ralink RT288x/RT305x SPI controller driver
47 + *
48 + * Copyright (C) 2011 Sergiy <piratfm@gmail.com>
49 + * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
50 + *
51 + * Some parts are based on spi-orion.c:
52 + * Author: Shadi Ammouri <shadi@marvell.com>
53 + * Copyright (C) 2007-2008 Marvell Ltd.
54 + *
55 + * This program is free software; you can redistribute it and/or modify
56 + * it under the terms of the GNU General Public License version 2 as
57 + * published by the Free Software Foundation.
58 + */
59 +
60 +#include <linux/init.h>
61 +#include <linux/module.h>
62 +#include <linux/clk.h>
63 +#include <linux/err.h>
64 +#include <linux/delay.h>
65 +#include <linux/io.h>
66 +#include <linux/reset.h>
67 +#include <linux/spi/spi.h>
68 +#include <linux/platform_device.h>
69 +
70 +#define DRIVER_NAME "spi-rt2880"
71 +/* only one slave is supported*/
72 +#define RALINK_NUM_CHIPSELECTS 1
73 +/* in usec */
74 +#define RALINK_SPI_WAIT_MAX_LOOP 2000
75 +
76 +#define RAMIPS_SPI_STAT 0x00
77 +#define RAMIPS_SPI_CFG 0x10
78 +#define RAMIPS_SPI_CTL 0x14
79 +#define RAMIPS_SPI_DATA 0x20
80 +#define RAMIPS_SPI_ADDR 0x24
81 +#define RAMIPS_SPI_BS 0x28
82 +#define RAMIPS_SPI_USER 0x2C
83 +#define RAMIPS_SPI_TXFIFO 0x30
84 +#define RAMIPS_SPI_RXFIFO 0x34
85 +#define RAMIPS_SPI_FIFO_STAT 0x38
86 +#define RAMIPS_SPI_MODE 0x3C
87 +#define RAMIPS_SPI_DEV_OFFSET 0x40
88 +#define RAMIPS_SPI_DMA 0x80
89 +#define RAMIPS_SPI_DMASTAT 0x84
90 +#define RAMIPS_SPI_ARBITER 0xF0
91 +
92 +/* SPISTAT register bit field */
93 +#define SPISTAT_BUSY BIT(0)
94 +
95 +/* SPICFG register bit field */
96 +#define SPICFG_ADDRMODE BIT(12)
97 +#define SPICFG_RXENVDIS BIT(11)
98 +#define SPICFG_RXCAP BIT(10)
99 +#define SPICFG_SPIENMODE BIT(9)
100 +#define SPICFG_MSBFIRST BIT(8)
101 +#define SPICFG_SPICLKPOL BIT(6)
102 +#define SPICFG_RXCLKEDGE_FALLING BIT(5)
103 +#define SPICFG_TXCLKEDGE_FALLING BIT(4)
104 +#define SPICFG_HIZSPI BIT(3)
105 +#define SPICFG_SPICLK_PRESCALE_MASK 0x7
106 +#define SPICFG_SPICLK_DIV2 0
107 +#define SPICFG_SPICLK_DIV4 1
108 +#define SPICFG_SPICLK_DIV8 2
109 +#define SPICFG_SPICLK_DIV16 3
110 +#define SPICFG_SPICLK_DIV32 4
111 +#define SPICFG_SPICLK_DIV64 5
112 +#define SPICFG_SPICLK_DIV128 6
113 +#define SPICFG_SPICLK_DISABLE 7
114 +
115 +/* SPICTL register bit field */
116 +#define SPICTL_START BIT(4)
117 +#define SPICTL_HIZSDO BIT(3)
118 +#define SPICTL_STARTWR BIT(2)
119 +#define SPICTL_STARTRD BIT(1)
120 +#define SPICTL_SPIENA BIT(0)
121 +
122 +/* SPIUSER register bit field */
123 +#define SPIUSER_USERMODE BIT(21)
124 +#define SPIUSER_INSTR_PHASE BIT(20)
125 +#define SPIUSER_ADDR_PHASE_MASK 0x7
126 +#define SPIUSER_ADDR_PHASE_OFFSET 17
127 +#define SPIUSER_MODE_PHASE BIT(16)
128 +#define SPIUSER_DUMMY_PHASE_MASK 0x3
129 +#define SPIUSER_DUMMY_PHASE_OFFSET 14
130 +#define SPIUSER_DATA_PHASE_MASK 0x3
131 +#define SPIUSER_DATA_PHASE_OFFSET 12
132 +#define SPIUSER_DATA_READ (BIT(0) << SPIUSER_DATA_PHASE_OFFSET)
133 +#define SPIUSER_DATA_WRITE (BIT(1) << SPIUSER_DATA_PHASE_OFFSET)
134 +#define SPIUSER_ADDR_TYPE_OFFSET 9
135 +#define SPIUSER_MODE_TYPE_OFFSET 6
136 +#define SPIUSER_DUMMY_TYPE_OFFSET 3
137 +#define SPIUSER_DATA_TYPE_OFFSET 0
138 +#define SPIUSER_TRANSFER_MASK 0x7
139 +#define SPIUSER_TRANSFER_SINGLE BIT(0)
140 +#define SPIUSER_TRANSFER_DUAL BIT(1)
141 +#define SPIUSER_TRANSFER_QUAD BIT(2)
142 +
143 +#define SPIUSER_TRANSFER_TYPE(type) ( \
144 + (type << SPIUSER_ADDR_TYPE_OFFSET) | \
145 + (type << SPIUSER_MODE_TYPE_OFFSET) | \
146 + (type << SPIUSER_DUMMY_TYPE_OFFSET) | \
147 + (type << SPIUSER_DATA_TYPE_OFFSET) \
148 +)
149 +
150 +/* SPIFIFOSTAT register bit field */
151 +#define SPIFIFOSTAT_TXEMPTY BIT(19)
152 +#define SPIFIFOSTAT_RXEMPTY BIT(18)
153 +#define SPIFIFOSTAT_TXFULL BIT(17)
154 +#define SPIFIFOSTAT_RXFULL BIT(16)
155 +#define SPIFIFOSTAT_FIFO_MASK 0xff
156 +#define SPIFIFOSTAT_TX_OFFSET 8
157 +#define SPIFIFOSTAT_RX_OFFSET 0
158 +
159 +#define SPI_FIFO_DEPTH 16
160 +
161 +/* SPIMODE register bit field */
162 +#define SPIMODE_MODE_OFFSET 24
163 +#define SPIMODE_DUMMY_OFFSET 0
164 +
165 +/* SPIARB register bit field */
166 +#define SPICTL_ARB_EN BIT(31)
167 +#define SPICTL_CSCTL1 BIT(16)
168 +#define SPI1_POR BIT(1)
169 +#define SPI0_POR BIT(0)
170 +
171 +struct rt2880_spi {
172 + struct spi_master *master;
173 + void __iomem *base;
174 + unsigned int sys_freq;
175 + unsigned int speed;
176 + struct clk *clk;
177 + spinlock_t lock;
178 +};
179 +
180 +static inline struct rt2880_spi *spidev_to_rt2880_spi(struct spi_device *spi)
181 +{
182 + return spi_master_get_devdata(spi->master);
183 +}
184 +
185 +static inline u32 rt2880_spi_read(struct rt2880_spi *rs, u32 reg)
186 +{
187 + return ioread32(rs->base + reg);
188 +}
189 +
190 +static inline void rt2880_spi_write(struct rt2880_spi *rs, u32 reg, u32 val)
191 +{
192 + iowrite32(val, rs->base + reg);
193 +}
194 +
195 +static inline void rt2880_spi_setbits(struct rt2880_spi *rs, u32 reg, u32 mask)
196 +{
197 + void __iomem *addr = rs->base + reg;
198 + unsigned long flags;
199 + u32 val;
200 +
201 + spin_lock_irqsave(&rs->lock, flags);
202 + val = ioread32(addr);
203 + val |= mask;
204 + iowrite32(val, addr);
205 + spin_unlock_irqrestore(&rs->lock, flags);
206 +}
207 +
208 +static inline void rt2880_spi_clrbits(struct rt2880_spi *rs, u32 reg, u32 mask)
209 +{
210 + void __iomem *addr = rs->base + reg;
211 + unsigned long flags;
212 + u32 val;
213 +
214 + spin_lock_irqsave(&rs->lock, flags);
215 + val = ioread32(addr);
216 + val &= ~mask;
217 + iowrite32(val, addr);
218 + spin_unlock_irqrestore(&rs->lock, flags);
219 +}
220 +
221 +static int rt2880_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
222 +{
223 + struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
224 + u32 rate;
225 + u32 prescale;
226 + u32 reg;
227 +
228 + dev_dbg(&spi->dev, "speed:%u\n", speed);
229 +
230 + /*
231 + * the supported rates are: 2, 4, 8, ... 128
232 + * round up as we look for equal or less speed
233 + */
234 + rate = DIV_ROUND_UP(rs->sys_freq, speed);
235 + dev_dbg(&spi->dev, "rate-1:%u\n", rate);
236 + rate = roundup_pow_of_two(rate);
237 + dev_dbg(&spi->dev, "rate-2:%u\n", rate);
238 +
239 + /* check if requested speed is too small */
240 + if (rate > 128)
241 + return -EINVAL;
242 +
243 + if (rate < 2)
244 + rate = 2;
245 +
246 + /* Convert the rate to SPI clock divisor value. */
247 + prescale = ilog2(rate / 2);
248 + dev_dbg(&spi->dev, "prescale:%u\n", prescale);
249 +
250 + reg = rt2880_spi_read(rs, RAMIPS_SPI_CFG);
251 + reg = ((reg & ~SPICFG_SPICLK_PRESCALE_MASK) | prescale);
252 + rt2880_spi_write(rs, RAMIPS_SPI_CFG, reg);
253 + rs->speed = speed;
254 + return 0;
255 +}
256 +
257 +/*
258 + * called only when no transfer is active on the bus
259 + */
260 +static int
261 +rt2880_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
262 +{
263 + struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
264 + unsigned int speed = spi->max_speed_hz;
265 + int rc;
266 +
267 + if ((t != NULL) && t->speed_hz)
268 + speed = t->speed_hz;
269 +
270 + if (rs->speed != speed) {
271 + dev_dbg(&spi->dev, "speed_hz:%u\n", speed);
272 + rc = rt2880_spi_baudrate_set(spi, speed);
273 + if (rc)
274 + return rc;
275 + }
276 +
277 + return 0;
278 +}
279 +
280 +static void rt2880_spi_set_cs(struct rt2880_spi *rs, int enable)
281 +{
282 + if (enable)
283 + rt2880_spi_clrbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
284 + else
285 + rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
286 +}
287 +
288 +static inline int rt2880_spi_wait_till_ready(struct rt2880_spi *rs)
289 +{
290 + int i;
291 +
292 + for (i = 0; i < RALINK_SPI_WAIT_MAX_LOOP; i++) {
293 + u32 status;
294 +
295 + status = rt2880_spi_read(rs, RAMIPS_SPI_STAT);
296 + if ((status & SPISTAT_BUSY) == 0)
297 + return 0;
298 +
299 + cpu_relax();
300 + udelay(1);
301 + }
302 +
303 + return -ETIMEDOUT;
304 +}
305 +
306 +static unsigned int
307 +rt2880_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer)
308 +{
309 + struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
310 + unsigned count = 0;
311 + u8 *rx = xfer->rx_buf;
312 + const u8 *tx = xfer->tx_buf;
313 + int err;
314 +
315 + dev_dbg(&spi->dev, "read (%d): %s %s\n", xfer->len,
316 + (tx != NULL) ? "tx" : " ",
317 + (rx != NULL) ? "rx" : " ");
318 +
319 + if (tx) {
320 + for (count = 0; count < xfer->len; count++) {
321 + rt2880_spi_write(rs, RAMIPS_SPI_DATA, tx[count]);
322 + rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTWR);
323 + err = rt2880_spi_wait_till_ready(rs);
324 + if (err) {
325 + dev_err(&spi->dev, "TX failed, err=%d\n", err);
326 + goto out;
327 + }
328 + }
329 + }
330 +
331 + if (rx) {
332 + for (count = 0; count < xfer->len; count++) {
333 + rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTRD);
334 + err = rt2880_spi_wait_till_ready(rs);
335 + if (err) {
336 + dev_err(&spi->dev, "RX failed, err=%d\n", err);
337 + goto out;
338 + }
339 + rx[count] = (u8) rt2880_spi_read(rs, RAMIPS_SPI_DATA);
340 + }
341 + }
342 +
343 +out:
344 + return count;
345 +}
346 +
347 +static int rt2880_spi_transfer_one_message(struct spi_master *master,
348 + struct spi_message *m)
349 +{
350 + struct rt2880_spi *rs = spi_master_get_devdata(master);
351 + struct spi_device *spi = m->spi;
352 + struct spi_transfer *t = NULL;
353 + int par_override = 0;
354 + int status = 0;
355 + int cs_active = 0;
356 +
357 + /* Load defaults */
358 + status = rt2880_spi_setup_transfer(spi, NULL);
359 + if (status < 0)
360 + goto msg_done;
361 +
362 + list_for_each_entry(t, &m->transfers, transfer_list) {
363 + if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
364 + dev_err(&spi->dev,
365 + "message rejected: invalid transfer data buffers\n");
366 + status = -EIO;
367 + goto msg_done;
368 + }
369 +
370 + if (t->speed_hz && t->speed_hz < (rs->sys_freq / 128)) {
371 + dev_err(&spi->dev,
372 + "message rejected: device min speed (%d Hz) exceeds required transfer speed (%d Hz)\n",
373 + (rs->sys_freq / 128), t->speed_hz);
374 + status = -EIO;
375 + goto msg_done;
376 + }
377 +
378 + if (par_override || t->speed_hz || t->bits_per_word) {
379 + par_override = 1;
380 + status = rt2880_spi_setup_transfer(spi, t);
381 + if (status < 0)
382 + goto msg_done;
383 + if (!t->speed_hz && !t->bits_per_word)
384 + par_override = 0;
385 + }
386 +
387 + if (!cs_active) {
388 + rt2880_spi_set_cs(rs, 1);
389 + cs_active = 1;
390 + }
391 +
392 + if (t->len)
393 + m->actual_length += rt2880_spi_write_read(spi, t);
394 +
395 + if (t->delay_usecs)
396 + udelay(t->delay_usecs);
397 +
398 + if (t->cs_change) {
399 + rt2880_spi_set_cs(rs, 0);
400 + cs_active = 0;
401 + }
402 + }
403 +
404 +msg_done:
405 + if (cs_active)
406 + rt2880_spi_set_cs(rs, 0);
407 +
408 + m->status = status;
409 + spi_finalize_current_message(master);
410 +
411 + return 0;
412 +}
413 +
414 +static int rt2880_spi_setup(struct spi_device *spi)
415 +{
416 + struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
417 +
418 + if ((spi->max_speed_hz == 0) ||
419 + (spi->max_speed_hz > (rs->sys_freq / 2)))
420 + spi->max_speed_hz = (rs->sys_freq / 2);
421 +
422 + if (spi->max_speed_hz < (rs->sys_freq / 128)) {
423 + dev_err(&spi->dev, "setup: requested speed is too low %d Hz\n",
424 + spi->max_speed_hz);
425 + return -EINVAL;
426 + }
427 +
428 + /*
429 + * baudrate & width will be set rt2880_spi_setup_transfer
430 + */
431 + return 0;
432 +}
433 +
434 +static void rt2880_spi_reset(struct rt2880_spi *rs)
435 +{
436 + rt2880_spi_write(rs, RAMIPS_SPI_CFG,
437 + SPICFG_MSBFIRST | SPICFG_TXCLKEDGE_FALLING |
438 + SPICFG_SPICLK_DIV16 | SPICFG_SPICLKPOL);
439 + rt2880_spi_write(rs, RAMIPS_SPI_CTL, SPICTL_HIZSDO | SPICTL_SPIENA);
440 +}
441 +
442 +static int rt2880_spi_probe(struct platform_device *pdev)
443 +{
444 + struct spi_master *master;
445 + struct rt2880_spi *rs;
446 + unsigned long flags;
447 + void __iomem *base;
448 + struct resource *r;
449 + int status = 0;
450 + struct clk *clk;
451 +
452 + r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
453 + base = devm_ioremap_resource(&pdev->dev, r);
454 + if (IS_ERR(base))
455 + return PTR_ERR(base);
456 +
457 + clk = devm_clk_get(&pdev->dev, NULL);
458 + if (IS_ERR(clk)) {
459 + dev_err(&pdev->dev, "unable to get SYS clock, err=%d\n",
460 + status);
461 + return PTR_ERR(clk);
462 + }
463 +
464 + status = clk_prepare_enable(clk);
465 + if (status)
466 + return status;
467 +
468 + master = spi_alloc_master(&pdev->dev, sizeof(*rs));
469 + if (master == NULL) {
470 + dev_dbg(&pdev->dev, "master allocation failed\n");
471 + return -ENOMEM;
472 + }
473 +
474 + /* we support only mode 0, and no options */
475 + master->mode_bits = 0;
476 +
477 + master->setup = rt2880_spi_setup;
478 + master->transfer_one_message = rt2880_spi_transfer_one_message;
479 + master->num_chipselect = RALINK_NUM_CHIPSELECTS;
480 + master->bits_per_word_mask = SPI_BPW_MASK(8);
481 + master->dev.of_node = pdev->dev.of_node;
482 +
483 + dev_set_drvdata(&pdev->dev, master);
484 +
485 + rs = spi_master_get_devdata(master);
486 + rs->base = base;
487 + rs->clk = clk;
488 + rs->master = master;
489 + rs->sys_freq = clk_get_rate(rs->clk);
490 + dev_dbg(&pdev->dev, "sys_freq: %u\n", rs->sys_freq);
491 + spin_lock_irqsave(&rs->lock, flags);
492 +
493 + device_reset(&pdev->dev);
494 +
495 + rt2880_spi_reset(rs);
496 +
497 + return spi_register_master(master);
498 +}
499 +
500 +static int rt2880_spi_remove(struct platform_device *pdev)
501 +{
502 + struct spi_master *master;
503 + struct rt2880_spi *rs;
504 +
505 + master = dev_get_drvdata(&pdev->dev);
506 + rs = spi_master_get_devdata(master);
507 +
508 + clk_disable(rs->clk);
509 + spi_unregister_master(master);
510 +
511 + return 0;
512 +}
513 +
514 +MODULE_ALIAS("platform:" DRIVER_NAME);
515 +
516 +static const struct of_device_id rt2880_spi_match[] = {
517 + { .compatible = "ralink,rt2880-spi" },
518 + {},
519 +};
520 +MODULE_DEVICE_TABLE(of, rt2880_spi_match);
521 +
522 +static struct platform_driver rt2880_spi_driver = {
523 + .driver = {
524 + .name = DRIVER_NAME,
525 + .owner = THIS_MODULE,
526 + .of_match_table = rt2880_spi_match,
527 + },
528 + .probe = rt2880_spi_probe,
529 + .remove = rt2880_spi_remove,
530 +};
531 +
532 +module_platform_driver(rt2880_spi_driver);
533 +
534 +MODULE_DESCRIPTION("Ralink SPI driver");
535 +MODULE_AUTHOR("Sergiy <piratfm@gmail.com>");
536 +MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
537 +MODULE_LICENSE("GPL");
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