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mac80211: make it work with 3.18.12+
[openwrt/openwrt.git] / target / linux / ramips / patches-3.18 / 0062-mt7621-add-ECHI-OCHI-XCHI-support.patch
1 --- a/drivers/usb/core/hcd-pci.c
2 +++ b/drivers/usb/core/hcd-pci.c
3 @@ -214,8 +214,13 @@
4 goto disable_pci;
5 }
6
7 +
8 +#ifdef CONFIG_USB_MT7621_XHCI_PLATFORM
9 + hcd->amd_resume_bug = 0;
10 +#else
11 hcd->amd_resume_bug = (usb_hcd_amd_remote_wakeup_quirk(dev) &&
12 driver->flags & (HCD_USB11 | HCD_USB3)) ? 1 : 0;
13 +#endif
14
15 if (driver->flags & HCD_MEMORY) {
16 /* EHCI, OHCI */
17 --- a/drivers/usb/core/hub.c
18 +++ b/drivers/usb/core/hub.c
19 @@ -1286,7 +1286,7 @@
20 if (type != HUB_SUSPEND) {
21 /* Disconnect all the children */
22 for (i = 0; i < hdev->maxchild; ++i) {
23 - if (hub->ports[i]->child)
24 + if (hub->ports[i] && hub->ports[i]->child)
25 usb_disconnect(&hub->ports[i]->child);
26 }
27 }
28 --- a/drivers/usb/core/port.c
29 +++ b/drivers/usb/core/port.c
30 @@ -480,8 +480,10 @@
31 struct usb_port *port_dev = hub->ports[port1 - 1];
32 struct usb_port *peer;
33
34 - peer = port_dev->peer;
35 - if (peer)
36 - unlink_peers(port_dev, peer);
37 - device_unregister(&port_dev->dev);
38 + if(port_dev) {
39 + peer = port_dev->peer;
40 + if (peer)
41 + unlink_peers(port_dev, peer);
42 + device_unregister(&port_dev->dev);
43 + }
44 }
45 --- a/drivers/usb/host/Kconfig
46 +++ b/drivers/usb/host/Kconfig
47 @@ -32,7 +32,13 @@
48 default y
49
50 config USB_XHCI_PLATFORM
51 - tristate
52 + tristate "xHCI platform"
53 +
54 +config USB_MT7621_XHCI_PLATFORM
55 + bool "MTK MT7621 xHCI"
56 + depends on USB_XHCI_PLATFORM
57 + depends on SOC_MT7621
58 + select USB_PHY
59
60 config USB_XHCI_MVEBU
61 tristate "xHCI support for Marvell Armada 375/38x"
62 @@ -589,7 +595,7 @@
63
64 config USB_UHCI_HCD
65 tristate "UHCI HCD (most Intel and VIA) support"
66 - depends on PCI || USB_UHCI_SUPPORT_NON_PCI_HC
67 + depends on BROKEN && (PCI || USB_UHCI_SUPPORT_NON_PCI_HC)
68 ---help---
69 The Universal Host Controller Interface is a standard by Intel for
70 accessing the USB hardware in the PC (which is also called the USB
71 --- a/drivers/usb/host/Makefile
72 +++ b/drivers/usb/host/Makefile
73 @@ -16,7 +16,12 @@
74 xhci-hcd-y += xhci-ring.o xhci-hub.o xhci-dbg.o
75 xhci-hcd-y += xhci-trace.o
76
77 +ifdef CONFIG_USB_MT7621_XHCI_PLATFORM
78 +xhci-hcd-y += mtk-phy.o xhci-mtk-scheduler.o xhci-mtk-power.o xhci-mtk.o mtk-phy-7621.o mtk-phy-ahb.o
79 +endif
80 +
81 xhci-plat-hcd-y := xhci-plat.o
82 +
83 ifneq ($(CONFIG_USB_XHCI_MVEBU), )
84 xhci-plat-hcd-y += xhci-mvebu.o
85 endif
86 @@ -26,9 +31,14 @@
87
88 obj-$(CONFIG_USB_WHCI_HCD) += whci/
89
90 +ifndef CONFIG_USB_MT7621_XHCI_PLATFORM
91 obj-$(CONFIG_PCI) += pci-quirks.o
92 +endif
93
94 +ifndef CONFIG_USB_MT7621_XHCI_PLATFORM
95 obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o
96 +endif
97 +
98 obj-$(CONFIG_USB_XHCI_PLATFORM) += xhci-plat-hcd.o
99
100 obj-$(CONFIG_USB_EHCI_HCD) += ehci-hcd.o
101 --- /dev/null
102 +++ b/drivers/usb/host/mtk-phy-7621.c
103 @@ -0,0 +1,445 @@
104 +#include "mtk-phy.h"
105 +
106 +#ifdef CONFIG_PROJECT_7621
107 +#include "mtk-phy-7621.h"
108 +
109 +//not used on SoC
110 +PHY_INT32 phy_init(struct u3phy_info *info){
111 + return PHY_TRUE;
112 +}
113 +
114 +//not used on SoC
115 +PHY_INT32 phy_change_pipe_phase(struct u3phy_info *info, PHY_INT32 phy_drv, PHY_INT32 pipe_phase){
116 + return PHY_TRUE;
117 +}
118 +
119 +//--------------------------------------------------------
120 +// Function : fgEyeScanHelper_CheckPtInRegion()
121 +// Description : Check if the test point is in a rectangle region.
122 +// If it is in the rectangle, also check if this point
123 +// is on the multiple of deltaX and deltaY.
124 +// Parameter : strucScanRegion * prEye - the region
125 +// BYTE bX
126 +// BYTE bY
127 +// Return : BYTE - TRUE : This point needs to be tested
128 +// FALSE: This point will be omitted
129 +// Note : First check within the rectangle.
130 +// Secondly, use modulous to check if the point will be tested.
131 +//--------------------------------------------------------
132 +static PHY_INT8 fgEyeScanHelper_CheckPtInRegion(struct strucScanRegion * prEye, PHY_INT8 bX, PHY_INT8 bY)
133 +{
134 + PHY_INT8 fgValid = true;
135 +
136 +
137 + /// Be careful, the axis origin is on the TOP-LEFT corner.
138 + /// Therefore the top-left point has the minimum X and Y
139 + /// Botton-right point is the maximum X and Y
140 + if ( (prEye->bX_tl <= bX) && (bX <= prEye->bX_br)
141 + && (prEye->bY_tl <= bY) && (bY <= prEye->bX_br))
142 + {
143 + // With the region, now check whether or not the input test point is
144 + // on the multiples of X and Y
145 + // Do not have to worry about negative value, because we have already
146 + // check the input bX, and bY is within the region.
147 + if ( ((bX - prEye->bX_tl) % (prEye->bDeltaX))
148 + || ((bY - prEye->bY_tl) % (prEye->bDeltaY)) )
149 + {
150 + // if the division will have remainder, that means
151 + // the input test point is on the multiples of X and Y
152 + fgValid = false;
153 + }
154 + else
155 + {
156 + }
157 + }
158 + else
159 + {
160 +
161 + fgValid = false;
162 + }
163 + return fgValid;
164 +}
165 +
166 +//--------------------------------------------------------
167 +// Function : EyeScanHelper_RunTest()
168 +// Description : Enable the test, and wait til it is completed
169 +// Parameter : None
170 +// Return : None
171 +// Note : None
172 +//--------------------------------------------------------
173 +static void EyeScanHelper_RunTest(struct u3phy_info *info)
174 +{
175 + DRV_UDELAY(100);
176 + // Disable the test
177 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
178 + , RG_SSUSB_EQ_EYE_CNT_EN_OFST, RG_SSUSB_EQ_EYE_CNT_EN, 0); //RG_SSUSB_RX_EYE_CNT_EN = 0
179 + DRV_UDELAY(100);
180 + // Run the test
181 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
182 + , RG_SSUSB_EQ_EYE_CNT_EN_OFST, RG_SSUSB_EQ_EYE_CNT_EN, 1); //RG_SSUSB_RX_EYE_CNT_EN = 1
183 + DRV_UDELAY(100);
184 + // Wait til it's done
185 + //RGS_SSUSB_RX_EYE_CNT_RDY
186 + while(!U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->phya_rx_mon5)
187 + , RGS_SSUSB_EQ_EYE_CNT_RDY_OFST, RGS_SSUSB_EQ_EYE_CNT_RDY));
188 +}
189 +
190 +//--------------------------------------------------------
191 +// Function : fgEyeScanHelper_CalNextPoint()
192 +// Description : Calcualte the test point for the measurement
193 +// Parameter : None
194 +// Return : BOOL - TRUE : the next point is within the
195 +// boundaryof HW limit
196 +// FALSE: the next point is out of the HW limit
197 +// Note : The next point is obtained by calculating
198 +// from the bottom left of the region rectangle
199 +// and then scanning up until it reaches the upper
200 +// limit. At this time, the x will increment, and
201 +// start scanning downwards until the y hits the
202 +// zero.
203 +//--------------------------------------------------------
204 +static PHY_INT8 fgEyeScanHelper_CalNextPoint(void)
205 +{
206 + if ( ((_bYcurr == MAX_Y) && (_eScanDir == SCAN_DN))
207 + || ((_bYcurr == MIN_Y) && (_eScanDir == SCAN_UP))
208 + )
209 + {
210 + /// Reaches the limit of Y axis
211 + /// Increment X
212 + _bXcurr++;
213 + _fgXChged = true;
214 + _eScanDir = (_eScanDir == SCAN_UP) ? SCAN_DN : SCAN_UP;
215 +
216 + if (_bXcurr > MAX_X)
217 + {
218 + return false;
219 + }
220 + }
221 + else
222 + {
223 + _bYcurr = (_eScanDir == SCAN_DN) ? _bYcurr + 1 : _bYcurr - 1;
224 + _fgXChged = false;
225 + }
226 + return PHY_TRUE;
227 +}
228 +
229 +PHY_INT32 eyescan_init(struct u3phy_info *info){
230 + //initial PHY setting
231 + U3PhyWriteField32(((PHY_UINT32)&info->u3phya_regs->rega)
232 + , RG_SSUSB_CDR_EPEN_OFST, RG_SSUSB_CDR_EPEN, 1);
233 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->phyd_mix3)
234 + , RG_SSUSB_FORCE_CDR_PI_PWD_OFST, RG_SSUSB_FORCE_CDR_PI_PWD, 1);
235 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
236 + , RG_SSUSB_RX_PI_CAL_EN_SEL_OFST, RG_SSUSB_RX_PI_CAL_EN_SEL, 1); //RG_SSUSB_RX_PI_CAL_MANUAL_SEL = 1
237 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
238 + , RG_SSUSB_RX_PI_CAL_EN_OFST, RG_SSUSB_RX_PI_CAL_EN, 1); //RG_SSUSB_RX_PI_CAL_MANUAL_EN = 1
239 + return PHY_TRUE;
240 +}
241 +
242 +PHY_INT32 phy_eyescan(struct u3phy_info *info, PHY_INT32 x_t1, PHY_INT32 y_t1, PHY_INT32 x_br, PHY_INT32 y_br, PHY_INT32 delta_x, PHY_INT32 delta_y
243 + , PHY_INT32 eye_cnt, PHY_INT32 num_cnt, PHY_INT32 PI_cal_en, PHY_INT32 num_ignore_cnt){
244 + PHY_INT32 cOfst = 0;
245 + PHY_UINT8 bIdxX = 0;
246 + PHY_UINT8 bIdxY = 0;
247 + //PHY_INT8 bCnt = 0;
248 + PHY_UINT8 bIdxCycCnt = 0;
249 + PHY_INT8 fgValid;
250 + PHY_INT8 cX;
251 + PHY_INT8 cY;
252 + PHY_UINT8 bExtendCnt;
253 + PHY_INT8 isContinue;
254 + //PHY_INT8 isBreak;
255 + PHY_UINT32 wErr0 = 0, wErr1 = 0;
256 + //PHY_UINT32 temp;
257 +
258 + PHY_UINT32 pwErrCnt0[CYCLE_COUNT_MAX][ERRCNT_MAX][ERRCNT_MAX];
259 + PHY_UINT32 pwErrCnt1[CYCLE_COUNT_MAX][ERRCNT_MAX][ERRCNT_MAX];
260 +
261 + _rEye1.bX_tl = x_t1;
262 + _rEye1.bY_tl = y_t1;
263 + _rEye1.bX_br = x_br;
264 + _rEye1.bY_br = y_br;
265 + _rEye1.bDeltaX = delta_x;
266 + _rEye1.bDeltaY = delta_y;
267 +
268 + _rEye2.bX_tl = x_t1;
269 + _rEye2.bY_tl = y_t1;
270 + _rEye2.bX_br = x_br;
271 + _rEye2.bY_br = y_br;
272 + _rEye2.bDeltaX = delta_x;
273 + _rEye2.bDeltaY = delta_y;
274 +
275 + _rTestCycle.wEyeCnt = eye_cnt;
276 + _rTestCycle.bNumOfEyeCnt = num_cnt;
277 + _rTestCycle.bNumOfIgnoreCnt = num_ignore_cnt;
278 + _rTestCycle.bPICalEn = PI_cal_en;
279 +
280 + _bXcurr = 0;
281 + _bYcurr = 0;
282 + _eScanDir = SCAN_DN;
283 + _fgXChged = false;
284 +
285 + printk("x_t1: %x, y_t1: %x, x_br: %x, y_br: %x, delta_x: %x, delta_y: %x, \
286 + eye_cnt: %x, num_cnt: %x, PI_cal_en: %x, num_ignore_cnt: %x\n", \
287 + x_t1, y_t1, x_br, y_br, delta_x, delta_y, eye_cnt, num_cnt, PI_cal_en, num_ignore_cnt);
288 +
289 + //force SIGDET to OFF
290 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
291 + , RG_SSUSB_RX_SIGDET_EN_SEL_OFST, RG_SSUSB_RX_SIGDET_EN_SEL, 1); //RG_SSUSB_RX_SIGDET_SEL = 1
292 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
293 + , RG_SSUSB_RX_SIGDET_EN_OFST, RG_SSUSB_RX_SIGDET_EN, 0); //RG_SSUSB_RX_SIGDET_EN = 0
294 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye1)
295 + , RG_SSUSB_EQ_SIGDET_OFST, RG_SSUSB_EQ_SIGDET, 0); //RG_SSUSB_RX_SIGDET = 0
296 +
297 + // RX_TRI_DET_EN to Disable
298 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq3)
299 + , RG_SSUSB_EQ_TRI_DET_EN_OFST, RG_SSUSB_EQ_TRI_DET_EN, 0); //RG_SSUSB_RX_TRI_DET_EN = 0
300 +
301 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
302 + , RG_SSUSB_EQ_EYE_MON_EN_OFST, RG_SSUSB_EQ_EYE_MON_EN, 1); //RG_SSUSB_EYE_MON_EN = 1
303 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
304 + , RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET, 0); //RG_SSUSB_RX_EYE_XOFFSET = 0
305 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
306 + , RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y, 0); //RG_SSUSB_RX_EYE0_Y = 0
307 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
308 + , RG_SSUSB_EQ_EYE1_Y_OFST, RG_SSUSB_EQ_EYE1_Y, 0); //RG_SSUSB_RX_EYE1_Y = 0
309 +
310 +
311 + if (PI_cal_en){
312 + // PI Calibration
313 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
314 + , RG_SSUSB_RX_PI_CAL_EN_SEL_OFST, RG_SSUSB_RX_PI_CAL_EN_SEL, 1); //RG_SSUSB_RX_PI_CAL_MANUAL_SEL = 1
315 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
316 + , RG_SSUSB_RX_PI_CAL_EN_OFST, RG_SSUSB_RX_PI_CAL_EN, 0); //RG_SSUSB_RX_PI_CAL_MANUAL_EN = 0
317 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
318 + , RG_SSUSB_RX_PI_CAL_EN_OFST, RG_SSUSB_RX_PI_CAL_EN, 1); //RG_SSUSB_RX_PI_CAL_MANUAL_EN = 1
319 +
320 + DRV_UDELAY(20);
321 +
322 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
323 + , RG_SSUSB_RX_PI_CAL_EN_OFST, RG_SSUSB_RX_PI_CAL_EN, 0); //RG_SSUSB_RX_PI_CAL_MANUAL_EN = 0
324 + _bPIResult = U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->phya_rx_mon5)
325 + , RGS_SSUSB_EQ_PILPO_OFST, RGS_SSUSB_EQ_PILPO); //read RGS_SSUSB_RX_PILPO
326 +
327 + printk(KERN_ERR "PI result: %d\n", _bPIResult);
328 + }
329 + // Read Initial DAC
330 + // Set CYCLE
331 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye3)
332 + ,RG_SSUSB_EQ_EYE_CNT_OFST, RG_SSUSB_EQ_EYE_CNT, eye_cnt); //RG_SSUSB_RX_EYE_CNT
333 +
334 + // Eye Monitor Feature
335 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye1)
336 + , RG_SSUSB_EQ_EYE_MASK_OFST, RG_SSUSB_EQ_EYE_MASK, 0x3ff); //RG_SSUSB_RX_EYE_MASK = 0x3ff
337 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
338 + , RG_SSUSB_EQ_EYE_MON_EN_OFST, RG_SSUSB_EQ_EYE_MON_EN, 1); //RG_SSUSB_EYE_MON_EN = 1
339 +
340 + // Move X,Y to the top-left corner
341 + for (cOfst = 0; cOfst >= -64; cOfst--)
342 + {
343 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
344 + ,RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET, cOfst); //RG_SSUSB_RX_EYE_XOFFSET
345 + }
346 + for (cOfst = 0; cOfst < 64; cOfst++)
347 + {
348 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
349 + , RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y, cOfst); //RG_SSUSB_RX_EYE0_Y
350 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
351 + , RG_SSUSB_EQ_EYE1_Y_OFST, RG_SSUSB_EQ_EYE1_Y, cOfst); //RG_SSUSB_RX_EYE1_Y
352 + }
353 + //ClearErrorResult
354 + for(bIdxCycCnt = 0; bIdxCycCnt < CYCLE_COUNT_MAX; bIdxCycCnt++){
355 + for(bIdxX = 0; bIdxX < ERRCNT_MAX; bIdxX++)
356 + {
357 + for(bIdxY = 0; bIdxY < ERRCNT_MAX; bIdxY++){
358 + pwErrCnt0[bIdxCycCnt][bIdxX][bIdxY] = 0;
359 + pwErrCnt1[bIdxCycCnt][bIdxX][bIdxY] = 0;
360 + }
361 + }
362 + }
363 + isContinue = true;
364 + while(isContinue){
365 + //printk(KERN_ERR "_bXcurr: %d, _bYcurr: %d\n", _bXcurr, _bYcurr);
366 + // The point is within the boundary, then let's check if it is within
367 + // the testing region.
368 + // The point is only test-able if one of the eye region
369 + // includes this point.
370 + fgValid = fgEyeScanHelper_CheckPtInRegion(&_rEye1, _bXcurr, _bYcurr)
371 + || fgEyeScanHelper_CheckPtInRegion(&_rEye2, _bXcurr, _bYcurr);
372 + // Translate bX and bY to 2's complement from where the origin was on the
373 + // top left corner.
374 + // 0x40 and 0x3F needs a bit of thinking!!!! >"<
375 + cX = (_bXcurr ^ 0x40);
376 + cY = (_bYcurr ^ 0x3F);
377 +
378 + // Set X if necessary
379 + if (_fgXChged == true)
380 + {
381 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
382 + , RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET, cX); //RG_SSUSB_RX_EYE_XOFFSET
383 + }
384 + // Set Y
385 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
386 + , RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y, cY); //RG_SSUSB_RX_EYE0_Y
387 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
388 + , RG_SSUSB_EQ_EYE1_Y_OFST, RG_SSUSB_EQ_EYE1_Y, cY); //RG_SSUSB_RX_EYE1_Y
389 +
390 + /// Test this point!
391 + if (fgValid){
392 + for (bExtendCnt = 0; bExtendCnt < num_ignore_cnt; bExtendCnt++)
393 + {
394 + //run test
395 + EyeScanHelper_RunTest(info);
396 + }
397 + for (bExtendCnt = 0; bExtendCnt < num_cnt; bExtendCnt++)
398 + {
399 + EyeScanHelper_RunTest(info);
400 + wErr0 = U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->phya_rx_mon3)
401 + , RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_0_OFST, RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_0);
402 + wErr1 = U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->phya_rx_mon4)
403 + , RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_1_OFST, RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_1);
404 +
405 + pwErrCnt0[bExtendCnt][_bXcurr][_bYcurr] = wErr0;
406 + pwErrCnt1[bExtendCnt][_bXcurr][_bYcurr] = wErr1;
407 +
408 + //EyeScanHelper_GetResult(&_rRes.pwErrCnt0[bCnt], &_rRes.pwErrCnt1[bCnt]);
409 +// printk(KERN_ERR "cnt[%d] cur_x,y [0x%x][0x%x], cX,cY [0x%x][0x%x], ErrCnt[%d][%d]\n"
410 +// , bExtendCnt, _bXcurr, _bYcurr, cX, cY, pwErrCnt0[bExtendCnt][_bXcurr][_bYcurr], pwErrCnt1[bExtendCnt][_bXcurr][_bYcurr]);
411 + }
412 + //printk(KERN_ERR "cur_x,y [0x%x][0x%x], cX,cY [0x%x][0x%x], ErrCnt[%d][%d]\n", _bXcurr, _bYcurr, cX, cY, pwErrCnt0[0][_bXcurr][_bYcurr], pwErrCnt1[0][_bXcurr][_bYcurr]);
413 + }
414 + else{
415 +
416 + }
417 + if (fgEyeScanHelper_CalNextPoint() == false){
418 +#if 0
419 + printk(KERN_ERR "Xcurr [0x%x] Ycurr [0x%x]\n", _bXcurr, _bYcurr);
420 + printk(KERN_ERR "XcurrREG [0x%x] YcurrREG [0x%x]\n", cX, cY);
421 +#endif
422 + printk(KERN_ERR "end of eye scan\n");
423 + isContinue = false;
424 + }
425 + }
426 + printk(KERN_ERR "CurX [0x%x] CurY [0x%x]\n"
427 + , U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0), RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET)
428 + , U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0), RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y));
429 +
430 + // Move X,Y to the top-left corner
431 + for (cOfst = 63; cOfst >= 0; cOfst--)
432 + {
433 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
434 + , RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET, cOfst); //RG_SSUSB_RX_EYE_XOFFSET
435 + }
436 + for (cOfst = 63; cOfst >= 0; cOfst--)
437 + {
438 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
439 + , RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y, cOfst);
440 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
441 + , RG_SSUSB_EQ_EYE1_Y_OFST, RG_SSUSB_EQ_EYE1_Y, cOfst);
442 +
443 + }
444 + printk(KERN_ERR "CurX [0x%x] CurY [0x%x]\n"
445 + , U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0), RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET)
446 + , U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0), RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y));
447 +
448 + printk(KERN_ERR "PI result: %d\n", _bPIResult);
449 + printk(KERN_ERR "pwErrCnt0 addr: 0x%x\n", (PHY_UINT32)pwErrCnt0);
450 + printk(KERN_ERR "pwErrCnt1 addr: 0x%x\n", (PHY_UINT32)pwErrCnt1);
451 +
452 + return PHY_TRUE;
453 +}
454 +
455 +//not used on SoC
456 +PHY_INT32 u2_save_cur_en(struct u3phy_info *info){
457 + return PHY_TRUE;
458 +}
459 +
460 +//not used on SoC
461 +PHY_INT32 u2_save_cur_re(struct u3phy_info *info){
462 + return PHY_TRUE;
463 +}
464 +
465 +PHY_INT32 u2_slew_rate_calibration(struct u3phy_info *info){
466 + PHY_INT32 i=0;
467 + //PHY_INT32 j=0;
468 + //PHY_INT8 u1SrCalVal = 0;
469 + //PHY_INT8 u1Reg_addr_HSTX_SRCAL_EN;
470 + PHY_INT32 fgRet = 0;
471 + PHY_INT32 u4FmOut = 0;
472 + PHY_INT32 u4Tmp = 0;
473 + //PHY_INT32 temp;
474 +
475 + // => RG_USB20_HSTX_SRCAL_EN = 1
476 + // enable HS TX SR calibration
477 + U3PhyWriteField32(((PHY_UINT32)&info->u2phy_regs->u2phyacr0)
478 + , RG_USB20_HSTX_SRCAL_EN_OFST, RG_USB20_HSTX_SRCAL_EN, 0x1);
479 + DRV_MSLEEP(1);
480 +
481 + // => RG_FRCK_EN = 1
482 + // Enable free run clock
483 + U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmmonr1)
484 + , RG_FRCK_EN_OFST, RG_FRCK_EN, 1);
485 +
486 + // MT6290 HS signal quality patch
487 + // => RG_CYCLECNT = 400
488 + // Setting cyclecnt =400
489 + U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmcr0)
490 + , RG_CYCLECNT_OFST, RG_CYCLECNT, 0x400);
491 +
492 + // => RG_FREQDET_EN = 1
493 + // Enable frequency meter
494 + U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmcr0)
495 + , RG_FREQDET_EN_OFST, RG_FREQDET_EN, 0x1);
496 +
497 + // wait for FM detection done, set 10ms timeout
498 + for(i=0; i<10; i++){
499 + // => u4FmOut = USB_FM_OUT
500 + // read FM_OUT
501 + u4FmOut = U3PhyReadReg32(((PHY_UINT32)&info->sifslv_fm_regs->fmmonr0));
502 + printk("FM_OUT value: u4FmOut = %d(0x%08X)\n", u4FmOut, u4FmOut);
503 +
504 + // check if FM detection done
505 + if (u4FmOut != 0)
506 + {
507 + fgRet = 0;
508 + printk("FM detection done! loop = %d\n", i);
509 +
510 + break;
511 + }
512 +
513 + fgRet = 1;
514 + DRV_MSLEEP(1);
515 + }
516 + // => RG_FREQDET_EN = 0
517 + // disable frequency meter
518 + U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmcr0)
519 + , RG_FREQDET_EN_OFST, RG_FREQDET_EN, 0);
520 +
521 + // => RG_FRCK_EN = 0
522 + // disable free run clock
523 + U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmmonr1)
524 + , RG_FRCK_EN_OFST, RG_FRCK_EN, 0);
525 +
526 + // => RG_USB20_HSTX_SRCAL_EN = 0
527 + // disable HS TX SR calibration
528 + U3PhyWriteField32(((PHY_UINT32)&info->u2phy_regs->u2phyacr0)
529 + , RG_USB20_HSTX_SRCAL_EN_OFST, RG_USB20_HSTX_SRCAL_EN, 0);
530 + DRV_MSLEEP(1);
531 +
532 + if(u4FmOut == 0){
533 + U3PhyWriteField32(((PHY_UINT32)&info->u2phy_regs->u2phyacr0)
534 + , RG_USB20_HSTX_SRCTRL_OFST, RG_USB20_HSTX_SRCTRL, 0x4);
535 +
536 + fgRet = 1;
537 + }
538 + else{
539 + // set reg = (1024/FM_OUT) * 25 * 0.028 (round to the nearest digits)
540 + u4Tmp = (((1024 * 25 * U2_SR_COEF_7621) / u4FmOut) + 500) / 1000;
541 + printk("SR calibration value u1SrCalVal = %d\n", (PHY_UINT8)u4Tmp);
542 + U3PhyWriteField32(((PHY_UINT32)&info->u2phy_regs->u2phyacr0)
543 + , RG_USB20_HSTX_SRCTRL_OFST, RG_USB20_HSTX_SRCTRL, u4Tmp);
544 + }
545 + return fgRet;
546 +}
547 +
548 +#endif
549 --- /dev/null
550 +++ b/drivers/usb/host/mtk-phy-7621.h
551 @@ -0,0 +1,2871 @@
552 +#ifdef CONFIG_PROJECT_7621
553 +#ifndef __MTK_PHY_7621_H
554 +#define __MTK_PHY_7621_H
555 +
556 +#define U2_SR_COEF_7621 28
557 +
558 +///////////////////////////////////////////////////////////////////////////////
559 +
560 +struct u2phy_reg {
561 + //0x0
562 + PHY_LE32 u2phyac0;
563 + PHY_LE32 u2phyac1;
564 + PHY_LE32 u2phyac2;
565 + PHY_LE32 reserve0;
566 + //0x10
567 + PHY_LE32 u2phyacr0;
568 + PHY_LE32 u2phyacr1;
569 + PHY_LE32 u2phyacr2;
570 + PHY_LE32 u2phyacr3;
571 + //0x20
572 + PHY_LE32 u2phyacr4;
573 + PHY_LE32 u2phyamon0;
574 + PHY_LE32 reserve1[2];
575 + //0x30~0x50
576 + PHY_LE32 reserve2[12];
577 + //0x60
578 + PHY_LE32 u2phydcr0;
579 + PHY_LE32 u2phydcr1;
580 + PHY_LE32 u2phydtm0;
581 + PHY_LE32 u2phydtm1;
582 + //0x70
583 + PHY_LE32 u2phydmon0;
584 + PHY_LE32 u2phydmon1;
585 + PHY_LE32 u2phydmon2;
586 + PHY_LE32 u2phydmon3;
587 + //0x80
588 + PHY_LE32 u2phybc12c;
589 + PHY_LE32 u2phybc12c1;
590 + PHY_LE32 reserve3[2];
591 + //0x90~0xe0
592 + PHY_LE32 reserve4[24];
593 + //0xf0
594 + PHY_LE32 reserve6[3];
595 + PHY_LE32 regfcom;
596 +};
597 +
598 +//U3D_U2PHYAC0
599 +#define RG_USB20_USBPLL_DIVEN (0x7<<28) //30:28
600 +#define RG_USB20_USBPLL_CKCTRL (0x3<<26) //27:26
601 +#define RG_USB20_USBPLL_PREDIV (0x3<<24) //25:24
602 +#define RG_USB20_USBPLL_FORCE_ON (0x1<<23) //23:23
603 +#define RG_USB20_USBPLL_FBDIV (0x7f<<16) //22:16
604 +#define RG_USB20_REF_EN (0x1<<15) //15:15
605 +#define RG_USB20_INTR_EN (0x1<<14) //14:14
606 +#define RG_USB20_BG_TRIM (0xf<<8) //11:8
607 +#define RG_USB20_BG_RBSEL (0x3<<6) //7:6
608 +#define RG_USB20_BG_RASEL (0x3<<4) //5:4
609 +#define RG_USB20_BGR_DIV (0x3<<2) //3:2
610 +#define RG_SIFSLV_CHP_EN (0x1<<1) //1:1
611 +#define RG_SIFSLV_BGR_EN (0x1<<0) //0:0
612 +
613 +//U3D_U2PHYAC1
614 +#define RG_USB20_VRT_VREF_SEL (0x7<<28) //30:28
615 +#define RG_USB20_TERM_VREF_SEL (0x7<<24) //26:24
616 +#define RG_USB20_MPX_SEL (0xff<<16) //23:16
617 +#define RG_USB20_MPX_OUT_SEL (0x3<<12) //13:12
618 +#define RG_USB20_TX_PH_ROT_SEL (0x7<<8) //10:8
619 +#define RG_USB20_USBPLL_ACCEN (0x1<<3) //3:3
620 +#define RG_USB20_USBPLL_LF (0x1<<2) //2:2
621 +#define RG_USB20_USBPLL_BR (0x1<<1) //1:1
622 +#define RG_USB20_USBPLL_BP (0x1<<0) //0:0
623 +
624 +//U3D_U2PHYAC2
625 +#define RG_SIFSLV_MAC_BANDGAP_EN (0x1<<17) //17:17
626 +#define RG_SIFSLV_MAC_CHOPPER_EN (0x1<<16) //16:16
627 +#define RG_USB20_CLKREF_REV (0xff<<0) //7:0
628 +
629 +//U3D_U2PHYACR0
630 +#define RG_USB20_ICUSB_EN (0x1<<24) //24:24
631 +#define RG_USB20_HSTX_SRCAL_EN (0x1<<23) //23:23
632 +#define RG_USB20_HSTX_SRCTRL (0x7<<16) //18:16
633 +#define RG_USB20_LS_CR (0x7<<12) //14:12
634 +#define RG_USB20_FS_CR (0x7<<8) //10:8
635 +#define RG_USB20_LS_SR (0x7<<4) //6:4
636 +#define RG_USB20_FS_SR (0x7<<0) //2:0
637 +
638 +//U3D_U2PHYACR1
639 +#define RG_USB20_INIT_SQ_EN_DG (0x3<<28) //29:28
640 +#define RG_USB20_SQD (0x3<<24) //25:24
641 +#define RG_USB20_HSTX_TMODE_SEL (0x3<<20) //21:20
642 +#define RG_USB20_HSTX_TMODE_EN (0x1<<19) //19:19
643 +#define RG_USB20_PHYD_MONEN (0x1<<18) //18:18
644 +#define RG_USB20_INLPBK_EN (0x1<<17) //17:17
645 +#define RG_USB20_CHIRP_EN (0x1<<16) //16:16
646 +#define RG_USB20_DM_ABIST_SOURCE_EN (0x1<<15) //15:15
647 +#define RG_USB20_DM_ABIST_SELE (0xf<<8) //11:8
648 +#define RG_USB20_DP_ABIST_SOURCE_EN (0x1<<7) //7:7
649 +#define RG_USB20_DP_ABIST_SELE (0xf<<0) //3:0
650 +
651 +//U3D_U2PHYACR2
652 +#define RG_USB20_OTG_ABIST_SELE (0x7<<29) //31:29
653 +#define RG_USB20_OTG_ABIST_EN (0x1<<28) //28:28
654 +#define RG_USB20_OTG_VBUSCMP_EN (0x1<<27) //27:27
655 +#define RG_USB20_OTG_VBUSTH (0x7<<24) //26:24
656 +#define RG_USB20_DISC_FIT_EN (0x1<<22) //22:22
657 +#define RG_USB20_DISCD (0x3<<20) //21:20
658 +#define RG_USB20_DISCTH (0xf<<16) //19:16
659 +#define RG_USB20_SQCAL_EN (0x1<<15) //15:15
660 +#define RG_USB20_SQCAL (0xf<<8) //11:8
661 +#define RG_USB20_SQTH (0xf<<0) //3:0
662 +
663 +//U3D_U2PHYACR3
664 +#define RG_USB20_HSTX_DBIST (0xf<<28) //31:28
665 +#define RG_USB20_HSTX_BIST_EN (0x1<<26) //26:26
666 +#define RG_USB20_HSTX_I_EN_MODE (0x3<<24) //25:24
667 +#define RG_USB20_HSRX_TMODE_EN (0x1<<23) //23:23
668 +#define RG_USB20_HSRX_BIAS_EN_SEL (0x3<<20) //21:20
669 +#define RG_USB20_USB11_TMODE_EN (0x1<<19) //19:19
670 +#define RG_USB20_TMODE_FS_LS_TX_EN (0x1<<18) //18:18
671 +#define RG_USB20_TMODE_FS_LS_RCV_EN (0x1<<17) //17:17
672 +#define RG_USB20_TMODE_FS_LS_MODE (0x1<<16) //16:16
673 +#define RG_USB20_HS_TERM_EN_MODE (0x3<<13) //14:13
674 +#define RG_USB20_PUPD_BIST_EN (0x1<<12) //12:12
675 +#define RG_USB20_EN_PU_DM (0x1<<11) //11:11
676 +#define RG_USB20_EN_PD_DM (0x1<<10) //10:10
677 +#define RG_USB20_EN_PU_DP (0x1<<9) //9:9
678 +#define RG_USB20_EN_PD_DP (0x1<<8) //8:8
679 +#define RG_USB20_PHY_REV (0xff<<0) //7:0
680 +
681 +//U3D_U2PHYACR4
682 +#define RG_USB20_DP_100K_MODE (0x1<<18) //18:18
683 +#define RG_USB20_DM_100K_EN (0x1<<17) //17:17
684 +#define USB20_DP_100K_EN (0x1<<16) //16:16
685 +#define USB20_GPIO_DM_I (0x1<<15) //15:15
686 +#define USB20_GPIO_DP_I (0x1<<14) //14:14
687 +#define USB20_GPIO_DM_OE (0x1<<13) //13:13
688 +#define USB20_GPIO_DP_OE (0x1<<12) //12:12
689 +#define RG_USB20_GPIO_CTL (0x1<<9) //9:9
690 +#define USB20_GPIO_MODE (0x1<<8) //8:8
691 +#define RG_USB20_TX_BIAS_EN (0x1<<5) //5:5
692 +#define RG_USB20_TX_VCMPDN_EN (0x1<<4) //4:4
693 +#define RG_USB20_HS_SQ_EN_MODE (0x3<<2) //3:2
694 +#define RG_USB20_HS_RCV_EN_MODE (0x3<<0) //1:0
695 +
696 +//U3D_U2PHYAMON0
697 +#define RGO_USB20_GPIO_DM_O (0x1<<1) //1:1
698 +#define RGO_USB20_GPIO_DP_O (0x1<<0) //0:0
699 +
700 +//U3D_U2PHYDCR0
701 +#define RG_USB20_CDR_TST (0x3<<30) //31:30
702 +#define RG_USB20_GATED_ENB (0x1<<29) //29:29
703 +#define RG_USB20_TESTMODE (0x3<<26) //27:26
704 +#define RG_USB20_PLL_STABLE (0x1<<25) //25:25
705 +#define RG_USB20_PLL_FORCE_ON (0x1<<24) //24:24
706 +#define RG_USB20_PHYD_RESERVE (0xffff<<8) //23:8
707 +#define RG_USB20_EBTHRLD (0x1<<7) //7:7
708 +#define RG_USB20_EARLY_HSTX_I (0x1<<6) //6:6
709 +#define RG_USB20_TX_TST (0x1<<5) //5:5
710 +#define RG_USB20_NEGEDGE_ENB (0x1<<4) //4:4
711 +#define RG_USB20_CDR_FILT (0xf<<0) //3:0
712 +
713 +//U3D_U2PHYDCR1
714 +#define RG_USB20_PROBE_SEL (0xff<<24) //31:24
715 +#define RG_USB20_DRVVBUS (0x1<<23) //23:23
716 +#define RG_DEBUG_EN (0x1<<22) //22:22
717 +#define RG_USB20_OTG_PROBE (0x3<<20) //21:20
718 +#define RG_USB20_SW_PLLMODE (0x3<<18) //19:18
719 +#define RG_USB20_BERTH (0x3<<16) //17:16
720 +#define RG_USB20_LBMODE (0x3<<13) //14:13
721 +#define RG_USB20_FORCE_TAP (0x1<<12) //12:12
722 +#define RG_USB20_TAPSEL (0xfff<<0) //11:0
723 +
724 +//U3D_U2PHYDTM0
725 +#define RG_UART_MODE (0x3<<30) //31:30
726 +#define FORCE_UART_I (0x1<<29) //29:29
727 +#define FORCE_UART_BIAS_EN (0x1<<28) //28:28
728 +#define FORCE_UART_TX_OE (0x1<<27) //27:27
729 +#define FORCE_UART_EN (0x1<<26) //26:26
730 +#define FORCE_USB_CLKEN (0x1<<25) //25:25
731 +#define FORCE_DRVVBUS (0x1<<24) //24:24
732 +#define FORCE_DATAIN (0x1<<23) //23:23
733 +#define FORCE_TXVALID (0x1<<22) //22:22
734 +#define FORCE_DM_PULLDOWN (0x1<<21) //21:21
735 +#define FORCE_DP_PULLDOWN (0x1<<20) //20:20
736 +#define FORCE_XCVRSEL (0x1<<19) //19:19
737 +#define FORCE_SUSPENDM (0x1<<18) //18:18
738 +#define FORCE_TERMSEL (0x1<<17) //17:17
739 +#define FORCE_OPMODE (0x1<<16) //16:16
740 +#define UTMI_MUXSEL (0x1<<15) //15:15
741 +#define RG_RESET (0x1<<14) //14:14
742 +#define RG_DATAIN (0xf<<10) //13:10
743 +#define RG_TXVALIDH (0x1<<9) //9:9
744 +#define RG_TXVALID (0x1<<8) //8:8
745 +#define RG_DMPULLDOWN (0x1<<7) //7:7
746 +#define RG_DPPULLDOWN (0x1<<6) //6:6
747 +#define RG_XCVRSEL (0x3<<4) //5:4
748 +#define RG_SUSPENDM (0x1<<3) //3:3
749 +#define RG_TERMSEL (0x1<<2) //2:2
750 +#define RG_OPMODE (0x3<<0) //1:0
751 +
752 +//U3D_U2PHYDTM1
753 +#define RG_USB20_PRBS7_EN (0x1<<31) //31:31
754 +#define RG_USB20_PRBS7_BITCNT (0x3f<<24) //29:24
755 +#define RG_USB20_CLK48M_EN (0x1<<23) //23:23
756 +#define RG_USB20_CLK60M_EN (0x1<<22) //22:22
757 +#define RG_UART_I (0x1<<19) //19:19
758 +#define RG_UART_BIAS_EN (0x1<<18) //18:18
759 +#define RG_UART_TX_OE (0x1<<17) //17:17
760 +#define RG_UART_EN (0x1<<16) //16:16
761 +#define FORCE_VBUSVALID (0x1<<13) //13:13
762 +#define FORCE_SESSEND (0x1<<12) //12:12
763 +#define FORCE_BVALID (0x1<<11) //11:11
764 +#define FORCE_AVALID (0x1<<10) //10:10
765 +#define FORCE_IDDIG (0x1<<9) //9:9
766 +#define FORCE_IDPULLUP (0x1<<8) //8:8
767 +#define RG_VBUSVALID (0x1<<5) //5:5
768 +#define RG_SESSEND (0x1<<4) //4:4
769 +#define RG_BVALID (0x1<<3) //3:3
770 +#define RG_AVALID (0x1<<2) //2:2
771 +#define RG_IDDIG (0x1<<1) //1:1
772 +#define RG_IDPULLUP (0x1<<0) //0:0
773 +
774 +//U3D_U2PHYDMON0
775 +#define RG_USB20_PRBS7_BERTH (0xff<<0) //7:0
776 +
777 +//U3D_U2PHYDMON1
778 +#define USB20_UART_O (0x1<<31) //31:31
779 +#define RGO_USB20_LB_PASS (0x1<<30) //30:30
780 +#define RGO_USB20_LB_DONE (0x1<<29) //29:29
781 +#define AD_USB20_BVALID (0x1<<28) //28:28
782 +#define USB20_IDDIG (0x1<<27) //27:27
783 +#define AD_USB20_VBUSVALID (0x1<<26) //26:26
784 +#define AD_USB20_SESSEND (0x1<<25) //25:25
785 +#define AD_USB20_AVALID (0x1<<24) //24:24
786 +#define USB20_LINE_STATE (0x3<<22) //23:22
787 +#define USB20_HST_DISCON (0x1<<21) //21:21
788 +#define USB20_TX_READY (0x1<<20) //20:20
789 +#define USB20_RX_ERROR (0x1<<19) //19:19
790 +#define USB20_RX_ACTIVE (0x1<<18) //18:18
791 +#define USB20_RX_VALIDH (0x1<<17) //17:17
792 +#define USB20_RX_VALID (0x1<<16) //16:16
793 +#define USB20_DATA_OUT (0xffff<<0) //15:0
794 +
795 +//U3D_U2PHYDMON2
796 +#define RGO_TXVALID_CNT (0xff<<24) //31:24
797 +#define RGO_RXACTIVE_CNT (0xff<<16) //23:16
798 +#define RGO_USB20_LB_BERCNT (0xff<<8) //15:8
799 +#define USB20_PROBE_OUT (0xff<<0) //7:0
800 +
801 +//U3D_U2PHYDMON3
802 +#define RGO_USB20_PRBS7_ERRCNT (0xffff<<16) //31:16
803 +#define RGO_USB20_PRBS7_DONE (0x1<<3) //3:3
804 +#define RGO_USB20_PRBS7_LOCK (0x1<<2) //2:2
805 +#define RGO_USB20_PRBS7_PASS (0x1<<1) //1:1
806 +#define RGO_USB20_PRBS7_PASSTH (0x1<<0) //0:0
807 +
808 +//U3D_U2PHYBC12C
809 +#define RG_SIFSLV_CHGDT_DEGLCH_CNT (0xf<<28) //31:28
810 +#define RG_SIFSLV_CHGDT_CTRL_CNT (0xf<<24) //27:24
811 +#define RG_SIFSLV_CHGDT_FORCE_MODE (0x1<<16) //16:16
812 +#define RG_CHGDT_ISRC_LEV (0x3<<14) //15:14
813 +#define RG_CHGDT_VDATSRC (0x1<<13) //13:13
814 +#define RG_CHGDT_BGVREF_SEL (0x7<<10) //12:10
815 +#define RG_CHGDT_RDVREF_SEL (0x3<<8) //9:8
816 +#define RG_CHGDT_ISRC_DP (0x1<<7) //7:7
817 +#define RG_SIFSLV_CHGDT_OPOUT_DM (0x1<<6) //6:6
818 +#define RG_CHGDT_VDAT_DM (0x1<<5) //5:5
819 +#define RG_CHGDT_OPOUT_DP (0x1<<4) //4:4
820 +#define RG_SIFSLV_CHGDT_VDAT_DP (0x1<<3) //3:3
821 +#define RG_SIFSLV_CHGDT_COMP_EN (0x1<<2) //2:2
822 +#define RG_SIFSLV_CHGDT_OPDRV_EN (0x1<<1) //1:1
823 +#define RG_CHGDT_EN (0x1<<0) //0:0
824 +
825 +//U3D_U2PHYBC12C1
826 +#define RG_CHGDT_REV (0xff<<0) //7:0
827 +
828 +//U3D_REGFCOM
829 +#define RG_PAGE (0xff<<24) //31:24
830 +#define I2C_MODE (0x1<<16) //16:16
831 +
832 +
833 +/* OFFSET */
834 +
835 +//U3D_U2PHYAC0
836 +#define RG_USB20_USBPLL_DIVEN_OFST (28)
837 +#define RG_USB20_USBPLL_CKCTRL_OFST (26)
838 +#define RG_USB20_USBPLL_PREDIV_OFST (24)
839 +#define RG_USB20_USBPLL_FORCE_ON_OFST (23)
840 +#define RG_USB20_USBPLL_FBDIV_OFST (16)
841 +#define RG_USB20_REF_EN_OFST (15)
842 +#define RG_USB20_INTR_EN_OFST (14)
843 +#define RG_USB20_BG_TRIM_OFST (8)
844 +#define RG_USB20_BG_RBSEL_OFST (6)
845 +#define RG_USB20_BG_RASEL_OFST (4)
846 +#define RG_USB20_BGR_DIV_OFST (2)
847 +#define RG_SIFSLV_CHP_EN_OFST (1)
848 +#define RG_SIFSLV_BGR_EN_OFST (0)
849 +
850 +//U3D_U2PHYAC1
851 +#define RG_USB20_VRT_VREF_SEL_OFST (28)
852 +#define RG_USB20_TERM_VREF_SEL_OFST (24)
853 +#define RG_USB20_MPX_SEL_OFST (16)
854 +#define RG_USB20_MPX_OUT_SEL_OFST (12)
855 +#define RG_USB20_TX_PH_ROT_SEL_OFST (8)
856 +#define RG_USB20_USBPLL_ACCEN_OFST (3)
857 +#define RG_USB20_USBPLL_LF_OFST (2)
858 +#define RG_USB20_USBPLL_BR_OFST (1)
859 +#define RG_USB20_USBPLL_BP_OFST (0)
860 +
861 +//U3D_U2PHYAC2
862 +#define RG_SIFSLV_MAC_BANDGAP_EN_OFST (17)
863 +#define RG_SIFSLV_MAC_CHOPPER_EN_OFST (16)
864 +#define RG_USB20_CLKREF_REV_OFST (0)
865 +
866 +//U3D_U2PHYACR0
867 +#define RG_USB20_ICUSB_EN_OFST (24)
868 +#define RG_USB20_HSTX_SRCAL_EN_OFST (23)
869 +#define RG_USB20_HSTX_SRCTRL_OFST (16)
870 +#define RG_USB20_LS_CR_OFST (12)
871 +#define RG_USB20_FS_CR_OFST (8)
872 +#define RG_USB20_LS_SR_OFST (4)
873 +#define RG_USB20_FS_SR_OFST (0)
874 +
875 +//U3D_U2PHYACR1
876 +#define RG_USB20_INIT_SQ_EN_DG_OFST (28)
877 +#define RG_USB20_SQD_OFST (24)
878 +#define RG_USB20_HSTX_TMODE_SEL_OFST (20)
879 +#define RG_USB20_HSTX_TMODE_EN_OFST (19)
880 +#define RG_USB20_PHYD_MONEN_OFST (18)
881 +#define RG_USB20_INLPBK_EN_OFST (17)
882 +#define RG_USB20_CHIRP_EN_OFST (16)
883 +#define RG_USB20_DM_ABIST_SOURCE_EN_OFST (15)
884 +#define RG_USB20_DM_ABIST_SELE_OFST (8)
885 +#define RG_USB20_DP_ABIST_SOURCE_EN_OFST (7)
886 +#define RG_USB20_DP_ABIST_SELE_OFST (0)
887 +
888 +//U3D_U2PHYACR2
889 +#define RG_USB20_OTG_ABIST_SELE_OFST (29)
890 +#define RG_USB20_OTG_ABIST_EN_OFST (28)
891 +#define RG_USB20_OTG_VBUSCMP_EN_OFST (27)
892 +#define RG_USB20_OTG_VBUSTH_OFST (24)
893 +#define RG_USB20_DISC_FIT_EN_OFST (22)
894 +#define RG_USB20_DISCD_OFST (20)
895 +#define RG_USB20_DISCTH_OFST (16)
896 +#define RG_USB20_SQCAL_EN_OFST (15)
897 +#define RG_USB20_SQCAL_OFST (8)
898 +#define RG_USB20_SQTH_OFST (0)
899 +
900 +//U3D_U2PHYACR3
901 +#define RG_USB20_HSTX_DBIST_OFST (28)
902 +#define RG_USB20_HSTX_BIST_EN_OFST (26)
903 +#define RG_USB20_HSTX_I_EN_MODE_OFST (24)
904 +#define RG_USB20_HSRX_TMODE_EN_OFST (23)
905 +#define RG_USB20_HSRX_BIAS_EN_SEL_OFST (20)
906 +#define RG_USB20_USB11_TMODE_EN_OFST (19)
907 +#define RG_USB20_TMODE_FS_LS_TX_EN_OFST (18)
908 +#define RG_USB20_TMODE_FS_LS_RCV_EN_OFST (17)
909 +#define RG_USB20_TMODE_FS_LS_MODE_OFST (16)
910 +#define RG_USB20_HS_TERM_EN_MODE_OFST (13)
911 +#define RG_USB20_PUPD_BIST_EN_OFST (12)
912 +#define RG_USB20_EN_PU_DM_OFST (11)
913 +#define RG_USB20_EN_PD_DM_OFST (10)
914 +#define RG_USB20_EN_PU_DP_OFST (9)
915 +#define RG_USB20_EN_PD_DP_OFST (8)
916 +#define RG_USB20_PHY_REV_OFST (0)
917 +
918 +//U3D_U2PHYACR4
919 +#define RG_USB20_DP_100K_MODE_OFST (18)
920 +#define RG_USB20_DM_100K_EN_OFST (17)
921 +#define USB20_DP_100K_EN_OFST (16)
922 +#define USB20_GPIO_DM_I_OFST (15)
923 +#define USB20_GPIO_DP_I_OFST (14)
924 +#define USB20_GPIO_DM_OE_OFST (13)
925 +#define USB20_GPIO_DP_OE_OFST (12)
926 +#define RG_USB20_GPIO_CTL_OFST (9)
927 +#define USB20_GPIO_MODE_OFST (8)
928 +#define RG_USB20_TX_BIAS_EN_OFST (5)
929 +#define RG_USB20_TX_VCMPDN_EN_OFST (4)
930 +#define RG_USB20_HS_SQ_EN_MODE_OFST (2)
931 +#define RG_USB20_HS_RCV_EN_MODE_OFST (0)
932 +
933 +//U3D_U2PHYAMON0
934 +#define RGO_USB20_GPIO_DM_O_OFST (1)
935 +#define RGO_USB20_GPIO_DP_O_OFST (0)
936 +
937 +//U3D_U2PHYDCR0
938 +#define RG_USB20_CDR_TST_OFST (30)
939 +#define RG_USB20_GATED_ENB_OFST (29)
940 +#define RG_USB20_TESTMODE_OFST (26)
941 +#define RG_USB20_PLL_STABLE_OFST (25)
942 +#define RG_USB20_PLL_FORCE_ON_OFST (24)
943 +#define RG_USB20_PHYD_RESERVE_OFST (8)
944 +#define RG_USB20_EBTHRLD_OFST (7)
945 +#define RG_USB20_EARLY_HSTX_I_OFST (6)
946 +#define RG_USB20_TX_TST_OFST (5)
947 +#define RG_USB20_NEGEDGE_ENB_OFST (4)
948 +#define RG_USB20_CDR_FILT_OFST (0)
949 +
950 +//U3D_U2PHYDCR1
951 +#define RG_USB20_PROBE_SEL_OFST (24)
952 +#define RG_USB20_DRVVBUS_OFST (23)
953 +#define RG_DEBUG_EN_OFST (22)
954 +#define RG_USB20_OTG_PROBE_OFST (20)
955 +#define RG_USB20_SW_PLLMODE_OFST (18)
956 +#define RG_USB20_BERTH_OFST (16)
957 +#define RG_USB20_LBMODE_OFST (13)
958 +#define RG_USB20_FORCE_TAP_OFST (12)
959 +#define RG_USB20_TAPSEL_OFST (0)
960 +
961 +//U3D_U2PHYDTM0
962 +#define RG_UART_MODE_OFST (30)
963 +#define FORCE_UART_I_OFST (29)
964 +#define FORCE_UART_BIAS_EN_OFST (28)
965 +#define FORCE_UART_TX_OE_OFST (27)
966 +#define FORCE_UART_EN_OFST (26)
967 +#define FORCE_USB_CLKEN_OFST (25)
968 +#define FORCE_DRVVBUS_OFST (24)
969 +#define FORCE_DATAIN_OFST (23)
970 +#define FORCE_TXVALID_OFST (22)
971 +#define FORCE_DM_PULLDOWN_OFST (21)
972 +#define FORCE_DP_PULLDOWN_OFST (20)
973 +#define FORCE_XCVRSEL_OFST (19)
974 +#define FORCE_SUSPENDM_OFST (18)
975 +#define FORCE_TERMSEL_OFST (17)
976 +#define FORCE_OPMODE_OFST (16)
977 +#define UTMI_MUXSEL_OFST (15)
978 +#define RG_RESET_OFST (14)
979 +#define RG_DATAIN_OFST (10)
980 +#define RG_TXVALIDH_OFST (9)
981 +#define RG_TXVALID_OFST (8)
982 +#define RG_DMPULLDOWN_OFST (7)
983 +#define RG_DPPULLDOWN_OFST (6)
984 +#define RG_XCVRSEL_OFST (4)
985 +#define RG_SUSPENDM_OFST (3)
986 +#define RG_TERMSEL_OFST (2)
987 +#define RG_OPMODE_OFST (0)
988 +
989 +//U3D_U2PHYDTM1
990 +#define RG_USB20_PRBS7_EN_OFST (31)
991 +#define RG_USB20_PRBS7_BITCNT_OFST (24)
992 +#define RG_USB20_CLK48M_EN_OFST (23)
993 +#define RG_USB20_CLK60M_EN_OFST (22)
994 +#define RG_UART_I_OFST (19)
995 +#define RG_UART_BIAS_EN_OFST (18)
996 +#define RG_UART_TX_OE_OFST (17)
997 +#define RG_UART_EN_OFST (16)
998 +#define FORCE_VBUSVALID_OFST (13)
999 +#define FORCE_SESSEND_OFST (12)
1000 +#define FORCE_BVALID_OFST (11)
1001 +#define FORCE_AVALID_OFST (10)
1002 +#define FORCE_IDDIG_OFST (9)
1003 +#define FORCE_IDPULLUP_OFST (8)
1004 +#define RG_VBUSVALID_OFST (5)
1005 +#define RG_SESSEND_OFST (4)
1006 +#define RG_BVALID_OFST (3)
1007 +#define RG_AVALID_OFST (2)
1008 +#define RG_IDDIG_OFST (1)
1009 +#define RG_IDPULLUP_OFST (0)
1010 +
1011 +//U3D_U2PHYDMON0
1012 +#define RG_USB20_PRBS7_BERTH_OFST (0)
1013 +
1014 +//U3D_U2PHYDMON1
1015 +#define USB20_UART_O_OFST (31)
1016 +#define RGO_USB20_LB_PASS_OFST (30)
1017 +#define RGO_USB20_LB_DONE_OFST (29)
1018 +#define AD_USB20_BVALID_OFST (28)
1019 +#define USB20_IDDIG_OFST (27)
1020 +#define AD_USB20_VBUSVALID_OFST (26)
1021 +#define AD_USB20_SESSEND_OFST (25)
1022 +#define AD_USB20_AVALID_OFST (24)
1023 +#define USB20_LINE_STATE_OFST (22)
1024 +#define USB20_HST_DISCON_OFST (21)
1025 +#define USB20_TX_READY_OFST (20)
1026 +#define USB20_RX_ERROR_OFST (19)
1027 +#define USB20_RX_ACTIVE_OFST (18)
1028 +#define USB20_RX_VALIDH_OFST (17)
1029 +#define USB20_RX_VALID_OFST (16)
1030 +#define USB20_DATA_OUT_OFST (0)
1031 +
1032 +//U3D_U2PHYDMON2
1033 +#define RGO_TXVALID_CNT_OFST (24)
1034 +#define RGO_RXACTIVE_CNT_OFST (16)
1035 +#define RGO_USB20_LB_BERCNT_OFST (8)
1036 +#define USB20_PROBE_OUT_OFST (0)
1037 +
1038 +//U3D_U2PHYDMON3
1039 +#define RGO_USB20_PRBS7_ERRCNT_OFST (16)
1040 +#define RGO_USB20_PRBS7_DONE_OFST (3)
1041 +#define RGO_USB20_PRBS7_LOCK_OFST (2)
1042 +#define RGO_USB20_PRBS7_PASS_OFST (1)
1043 +#define RGO_USB20_PRBS7_PASSTH_OFST (0)
1044 +
1045 +//U3D_U2PHYBC12C
1046 +#define RG_SIFSLV_CHGDT_DEGLCH_CNT_OFST (28)
1047 +#define RG_SIFSLV_CHGDT_CTRL_CNT_OFST (24)
1048 +#define RG_SIFSLV_CHGDT_FORCE_MODE_OFST (16)
1049 +#define RG_CHGDT_ISRC_LEV_OFST (14)
1050 +#define RG_CHGDT_VDATSRC_OFST (13)
1051 +#define RG_CHGDT_BGVREF_SEL_OFST (10)
1052 +#define RG_CHGDT_RDVREF_SEL_OFST (8)
1053 +#define RG_CHGDT_ISRC_DP_OFST (7)
1054 +#define RG_SIFSLV_CHGDT_OPOUT_DM_OFST (6)
1055 +#define RG_CHGDT_VDAT_DM_OFST (5)
1056 +#define RG_CHGDT_OPOUT_DP_OFST (4)
1057 +#define RG_SIFSLV_CHGDT_VDAT_DP_OFST (3)
1058 +#define RG_SIFSLV_CHGDT_COMP_EN_OFST (2)
1059 +#define RG_SIFSLV_CHGDT_OPDRV_EN_OFST (1)
1060 +#define RG_CHGDT_EN_OFST (0)
1061 +
1062 +//U3D_U2PHYBC12C1
1063 +#define RG_CHGDT_REV_OFST (0)
1064 +
1065 +//U3D_REGFCOM
1066 +#define RG_PAGE_OFST (24)
1067 +#define I2C_MODE_OFST (16)
1068 +
1069 +
1070 +///////////////////////////////////////////////////////////////////////////////
1071 +
1072 +struct u3phya_reg {
1073 + //0x0
1074 + PHY_LE32 reg0;
1075 + PHY_LE32 reg1;
1076 + PHY_LE32 reg2;
1077 + PHY_LE32 reg3;
1078 + //0x10
1079 + PHY_LE32 reg4;
1080 + PHY_LE32 reg5;
1081 + PHY_LE32 reg6;
1082 + PHY_LE32 reg7;
1083 + //0x20
1084 + PHY_LE32 reg8;
1085 + PHY_LE32 reg9;
1086 + PHY_LE32 rega;
1087 + PHY_LE32 regb;
1088 + //0x30
1089 + PHY_LE32 regc;
1090 + PHY_LE32 regd;
1091 + PHY_LE32 rege;
1092 +};
1093 +
1094 +//U3D_reg0
1095 +#define RG_SSUSB_BGR_EN (0x1<<31) //31:31
1096 +#define RG_SSUSB_CHPEN (0x1<<30) //30:30
1097 +#define RG_SSUSB_BG_DIV (0x3<<28) //29:28
1098 +#define RG_SSUSB_INTR_EN (0x1<<26) //26:26
1099 +#define RG_SSUSB_MPX_OUT_SEL (0x3<<24) //25:24
1100 +#define RG_SSUSB_MPX_SEL (0xff<<16) //23:16
1101 +#define RG_SSUSB_REF_EN (0x1<<15) //15:15
1102 +#define RG_SSUSB_VRT_VREF_SEL (0xf<<11) //14:11
1103 +#define RG_SSUSB_BG_RASEL (0x3<<9) //10:9
1104 +#define RG_SSUSB_BG_RBSEL (0x3<<7) //8:7
1105 +#define RG_SSUSB_BG_MONEN (0x1<<6) //6:6
1106 +#define RG_PCIE_CLKDRV_OFFSET (0x3<<0) //1:0
1107 +
1108 +//U3D_reg1
1109 +#define RG_PCIE_CLKDRV_SLEW (0x3<<30) //31:30
1110 +#define RG_PCIE_CLKDRV_AMP (0x7<<27) //29:27
1111 +#define RG_SSUSB_XTAL_TST_A2DCK_EN (0x1<<26) //26:26
1112 +#define RG_SSUSB_XTAL_MON_EN (0x1<<25) //25:25
1113 +#define RG_SSUSB_XTAL_HYS (0x1<<24) //24:24
1114 +#define RG_SSUSB_XTAL_TOP_RESERVE (0xffff<<8) //23:8
1115 +#define RG_SSUSB_SYSPLL_RESERVE (0xf<<4) //7:4
1116 +#define RG_SSUSB_SYSPLL_FBSEL (0x3<<2) //3:2
1117 +#define RG_SSUSB_SYSPLL_PREDIV (0x3<<0) //1:0
1118 +
1119 +//U3D_reg2
1120 +#define RG_SSUSB_SYSPLL_LF (0x1<<31) //31:31
1121 +#define RG_SSUSB_SYSPLL_FBDIV (0x7f<<24) //30:24
1122 +#define RG_SSUSB_SYSPLL_POSDIV (0x3<<22) //23:22
1123 +#define RG_SSUSB_SYSPLL_VCO_DIV_SEL (0x1<<21) //21:21
1124 +#define RG_SSUSB_SYSPLL_BLP (0x1<<20) //20:20
1125 +#define RG_SSUSB_SYSPLL_BP (0x1<<19) //19:19
1126 +#define RG_SSUSB_SYSPLL_BR (0x1<<18) //18:18
1127 +#define RG_SSUSB_SYSPLL_BC (0x1<<17) //17:17
1128 +#define RG_SSUSB_SYSPLL_DIVEN (0x7<<14) //16:14
1129 +#define RG_SSUSB_SYSPLL_FPEN (0x1<<13) //13:13
1130 +#define RG_SSUSB_SYSPLL_MONCK_EN (0x1<<12) //12:12
1131 +#define RG_SSUSB_SYSPLL_MONVC_EN (0x1<<11) //11:11
1132 +#define RG_SSUSB_SYSPLL_MONREF_EN (0x1<<10) //10:10
1133 +#define RG_SSUSB_SYSPLL_VOD_EN (0x1<<9) //9:9
1134 +#define RG_SSUSB_SYSPLL_CK_SEL (0x1<<8) //8:8
1135 +
1136 +//U3D_reg3
1137 +#define RG_SSUSB_SYSPLL_TOP_RESERVE (0xffff<<16) //31:16
1138 +
1139 +//U3D_reg4
1140 +#define RG_SSUSB_SYSPLL_PCW_NCPO (0x7fffffff<<1) //31:1
1141 +
1142 +//U3D_reg5
1143 +#define RG_SSUSB_SYSPLL_DDS_PI_C (0x7<<29) //31:29
1144 +#define RG_SSUSB_SYSPLL_DDS_HF_EN (0x1<<28) //28:28
1145 +#define RG_SSUSB_SYSPLL_DDS_PREDIV2 (0x1<<27) //27:27
1146 +#define RG_SSUSB_SYSPLL_DDS_POSTDIV2 (0x1<<26) //26:26
1147 +#define RG_SSUSB_SYSPLL_DDS_PI_PL_EN (0x1<<25) //25:25
1148 +#define RG_SSUSB_SYSPLL_DDS_PI_RST_SEL (0x1<<24) //24:24
1149 +#define RG_SSUSB_SYSPLL_DDS_MONEN (0x1<<23) //23:23
1150 +#define RG_SSUSB_SYSPLL_DDS_LPF_EN (0x1<<22) //22:22
1151 +#define RG_SSUSB_SYSPLL_CLK_PH_INV (0x1<<21) //21:21
1152 +#define RG_SSUSB_SYSPLL_DDS_SEL_EXT (0x1<<20) //20:20
1153 +#define RG_SSUSB_SYSPLL_DDS_DMY (0xffff<<0) //15:0
1154 +
1155 +//U3D_reg6
1156 +#define RG_SSUSB_TX250MCK_INVB (0x1<<31) //31:31
1157 +#define RG_SSUSB_IDRV_ITAILOP_EN (0x1<<30) //30:30
1158 +#define RG_SSUSB_IDRV_CALIB (0x3f<<24) //29:24
1159 +#define RG_SSUSB_TX_R50_FON (0x1<<23) //23:23
1160 +#define RG_SSUSB_TX_SR (0x7<<20) //22:20
1161 +#define RG_SSUSB_TX_EIDLE_CM (0xf<<16) //19:16
1162 +#define RG_SSUSB_RXDET_RSEL (0x3<<14) //15:14
1163 +#define RG_SSUSB_RXDET_VTHSEL (0x3<<12) //13:12
1164 +#define RG_SSUSB_CKMON_EN (0x1<<11) //11:11
1165 +#define RG_SSUSB_CKMON_SEL (0x7<<8) //10:8
1166 +#define RG_SSUSB_TX_VLMON_EN (0x1<<7) //7:7
1167 +#define RG_SSUSB_TX_VLMON_SEL (0x1<<6) //6:6
1168 +#define RG_SSUSB_RXLBTX_EN (0x1<<5) //5:5
1169 +#define RG_SSUSB_TXLBRX_EN (0x1<<4) //4:4
1170 +
1171 +//U3D_reg7
1172 +#define RG_SSUSB_RESERVE (0xfffff<<12) //31:12
1173 +#define RG_SSUSB_PLL_CKCTRL (0x3<<10) //11:10
1174 +#define RG_SSUSB_PLL_POSDIV (0x3<<8) //9:8
1175 +#define RG_SSUSB_PLL_AUTOK_LOAD (0x1<<7) //7:7
1176 +#define RG_SSUSB_PLL_LOAD_RSTB (0x1<<6) //6:6
1177 +#define RG_SSUSB_PLL_EP_EN (0x1<<5) //5:5
1178 +#define RG_SSUSB_PLL_VOD_EN (0x1<<4) //4:4
1179 +#define RG_SSUSB_PLL_V11_EN (0x1<<3) //3:3
1180 +#define RG_SSUSB_PLL_MONREF_EN (0x1<<2) //2:2
1181 +#define RG_SSUSB_PLL_MONCK_EN (0x1<<1) //1:1
1182 +#define RG_SSUSB_PLL_MONVC_EN (0x1<<0) //0:0
1183 +
1184 +//U3D_reg8
1185 +#define RG_SSUSB_PLL_RESERVE (0xffff<<0) //15:0
1186 +
1187 +//U3D_reg9
1188 +#define RG_SSUSB_PLL_DDS_DMY (0xffff<<16) //31:16
1189 +#define RG_SSUSB_PLL_SSC_PRD (0xffff<<0) //15:0
1190 +
1191 +//U3D_regA
1192 +#define RG_SSUSB_PLL_SSC_PHASE_INI (0x1<<31) //31:31
1193 +#define RG_SSUSB_PLL_SSC_TRI_EN (0x1<<30) //30:30
1194 +#define RG_SSUSB_PLL_CLK_PH_INV (0x1<<29) //29:29
1195 +#define RG_SSUSB_PLL_DDS_LPF_EN (0x1<<28) //28:28
1196 +#define RG_SSUSB_PLL_DDS_VADJ (0x7<<21) //23:21
1197 +#define RG_SSUSB_PLL_DDS_MONEN (0x1<<20) //20:20
1198 +#define RG_SSUSB_PLL_DDS_PS_VADJ (0x7<<17) //19:17
1199 +#define RG_SSUSB_PLL_DDS_SEL_EXT (0x1<<16) //16:16
1200 +#define RG_SSUSB_CDR_PD_DIV_BYPASS (0x1<<15) //15:15
1201 +#define RG_SSUSB_CDR_PD_DIV_SEL (0x1<<14) //14:14
1202 +#define RG_SSUSB_CDR_CPBIAS_SEL (0x1<<13) //13:13
1203 +#define RG_SSUSB_CDR_OSCDET_EN (0x1<<12) //12:12
1204 +#define RG_SSUSB_CDR_MONMUX (0x1<<11) //11:11
1205 +#define RG_SSUSB_CDR_CKCTRL (0x3<<9) //10:9
1206 +#define RG_SSUSB_CDR_ACCEN (0x1<<8) //8:8
1207 +#define RG_SSUSB_CDR_BYPASS (0x3<<6) //7:6
1208 +#define RG_SSUSB_CDR_PI_SLEW (0x3<<4) //5:4
1209 +#define RG_SSUSB_CDR_EPEN (0x1<<3) //3:3
1210 +#define RG_SSUSB_CDR_AUTOK_LOAD (0x1<<2) //2:2
1211 +#define RG_SSUSB_CDR_LOAD_RSTB (0x1<<1) //1:1
1212 +#define RG_SSUSB_CDR_MONEN (0x1<<0) //0:0
1213 +
1214 +//U3D_regB
1215 +#define RG_SSUSB_CDR_MONEN_DIG (0x1<<31) //31:31
1216 +#define RG_SSUSB_CDR_REGOD (0x3<<29) //30:29
1217 +#define RG_SSUSB_RX_DAC_EN (0x1<<26) //26:26
1218 +#define RG_SSUSB_RX_DAC_PWD (0x1<<25) //25:25
1219 +#define RG_SSUSB_EQ_CURSEL (0x1<<24) //24:24
1220 +#define RG_SSUSB_RX_DAC_MUX (0x1f<<19) //23:19
1221 +#define RG_SSUSB_RX_R2T_EN (0x1<<18) //18:18
1222 +#define RG_SSUSB_RX_T2R_EN (0x1<<17) //17:17
1223 +#define RG_SSUSB_RX_50_LOWER (0x7<<14) //16:14
1224 +#define RG_SSUSB_RX_50_TAR (0x3<<12) //13:12
1225 +#define RG_SSUSB_RX_SW_CTRL (0xf<<7) //10:7
1226 +#define RG_PCIE_SIGDET_VTH (0x3<<5) //6:5
1227 +#define RG_PCIE_SIGDET_LPF (0x3<<3) //4:3
1228 +#define RG_SSUSB_LFPS_MON_EN (0x1<<2) //2:2
1229 +
1230 +//U3D_regC
1231 +#define RG_SSUSB_RXAFE_DCMON_SEL (0xf<<28) //31:28
1232 +#define RG_SSUSB_CDR_RESERVE (0xff<<16) //23:16
1233 +#define RG_SSUSB_RXAFE_RESERVE (0xff<<8) //15:8
1234 +#define RG_PCIE_RX_RESERVE (0xff<<0) //7:0
1235 +
1236 +//U3D_redD
1237 +#define RGS_SSUSB_CDR_NO_OSC (0x1<<8) //8:8
1238 +#define RGS_SSUSB_RX_DEBUG_RESERVE (0xff<<0) //7:0
1239 +
1240 +//U3D_regE
1241 +#define RG_SSUSB_INT_BIAS_SEL (0x1<<4) //4:4
1242 +#define RG_SSUSB_EXT_BIAS_SEL (0x1<<3) //3:3
1243 +#define RG_SSUSB_RX_P1_ENTRY_PASS (0x1<<2) //2:2
1244 +#define RG_SSUSB_RX_PD_RST (0x1<<1) //1:1
1245 +#define RG_SSUSB_RX_PD_RST_PASS (0x1<<0) //0:0
1246 +
1247 +
1248 +/* OFFSET */
1249 +
1250 +//U3D_reg0
1251 +#define RG_SSUSB_BGR_EN_OFST (31)
1252 +#define RG_SSUSB_CHPEN_OFST (30)
1253 +#define RG_SSUSB_BG_DIV_OFST (28)
1254 +#define RG_SSUSB_INTR_EN_OFST (26)
1255 +#define RG_SSUSB_MPX_OUT_SEL_OFST (24)
1256 +#define RG_SSUSB_MPX_SEL_OFST (16)
1257 +#define RG_SSUSB_REF_EN_OFST (15)
1258 +#define RG_SSUSB_VRT_VREF_SEL_OFST (11)
1259 +#define RG_SSUSB_BG_RASEL_OFST (9)
1260 +#define RG_SSUSB_BG_RBSEL_OFST (7)
1261 +#define RG_SSUSB_BG_MONEN_OFST (6)
1262 +#define RG_PCIE_CLKDRV_OFFSET_OFST (0)
1263 +
1264 +//U3D_reg1
1265 +#define RG_PCIE_CLKDRV_SLEW_OFST (30)
1266 +#define RG_PCIE_CLKDRV_AMP_OFST (27)
1267 +#define RG_SSUSB_XTAL_TST_A2DCK_EN_OFST (26)
1268 +#define RG_SSUSB_XTAL_MON_EN_OFST (25)
1269 +#define RG_SSUSB_XTAL_HYS_OFST (24)
1270 +#define RG_SSUSB_XTAL_TOP_RESERVE_OFST (8)
1271 +#define RG_SSUSB_SYSPLL_RESERVE_OFST (4)
1272 +#define RG_SSUSB_SYSPLL_FBSEL_OFST (2)
1273 +#define RG_SSUSB_SYSPLL_PREDIV_OFST (0)
1274 +
1275 +//U3D_reg2
1276 +#define RG_SSUSB_SYSPLL_LF_OFST (31)
1277 +#define RG_SSUSB_SYSPLL_FBDIV_OFST (24)
1278 +#define RG_SSUSB_SYSPLL_POSDIV_OFST (22)
1279 +#define RG_SSUSB_SYSPLL_VCO_DIV_SEL_OFST (21)
1280 +#define RG_SSUSB_SYSPLL_BLP_OFST (20)
1281 +#define RG_SSUSB_SYSPLL_BP_OFST (19)
1282 +#define RG_SSUSB_SYSPLL_BR_OFST (18)
1283 +#define RG_SSUSB_SYSPLL_BC_OFST (17)
1284 +#define RG_SSUSB_SYSPLL_DIVEN_OFST (14)
1285 +#define RG_SSUSB_SYSPLL_FPEN_OFST (13)
1286 +#define RG_SSUSB_SYSPLL_MONCK_EN_OFST (12)
1287 +#define RG_SSUSB_SYSPLL_MONVC_EN_OFST (11)
1288 +#define RG_SSUSB_SYSPLL_MONREF_EN_OFST (10)
1289 +#define RG_SSUSB_SYSPLL_VOD_EN_OFST (9)
1290 +#define RG_SSUSB_SYSPLL_CK_SEL_OFST (8)
1291 +
1292 +//U3D_reg3
1293 +#define RG_SSUSB_SYSPLL_TOP_RESERVE_OFST (16)
1294 +
1295 +//U3D_reg4
1296 +#define RG_SSUSB_SYSPLL_PCW_NCPO_OFST (1)
1297 +
1298 +//U3D_reg5
1299 +#define RG_SSUSB_SYSPLL_DDS_PI_C_OFST (29)
1300 +#define RG_SSUSB_SYSPLL_DDS_HF_EN_OFST (28)
1301 +#define RG_SSUSB_SYSPLL_DDS_PREDIV2_OFST (27)
1302 +#define RG_SSUSB_SYSPLL_DDS_POSTDIV2_OFST (26)
1303 +#define RG_SSUSB_SYSPLL_DDS_PI_PL_EN_OFST (25)
1304 +#define RG_SSUSB_SYSPLL_DDS_PI_RST_SEL_OFST (24)
1305 +#define RG_SSUSB_SYSPLL_DDS_MONEN_OFST (23)
1306 +#define RG_SSUSB_SYSPLL_DDS_LPF_EN_OFST (22)
1307 +#define RG_SSUSB_SYSPLL_CLK_PH_INV_OFST (21)
1308 +#define RG_SSUSB_SYSPLL_DDS_SEL_EXT_OFST (20)
1309 +#define RG_SSUSB_SYSPLL_DDS_DMY_OFST (0)
1310 +
1311 +//U3D_reg6
1312 +#define RG_SSUSB_TX250MCK_INVB_OFST (31)
1313 +#define RG_SSUSB_IDRV_ITAILOP_EN_OFST (30)
1314 +#define RG_SSUSB_IDRV_CALIB_OFST (24)
1315 +#define RG_SSUSB_TX_R50_FON_OFST (23)
1316 +#define RG_SSUSB_TX_SR_OFST (20)
1317 +#define RG_SSUSB_TX_EIDLE_CM_OFST (16)
1318 +#define RG_SSUSB_RXDET_RSEL_OFST (14)
1319 +#define RG_SSUSB_RXDET_VTHSEL_OFST (12)
1320 +#define RG_SSUSB_CKMON_EN_OFST (11)
1321 +#define RG_SSUSB_CKMON_SEL_OFST (8)
1322 +#define RG_SSUSB_TX_VLMON_EN_OFST (7)
1323 +#define RG_SSUSB_TX_VLMON_SEL_OFST (6)
1324 +#define RG_SSUSB_RXLBTX_EN_OFST (5)
1325 +#define RG_SSUSB_TXLBRX_EN_OFST (4)
1326 +
1327 +//U3D_reg7
1328 +#define RG_SSUSB_RESERVE_OFST (12)
1329 +#define RG_SSUSB_PLL_CKCTRL_OFST (10)
1330 +#define RG_SSUSB_PLL_POSDIV_OFST (8)
1331 +#define RG_SSUSB_PLL_AUTOK_LOAD_OFST (7)
1332 +#define RG_SSUSB_PLL_LOAD_RSTB_OFST (6)
1333 +#define RG_SSUSB_PLL_EP_EN_OFST (5)
1334 +#define RG_SSUSB_PLL_VOD_EN_OFST (4)
1335 +#define RG_SSUSB_PLL_V11_EN_OFST (3)
1336 +#define RG_SSUSB_PLL_MONREF_EN_OFST (2)
1337 +#define RG_SSUSB_PLL_MONCK_EN_OFST (1)
1338 +#define RG_SSUSB_PLL_MONVC_EN_OFST (0)
1339 +
1340 +//U3D_reg8
1341 +#define RG_SSUSB_PLL_RESERVE_OFST (0)
1342 +
1343 +//U3D_reg9
1344 +#define RG_SSUSB_PLL_DDS_DMY_OFST (16)
1345 +#define RG_SSUSB_PLL_SSC_PRD_OFST (0)
1346 +
1347 +//U3D_regA
1348 +#define RG_SSUSB_PLL_SSC_PHASE_INI_OFST (31)
1349 +#define RG_SSUSB_PLL_SSC_TRI_EN_OFST (30)
1350 +#define RG_SSUSB_PLL_CLK_PH_INV_OFST (29)
1351 +#define RG_SSUSB_PLL_DDS_LPF_EN_OFST (28)
1352 +#define RG_SSUSB_PLL_DDS_VADJ_OFST (21)
1353 +#define RG_SSUSB_PLL_DDS_MONEN_OFST (20)
1354 +#define RG_SSUSB_PLL_DDS_PS_VADJ_OFST (17)
1355 +#define RG_SSUSB_PLL_DDS_SEL_EXT_OFST (16)
1356 +#define RG_SSUSB_CDR_PD_DIV_BYPASS_OFST (15)
1357 +#define RG_SSUSB_CDR_PD_DIV_SEL_OFST (14)
1358 +#define RG_SSUSB_CDR_CPBIAS_SEL_OFST (13)
1359 +#define RG_SSUSB_CDR_OSCDET_EN_OFST (12)
1360 +#define RG_SSUSB_CDR_MONMUX_OFST (11)
1361 +#define RG_SSUSB_CDR_CKCTRL_OFST (9)
1362 +#define RG_SSUSB_CDR_ACCEN_OFST (8)
1363 +#define RG_SSUSB_CDR_BYPASS_OFST (6)
1364 +#define RG_SSUSB_CDR_PI_SLEW_OFST (4)
1365 +#define RG_SSUSB_CDR_EPEN_OFST (3)
1366 +#define RG_SSUSB_CDR_AUTOK_LOAD_OFST (2)
1367 +#define RG_SSUSB_CDR_LOAD_RSTB_OFST (1)
1368 +#define RG_SSUSB_CDR_MONEN_OFST (0)
1369 +
1370 +//U3D_regB
1371 +#define RG_SSUSB_CDR_MONEN_DIG_OFST (31)
1372 +#define RG_SSUSB_CDR_REGOD_OFST (29)
1373 +#define RG_SSUSB_RX_DAC_EN_OFST (26)
1374 +#define RG_SSUSB_RX_DAC_PWD_OFST (25)
1375 +#define RG_SSUSB_EQ_CURSEL_OFST (24)
1376 +#define RG_SSUSB_RX_DAC_MUX_OFST (19)
1377 +#define RG_SSUSB_RX_R2T_EN_OFST (18)
1378 +#define RG_SSUSB_RX_T2R_EN_OFST (17)
1379 +#define RG_SSUSB_RX_50_LOWER_OFST (14)
1380 +#define RG_SSUSB_RX_50_TAR_OFST (12)
1381 +#define RG_SSUSB_RX_SW_CTRL_OFST (7)
1382 +#define RG_PCIE_SIGDET_VTH_OFST (5)
1383 +#define RG_PCIE_SIGDET_LPF_OFST (3)
1384 +#define RG_SSUSB_LFPS_MON_EN_OFST (2)
1385 +
1386 +//U3D_regC
1387 +#define RG_SSUSB_RXAFE_DCMON_SEL_OFST (28)
1388 +#define RG_SSUSB_CDR_RESERVE_OFST (16)
1389 +#define RG_SSUSB_RXAFE_RESERVE_OFST (8)
1390 +#define RG_PCIE_RX_RESERVE_OFST (0)
1391 +
1392 +//U3D_redD
1393 +#define RGS_SSUSB_CDR_NO_OSC_OFST (8)
1394 +#define RGS_SSUSB_RX_DEBUG_RESERVE_OFST (0)
1395 +
1396 +//U3D_regE
1397 +#define RG_SSUSB_INT_BIAS_SEL_OFST (4)
1398 +#define RG_SSUSB_EXT_BIAS_SEL_OFST (3)
1399 +#define RG_SSUSB_RX_P1_ENTRY_PASS_OFST (2)
1400 +#define RG_SSUSB_RX_PD_RST_OFST (1)
1401 +#define RG_SSUSB_RX_PD_RST_PASS_OFST (0)
1402 +
1403 +///////////////////////////////////////////////////////////////////////////////
1404 +
1405 +struct u3phya_da_reg {
1406 + //0x0
1407 + PHY_LE32 reg0;
1408 + PHY_LE32 reg1;
1409 + PHY_LE32 reg4;
1410 + PHY_LE32 reg5;
1411 + //0x10
1412 + PHY_LE32 reg6;
1413 + PHY_LE32 reg7;
1414 + PHY_LE32 reg8;
1415 + PHY_LE32 reg9;
1416 + //0x20
1417 + PHY_LE32 reg10;
1418 + PHY_LE32 reg12;
1419 + PHY_LE32 reg13;
1420 + PHY_LE32 reg14;
1421 + //0x30
1422 + PHY_LE32 reg15;
1423 + PHY_LE32 reg16;
1424 + PHY_LE32 reg19;
1425 + PHY_LE32 reg20;
1426 + //0x40
1427 + PHY_LE32 reg21;
1428 + PHY_LE32 reg23;
1429 + PHY_LE32 reg25;
1430 + PHY_LE32 reg26;
1431 + //0x50
1432 + PHY_LE32 reg28;
1433 + PHY_LE32 reg29;
1434 + PHY_LE32 reg30;
1435 + PHY_LE32 reg31;
1436 + //0x60
1437 + PHY_LE32 reg32;
1438 + PHY_LE32 reg33;
1439 +};
1440 +
1441 +//U3D_reg0
1442 +#define RG_PCIE_SPEED_PE2D (0x1<<24) //24:24
1443 +#define RG_PCIE_SPEED_PE2H (0x1<<23) //23:23
1444 +#define RG_PCIE_SPEED_PE1D (0x1<<22) //22:22
1445 +#define RG_PCIE_SPEED_PE1H (0x1<<21) //21:21
1446 +#define RG_PCIE_SPEED_U3 (0x1<<20) //20:20
1447 +#define RG_SSUSB_XTAL_EXT_EN_PE2D (0x3<<18) //19:18
1448 +#define RG_SSUSB_XTAL_EXT_EN_PE2H (0x3<<16) //17:16
1449 +#define RG_SSUSB_XTAL_EXT_EN_PE1D (0x3<<14) //15:14
1450 +#define RG_SSUSB_XTAL_EXT_EN_PE1H (0x3<<12) //13:12
1451 +#define RG_SSUSB_XTAL_EXT_EN_U3 (0x3<<10) //11:10
1452 +#define RG_SSUSB_CDR_REFCK_SEL_PE2D (0x3<<8) //9:8
1453 +#define RG_SSUSB_CDR_REFCK_SEL_PE2H (0x3<<6) //7:6
1454 +#define RG_SSUSB_CDR_REFCK_SEL_PE1D (0x3<<4) //5:4
1455 +#define RG_SSUSB_CDR_REFCK_SEL_PE1H (0x3<<2) //3:2
1456 +#define RG_SSUSB_CDR_REFCK_SEL_U3 (0x3<<0) //1:0
1457 +
1458 +//U3D_reg1
1459 +#define RG_USB20_REFCK_SEL_PE2D (0x1<<30) //30:30
1460 +#define RG_USB20_REFCK_SEL_PE2H (0x1<<29) //29:29
1461 +#define RG_USB20_REFCK_SEL_PE1D (0x1<<28) //28:28
1462 +#define RG_USB20_REFCK_SEL_PE1H (0x1<<27) //27:27
1463 +#define RG_USB20_REFCK_SEL_U3 (0x1<<26) //26:26
1464 +#define RG_PCIE_REFCK_DIV4_PE2D (0x1<<25) //25:25
1465 +#define RG_PCIE_REFCK_DIV4_PE2H (0x1<<24) //24:24
1466 +#define RG_PCIE_REFCK_DIV4_PE1D (0x1<<18) //18:18
1467 +#define RG_PCIE_REFCK_DIV4_PE1H (0x1<<17) //17:17
1468 +#define RG_PCIE_REFCK_DIV4_U3 (0x1<<16) //16:16
1469 +#define RG_PCIE_MODE_PE2D (0x1<<8) //8:8
1470 +#define RG_PCIE_MODE_PE2H (0x1<<3) //3:3
1471 +#define RG_PCIE_MODE_PE1D (0x1<<2) //2:2
1472 +#define RG_PCIE_MODE_PE1H (0x1<<1) //1:1
1473 +#define RG_PCIE_MODE_U3 (0x1<<0) //0:0
1474 +
1475 +//U3D_reg4
1476 +#define RG_SSUSB_PLL_DIVEN_PE2D (0x7<<22) //24:22
1477 +#define RG_SSUSB_PLL_DIVEN_PE2H (0x7<<19) //21:19
1478 +#define RG_SSUSB_PLL_DIVEN_PE1D (0x7<<16) //18:16
1479 +#define RG_SSUSB_PLL_DIVEN_PE1H (0x7<<13) //15:13
1480 +#define RG_SSUSB_PLL_DIVEN_U3 (0x7<<10) //12:10
1481 +#define RG_SSUSB_PLL_BC_PE2D (0x3<<8) //9:8
1482 +#define RG_SSUSB_PLL_BC_PE2H (0x3<<6) //7:6
1483 +#define RG_SSUSB_PLL_BC_PE1D (0x3<<4) //5:4
1484 +#define RG_SSUSB_PLL_BC_PE1H (0x3<<2) //3:2
1485 +#define RG_SSUSB_PLL_BC_U3 (0x3<<0) //1:0
1486 +
1487 +//U3D_reg5
1488 +#define RG_SSUSB_PLL_BR_PE2D (0x7<<27) //29:27
1489 +#define RG_SSUSB_PLL_BR_PE2H (0x7<<24) //26:24
1490 +#define RG_SSUSB_PLL_BR_PE1D (0x7<<21) //23:21
1491 +#define RG_SSUSB_PLL_BR_PE1H (0x7<<18) //20:18
1492 +#define RG_SSUSB_PLL_BR_U3 (0x7<<15) //17:15
1493 +#define RG_SSUSB_PLL_IC_PE2D (0x7<<12) //14:12
1494 +#define RG_SSUSB_PLL_IC_PE2H (0x7<<9) //11:9
1495 +#define RG_SSUSB_PLL_IC_PE1D (0x7<<6) //8:6
1496 +#define RG_SSUSB_PLL_IC_PE1H (0x7<<3) //5:3
1497 +#define RG_SSUSB_PLL_IC_U3 (0x7<<0) //2:0
1498 +
1499 +//U3D_reg6
1500 +#define RG_SSUSB_PLL_IR_PE2D (0xf<<24) //27:24
1501 +#define RG_SSUSB_PLL_IR_PE2H (0xf<<16) //19:16
1502 +#define RG_SSUSB_PLL_IR_PE1D (0xf<<8) //11:8
1503 +#define RG_SSUSB_PLL_IR_PE1H (0xf<<4) //7:4
1504 +#define RG_SSUSB_PLL_IR_U3 (0xf<<0) //3:0
1505 +
1506 +//U3D_reg7
1507 +#define RG_SSUSB_PLL_BP_PE2D (0xf<<24) //27:24
1508 +#define RG_SSUSB_PLL_BP_PE2H (0xf<<16) //19:16
1509 +#define RG_SSUSB_PLL_BP_PE1D (0xf<<8) //11:8
1510 +#define RG_SSUSB_PLL_BP_PE1H (0xf<<4) //7:4
1511 +#define RG_SSUSB_PLL_BP_U3 (0xf<<0) //3:0
1512 +
1513 +//U3D_reg8
1514 +#define RG_SSUSB_PLL_FBKSEL_PE2D (0x3<<24) //25:24
1515 +#define RG_SSUSB_PLL_FBKSEL_PE2H (0x3<<16) //17:16
1516 +#define RG_SSUSB_PLL_FBKSEL_PE1D (0x3<<8) //9:8
1517 +#define RG_SSUSB_PLL_FBKSEL_PE1H (0x3<<2) //3:2
1518 +#define RG_SSUSB_PLL_FBKSEL_U3 (0x3<<0) //1:0
1519 +
1520 +//U3D_reg9
1521 +#define RG_SSUSB_PLL_FBKDIV_PE2H (0x7f<<24) //30:24
1522 +#define RG_SSUSB_PLL_FBKDIV_PE1D (0x7f<<16) //22:16
1523 +#define RG_SSUSB_PLL_FBKDIV_PE1H (0x7f<<8) //14:8
1524 +#define RG_SSUSB_PLL_FBKDIV_U3 (0x7f<<0) //6:0
1525 +
1526 +//U3D_reg10
1527 +#define RG_SSUSB_PLL_PREDIV_PE2D (0x3<<26) //27:26
1528 +#define RG_SSUSB_PLL_PREDIV_PE2H (0x3<<24) //25:24
1529 +#define RG_SSUSB_PLL_PREDIV_PE1D (0x3<<18) //19:18
1530 +#define RG_SSUSB_PLL_PREDIV_PE1H (0x3<<16) //17:16
1531 +#define RG_SSUSB_PLL_PREDIV_U3 (0x3<<8) //9:8
1532 +#define RG_SSUSB_PLL_FBKDIV_PE2D (0x7f<<0) //6:0
1533 +
1534 +//U3D_reg12
1535 +#define RG_SSUSB_PLL_PCW_NCPO_U3 (0x7fffffff<<0) //30:0
1536 +
1537 +//U3D_reg13
1538 +#define RG_SSUSB_PLL_PCW_NCPO_PE1H (0x7fffffff<<0) //30:0
1539 +
1540 +//U3D_reg14
1541 +#define RG_SSUSB_PLL_PCW_NCPO_PE1D (0x7fffffff<<0) //30:0
1542 +
1543 +//U3D_reg15
1544 +#define RG_SSUSB_PLL_PCW_NCPO_PE2H (0x7fffffff<<0) //30:0
1545 +
1546 +//U3D_reg16
1547 +#define RG_SSUSB_PLL_PCW_NCPO_PE2D (0x7fffffff<<0) //30:0
1548 +
1549 +//U3D_reg19
1550 +#define RG_SSUSB_PLL_SSC_DELTA1_PE1H (0xffff<<16) //31:16
1551 +#define RG_SSUSB_PLL_SSC_DELTA1_U3 (0xffff<<0) //15:0
1552 +
1553 +//U3D_reg20
1554 +#define RG_SSUSB_PLL_SSC_DELTA1_PE2H (0xffff<<16) //31:16
1555 +#define RG_SSUSB_PLL_SSC_DELTA1_PE1D (0xffff<<0) //15:0
1556 +
1557 +//U3D_reg21
1558 +#define RG_SSUSB_PLL_SSC_DELTA_U3 (0xffff<<16) //31:16
1559 +#define RG_SSUSB_PLL_SSC_DELTA1_PE2D (0xffff<<0) //15:0
1560 +
1561 +//U3D_reg23
1562 +#define RG_SSUSB_PLL_SSC_DELTA_PE1D (0xffff<<16) //31:16
1563 +#define RG_SSUSB_PLL_SSC_DELTA_PE1H (0xffff<<0) //15:0
1564 +
1565 +//U3D_reg25
1566 +#define RG_SSUSB_PLL_SSC_DELTA_PE2D (0xffff<<16) //31:16
1567 +#define RG_SSUSB_PLL_SSC_DELTA_PE2H (0xffff<<0) //15:0
1568 +
1569 +//U3D_reg26
1570 +#define RG_SSUSB_PLL_REFCKDIV_PE2D (0x1<<25) //25:25
1571 +#define RG_SSUSB_PLL_REFCKDIV_PE2H (0x1<<24) //24:24
1572 +#define RG_SSUSB_PLL_REFCKDIV_PE1D (0x1<<16) //16:16
1573 +#define RG_SSUSB_PLL_REFCKDIV_PE1H (0x1<<8) //8:8
1574 +#define RG_SSUSB_PLL_REFCKDIV_U3 (0x1<<0) //0:0
1575 +
1576 +//U3D_reg28
1577 +#define RG_SSUSB_CDR_BPA_PE2D (0x3<<24) //25:24
1578 +#define RG_SSUSB_CDR_BPA_PE2H (0x3<<16) //17:16
1579 +#define RG_SSUSB_CDR_BPA_PE1D (0x3<<10) //11:10
1580 +#define RG_SSUSB_CDR_BPA_PE1H (0x3<<8) //9:8
1581 +#define RG_SSUSB_CDR_BPA_U3 (0x3<<0) //1:0
1582 +
1583 +//U3D_reg29
1584 +#define RG_SSUSB_CDR_BPB_PE2D (0x7<<24) //26:24
1585 +#define RG_SSUSB_CDR_BPB_PE2H (0x7<<16) //18:16
1586 +#define RG_SSUSB_CDR_BPB_PE1D (0x7<<6) //8:6
1587 +#define RG_SSUSB_CDR_BPB_PE1H (0x7<<3) //5:3
1588 +#define RG_SSUSB_CDR_BPB_U3 (0x7<<0) //2:0
1589 +
1590 +//U3D_reg30
1591 +#define RG_SSUSB_CDR_BR_PE2D (0x7<<24) //26:24
1592 +#define RG_SSUSB_CDR_BR_PE2H (0x7<<16) //18:16
1593 +#define RG_SSUSB_CDR_BR_PE1D (0x7<<6) //8:6
1594 +#define RG_SSUSB_CDR_BR_PE1H (0x7<<3) //5:3
1595 +#define RG_SSUSB_CDR_BR_U3 (0x7<<0) //2:0
1596 +
1597 +//U3D_reg31
1598 +#define RG_SSUSB_CDR_FBDIV_PE2H (0x7f<<24) //30:24
1599 +#define RG_SSUSB_CDR_FBDIV_PE1D (0x7f<<16) //22:16
1600 +#define RG_SSUSB_CDR_FBDIV_PE1H (0x7f<<8) //14:8
1601 +#define RG_SSUSB_CDR_FBDIV_U3 (0x7f<<0) //6:0
1602 +
1603 +//U3D_reg32
1604 +#define RG_SSUSB_EQ_RSTEP1_PE2D (0x3<<30) //31:30
1605 +#define RG_SSUSB_EQ_RSTEP1_PE2H (0x3<<28) //29:28
1606 +#define RG_SSUSB_EQ_RSTEP1_PE1D (0x3<<26) //27:26
1607 +#define RG_SSUSB_EQ_RSTEP1_PE1H (0x3<<24) //25:24
1608 +#define RG_SSUSB_EQ_RSTEP1_U3 (0x3<<22) //23:22
1609 +#define RG_SSUSB_LFPS_DEGLITCH_PE2D (0x3<<20) //21:20
1610 +#define RG_SSUSB_LFPS_DEGLITCH_PE2H (0x3<<18) //19:18
1611 +#define RG_SSUSB_LFPS_DEGLITCH_PE1D (0x3<<16) //17:16
1612 +#define RG_SSUSB_LFPS_DEGLITCH_PE1H (0x3<<14) //15:14
1613 +#define RG_SSUSB_LFPS_DEGLITCH_U3 (0x3<<12) //13:12
1614 +#define RG_SSUSB_CDR_KVSEL_PE2D (0x1<<11) //11:11
1615 +#define RG_SSUSB_CDR_KVSEL_PE2H (0x1<<10) //10:10
1616 +#define RG_SSUSB_CDR_KVSEL_PE1D (0x1<<9) //9:9
1617 +#define RG_SSUSB_CDR_KVSEL_PE1H (0x1<<8) //8:8
1618 +#define RG_SSUSB_CDR_KVSEL_U3 (0x1<<7) //7:7
1619 +#define RG_SSUSB_CDR_FBDIV_PE2D (0x7f<<0) //6:0
1620 +
1621 +//U3D_reg33
1622 +#define RG_SSUSB_RX_CMPWD_PE2D (0x1<<26) //26:26
1623 +#define RG_SSUSB_RX_CMPWD_PE2H (0x1<<25) //25:25
1624 +#define RG_SSUSB_RX_CMPWD_PE1D (0x1<<24) //24:24
1625 +#define RG_SSUSB_RX_CMPWD_PE1H (0x1<<23) //23:23
1626 +#define RG_SSUSB_RX_CMPWD_U3 (0x1<<16) //16:16
1627 +#define RG_SSUSB_EQ_RSTEP2_PE2D (0x3<<8) //9:8
1628 +#define RG_SSUSB_EQ_RSTEP2_PE2H (0x3<<6) //7:6
1629 +#define RG_SSUSB_EQ_RSTEP2_PE1D (0x3<<4) //5:4
1630 +#define RG_SSUSB_EQ_RSTEP2_PE1H (0x3<<2) //3:2
1631 +#define RG_SSUSB_EQ_RSTEP2_U3 (0x3<<0) //1:0
1632 +
1633 +
1634 +/* OFFSET */
1635 +
1636 +//U3D_reg0
1637 +#define RG_PCIE_SPEED_PE2D_OFST (24)
1638 +#define RG_PCIE_SPEED_PE2H_OFST (23)
1639 +#define RG_PCIE_SPEED_PE1D_OFST (22)
1640 +#define RG_PCIE_SPEED_PE1H_OFST (21)
1641 +#define RG_PCIE_SPEED_U3_OFST (20)
1642 +#define RG_SSUSB_XTAL_EXT_EN_PE2D_OFST (18)
1643 +#define RG_SSUSB_XTAL_EXT_EN_PE2H_OFST (16)
1644 +#define RG_SSUSB_XTAL_EXT_EN_PE1D_OFST (14)
1645 +#define RG_SSUSB_XTAL_EXT_EN_PE1H_OFST (12)
1646 +#define RG_SSUSB_XTAL_EXT_EN_U3_OFST (10)
1647 +#define RG_SSUSB_CDR_REFCK_SEL_PE2D_OFST (8)
1648 +#define RG_SSUSB_CDR_REFCK_SEL_PE2H_OFST (6)
1649 +#define RG_SSUSB_CDR_REFCK_SEL_PE1D_OFST (4)
1650 +#define RG_SSUSB_CDR_REFCK_SEL_PE1H_OFST (2)
1651 +#define RG_SSUSB_CDR_REFCK_SEL_U3_OFST (0)
1652 +
1653 +//U3D_reg1
1654 +#define RG_USB20_REFCK_SEL_PE2D_OFST (30)
1655 +#define RG_USB20_REFCK_SEL_PE2H_OFST (29)
1656 +#define RG_USB20_REFCK_SEL_PE1D_OFST (28)
1657 +#define RG_USB20_REFCK_SEL_PE1H_OFST (27)
1658 +#define RG_USB20_REFCK_SEL_U3_OFST (26)
1659 +#define RG_PCIE_REFCK_DIV4_PE2D_OFST (25)
1660 +#define RG_PCIE_REFCK_DIV4_PE2H_OFST (24)
1661 +#define RG_PCIE_REFCK_DIV4_PE1D_OFST (18)
1662 +#define RG_PCIE_REFCK_DIV4_PE1H_OFST (17)
1663 +#define RG_PCIE_REFCK_DIV4_U3_OFST (16)
1664 +#define RG_PCIE_MODE_PE2D_OFST (8)
1665 +#define RG_PCIE_MODE_PE2H_OFST (3)
1666 +#define RG_PCIE_MODE_PE1D_OFST (2)
1667 +#define RG_PCIE_MODE_PE1H_OFST (1)
1668 +#define RG_PCIE_MODE_U3_OFST (0)
1669 +
1670 +//U3D_reg4
1671 +#define RG_SSUSB_PLL_DIVEN_PE2D_OFST (22)
1672 +#define RG_SSUSB_PLL_DIVEN_PE2H_OFST (19)
1673 +#define RG_SSUSB_PLL_DIVEN_PE1D_OFST (16)
1674 +#define RG_SSUSB_PLL_DIVEN_PE1H_OFST (13)
1675 +#define RG_SSUSB_PLL_DIVEN_U3_OFST (10)
1676 +#define RG_SSUSB_PLL_BC_PE2D_OFST (8)
1677 +#define RG_SSUSB_PLL_BC_PE2H_OFST (6)
1678 +#define RG_SSUSB_PLL_BC_PE1D_OFST (4)
1679 +#define RG_SSUSB_PLL_BC_PE1H_OFST (2)
1680 +#define RG_SSUSB_PLL_BC_U3_OFST (0)
1681 +
1682 +//U3D_reg5
1683 +#define RG_SSUSB_PLL_BR_PE2D_OFST (27)
1684 +#define RG_SSUSB_PLL_BR_PE2H_OFST (24)
1685 +#define RG_SSUSB_PLL_BR_PE1D_OFST (21)
1686 +#define RG_SSUSB_PLL_BR_PE1H_OFST (18)
1687 +#define RG_SSUSB_PLL_BR_U3_OFST (15)
1688 +#define RG_SSUSB_PLL_IC_PE2D_OFST (12)
1689 +#define RG_SSUSB_PLL_IC_PE2H_OFST (9)
1690 +#define RG_SSUSB_PLL_IC_PE1D_OFST (6)
1691 +#define RG_SSUSB_PLL_IC_PE1H_OFST (3)
1692 +#define RG_SSUSB_PLL_IC_U3_OFST (0)
1693 +
1694 +//U3D_reg6
1695 +#define RG_SSUSB_PLL_IR_PE2D_OFST (24)
1696 +#define RG_SSUSB_PLL_IR_PE2H_OFST (16)
1697 +#define RG_SSUSB_PLL_IR_PE1D_OFST (8)
1698 +#define RG_SSUSB_PLL_IR_PE1H_OFST (4)
1699 +#define RG_SSUSB_PLL_IR_U3_OFST (0)
1700 +
1701 +//U3D_reg7
1702 +#define RG_SSUSB_PLL_BP_PE2D_OFST (24)
1703 +#define RG_SSUSB_PLL_BP_PE2H_OFST (16)
1704 +#define RG_SSUSB_PLL_BP_PE1D_OFST (8)
1705 +#define RG_SSUSB_PLL_BP_PE1H_OFST (4)
1706 +#define RG_SSUSB_PLL_BP_U3_OFST (0)
1707 +
1708 +//U3D_reg8
1709 +#define RG_SSUSB_PLL_FBKSEL_PE2D_OFST (24)
1710 +#define RG_SSUSB_PLL_FBKSEL_PE2H_OFST (16)
1711 +#define RG_SSUSB_PLL_FBKSEL_PE1D_OFST (8)
1712 +#define RG_SSUSB_PLL_FBKSEL_PE1H_OFST (2)
1713 +#define RG_SSUSB_PLL_FBKSEL_U3_OFST (0)
1714 +
1715 +//U3D_reg9
1716 +#define RG_SSUSB_PLL_FBKDIV_PE2H_OFST (24)
1717 +#define RG_SSUSB_PLL_FBKDIV_PE1D_OFST (16)
1718 +#define RG_SSUSB_PLL_FBKDIV_PE1H_OFST (8)
1719 +#define RG_SSUSB_PLL_FBKDIV_U3_OFST (0)
1720 +
1721 +//U3D_reg10
1722 +#define RG_SSUSB_PLL_PREDIV_PE2D_OFST (26)
1723 +#define RG_SSUSB_PLL_PREDIV_PE2H_OFST (24)
1724 +#define RG_SSUSB_PLL_PREDIV_PE1D_OFST (18)
1725 +#define RG_SSUSB_PLL_PREDIV_PE1H_OFST (16)
1726 +#define RG_SSUSB_PLL_PREDIV_U3_OFST (8)
1727 +#define RG_SSUSB_PLL_FBKDIV_PE2D_OFST (0)
1728 +
1729 +//U3D_reg12
1730 +#define RG_SSUSB_PLL_PCW_NCPO_U3_OFST (0)
1731 +
1732 +//U3D_reg13
1733 +#define RG_SSUSB_PLL_PCW_NCPO_PE1H_OFST (0)
1734 +
1735 +//U3D_reg14
1736 +#define RG_SSUSB_PLL_PCW_NCPO_PE1D_OFST (0)
1737 +
1738 +//U3D_reg15
1739 +#define RG_SSUSB_PLL_PCW_NCPO_PE2H_OFST (0)
1740 +
1741 +//U3D_reg16
1742 +#define RG_SSUSB_PLL_PCW_NCPO_PE2D_OFST (0)
1743 +
1744 +//U3D_reg19
1745 +#define RG_SSUSB_PLL_SSC_DELTA1_PE1H_OFST (16)
1746 +#define RG_SSUSB_PLL_SSC_DELTA1_U3_OFST (0)
1747 +
1748 +//U3D_reg20
1749 +#define RG_SSUSB_PLL_SSC_DELTA1_PE2H_OFST (16)
1750 +#define RG_SSUSB_PLL_SSC_DELTA1_PE1D_OFST (0)
1751 +
1752 +//U3D_reg21
1753 +#define RG_SSUSB_PLL_SSC_DELTA_U3_OFST (16)
1754 +#define RG_SSUSB_PLL_SSC_DELTA1_PE2D_OFST (0)
1755 +
1756 +//U3D_reg23
1757 +#define RG_SSUSB_PLL_SSC_DELTA_PE1D_OFST (16)
1758 +#define RG_SSUSB_PLL_SSC_DELTA_PE1H_OFST (0)
1759 +
1760 +//U3D_reg25
1761 +#define RG_SSUSB_PLL_SSC_DELTA_PE2D_OFST (16)
1762 +#define RG_SSUSB_PLL_SSC_DELTA_PE2H_OFST (0)
1763 +
1764 +//U3D_reg26
1765 +#define RG_SSUSB_PLL_REFCKDIV_PE2D_OFST (25)
1766 +#define RG_SSUSB_PLL_REFCKDIV_PE2H_OFST (24)
1767 +#define RG_SSUSB_PLL_REFCKDIV_PE1D_OFST (16)
1768 +#define RG_SSUSB_PLL_REFCKDIV_PE1H_OFST (8)
1769 +#define RG_SSUSB_PLL_REFCKDIV_U3_OFST (0)
1770 +
1771 +//U3D_reg28
1772 +#define RG_SSUSB_CDR_BPA_PE2D_OFST (24)
1773 +#define RG_SSUSB_CDR_BPA_PE2H_OFST (16)
1774 +#define RG_SSUSB_CDR_BPA_PE1D_OFST (10)
1775 +#define RG_SSUSB_CDR_BPA_PE1H_OFST (8)
1776 +#define RG_SSUSB_CDR_BPA_U3_OFST (0)
1777 +
1778 +//U3D_reg29
1779 +#define RG_SSUSB_CDR_BPB_PE2D_OFST (24)
1780 +#define RG_SSUSB_CDR_BPB_PE2H_OFST (16)
1781 +#define RG_SSUSB_CDR_BPB_PE1D_OFST (6)
1782 +#define RG_SSUSB_CDR_BPB_PE1H_OFST (3)
1783 +#define RG_SSUSB_CDR_BPB_U3_OFST (0)
1784 +
1785 +//U3D_reg30
1786 +#define RG_SSUSB_CDR_BR_PE2D_OFST (24)
1787 +#define RG_SSUSB_CDR_BR_PE2H_OFST (16)
1788 +#define RG_SSUSB_CDR_BR_PE1D_OFST (6)
1789 +#define RG_SSUSB_CDR_BR_PE1H_OFST (3)
1790 +#define RG_SSUSB_CDR_BR_U3_OFST (0)
1791 +
1792 +//U3D_reg31
1793 +#define RG_SSUSB_CDR_FBDIV_PE2H_OFST (24)
1794 +#define RG_SSUSB_CDR_FBDIV_PE1D_OFST (16)
1795 +#define RG_SSUSB_CDR_FBDIV_PE1H_OFST (8)
1796 +#define RG_SSUSB_CDR_FBDIV_U3_OFST (0)
1797 +
1798 +//U3D_reg32
1799 +#define RG_SSUSB_EQ_RSTEP1_PE2D_OFST (30)
1800 +#define RG_SSUSB_EQ_RSTEP1_PE2H_OFST (28)
1801 +#define RG_SSUSB_EQ_RSTEP1_PE1D_OFST (26)
1802 +#define RG_SSUSB_EQ_RSTEP1_PE1H_OFST (24)
1803 +#define RG_SSUSB_EQ_RSTEP1_U3_OFST (22)
1804 +#define RG_SSUSB_LFPS_DEGLITCH_PE2D_OFST (20)
1805 +#define RG_SSUSB_LFPS_DEGLITCH_PE2H_OFST (18)
1806 +#define RG_SSUSB_LFPS_DEGLITCH_PE1D_OFST (16)
1807 +#define RG_SSUSB_LFPS_DEGLITCH_PE1H_OFST (14)
1808 +#define RG_SSUSB_LFPS_DEGLITCH_U3_OFST (12)
1809 +#define RG_SSUSB_CDR_KVSEL_PE2D_OFST (11)
1810 +#define RG_SSUSB_CDR_KVSEL_PE2H_OFST (10)
1811 +#define RG_SSUSB_CDR_KVSEL_PE1D_OFST (9)
1812 +#define RG_SSUSB_CDR_KVSEL_PE1H_OFST (8)
1813 +#define RG_SSUSB_CDR_KVSEL_U3_OFST (7)
1814 +#define RG_SSUSB_CDR_FBDIV_PE2D_OFST (0)
1815 +
1816 +//U3D_reg33
1817 +#define RG_SSUSB_RX_CMPWD_PE2D_OFST (26)
1818 +#define RG_SSUSB_RX_CMPWD_PE2H_OFST (25)
1819 +#define RG_SSUSB_RX_CMPWD_PE1D_OFST (24)
1820 +#define RG_SSUSB_RX_CMPWD_PE1H_OFST (23)
1821 +#define RG_SSUSB_RX_CMPWD_U3_OFST (16)
1822 +#define RG_SSUSB_EQ_RSTEP2_PE2D_OFST (8)
1823 +#define RG_SSUSB_EQ_RSTEP2_PE2H_OFST (6)
1824 +#define RG_SSUSB_EQ_RSTEP2_PE1D_OFST (4)
1825 +#define RG_SSUSB_EQ_RSTEP2_PE1H_OFST (2)
1826 +#define RG_SSUSB_EQ_RSTEP2_U3_OFST (0)
1827 +
1828 +
1829 +///////////////////////////////////////////////////////////////////////////////
1830 +
1831 +struct u3phyd_reg {
1832 + //0x0
1833 + PHY_LE32 phyd_mix0;
1834 + PHY_LE32 phyd_mix1;
1835 + PHY_LE32 phyd_lfps0;
1836 + PHY_LE32 phyd_lfps1;
1837 + //0x10
1838 + PHY_LE32 phyd_impcal0;
1839 + PHY_LE32 phyd_impcal1;
1840 + PHY_LE32 phyd_txpll0;
1841 + PHY_LE32 phyd_txpll1;
1842 + //0x20
1843 + PHY_LE32 phyd_txpll2;
1844 + PHY_LE32 phyd_fl0;
1845 + PHY_LE32 phyd_mix2;
1846 + PHY_LE32 phyd_rx0;
1847 + //0x30
1848 + PHY_LE32 phyd_t2rlb;
1849 + PHY_LE32 phyd_cppat;
1850 + PHY_LE32 phyd_mix3;
1851 + PHY_LE32 phyd_ebufctl;
1852 + //0x40
1853 + PHY_LE32 phyd_pipe0;
1854 + PHY_LE32 phyd_pipe1;
1855 + PHY_LE32 phyd_mix4;
1856 + PHY_LE32 phyd_ckgen0;
1857 + //0x50
1858 + PHY_LE32 phyd_mix5;
1859 + PHY_LE32 phyd_reserved;
1860 + PHY_LE32 phyd_cdr0;
1861 + PHY_LE32 phyd_cdr1;
1862 + //0x60
1863 + PHY_LE32 phyd_pll_0;
1864 + PHY_LE32 phyd_pll_1;
1865 + PHY_LE32 phyd_bcn_det_1;
1866 + PHY_LE32 phyd_bcn_det_2;
1867 + //0x70
1868 + PHY_LE32 eq0;
1869 + PHY_LE32 eq1;
1870 + PHY_LE32 eq2;
1871 + PHY_LE32 eq3;
1872 + //0x80
1873 + PHY_LE32 eq_eye0;
1874 + PHY_LE32 eq_eye1;
1875 + PHY_LE32 eq_eye2;
1876 + PHY_LE32 eq_dfe0;
1877 + //0x90
1878 + PHY_LE32 eq_dfe1;
1879 + PHY_LE32 eq_dfe2;
1880 + PHY_LE32 eq_dfe3;
1881 + PHY_LE32 reserve0;
1882 + //0xa0
1883 + PHY_LE32 phyd_mon0;
1884 + PHY_LE32 phyd_mon1;
1885 + PHY_LE32 phyd_mon2;
1886 + PHY_LE32 phyd_mon3;
1887 + //0xb0
1888 + PHY_LE32 phyd_mon4;
1889 + PHY_LE32 phyd_mon5;
1890 + PHY_LE32 phyd_mon6;
1891 + PHY_LE32 phyd_mon7;
1892 + //0xc0
1893 + PHY_LE32 phya_rx_mon0;
1894 + PHY_LE32 phya_rx_mon1;
1895 + PHY_LE32 phya_rx_mon2;
1896 + PHY_LE32 phya_rx_mon3;
1897 + //0xd0
1898 + PHY_LE32 phya_rx_mon4;
1899 + PHY_LE32 phya_rx_mon5;
1900 + PHY_LE32 phyd_cppat2;
1901 + PHY_LE32 eq_eye3;
1902 + //0xe0
1903 + PHY_LE32 kband_out;
1904 + PHY_LE32 kband_out1;
1905 +};
1906 +
1907 +//U3D_PHYD_MIX0
1908 +#define RG_SSUSB_P_P3_TX_NG (0x1<<31) //31:31
1909 +#define RG_SSUSB_TSEQ_EN (0x1<<30) //30:30
1910 +#define RG_SSUSB_TSEQ_POLEN (0x1<<29) //29:29
1911 +#define RG_SSUSB_TSEQ_POL (0x1<<28) //28:28
1912 +#define RG_SSUSB_P_P3_PCLK_NG (0x1<<27) //27:27
1913 +#define RG_SSUSB_TSEQ_TH (0x7<<24) //26:24
1914 +#define RG_SSUSB_PRBS_BERTH (0xff<<16) //23:16
1915 +#define RG_SSUSB_DISABLE_PHY_U2_ON (0x1<<15) //15:15
1916 +#define RG_SSUSB_DISABLE_PHY_U2_OFF (0x1<<14) //14:14
1917 +#define RG_SSUSB_PRBS_EN (0x1<<13) //13:13
1918 +#define RG_SSUSB_BPSLOCK (0x1<<12) //12:12
1919 +#define RG_SSUSB_RTCOMCNT (0xf<<8) //11:8
1920 +#define RG_SSUSB_COMCNT (0xf<<4) //7:4
1921 +#define RG_SSUSB_PRBSEL_CALIB (0xf<<0) //3:0
1922 +
1923 +//U3D_PHYD_MIX1
1924 +#define RG_SSUSB_SLEEP_EN (0x1<<31) //31:31
1925 +#define RG_SSUSB_PRBSEL_PCS (0x7<<28) //30:28
1926 +#define RG_SSUSB_TXLFPS_PRD (0xf<<24) //27:24
1927 +#define RG_SSUSB_P_RX_P0S_CK (0x1<<23) //23:23
1928 +#define RG_SSUSB_P_TX_P0S_CK (0x1<<22) //22:22
1929 +#define RG_SSUSB_PDNCTL (0x3f<<16) //21:16
1930 +#define RG_SSUSB_TX_DRV_EN (0x1<<15) //15:15
1931 +#define RG_SSUSB_TX_DRV_SEL (0x1<<14) //14:14
1932 +#define RG_SSUSB_TX_DRV_DLY (0x3f<<8) //13:8
1933 +#define RG_SSUSB_BERT_EN (0x1<<7) //7:7
1934 +#define RG_SSUSB_SCP_TH (0x7<<4) //6:4
1935 +#define RG_SSUSB_SCP_EN (0x1<<3) //3:3
1936 +#define RG_SSUSB_RXANSIDEC_TEST (0x7<<0) //2:0
1937 +
1938 +//U3D_PHYD_LFPS0
1939 +#define RG_SSUSB_LFPS_PWD (0x1<<30) //30:30
1940 +#define RG_SSUSB_FORCE_LFPS_PWD (0x1<<29) //29:29
1941 +#define RG_SSUSB_RXLFPS_OVF (0x1f<<24) //28:24
1942 +#define RG_SSUSB_P3_ENTRY_SEL (0x1<<23) //23:23
1943 +#define RG_SSUSB_P3_ENTRY (0x1<<22) //22:22
1944 +#define RG_SSUSB_RXLFPS_CDRSEL (0x3<<20) //21:20
1945 +#define RG_SSUSB_RXLFPS_CDRTH (0xf<<16) //19:16
1946 +#define RG_SSUSB_LOCK5G_BLOCK (0x1<<15) //15:15
1947 +#define RG_SSUSB_TFIFO_EXT_D_SEL (0x1<<14) //14:14
1948 +#define RG_SSUSB_TFIFO_NO_EXTEND (0x1<<13) //13:13
1949 +#define RG_SSUSB_RXLFPS_LOB (0x1f<<8) //12:8
1950 +#define RG_SSUSB_TXLFPS_EN (0x1<<7) //7:7
1951 +#define RG_SSUSB_TXLFPS_SEL (0x1<<6) //6:6
1952 +#define RG_SSUSB_RXLFPS_CDRLOCK (0x1<<5) //5:5
1953 +#define RG_SSUSB_RXLFPS_UPB (0x1f<<0) //4:0
1954 +
1955 +//U3D_PHYD_LFPS1
1956 +#define RG_SSUSB_RX_IMP_BIAS (0xf<<28) //31:28
1957 +#define RG_SSUSB_TX_IMP_BIAS (0xf<<24) //27:24
1958 +#define RG_SSUSB_FWAKE_TH (0x3f<<16) //21:16
1959 +#define RG_SSUSB_RXLFPS_UDF (0x1f<<8) //12:8
1960 +#define RG_SSUSB_RXLFPS_P0IDLETH (0xff<<0) //7:0
1961 +
1962 +//U3D_PHYD_IMPCAL0
1963 +#define RG_SSUSB_FORCE_TX_IMPSEL (0x1<<31) //31:31
1964 +#define RG_SSUSB_TX_IMPCAL_EN (0x1<<30) //30:30
1965 +#define RG_SSUSB_FORCE_TX_IMPCAL_EN (0x1<<29) //29:29
1966 +#define RG_SSUSB_TX_IMPSEL (0x1f<<24) //28:24
1967 +#define RG_SSUSB_TX_IMPCAL_CALCYC (0x3f<<16) //21:16
1968 +#define RG_SSUSB_TX_IMPCAL_STBCYC (0x1f<<10) //14:10
1969 +#define RG_SSUSB_TX_IMPCAL_CYCCNT (0x3ff<<0) //9:0
1970 +
1971 +//U3D_PHYD_IMPCAL1
1972 +#define RG_SSUSB_FORCE_RX_IMPSEL (0x1<<31) //31:31
1973 +#define RG_SSUSB_RX_IMPCAL_EN (0x1<<30) //30:30
1974 +#define RG_SSUSB_FORCE_RX_IMPCAL_EN (0x1<<29) //29:29
1975 +#define RG_SSUSB_RX_IMPSEL (0x1f<<24) //28:24
1976 +#define RG_SSUSB_RX_IMPCAL_CALCYC (0x3f<<16) //21:16
1977 +#define RG_SSUSB_RX_IMPCAL_STBCYC (0x1f<<10) //14:10
1978 +#define RG_SSUSB_RX_IMPCAL_CYCCNT (0x3ff<<0) //9:0
1979 +
1980 +//U3D_PHYD_TXPLL0
1981 +#define RG_SSUSB_TXPLL_DDSEN_CYC (0x1f<<27) //31:27
1982 +#define RG_SSUSB_TXPLL_ON (0x1<<26) //26:26
1983 +#define RG_SSUSB_FORCE_TXPLLON (0x1<<25) //25:25
1984 +#define RG_SSUSB_TXPLL_STBCYC (0x1ff<<16) //24:16
1985 +#define RG_SSUSB_TXPLL_NCPOCHG_CYC (0xf<<12) //15:12
1986 +#define RG_SSUSB_TXPLL_NCPOEN_CYC (0x3<<10) //11:10
1987 +#define RG_SSUSB_TXPLL_DDSRSTB_CYC (0x7<<0) //2:0
1988 +
1989 +//U3D_PHYD_TXPLL1
1990 +#define RG_SSUSB_PLL_NCPO_EN (0x1<<31) //31:31
1991 +#define RG_SSUSB_PLL_FIFO_START_MAN (0x1<<30) //30:30
1992 +#define RG_SSUSB_PLL_NCPO_CHG (0x1<<28) //28:28
1993 +#define RG_SSUSB_PLL_DDS_RSTB (0x1<<27) //27:27
1994 +#define RG_SSUSB_PLL_DDS_PWDB (0x1<<26) //26:26
1995 +#define RG_SSUSB_PLL_DDSEN (0x1<<25) //25:25
1996 +#define RG_SSUSB_PLL_AUTOK_VCO (0x1<<24) //24:24
1997 +#define RG_SSUSB_PLL_PWD (0x1<<23) //23:23
1998 +#define RG_SSUSB_RX_AFE_PWD (0x1<<22) //22:22
1999 +#define RG_SSUSB_PLL_TCADJ (0x3f<<16) //21:16
2000 +#define RG_SSUSB_FORCE_CDR_TCADJ (0x1<<15) //15:15
2001 +#define RG_SSUSB_FORCE_CDR_AUTOK_VCO (0x1<<14) //14:14
2002 +#define RG_SSUSB_FORCE_CDR_PWD (0x1<<13) //13:13
2003 +#define RG_SSUSB_FORCE_PLL_NCPO_EN (0x1<<12) //12:12
2004 +#define RG_SSUSB_FORCE_PLL_FIFO_START_MAN (0x1<<11) //11:11
2005 +#define RG_SSUSB_FORCE_PLL_NCPO_CHG (0x1<<9) //9:9
2006 +#define RG_SSUSB_FORCE_PLL_DDS_RSTB (0x1<<8) //8:8
2007 +#define RG_SSUSB_FORCE_PLL_DDS_PWDB (0x1<<7) //7:7
2008 +#define RG_SSUSB_FORCE_PLL_DDSEN (0x1<<6) //6:6
2009 +#define RG_SSUSB_FORCE_PLL_TCADJ (0x1<<5) //5:5
2010 +#define RG_SSUSB_FORCE_PLL_AUTOK_VCO (0x1<<4) //4:4
2011 +#define RG_SSUSB_FORCE_PLL_PWD (0x1<<3) //3:3
2012 +#define RG_SSUSB_FLT_1_DISPERR_B (0x1<<2) //2:2
2013 +
2014 +//U3D_PHYD_TXPLL2
2015 +#define RG_SSUSB_TX_LFPS_EN (0x1<<31) //31:31
2016 +#define RG_SSUSB_FORCE_TX_LFPS_EN (0x1<<30) //30:30
2017 +#define RG_SSUSB_TX_LFPS (0x1<<29) //29:29
2018 +#define RG_SSUSB_FORCE_TX_LFPS (0x1<<28) //28:28
2019 +#define RG_SSUSB_RXPLL_STB (0x1<<27) //27:27
2020 +#define RG_SSUSB_TXPLL_STB (0x1<<26) //26:26
2021 +#define RG_SSUSB_FORCE_RXPLL_STB (0x1<<25) //25:25
2022 +#define RG_SSUSB_FORCE_TXPLL_STB (0x1<<24) //24:24
2023 +#define RG_SSUSB_RXPLL_REFCKSEL (0x1<<16) //16:16
2024 +#define RG_SSUSB_RXPLL_STBMODE (0x1<<11) //11:11
2025 +#define RG_SSUSB_RXPLL_ON (0x1<<10) //10:10
2026 +#define RG_SSUSB_FORCE_RXPLLON (0x1<<9) //9:9
2027 +#define RG_SSUSB_FORCE_RX_AFE_PWD (0x1<<8) //8:8
2028 +#define RG_SSUSB_CDR_AUTOK_VCO (0x1<<7) //7:7
2029 +#define RG_SSUSB_CDR_PWD (0x1<<6) //6:6
2030 +#define RG_SSUSB_CDR_TCADJ (0x3f<<0) //5:0
2031 +
2032 +//U3D_PHYD_FL0
2033 +#define RG_SSUSB_RX_FL_TARGET (0xffff<<16) //31:16
2034 +#define RG_SSUSB_RX_FL_CYCLECNT (0xffff<<0) //15:0
2035 +
2036 +//U3D_PHYD_MIX2
2037 +#define RG_SSUSB_RX_EQ_RST (0x1<<31) //31:31
2038 +#define RG_SSUSB_RX_EQ_RST_SEL (0x1<<30) //30:30
2039 +#define RG_SSUSB_RXVAL_RST (0x1<<29) //29:29
2040 +#define RG_SSUSB_RXVAL_CNT (0x1f<<24) //28:24
2041 +#define RG_SSUSB_CDROS_EN (0x1<<18) //18:18
2042 +#define RG_SSUSB_CDR_LCKOP (0x3<<16) //17:16
2043 +#define RG_SSUSB_RX_FL_LOCKTH (0xf<<8) //11:8
2044 +#define RG_SSUSB_RX_FL_OFFSET (0xff<<0) //7:0
2045 +
2046 +//U3D_PHYD_RX0
2047 +#define RG_SSUSB_T2RLB_BERTH (0xff<<24) //31:24
2048 +#define RG_SSUSB_T2RLB_PAT (0xff<<16) //23:16
2049 +#define RG_SSUSB_T2RLB_EN (0x1<<15) //15:15
2050 +#define RG_SSUSB_T2RLB_BPSCRAMB (0x1<<14) //14:14
2051 +#define RG_SSUSB_T2RLB_SERIAL (0x1<<13) //13:13
2052 +#define RG_SSUSB_T2RLB_MODE (0x3<<11) //12:11
2053 +#define RG_SSUSB_RX_SAOSC_EN (0x1<<10) //10:10
2054 +#define RG_SSUSB_RX_SAOSC_EN_SEL (0x1<<9) //9:9
2055 +#define RG_SSUSB_RX_DFE_OPTION (0x1<<8) //8:8
2056 +#define RG_SSUSB_RX_DFE_EN (0x1<<7) //7:7
2057 +#define RG_SSUSB_RX_DFE_EN_SEL (0x1<<6) //6:6
2058 +#define RG_SSUSB_RX_EQ_EN (0x1<<5) //5:5
2059 +#define RG_SSUSB_RX_EQ_EN_SEL (0x1<<4) //4:4
2060 +#define RG_SSUSB_RX_SAOSC_RST (0x1<<3) //3:3
2061 +#define RG_SSUSB_RX_SAOSC_RST_SEL (0x1<<2) //2:2
2062 +#define RG_SSUSB_RX_DFE_RST (0x1<<1) //1:1
2063 +#define RG_SSUSB_RX_DFE_RST_SEL (0x1<<0) //0:0
2064 +
2065 +//U3D_PHYD_T2RLB
2066 +#define RG_SSUSB_EQTRAIN_CH_MODE (0x1<<28) //28:28
2067 +#define RG_SSUSB_PRB_OUT_CPPAT (0x1<<27) //27:27
2068 +#define RG_SSUSB_BPANSIENC (0x1<<26) //26:26
2069 +#define RG_SSUSB_VALID_EN (0x1<<25) //25:25
2070 +#define RG_SSUSB_EBUF_SRST (0x1<<24) //24:24
2071 +#define RG_SSUSB_K_EMP (0xf<<20) //23:20
2072 +#define RG_SSUSB_K_FUL (0xf<<16) //19:16
2073 +#define RG_SSUSB_T2RLB_BDATRST (0xf<<12) //15:12
2074 +#define RG_SSUSB_P_T2RLB_SKP_EN (0x1<<10) //10:10
2075 +#define RG_SSUSB_T2RLB_PATMODE (0x3<<8) //9:8
2076 +#define RG_SSUSB_T2RLB_TSEQCNT (0xff<<0) //7:0
2077 +
2078 +//U3D_PHYD_CPPAT
2079 +#define RG_SSUSB_CPPAT_PROGRAM_EN (0x1<<24) //24:24
2080 +#define RG_SSUSB_CPPAT_TOZ (0x3<<21) //22:21
2081 +#define RG_SSUSB_CPPAT_PRBS_EN (0x1<<20) //20:20
2082 +#define RG_SSUSB_CPPAT_OUT_TMP2 (0xf<<16) //19:16
2083 +#define RG_SSUSB_CPPAT_OUT_TMP1 (0xff<<8) //15:8
2084 +#define RG_SSUSB_CPPAT_OUT_TMP0 (0xff<<0) //7:0
2085 +
2086 +//U3D_PHYD_MIX3
2087 +#define RG_SSUSB_CDR_TCADJ_MINUS (0x1<<31) //31:31
2088 +#define RG_SSUSB_P_CDROS_EN (0x1<<30) //30:30
2089 +#define RG_SSUSB_P_P2_TX_DRV_DIS (0x1<<28) //28:28
2090 +#define RG_SSUSB_CDR_TCADJ_OFFSET (0x7<<24) //26:24
2091 +#define RG_SSUSB_PLL_TCADJ_MINUS (0x1<<23) //23:23
2092 +#define RG_SSUSB_FORCE_PLL_BIAS_LPF_EN (0x1<<20) //20:20
2093 +#define RG_SSUSB_PLL_BIAS_LPF_EN (0x1<<19) //19:19
2094 +#define RG_SSUSB_PLL_TCADJ_OFFSET (0x7<<16) //18:16
2095 +#define RG_SSUSB_FORCE_PLL_SSCEN (0x1<<15) //15:15
2096 +#define RG_SSUSB_PLL_SSCEN (0x1<<14) //14:14
2097 +#define RG_SSUSB_FORCE_CDR_PI_PWD (0x1<<13) //13:13
2098 +#define RG_SSUSB_CDR_PI_PWD (0x1<<12) //12:12
2099 +#define RG_SSUSB_CDR_PI_MODE (0x1<<11) //11:11
2100 +#define RG_SSUSB_TXPLL_SSCEN_CYC (0x3ff<<0) //9:0
2101 +
2102 +//U3D_PHYD_EBUFCTL
2103 +#define RG_SSUSB_EBUFCTL (0xffffffff<<0) //31:0
2104 +
2105 +//U3D_PHYD_PIPE0
2106 +#define RG_SSUSB_RXTERMINATION (0x1<<30) //30:30
2107 +#define RG_SSUSB_RXEQTRAINING (0x1<<29) //29:29
2108 +#define RG_SSUSB_RXPOLARITY (0x1<<28) //28:28
2109 +#define RG_SSUSB_TXDEEMPH (0x3<<26) //27:26
2110 +#define RG_SSUSB_POWERDOWN (0x3<<24) //25:24
2111 +#define RG_SSUSB_TXONESZEROS (0x1<<23) //23:23
2112 +#define RG_SSUSB_TXELECIDLE (0x1<<22) //22:22
2113 +#define RG_SSUSB_TXDETECTRX (0x1<<21) //21:21
2114 +#define RG_SSUSB_PIPE_SEL (0x1<<20) //20:20
2115 +#define RG_SSUSB_TXDATAK (0xf<<16) //19:16
2116 +#define RG_SSUSB_CDR_STABLE_SEL (0x1<<15) //15:15
2117 +#define RG_SSUSB_CDR_STABLE (0x1<<14) //14:14
2118 +#define RG_SSUSB_CDR_RSTB_SEL (0x1<<13) //13:13
2119 +#define RG_SSUSB_CDR_RSTB (0x1<<12) //12:12
2120 +#define RG_SSUSB_P_ERROR_SEL (0x3<<4) //5:4
2121 +#define RG_SSUSB_TXMARGIN (0x7<<1) //3:1
2122 +#define RG_SSUSB_TXCOMPLIANCE (0x1<<0) //0:0
2123 +
2124 +//U3D_PHYD_PIPE1
2125 +#define RG_SSUSB_TXDATA (0xffffffff<<0) //31:0
2126 +
2127 +//U3D_PHYD_MIX4
2128 +#define RG_SSUSB_CDROS_CNT (0x3f<<24) //29:24
2129 +#define RG_SSUSB_T2RLB_BER_EN (0x1<<16) //16:16
2130 +#define RG_SSUSB_T2RLB_BER_RATE (0xffff<<0) //15:0
2131 +
2132 +//U3D_PHYD_CKGEN0
2133 +#define RG_SSUSB_RFIFO_IMPLAT (0x1<<27) //27:27
2134 +#define RG_SSUSB_TFIFO_PSEL (0x7<<24) //26:24
2135 +#define RG_SSUSB_CKGEN_PSEL (0x3<<8) //9:8
2136 +#define RG_SSUSB_RXCK_INV (0x1<<0) //0:0
2137 +
2138 +//U3D_PHYD_MIX5
2139 +#define RG_SSUSB_PRB_SEL (0xffff<<16) //31:16
2140 +#define RG_SSUSB_RXPLL_STBCYC (0x7ff<<0) //10:0
2141 +
2142 +//U3D_PHYD_RESERVED
2143 +#define RG_SSUSB_PHYD_RESERVE (0xffffffff<<0) //31:0
2144 +//#define RG_SSUSB_RX_SIGDET_SEL (0x1<<11)
2145 +//#define RG_SSUSB_RX_SIGDET_EN (0x1<<12)
2146 +//#define RG_SSUSB_RX_PI_CAL_MANUAL_SEL (0x1<<9)
2147 +//#define RG_SSUSB_RX_PI_CAL_MANUAL_EN (0x1<<10)
2148 +
2149 +//U3D_PHYD_CDR0
2150 +#define RG_SSUSB_CDR_BIC_LTR (0xf<<28) //31:28
2151 +#define RG_SSUSB_CDR_BIC_LTD0 (0xf<<24) //27:24
2152 +#define RG_SSUSB_CDR_BC_LTD1 (0x1f<<16) //20:16
2153 +#define RG_SSUSB_CDR_BC_LTR (0x1f<<8) //12:8
2154 +#define RG_SSUSB_CDR_BC_LTD0 (0x1f<<0) //4:0
2155 +
2156 +//U3D_PHYD_CDR1
2157 +#define RG_SSUSB_CDR_BIR_LTD1 (0x1f<<24) //28:24
2158 +#define RG_SSUSB_CDR_BIR_LTR (0x1f<<16) //20:16
2159 +#define RG_SSUSB_CDR_BIR_LTD0 (0x1f<<8) //12:8
2160 +#define RG_SSUSB_CDR_BW_SEL (0x3<<6) //7:6
2161 +#define RG_SSUSB_CDR_BIC_LTD1 (0xf<<0) //3:0
2162 +
2163 +//U3D_PHYD_PLL_0
2164 +#define RG_SSUSB_FORCE_CDR_BAND_5G (0x1<<28) //28:28
2165 +#define RG_SSUSB_FORCE_CDR_BAND_2P5G (0x1<<27) //27:27
2166 +#define RG_SSUSB_FORCE_PLL_BAND_5G (0x1<<26) //26:26
2167 +#define RG_SSUSB_FORCE_PLL_BAND_2P5G (0x1<<25) //25:25
2168 +#define RG_SSUSB_P_EQ_T_SEL (0x3ff<<15) //24:15
2169 +#define RG_SSUSB_PLL_ISO_EN_CYC (0x3ff<<5) //14:5
2170 +#define RG_SSUSB_PLLBAND_RECAL (0x1<<4) //4:4
2171 +#define RG_SSUSB_PLL_DDS_ISO_EN (0x1<<3) //3:3
2172 +#define RG_SSUSB_FORCE_PLL_DDS_ISO_EN (0x1<<2) //2:2
2173 +#define RG_SSUSB_PLL_DDS_PWR_ON (0x1<<1) //1:1
2174 +#define RG_SSUSB_FORCE_PLL_DDS_PWR_ON (0x1<<0) //0:0
2175 +
2176 +//U3D_PHYD_PLL_1
2177 +#define RG_SSUSB_CDR_BAND_5G (0xff<<24) //31:24
2178 +#define RG_SSUSB_CDR_BAND_2P5G (0xff<<16) //23:16
2179 +#define RG_SSUSB_PLL_BAND_5G (0xff<<8) //15:8
2180 +#define RG_SSUSB_PLL_BAND_2P5G (0xff<<0) //7:0
2181 +
2182 +//U3D_PHYD_BCN_DET_1
2183 +#define RG_SSUSB_P_BCN_OBS_PRD (0xffff<<16) //31:16
2184 +#define RG_SSUSB_U_BCN_OBS_PRD (0xffff<<0) //15:0
2185 +
2186 +//U3D_PHYD_BCN_DET_2
2187 +#define RG_SSUSB_P_BCN_OBS_SEL (0xfff<<16) //27:16
2188 +#define RG_SSUSB_BCN_DET_DIS (0x1<<12) //12:12
2189 +#define RG_SSUSB_U_BCN_OBS_SEL (0xfff<<0) //11:0
2190 +
2191 +//U3D_EQ0
2192 +#define RG_SSUSB_EQ_DLHL_LFI (0x7f<<24) //30:24
2193 +#define RG_SSUSB_EQ_DHHL_LFI (0x7f<<16) //22:16
2194 +#define RG_SSUSB_EQ_DD0HOS_LFI (0x7f<<8) //14:8
2195 +#define RG_SSUSB_EQ_DD0LOS_LFI (0x7f<<0) //6:0
2196 +
2197 +//U3D_EQ1
2198 +#define RG_SSUSB_EQ_DD1HOS_LFI (0x7f<<24) //30:24
2199 +#define RG_SSUSB_EQ_DD1LOS_LFI (0x7f<<16) //22:16
2200 +#define RG_SSUSB_EQ_DE0OS_LFI (0x7f<<8) //14:8
2201 +#define RG_SSUSB_EQ_DE1OS_LFI (0x7f<<0) //6:0
2202 +
2203 +//U3D_EQ2
2204 +#define RG_SSUSB_EQ_DLHLOS_LFI (0x7f<<24) //30:24
2205 +#define RG_SSUSB_EQ_DHHLOS_LFI (0x7f<<16) //22:16
2206 +#define RG_SSUSB_EQ_STOPTIME (0x1<<14) //14:14
2207 +#define RG_SSUSB_EQ_DHHL_LF_SEL (0x7<<11) //13:11
2208 +#define RG_SSUSB_EQ_DSAOS_LF_SEL (0x7<<8) //10:8
2209 +#define RG_SSUSB_EQ_STARTTIME (0x3<<6) //7:6
2210 +#define RG_SSUSB_EQ_DLEQ_LF_SEL (0x7<<3) //5:3
2211 +#define RG_SSUSB_EQ_DLHL_LF_SEL (0x7<<0) //2:0
2212 +
2213 +//U3D_EQ3
2214 +#define RG_SSUSB_EQ_DLEQ_LFI_GEN2 (0xf<<28) //31:28
2215 +#define RG_SSUSB_EQ_DLEQ_LFI_GEN1 (0xf<<24) //27:24
2216 +#define RG_SSUSB_EQ_DEYE0OS_LFI (0x7f<<16) //22:16
2217 +#define RG_SSUSB_EQ_DEYE1OS_LFI (0x7f<<8) //14:8
2218 +#define RG_SSUSB_EQ_TRI_DET_EN (0x1<<7) //7:7
2219 +#define RG_SSUSB_EQ_TRI_DET_TH (0x7f<<0) //6:0
2220 +
2221 +//U3D_EQ_EYE0
2222 +#define RG_SSUSB_EQ_EYE_XOFFSET (0x7f<<25) //31:25
2223 +#define RG_SSUSB_EQ_EYE_MON_EN (0x1<<24) //24:24
2224 +#define RG_SSUSB_EQ_EYE0_Y (0x7f<<16) //22:16
2225 +#define RG_SSUSB_EQ_EYE1_Y (0x7f<<8) //14:8
2226 +#define RG_SSUSB_EQ_PILPO_ROUT (0x1<<7) //7:7
2227 +#define RG_SSUSB_EQ_PI_KPGAIN (0x7<<4) //6:4
2228 +#define RG_SSUSB_EQ_EYE_CNT_EN (0x1<<3) //3:3
2229 +
2230 +//U3D_EQ_EYE1
2231 +#define RG_SSUSB_EQ_SIGDET (0x7f<<24) //30:24
2232 +#define RG_SSUSB_EQ_EYE_MASK (0x3ff<<7) //16:7
2233 +
2234 +//U3D_EQ_EYE2
2235 +#define RG_SSUSB_EQ_RX500M_CK_SEL (0x1<<31) //31:31
2236 +#define RG_SSUSB_EQ_SD_CNT1 (0x3f<<24) //29:24
2237 +#define RG_SSUSB_EQ_ISIFLAG_SEL (0x3<<22) //23:22
2238 +#define RG_SSUSB_EQ_SD_CNT0 (0x3f<<16) //21:16
2239 +
2240 +//U3D_EQ_DFE0
2241 +#define RG_SSUSB_EQ_LEQMAX (0xf<<28) //31:28
2242 +#define RG_SSUSB_EQ_DFEX_EN (0x1<<27) //27:27
2243 +#define RG_SSUSB_EQ_DFEX_LF_SEL (0x7<<24) //26:24
2244 +#define RG_SSUSB_EQ_CHK_EYE_H (0x1<<23) //23:23
2245 +#define RG_SSUSB_EQ_PIEYE_INI (0x7f<<16) //22:16
2246 +#define RG_SSUSB_EQ_PI90_INI (0x7f<<8) //14:8
2247 +#define RG_SSUSB_EQ_PI0_INI (0x7f<<0) //6:0
2248 +
2249 +//U3D_EQ_DFE1
2250 +#define RG_SSUSB_EQ_REV (0xffff<<16) //31:16
2251 +#define RG_SSUSB_EQ_DFEYEN_DUR (0x7<<12) //14:12
2252 +#define RG_SSUSB_EQ_DFEXEN_DUR (0x7<<8) //10:8
2253 +#define RG_SSUSB_EQ_DFEX_RST (0x1<<7) //7:7
2254 +#define RG_SSUSB_EQ_GATED_RXD_B (0x1<<6) //6:6
2255 +#define RG_SSUSB_EQ_PI90CK_SEL (0x3<<4) //5:4
2256 +#define RG_SSUSB_EQ_DFEX_DIS (0x1<<2) //2:2
2257 +#define RG_SSUSB_EQ_DFEYEN_STOP_DIS (0x1<<1) //1:1
2258 +#define RG_SSUSB_EQ_DFEXEN_SEL (0x1<<0) //0:0
2259 +
2260 +//U3D_EQ_DFE2
2261 +#define RG_SSUSB_EQ_MON_SEL (0x1f<<24) //28:24
2262 +#define RG_SSUSB_EQ_LEQOSC_DLYCNT (0x7<<16) //18:16
2263 +#define RG_SSUSB_EQ_DLEQOS_LFI (0x1f<<8) //12:8
2264 +#define RG_SSUSB_EQ_LEQ_STOP_TO (0x3<<0) //1:0
2265 +
2266 +//U3D_EQ_DFE3
2267 +#define RG_SSUSB_EQ_RESERVED (0xffffffff<<0) //31:0
2268 +
2269 +//U3D_PHYD_MON0
2270 +#define RGS_SSUSB_BERT_BERC (0xffff<<16) //31:16
2271 +#define RGS_SSUSB_LFPS (0xf<<12) //15:12
2272 +#define RGS_SSUSB_TRAINDEC (0x7<<8) //10:8
2273 +#define RGS_SSUSB_SCP_PAT (0xff<<0) //7:0
2274 +
2275 +//U3D_PHYD_MON1
2276 +#define RGS_SSUSB_RX_FL_OUT (0xffff<<0) //15:0
2277 +
2278 +//U3D_PHYD_MON2
2279 +#define RGS_SSUSB_T2RLB_ERRCNT (0xffff<<16) //31:16
2280 +#define RGS_SSUSB_RETRACK (0xf<<12) //15:12
2281 +#define RGS_SSUSB_RXPLL_LOCK (0x1<<10) //10:10
2282 +#define RGS_SSUSB_CDR_VCOCAL_CPLT_D (0x1<<9) //9:9
2283 +#define RGS_SSUSB_PLL_VCOCAL_CPLT_D (0x1<<8) //8:8
2284 +#define RGS_SSUSB_PDNCTL (0xff<<0) //7:0
2285 +
2286 +//U3D_PHYD_MON3
2287 +#define RGS_SSUSB_TSEQ_ERRCNT (0xffff<<16) //31:16
2288 +#define RGS_SSUSB_PRBS_ERRCNT (0xffff<<0) //15:0
2289 +
2290 +//U3D_PHYD_MON4
2291 +#define RGS_SSUSB_RX_LSLOCK_CNT (0xf<<24) //27:24
2292 +#define RGS_SSUSB_SCP_DETCNT (0xff<<16) //23:16
2293 +#define RGS_SSUSB_TSEQ_DETCNT (0xffff<<0) //15:0
2294 +
2295 +//U3D_PHYD_MON5
2296 +#define RGS_SSUSB_EBUFMSG (0xffff<<16) //31:16
2297 +#define RGS_SSUSB_BERT_LOCK (0x1<<15) //15:15
2298 +#define RGS_SSUSB_SCP_DET (0x1<<14) //14:14
2299 +#define RGS_SSUSB_TSEQ_DET (0x1<<13) //13:13
2300 +#define RGS_SSUSB_EBUF_UDF (0x1<<12) //12:12
2301 +#define RGS_SSUSB_EBUF_OVF (0x1<<11) //11:11
2302 +#define RGS_SSUSB_PRBS_PASSTH (0x1<<10) //10:10
2303 +#define RGS_SSUSB_PRBS_PASS (0x1<<9) //9:9
2304 +#define RGS_SSUSB_PRBS_LOCK (0x1<<8) //8:8
2305 +#define RGS_SSUSB_T2RLB_ERR (0x1<<6) //6:6
2306 +#define RGS_SSUSB_T2RLB_PASSTH (0x1<<5) //5:5
2307 +#define RGS_SSUSB_T2RLB_PASS (0x1<<4) //4:4
2308 +#define RGS_SSUSB_T2RLB_LOCK (0x1<<3) //3:3
2309 +#define RGS_SSUSB_RX_IMPCAL_DONE (0x1<<2) //2:2
2310 +#define RGS_SSUSB_TX_IMPCAL_DONE (0x1<<1) //1:1
2311 +#define RGS_SSUSB_RXDETECTED (0x1<<0) //0:0
2312 +
2313 +//U3D_PHYD_MON6
2314 +#define RGS_SSUSB_SIGCAL_DONE (0x1<<30) //30:30
2315 +#define RGS_SSUSB_SIGCAL_CAL_OUT (0x1<<29) //29:29
2316 +#define RGS_SSUSB_SIGCAL_OFFSET (0x1f<<24) //28:24
2317 +#define RGS_SSUSB_RX_IMP_SEL (0x1f<<16) //20:16
2318 +#define RGS_SSUSB_TX_IMP_SEL (0x1f<<8) //12:8
2319 +#define RGS_SSUSB_TFIFO_MSG (0xf<<4) //7:4
2320 +#define RGS_SSUSB_RFIFO_MSG (0xf<<0) //3:0
2321 +
2322 +//U3D_PHYD_MON7
2323 +#define RGS_SSUSB_FT_OUT (0xff<<8) //15:8
2324 +#define RGS_SSUSB_PRB_OUT (0xff<<0) //7:0
2325 +
2326 +//U3D_PHYA_RX_MON0
2327 +#define RGS_SSUSB_EQ_DCLEQ (0xf<<24) //27:24
2328 +#define RGS_SSUSB_EQ_DCD0H (0x7f<<16) //22:16
2329 +#define RGS_SSUSB_EQ_DCD0L (0x7f<<8) //14:8
2330 +#define RGS_SSUSB_EQ_DCD1H (0x7f<<0) //6:0
2331 +
2332 +//U3D_PHYA_RX_MON1
2333 +#define RGS_SSUSB_EQ_DCD1L (0x7f<<24) //30:24
2334 +#define RGS_SSUSB_EQ_DCE0 (0x7f<<16) //22:16
2335 +#define RGS_SSUSB_EQ_DCE1 (0x7f<<8) //14:8
2336 +#define RGS_SSUSB_EQ_DCHHL (0x7f<<0) //6:0
2337 +
2338 +//U3D_PHYA_RX_MON2
2339 +#define RGS_SSUSB_EQ_LEQ_STOP (0x1<<31) //31:31
2340 +#define RGS_SSUSB_EQ_DCLHL (0x7f<<24) //30:24
2341 +#define RGS_SSUSB_EQ_STATUS (0xff<<16) //23:16
2342 +#define RGS_SSUSB_EQ_DCEYE0 (0x7f<<8) //14:8
2343 +#define RGS_SSUSB_EQ_DCEYE1 (0x7f<<0) //6:0
2344 +
2345 +//U3D_PHYA_RX_MON3
2346 +#define RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_0 (0xfffff<<0) //19:0
2347 +
2348 +//U3D_PHYA_RX_MON4
2349 +#define RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_1 (0xfffff<<0) //19:0
2350 +
2351 +//U3D_PHYA_RX_MON5
2352 +#define RGS_SSUSB_EQ_DCLEQOS (0x1f<<8) //12:8
2353 +#define RGS_SSUSB_EQ_EYE_CNT_RDY (0x1<<7) //7:7
2354 +#define RGS_SSUSB_EQ_PILPO (0x7f<<0) //6:0
2355 +
2356 +//U3D_PHYD_CPPAT2
2357 +#define RG_SSUSB_CPPAT_OUT_H_TMP2 (0xf<<16) //19:16
2358 +#define RG_SSUSB_CPPAT_OUT_H_TMP1 (0xff<<8) //15:8
2359 +#define RG_SSUSB_CPPAT_OUT_H_TMP0 (0xff<<0) //7:0
2360 +
2361 +//U3D_EQ_EYE3
2362 +#define RG_SSUSB_EQ_LEQ_SHIFT (0x7<<24) //26:24
2363 +#define RG_SSUSB_EQ_EYE_CNT (0xfffff<<0) //19:0
2364 +
2365 +//U3D_KBAND_OUT
2366 +#define RGS_SSUSB_CDR_BAND_5G (0xff<<24) //31:24
2367 +#define RGS_SSUSB_CDR_BAND_2P5G (0xff<<16) //23:16
2368 +#define RGS_SSUSB_PLL_BAND_5G (0xff<<8) //15:8
2369 +#define RGS_SSUSB_PLL_BAND_2P5G (0xff<<0) //7:0
2370 +
2371 +//U3D_KBAND_OUT1
2372 +#define RGS_SSUSB_CDR_VCOCAL_FAIL (0x1<<24) //24:24
2373 +#define RGS_SSUSB_CDR_VCOCAL_STATE (0xff<<16) //23:16
2374 +#define RGS_SSUSB_PLL_VCOCAL_FAIL (0x1<<8) //8:8
2375 +#define RGS_SSUSB_PLL_VCOCAL_STATE (0xff<<0) //7:0
2376 +
2377 +
2378 +/* OFFSET */
2379 +
2380 +//U3D_PHYD_MIX0
2381 +#define RG_SSUSB_P_P3_TX_NG_OFST (31)
2382 +#define RG_SSUSB_TSEQ_EN_OFST (30)
2383 +#define RG_SSUSB_TSEQ_POLEN_OFST (29)
2384 +#define RG_SSUSB_TSEQ_POL_OFST (28)
2385 +#define RG_SSUSB_P_P3_PCLK_NG_OFST (27)
2386 +#define RG_SSUSB_TSEQ_TH_OFST (24)
2387 +#define RG_SSUSB_PRBS_BERTH_OFST (16)
2388 +#define RG_SSUSB_DISABLE_PHY_U2_ON_OFST (15)
2389 +#define RG_SSUSB_DISABLE_PHY_U2_OFF_OFST (14)
2390 +#define RG_SSUSB_PRBS_EN_OFST (13)
2391 +#define RG_SSUSB_BPSLOCK_OFST (12)
2392 +#define RG_SSUSB_RTCOMCNT_OFST (8)
2393 +#define RG_SSUSB_COMCNT_OFST (4)
2394 +#define RG_SSUSB_PRBSEL_CALIB_OFST (0)
2395 +
2396 +//U3D_PHYD_MIX1
2397 +#define RG_SSUSB_SLEEP_EN_OFST (31)
2398 +#define RG_SSUSB_PRBSEL_PCS_OFST (28)
2399 +#define RG_SSUSB_TXLFPS_PRD_OFST (24)
2400 +#define RG_SSUSB_P_RX_P0S_CK_OFST (23)
2401 +#define RG_SSUSB_P_TX_P0S_CK_OFST (22)
2402 +#define RG_SSUSB_PDNCTL_OFST (16)
2403 +#define RG_SSUSB_TX_DRV_EN_OFST (15)
2404 +#define RG_SSUSB_TX_DRV_SEL_OFST (14)
2405 +#define RG_SSUSB_TX_DRV_DLY_OFST (8)
2406 +#define RG_SSUSB_BERT_EN_OFST (7)
2407 +#define RG_SSUSB_SCP_TH_OFST (4)
2408 +#define RG_SSUSB_SCP_EN_OFST (3)
2409 +#define RG_SSUSB_RXANSIDEC_TEST_OFST (0)
2410 +
2411 +//U3D_PHYD_LFPS0
2412 +#define RG_SSUSB_LFPS_PWD_OFST (30)
2413 +#define RG_SSUSB_FORCE_LFPS_PWD_OFST (29)
2414 +#define RG_SSUSB_RXLFPS_OVF_OFST (24)
2415 +#define RG_SSUSB_P3_ENTRY_SEL_OFST (23)
2416 +#define RG_SSUSB_P3_ENTRY_OFST (22)
2417 +#define RG_SSUSB_RXLFPS_CDRSEL_OFST (20)
2418 +#define RG_SSUSB_RXLFPS_CDRTH_OFST (16)
2419 +#define RG_SSUSB_LOCK5G_BLOCK_OFST (15)
2420 +#define RG_SSUSB_TFIFO_EXT_D_SEL_OFST (14)
2421 +#define RG_SSUSB_TFIFO_NO_EXTEND_OFST (13)
2422 +#define RG_SSUSB_RXLFPS_LOB_OFST (8)
2423 +#define RG_SSUSB_TXLFPS_EN_OFST (7)
2424 +#define RG_SSUSB_TXLFPS_SEL_OFST (6)
2425 +#define RG_SSUSB_RXLFPS_CDRLOCK_OFST (5)
2426 +#define RG_SSUSB_RXLFPS_UPB_OFST (0)
2427 +
2428 +//U3D_PHYD_LFPS1
2429 +#define RG_SSUSB_RX_IMP_BIAS_OFST (28)
2430 +#define RG_SSUSB_TX_IMP_BIAS_OFST (24)
2431 +#define RG_SSUSB_FWAKE_TH_OFST (16)
2432 +#define RG_SSUSB_RXLFPS_UDF_OFST (8)
2433 +#define RG_SSUSB_RXLFPS_P0IDLETH_OFST (0)
2434 +
2435 +//U3D_PHYD_IMPCAL0
2436 +#define RG_SSUSB_FORCE_TX_IMPSEL_OFST (31)
2437 +#define RG_SSUSB_TX_IMPCAL_EN_OFST (30)
2438 +#define RG_SSUSB_FORCE_TX_IMPCAL_EN_OFST (29)
2439 +#define RG_SSUSB_TX_IMPSEL_OFST (24)
2440 +#define RG_SSUSB_TX_IMPCAL_CALCYC_OFST (16)
2441 +#define RG_SSUSB_TX_IMPCAL_STBCYC_OFST (10)
2442 +#define RG_SSUSB_TX_IMPCAL_CYCCNT_OFST (0)
2443 +
2444 +//U3D_PHYD_IMPCAL1
2445 +#define RG_SSUSB_FORCE_RX_IMPSEL_OFST (31)
2446 +#define RG_SSUSB_RX_IMPCAL_EN_OFST (30)
2447 +#define RG_SSUSB_FORCE_RX_IMPCAL_EN_OFST (29)
2448 +#define RG_SSUSB_RX_IMPSEL_OFST (24)
2449 +#define RG_SSUSB_RX_IMPCAL_CALCYC_OFST (16)
2450 +#define RG_SSUSB_RX_IMPCAL_STBCYC_OFST (10)
2451 +#define RG_SSUSB_RX_IMPCAL_CYCCNT_OFST (0)
2452 +
2453 +//U3D_PHYD_TXPLL0
2454 +#define RG_SSUSB_TXPLL_DDSEN_CYC_OFST (27)
2455 +#define RG_SSUSB_TXPLL_ON_OFST (26)
2456 +#define RG_SSUSB_FORCE_TXPLLON_OFST (25)
2457 +#define RG_SSUSB_TXPLL_STBCYC_OFST (16)
2458 +#define RG_SSUSB_TXPLL_NCPOCHG_CYC_OFST (12)
2459 +#define RG_SSUSB_TXPLL_NCPOEN_CYC_OFST (10)
2460 +#define RG_SSUSB_TXPLL_DDSRSTB_CYC_OFST (0)
2461 +
2462 +//U3D_PHYD_TXPLL1
2463 +#define RG_SSUSB_PLL_NCPO_EN_OFST (31)
2464 +#define RG_SSUSB_PLL_FIFO_START_MAN_OFST (30)
2465 +#define RG_SSUSB_PLL_NCPO_CHG_OFST (28)
2466 +#define RG_SSUSB_PLL_DDS_RSTB_OFST (27)
2467 +#define RG_SSUSB_PLL_DDS_PWDB_OFST (26)
2468 +#define RG_SSUSB_PLL_DDSEN_OFST (25)
2469 +#define RG_SSUSB_PLL_AUTOK_VCO_OFST (24)
2470 +#define RG_SSUSB_PLL_PWD_OFST (23)
2471 +#define RG_SSUSB_RX_AFE_PWD_OFST (22)
2472 +#define RG_SSUSB_PLL_TCADJ_OFST (16)
2473 +#define RG_SSUSB_FORCE_CDR_TCADJ_OFST (15)
2474 +#define RG_SSUSB_FORCE_CDR_AUTOK_VCO_OFST (14)
2475 +#define RG_SSUSB_FORCE_CDR_PWD_OFST (13)
2476 +#define RG_SSUSB_FORCE_PLL_NCPO_EN_OFST (12)
2477 +#define RG_SSUSB_FORCE_PLL_FIFO_START_MAN_OFST (11)
2478 +#define RG_SSUSB_FORCE_PLL_NCPO_CHG_OFST (9)
2479 +#define RG_SSUSB_FORCE_PLL_DDS_RSTB_OFST (8)
2480 +#define RG_SSUSB_FORCE_PLL_DDS_PWDB_OFST (7)
2481 +#define RG_SSUSB_FORCE_PLL_DDSEN_OFST (6)
2482 +#define RG_SSUSB_FORCE_PLL_TCADJ_OFST (5)
2483 +#define RG_SSUSB_FORCE_PLL_AUTOK_VCO_OFST (4)
2484 +#define RG_SSUSB_FORCE_PLL_PWD_OFST (3)
2485 +#define RG_SSUSB_FLT_1_DISPERR_B_OFST (2)
2486 +
2487 +//U3D_PHYD_TXPLL2
2488 +#define RG_SSUSB_TX_LFPS_EN_OFST (31)
2489 +#define RG_SSUSB_FORCE_TX_LFPS_EN_OFST (30)
2490 +#define RG_SSUSB_TX_LFPS_OFST (29)
2491 +#define RG_SSUSB_FORCE_TX_LFPS_OFST (28)
2492 +#define RG_SSUSB_RXPLL_STB_OFST (27)
2493 +#define RG_SSUSB_TXPLL_STB_OFST (26)
2494 +#define RG_SSUSB_FORCE_RXPLL_STB_OFST (25)
2495 +#define RG_SSUSB_FORCE_TXPLL_STB_OFST (24)
2496 +#define RG_SSUSB_RXPLL_REFCKSEL_OFST (16)
2497 +#define RG_SSUSB_RXPLL_STBMODE_OFST (11)
2498 +#define RG_SSUSB_RXPLL_ON_OFST (10)
2499 +#define RG_SSUSB_FORCE_RXPLLON_OFST (9)
2500 +#define RG_SSUSB_FORCE_RX_AFE_PWD_OFST (8)
2501 +#define RG_SSUSB_CDR_AUTOK_VCO_OFST (7)
2502 +#define RG_SSUSB_CDR_PWD_OFST (6)
2503 +#define RG_SSUSB_CDR_TCADJ_OFST (0)
2504 +
2505 +//U3D_PHYD_FL0
2506 +#define RG_SSUSB_RX_FL_TARGET_OFST (16)
2507 +#define RG_SSUSB_RX_FL_CYCLECNT_OFST (0)
2508 +
2509 +//U3D_PHYD_MIX2
2510 +#define RG_SSUSB_RX_EQ_RST_OFST (31)
2511 +#define RG_SSUSB_RX_EQ_RST_SEL_OFST (30)
2512 +#define RG_SSUSB_RXVAL_RST_OFST (29)
2513 +#define RG_SSUSB_RXVAL_CNT_OFST (24)
2514 +#define RG_SSUSB_CDROS_EN_OFST (18)
2515 +#define RG_SSUSB_CDR_LCKOP_OFST (16)
2516 +#define RG_SSUSB_RX_FL_LOCKTH_OFST (8)
2517 +#define RG_SSUSB_RX_FL_OFFSET_OFST (0)
2518 +
2519 +//U3D_PHYD_RX0
2520 +#define RG_SSUSB_T2RLB_BERTH_OFST (24)
2521 +#define RG_SSUSB_T2RLB_PAT_OFST (16)
2522 +#define RG_SSUSB_T2RLB_EN_OFST (15)
2523 +#define RG_SSUSB_T2RLB_BPSCRAMB_OFST (14)
2524 +#define RG_SSUSB_T2RLB_SERIAL_OFST (13)
2525 +#define RG_SSUSB_T2RLB_MODE_OFST (11)
2526 +#define RG_SSUSB_RX_SAOSC_EN_OFST (10)
2527 +#define RG_SSUSB_RX_SAOSC_EN_SEL_OFST (9)
2528 +#define RG_SSUSB_RX_DFE_OPTION_OFST (8)
2529 +#define RG_SSUSB_RX_DFE_EN_OFST (7)
2530 +#define RG_SSUSB_RX_DFE_EN_SEL_OFST (6)
2531 +#define RG_SSUSB_RX_EQ_EN_OFST (5)
2532 +#define RG_SSUSB_RX_EQ_EN_SEL_OFST (4)
2533 +#define RG_SSUSB_RX_SAOSC_RST_OFST (3)
2534 +#define RG_SSUSB_RX_SAOSC_RST_SEL_OFST (2)
2535 +#define RG_SSUSB_RX_DFE_RST_OFST (1)
2536 +#define RG_SSUSB_RX_DFE_RST_SEL_OFST (0)
2537 +
2538 +//U3D_PHYD_T2RLB
2539 +#define RG_SSUSB_EQTRAIN_CH_MODE_OFST (28)
2540 +#define RG_SSUSB_PRB_OUT_CPPAT_OFST (27)
2541 +#define RG_SSUSB_BPANSIENC_OFST (26)
2542 +#define RG_SSUSB_VALID_EN_OFST (25)
2543 +#define RG_SSUSB_EBUF_SRST_OFST (24)
2544 +#define RG_SSUSB_K_EMP_OFST (20)
2545 +#define RG_SSUSB_K_FUL_OFST (16)
2546 +#define RG_SSUSB_T2RLB_BDATRST_OFST (12)
2547 +#define RG_SSUSB_P_T2RLB_SKP_EN_OFST (10)
2548 +#define RG_SSUSB_T2RLB_PATMODE_OFST (8)
2549 +#define RG_SSUSB_T2RLB_TSEQCNT_OFST (0)
2550 +
2551 +//U3D_PHYD_CPPAT
2552 +#define RG_SSUSB_CPPAT_PROGRAM_EN_OFST (24)
2553 +#define RG_SSUSB_CPPAT_TOZ_OFST (21)
2554 +#define RG_SSUSB_CPPAT_PRBS_EN_OFST (20)
2555 +#define RG_SSUSB_CPPAT_OUT_TMP2_OFST (16)
2556 +#define RG_SSUSB_CPPAT_OUT_TMP1_OFST (8)
2557 +#define RG_SSUSB_CPPAT_OUT_TMP0_OFST (0)
2558 +
2559 +//U3D_PHYD_MIX3
2560 +#define RG_SSUSB_CDR_TCADJ_MINUS_OFST (31)
2561 +#define RG_SSUSB_P_CDROS_EN_OFST (30)
2562 +#define RG_SSUSB_P_P2_TX_DRV_DIS_OFST (28)
2563 +#define RG_SSUSB_CDR_TCADJ_OFFSET_OFST (24)
2564 +#define RG_SSUSB_PLL_TCADJ_MINUS_OFST (23)
2565 +#define RG_SSUSB_FORCE_PLL_BIAS_LPF_EN_OFST (20)
2566 +#define RG_SSUSB_PLL_BIAS_LPF_EN_OFST (19)
2567 +#define RG_SSUSB_PLL_TCADJ_OFFSET_OFST (16)
2568 +#define RG_SSUSB_FORCE_PLL_SSCEN_OFST (15)
2569 +#define RG_SSUSB_PLL_SSCEN_OFST (14)
2570 +#define RG_SSUSB_FORCE_CDR_PI_PWD_OFST (13)
2571 +#define RG_SSUSB_CDR_PI_PWD_OFST (12)
2572 +#define RG_SSUSB_CDR_PI_MODE_OFST (11)
2573 +#define RG_SSUSB_TXPLL_SSCEN_CYC_OFST (0)
2574 +
2575 +//U3D_PHYD_EBUFCTL
2576 +#define RG_SSUSB_EBUFCTL_OFST (0)
2577 +
2578 +//U3D_PHYD_PIPE0
2579 +#define RG_SSUSB_RXTERMINATION_OFST (30)
2580 +#define RG_SSUSB_RXEQTRAINING_OFST (29)
2581 +#define RG_SSUSB_RXPOLARITY_OFST (28)
2582 +#define RG_SSUSB_TXDEEMPH_OFST (26)
2583 +#define RG_SSUSB_POWERDOWN_OFST (24)
2584 +#define RG_SSUSB_TXONESZEROS_OFST (23)
2585 +#define RG_SSUSB_TXELECIDLE_OFST (22)
2586 +#define RG_SSUSB_TXDETECTRX_OFST (21)
2587 +#define RG_SSUSB_PIPE_SEL_OFST (20)
2588 +#define RG_SSUSB_TXDATAK_OFST (16)
2589 +#define RG_SSUSB_CDR_STABLE_SEL_OFST (15)
2590 +#define RG_SSUSB_CDR_STABLE_OFST (14)
2591 +#define RG_SSUSB_CDR_RSTB_SEL_OFST (13)
2592 +#define RG_SSUSB_CDR_RSTB_OFST (12)
2593 +#define RG_SSUSB_P_ERROR_SEL_OFST (4)
2594 +#define RG_SSUSB_TXMARGIN_OFST (1)
2595 +#define RG_SSUSB_TXCOMPLIANCE_OFST (0)
2596 +
2597 +//U3D_PHYD_PIPE1
2598 +#define RG_SSUSB_TXDATA_OFST (0)
2599 +
2600 +//U3D_PHYD_MIX4
2601 +#define RG_SSUSB_CDROS_CNT_OFST (24)
2602 +#define RG_SSUSB_T2RLB_BER_EN_OFST (16)
2603 +#define RG_SSUSB_T2RLB_BER_RATE_OFST (0)
2604 +
2605 +//U3D_PHYD_CKGEN0
2606 +#define RG_SSUSB_RFIFO_IMPLAT_OFST (27)
2607 +#define RG_SSUSB_TFIFO_PSEL_OFST (24)
2608 +#define RG_SSUSB_CKGEN_PSEL_OFST (8)
2609 +#define RG_SSUSB_RXCK_INV_OFST (0)
2610 +
2611 +//U3D_PHYD_MIX5
2612 +#define RG_SSUSB_PRB_SEL_OFST (16)
2613 +#define RG_SSUSB_RXPLL_STBCYC_OFST (0)
2614 +
2615 +//U3D_PHYD_RESERVED
2616 +#define RG_SSUSB_PHYD_RESERVE_OFST (0)
2617 +//#define RG_SSUSB_RX_SIGDET_SEL_OFST (11)
2618 +//#define RG_SSUSB_RX_SIGDET_EN_OFST (12)
2619 +//#define RG_SSUSB_RX_PI_CAL_MANUAL_SEL_OFST (9)
2620 +//#define RG_SSUSB_RX_PI_CAL_MANUAL_EN_OFST (10)
2621 +
2622 +//U3D_PHYD_CDR0
2623 +#define RG_SSUSB_CDR_BIC_LTR_OFST (28)
2624 +#define RG_SSUSB_CDR_BIC_LTD0_OFST (24)
2625 +#define RG_SSUSB_CDR_BC_LTD1_OFST (16)
2626 +#define RG_SSUSB_CDR_BC_LTR_OFST (8)
2627 +#define RG_SSUSB_CDR_BC_LTD0_OFST (0)
2628 +
2629 +//U3D_PHYD_CDR1
2630 +#define RG_SSUSB_CDR_BIR_LTD1_OFST (24)
2631 +#define RG_SSUSB_CDR_BIR_LTR_OFST (16)
2632 +#define RG_SSUSB_CDR_BIR_LTD0_OFST (8)
2633 +#define RG_SSUSB_CDR_BW_SEL_OFST (6)
2634 +#define RG_SSUSB_CDR_BIC_LTD1_OFST (0)
2635 +
2636 +//U3D_PHYD_PLL_0
2637 +#define RG_SSUSB_FORCE_CDR_BAND_5G_OFST (28)
2638 +#define RG_SSUSB_FORCE_CDR_BAND_2P5G_OFST (27)
2639 +#define RG_SSUSB_FORCE_PLL_BAND_5G_OFST (26)
2640 +#define RG_SSUSB_FORCE_PLL_BAND_2P5G_OFST (25)
2641 +#define RG_SSUSB_P_EQ_T_SEL_OFST (15)
2642 +#define RG_SSUSB_PLL_ISO_EN_CYC_OFST (5)
2643 +#define RG_SSUSB_PLLBAND_RECAL_OFST (4)
2644 +#define RG_SSUSB_PLL_DDS_ISO_EN_OFST (3)
2645 +#define RG_SSUSB_FORCE_PLL_DDS_ISO_EN_OFST (2)
2646 +#define RG_SSUSB_PLL_DDS_PWR_ON_OFST (1)
2647 +#define RG_SSUSB_FORCE_PLL_DDS_PWR_ON_OFST (0)
2648 +
2649 +//U3D_PHYD_PLL_1
2650 +#define RG_SSUSB_CDR_BAND_5G_OFST (24)
2651 +#define RG_SSUSB_CDR_BAND_2P5G_OFST (16)
2652 +#define RG_SSUSB_PLL_BAND_5G_OFST (8)
2653 +#define RG_SSUSB_PLL_BAND_2P5G_OFST (0)
2654 +
2655 +//U3D_PHYD_BCN_DET_1
2656 +#define RG_SSUSB_P_BCN_OBS_PRD_OFST (16)
2657 +#define RG_SSUSB_U_BCN_OBS_PRD_OFST (0)
2658 +
2659 +//U3D_PHYD_BCN_DET_2
2660 +#define RG_SSUSB_P_BCN_OBS_SEL_OFST (16)
2661 +#define RG_SSUSB_BCN_DET_DIS_OFST (12)
2662 +#define RG_SSUSB_U_BCN_OBS_SEL_OFST (0)
2663 +
2664 +//U3D_EQ0
2665 +#define RG_SSUSB_EQ_DLHL_LFI_OFST (24)
2666 +#define RG_SSUSB_EQ_DHHL_LFI_OFST (16)
2667 +#define RG_SSUSB_EQ_DD0HOS_LFI_OFST (8)
2668 +#define RG_SSUSB_EQ_DD0LOS_LFI_OFST (0)
2669 +
2670 +//U3D_EQ1
2671 +#define RG_SSUSB_EQ_DD1HOS_LFI_OFST (24)
2672 +#define RG_SSUSB_EQ_DD1LOS_LFI_OFST (16)
2673 +#define RG_SSUSB_EQ_DE0OS_LFI_OFST (8)
2674 +#define RG_SSUSB_EQ_DE1OS_LFI_OFST (0)
2675 +
2676 +//U3D_EQ2
2677 +#define RG_SSUSB_EQ_DLHLOS_LFI_OFST (24)
2678 +#define RG_SSUSB_EQ_DHHLOS_LFI_OFST (16)
2679 +#define RG_SSUSB_EQ_STOPTIME_OFST (14)
2680 +#define RG_SSUSB_EQ_DHHL_LF_SEL_OFST (11)
2681 +#define RG_SSUSB_EQ_DSAOS_LF_SEL_OFST (8)
2682 +#define RG_SSUSB_EQ_STARTTIME_OFST (6)
2683 +#define RG_SSUSB_EQ_DLEQ_LF_SEL_OFST (3)
2684 +#define RG_SSUSB_EQ_DLHL_LF_SEL_OFST (0)
2685 +
2686 +//U3D_EQ3
2687 +#define RG_SSUSB_EQ_DLEQ_LFI_GEN2_OFST (28)
2688 +#define RG_SSUSB_EQ_DLEQ_LFI_GEN1_OFST (24)
2689 +#define RG_SSUSB_EQ_DEYE0OS_LFI_OFST (16)
2690 +#define RG_SSUSB_EQ_DEYE1OS_LFI_OFST (8)
2691 +#define RG_SSUSB_EQ_TRI_DET_EN_OFST (7)
2692 +#define RG_SSUSB_EQ_TRI_DET_TH_OFST (0)
2693 +
2694 +//U3D_EQ_EYE0
2695 +#define RG_SSUSB_EQ_EYE_XOFFSET_OFST (25)
2696 +#define RG_SSUSB_EQ_EYE_MON_EN_OFST (24)
2697 +#define RG_SSUSB_EQ_EYE0_Y_OFST (16)
2698 +#define RG_SSUSB_EQ_EYE1_Y_OFST (8)
2699 +#define RG_SSUSB_EQ_PILPO_ROUT_OFST (7)
2700 +#define RG_SSUSB_EQ_PI_KPGAIN_OFST (4)
2701 +#define RG_SSUSB_EQ_EYE_CNT_EN_OFST (3)
2702 +
2703 +//U3D_EQ_EYE1
2704 +#define RG_SSUSB_EQ_SIGDET_OFST (24)
2705 +#define RG_SSUSB_EQ_EYE_MASK_OFST (7)
2706 +
2707 +//U3D_EQ_EYE2
2708 +#define RG_SSUSB_EQ_RX500M_CK_SEL_OFST (31)
2709 +#define RG_SSUSB_EQ_SD_CNT1_OFST (24)
2710 +#define RG_SSUSB_EQ_ISIFLAG_SEL_OFST (22)
2711 +#define RG_SSUSB_EQ_SD_CNT0_OFST (16)
2712 +
2713 +//U3D_EQ_DFE0
2714 +#define RG_SSUSB_EQ_LEQMAX_OFST (28)
2715 +#define RG_SSUSB_EQ_DFEX_EN_OFST (27)
2716 +#define RG_SSUSB_EQ_DFEX_LF_SEL_OFST (24)
2717 +#define RG_SSUSB_EQ_CHK_EYE_H_OFST (23)
2718 +#define RG_SSUSB_EQ_PIEYE_INI_OFST (16)
2719 +#define RG_SSUSB_EQ_PI90_INI_OFST (8)
2720 +#define RG_SSUSB_EQ_PI0_INI_OFST (0)
2721 +
2722 +//U3D_EQ_DFE1
2723 +#define RG_SSUSB_EQ_REV_OFST (16)
2724 +#define RG_SSUSB_EQ_DFEYEN_DUR_OFST (12)
2725 +#define RG_SSUSB_EQ_DFEXEN_DUR_OFST (8)
2726 +#define RG_SSUSB_EQ_DFEX_RST_OFST (7)
2727 +#define RG_SSUSB_EQ_GATED_RXD_B_OFST (6)
2728 +#define RG_SSUSB_EQ_PI90CK_SEL_OFST (4)
2729 +#define RG_SSUSB_EQ_DFEX_DIS_OFST (2)
2730 +#define RG_SSUSB_EQ_DFEYEN_STOP_DIS_OFST (1)
2731 +#define RG_SSUSB_EQ_DFEXEN_SEL_OFST (0)
2732 +
2733 +//U3D_EQ_DFE2
2734 +#define RG_SSUSB_EQ_MON_SEL_OFST (24)
2735 +#define RG_SSUSB_EQ_LEQOSC_DLYCNT_OFST (16)
2736 +#define RG_SSUSB_EQ_DLEQOS_LFI_OFST (8)
2737 +#define RG_SSUSB_EQ_LEQ_STOP_TO_OFST (0)
2738 +
2739 +//U3D_EQ_DFE3
2740 +#define RG_SSUSB_EQ_RESERVED_OFST (0)
2741 +
2742 +//U3D_PHYD_MON0
2743 +#define RGS_SSUSB_BERT_BERC_OFST (16)
2744 +#define RGS_SSUSB_LFPS_OFST (12)
2745 +#define RGS_SSUSB_TRAINDEC_OFST (8)
2746 +#define RGS_SSUSB_SCP_PAT_OFST (0)
2747 +
2748 +//U3D_PHYD_MON1
2749 +#define RGS_SSUSB_RX_FL_OUT_OFST (0)
2750 +
2751 +//U3D_PHYD_MON2
2752 +#define RGS_SSUSB_T2RLB_ERRCNT_OFST (16)
2753 +#define RGS_SSUSB_RETRACK_OFST (12)
2754 +#define RGS_SSUSB_RXPLL_LOCK_OFST (10)
2755 +#define RGS_SSUSB_CDR_VCOCAL_CPLT_D_OFST (9)
2756 +#define RGS_SSUSB_PLL_VCOCAL_CPLT_D_OFST (8)
2757 +#define RGS_SSUSB_PDNCTL_OFST (0)
2758 +
2759 +//U3D_PHYD_MON3
2760 +#define RGS_SSUSB_TSEQ_ERRCNT_OFST (16)
2761 +#define RGS_SSUSB_PRBS_ERRCNT_OFST (0)
2762 +
2763 +//U3D_PHYD_MON4
2764 +#define RGS_SSUSB_RX_LSLOCK_CNT_OFST (24)
2765 +#define RGS_SSUSB_SCP_DETCNT_OFST (16)
2766 +#define RGS_SSUSB_TSEQ_DETCNT_OFST (0)
2767 +
2768 +//U3D_PHYD_MON5
2769 +#define RGS_SSUSB_EBUFMSG_OFST (16)
2770 +#define RGS_SSUSB_BERT_LOCK_OFST (15)
2771 +#define RGS_SSUSB_SCP_DET_OFST (14)
2772 +#define RGS_SSUSB_TSEQ_DET_OFST (13)
2773 +#define RGS_SSUSB_EBUF_UDF_OFST (12)
2774 +#define RGS_SSUSB_EBUF_OVF_OFST (11)
2775 +#define RGS_SSUSB_PRBS_PASSTH_OFST (10)
2776 +#define RGS_SSUSB_PRBS_PASS_OFST (9)
2777 +#define RGS_SSUSB_PRBS_LOCK_OFST (8)
2778 +#define RGS_SSUSB_T2RLB_ERR_OFST (6)
2779 +#define RGS_SSUSB_T2RLB_PASSTH_OFST (5)
2780 +#define RGS_SSUSB_T2RLB_PASS_OFST (4)
2781 +#define RGS_SSUSB_T2RLB_LOCK_OFST (3)
2782 +#define RGS_SSUSB_RX_IMPCAL_DONE_OFST (2)
2783 +#define RGS_SSUSB_TX_IMPCAL_DONE_OFST (1)
2784 +#define RGS_SSUSB_RXDETECTED_OFST (0)
2785 +
2786 +//U3D_PHYD_MON6
2787 +#define RGS_SSUSB_SIGCAL_DONE_OFST (30)
2788 +#define RGS_SSUSB_SIGCAL_CAL_OUT_OFST (29)
2789 +#define RGS_SSUSB_SIGCAL_OFFSET_OFST (24)
2790 +#define RGS_SSUSB_RX_IMP_SEL_OFST (16)
2791 +#define RGS_SSUSB_TX_IMP_SEL_OFST (8)
2792 +#define RGS_SSUSB_TFIFO_MSG_OFST (4)
2793 +#define RGS_SSUSB_RFIFO_MSG_OFST (0)
2794 +
2795 +//U3D_PHYD_MON7
2796 +#define RGS_SSUSB_FT_OUT_OFST (8)
2797 +#define RGS_SSUSB_PRB_OUT_OFST (0)
2798 +
2799 +//U3D_PHYA_RX_MON0
2800 +#define RGS_SSUSB_EQ_DCLEQ_OFST (24)
2801 +#define RGS_SSUSB_EQ_DCD0H_OFST (16)
2802 +#define RGS_SSUSB_EQ_DCD0L_OFST (8)
2803 +#define RGS_SSUSB_EQ_DCD1H_OFST (0)
2804 +
2805 +//U3D_PHYA_RX_MON1
2806 +#define RGS_SSUSB_EQ_DCD1L_OFST (24)
2807 +#define RGS_SSUSB_EQ_DCE0_OFST (16)
2808 +#define RGS_SSUSB_EQ_DCE1_OFST (8)
2809 +#define RGS_SSUSB_EQ_DCHHL_OFST (0)
2810 +
2811 +//U3D_PHYA_RX_MON2
2812 +#define RGS_SSUSB_EQ_LEQ_STOP_OFST (31)
2813 +#define RGS_SSUSB_EQ_DCLHL_OFST (24)
2814 +#define RGS_SSUSB_EQ_STATUS_OFST (16)
2815 +#define RGS_SSUSB_EQ_DCEYE0_OFST (8)
2816 +#define RGS_SSUSB_EQ_DCEYE1_OFST (0)
2817 +
2818 +//U3D_PHYA_RX_MON3
2819 +#define RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_0_OFST (0)
2820 +
2821 +//U3D_PHYA_RX_MON4
2822 +#define RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_1_OFST (0)
2823 +
2824 +//U3D_PHYA_RX_MON5
2825 +#define RGS_SSUSB_EQ_DCLEQOS_OFST (8)
2826 +#define RGS_SSUSB_EQ_EYE_CNT_RDY_OFST (7)
2827 +#define RGS_SSUSB_EQ_PILPO_OFST (0)
2828 +
2829 +//U3D_PHYD_CPPAT2
2830 +#define RG_SSUSB_CPPAT_OUT_H_TMP2_OFST (16)
2831 +#define RG_SSUSB_CPPAT_OUT_H_TMP1_OFST (8)
2832 +#define RG_SSUSB_CPPAT_OUT_H_TMP0_OFST (0)
2833 +
2834 +//U3D_EQ_EYE3
2835 +#define RG_SSUSB_EQ_LEQ_SHIFT_OFST (24)
2836 +#define RG_SSUSB_EQ_EYE_CNT_OFST (0)
2837 +
2838 +//U3D_KBAND_OUT
2839 +#define RGS_SSUSB_CDR_BAND_5G_OFST (24)
2840 +#define RGS_SSUSB_CDR_BAND_2P5G_OFST (16)
2841 +#define RGS_SSUSB_PLL_BAND_5G_OFST (8)
2842 +#define RGS_SSUSB_PLL_BAND_2P5G_OFST (0)
2843 +
2844 +//U3D_KBAND_OUT1
2845 +#define RGS_SSUSB_CDR_VCOCAL_FAIL_OFST (24)
2846 +#define RGS_SSUSB_CDR_VCOCAL_STATE_OFST (16)
2847 +#define RGS_SSUSB_PLL_VCOCAL_FAIL_OFST (8)
2848 +#define RGS_SSUSB_PLL_VCOCAL_STATE_OFST (0)
2849 +
2850 +
2851 +///////////////////////////////////////////////////////////////////////////////
2852 +
2853 +struct u3phyd_bank2_reg {
2854 + //0x0
2855 + PHY_LE32 b2_phyd_top1;
2856 + PHY_LE32 b2_phyd_top2;
2857 + PHY_LE32 b2_phyd_top3;
2858 + PHY_LE32 b2_phyd_top4;
2859 + //0x10
2860 + PHY_LE32 b2_phyd_top5;
2861 + PHY_LE32 b2_phyd_top6;
2862 + PHY_LE32 b2_phyd_top7;
2863 + PHY_LE32 b2_phyd_p_sigdet1;
2864 + //0x20
2865 + PHY_LE32 b2_phyd_p_sigdet2;
2866 + PHY_LE32 b2_phyd_p_sigdet_cal1;
2867 + PHY_LE32 b2_phyd_rxdet1;
2868 + PHY_LE32 b2_phyd_rxdet2;
2869 + //0x30
2870 + PHY_LE32 b2_phyd_misc0;
2871 + PHY_LE32 b2_phyd_misc2;
2872 + PHY_LE32 b2_phyd_misc3;
2873 + PHY_LE32 reserve0;
2874 + //0x40
2875 + PHY_LE32 b2_rosc_0;
2876 + PHY_LE32 b2_rosc_1;
2877 + PHY_LE32 b2_rosc_2;
2878 + PHY_LE32 b2_rosc_3;
2879 + //0x50
2880 + PHY_LE32 b2_rosc_4;
2881 + PHY_LE32 b2_rosc_5;
2882 + PHY_LE32 b2_rosc_6;
2883 + PHY_LE32 b2_rosc_7;
2884 + //0x60
2885 + PHY_LE32 b2_rosc_8;
2886 + PHY_LE32 b2_rosc_9;
2887 + PHY_LE32 b2_rosc_a;
2888 + PHY_LE32 reserve1;
2889 + //0x70~0xd0
2890 + PHY_LE32 reserve2[28];
2891 + //0xe0
2892 + PHY_LE32 phyd_version;
2893 + PHY_LE32 phyd_model;
2894 +};
2895 +
2896 +//U3D_B2_PHYD_TOP1
2897 +#define RG_SSUSB_PCIE2_K_EMP (0xf<<28) //31:28
2898 +#define RG_SSUSB_PCIE2_K_FUL (0xf<<24) //27:24
2899 +#define RG_SSUSB_TX_EIDLE_LP_EN (0x1<<17) //17:17
2900 +#define RG_SSUSB_FORCE_TX_EIDLE_LP_EN (0x1<<16) //16:16
2901 +#define RG_SSUSB_SIGDET_EN (0x1<<15) //15:15
2902 +#define RG_SSUSB_FORCE_SIGDET_EN (0x1<<14) //14:14
2903 +#define RG_SSUSB_CLKRX_EN (0x1<<13) //13:13
2904 +#define RG_SSUSB_FORCE_CLKRX_EN (0x1<<12) //12:12
2905 +#define RG_SSUSB_CLKTX_EN (0x1<<11) //11:11
2906 +#define RG_SSUSB_FORCE_CLKTX_EN (0x1<<10) //10:10
2907 +#define RG_SSUSB_CLK_REQ_N_I (0x1<<9) //9:9
2908 +#define RG_SSUSB_FORCE_CLK_REQ_N_I (0x1<<8) //8:8
2909 +#define RG_SSUSB_RATE (0x1<<6) //6:6
2910 +#define RG_SSUSB_FORCE_RATE (0x1<<5) //5:5
2911 +#define RG_SSUSB_PCIE_MODE_SEL (0x1<<4) //4:4
2912 +#define RG_SSUSB_FORCE_PCIE_MODE_SEL (0x1<<3) //3:3
2913 +#define RG_SSUSB_PHY_MODE (0x3<<1) //2:1
2914 +#define RG_SSUSB_FORCE_PHY_MODE (0x1<<0) //0:0
2915 +
2916 +//U3D_B2_PHYD_TOP2
2917 +#define RG_SSUSB_FORCE_IDRV_6DB (0x1<<30) //30:30
2918 +#define RG_SSUSB_IDRV_6DB (0x3f<<24) //29:24
2919 +#define RG_SSUSB_FORCE_IDEM_3P5DB (0x1<<22) //22:22
2920 +#define RG_SSUSB_IDEM_3P5DB (0x3f<<16) //21:16
2921 +#define RG_SSUSB_FORCE_IDRV_3P5DB (0x1<<14) //14:14
2922 +#define RG_SSUSB_IDRV_3P5DB (0x3f<<8) //13:8
2923 +#define RG_SSUSB_FORCE_IDRV_0DB (0x1<<6) //6:6
2924 +#define RG_SSUSB_IDRV_0DB (0x3f<<0) //5:0
2925 +
2926 +//U3D_B2_PHYD_TOP3
2927 +#define RG_SSUSB_TX_BIASI (0x7<<25) //27:25
2928 +#define RG_SSUSB_FORCE_TX_BIASI_EN (0x1<<24) //24:24
2929 +#define RG_SSUSB_TX_BIASI_EN (0x1<<16) //16:16
2930 +#define RG_SSUSB_FORCE_TX_BIASI (0x1<<13) //13:13
2931 +#define RG_SSUSB_FORCE_IDEM_6DB (0x1<<8) //8:8
2932 +#define RG_SSUSB_IDEM_6DB (0x3f<<0) //5:0
2933 +
2934 +//U3D_B2_PHYD_TOP4
2935 +#define RG_SSUSB_G1_CDR_BIC_LTR (0xf<<28) //31:28
2936 +#define RG_SSUSB_G1_CDR_BIC_LTD0 (0xf<<24) //27:24
2937 +#define RG_SSUSB_G1_CDR_BC_LTD1 (0x1f<<16) //20:16
2938 +#define RG_SSUSB_G1_CDR_BC_LTR (0x1f<<8) //12:8
2939 +#define RG_SSUSB_G1_CDR_BC_LTD0 (0x1f<<0) //4:0
2940 +
2941 +//U3D_B2_PHYD_TOP5
2942 +#define RG_SSUSB_G1_CDR_BIR_LTD1 (0x1f<<24) //28:24
2943 +#define RG_SSUSB_G1_CDR_BIR_LTR (0x1f<<16) //20:16
2944 +#define RG_SSUSB_G1_CDR_BIR_LTD0 (0x1f<<8) //12:8
2945 +#define RG_SSUSB_G1_CDR_BIC_LTD1 (0xf<<0) //3:0
2946 +
2947 +//U3D_B2_PHYD_TOP6
2948 +#define RG_SSUSB_G2_CDR_BIC_LTR (0xf<<28) //31:28
2949 +#define RG_SSUSB_G2_CDR_BIC_LTD0 (0xf<<24) //27:24
2950 +#define RG_SSUSB_G2_CDR_BC_LTD1 (0x1f<<16) //20:16
2951 +#define RG_SSUSB_G2_CDR_BC_LTR (0x1f<<8) //12:8
2952 +#define RG_SSUSB_G2_CDR_BC_LTD0 (0x1f<<0) //4:0
2953 +
2954 +//U3D_B2_PHYD_TOP7
2955 +#define RG_SSUSB_G2_CDR_BIR_LTD1 (0x1f<<24) //28:24
2956 +#define RG_SSUSB_G2_CDR_BIR_LTR (0x1f<<16) //20:16
2957 +#define RG_SSUSB_G2_CDR_BIR_LTD0 (0x1f<<8) //12:8
2958 +#define RG_SSUSB_G2_CDR_BIC_LTD1 (0xf<<0) //3:0
2959 +
2960 +//U3D_B2_PHYD_P_SIGDET1
2961 +#define RG_SSUSB_P_SIGDET_FLT_DIS (0x1<<31) //31:31
2962 +#define RG_SSUSB_P_SIGDET_FLT_G2_DEAST_SEL (0x7f<<24) //30:24
2963 +#define RG_SSUSB_P_SIGDET_FLT_G1_DEAST_SEL (0x7f<<16) //22:16
2964 +#define RG_SSUSB_P_SIGDET_FLT_P2_AST_SEL (0x7f<<8) //14:8
2965 +#define RG_SSUSB_P_SIGDET_FLT_PX_AST_SEL (0x7f<<0) //6:0
2966 +
2967 +//U3D_B2_PHYD_P_SIGDET2
2968 +#define RG_SSUSB_P_SIGDET_RX_VAL_S (0x1<<29) //29:29
2969 +#define RG_SSUSB_P_SIGDET_L0S_DEAS_SEL (0x1<<28) //28:28
2970 +#define RG_SSUSB_P_SIGDET_L0_EXIT_S (0x1<<27) //27:27
2971 +#define RG_SSUSB_P_SIGDET_L0S_EXIT_T_S (0x3<<25) //26:25
2972 +#define RG_SSUSB_P_SIGDET_L0S_EXIT_S (0x1<<24) //24:24
2973 +#define RG_SSUSB_P_SIGDET_L0S_ENTRY_S (0x1<<16) //16:16
2974 +#define RG_SSUSB_P_SIGDET_PRB_SEL (0x1<<10) //10:10
2975 +#define RG_SSUSB_P_SIGDET_BK_SIG_T (0x3<<8) //9:8
2976 +#define RG_SSUSB_P_SIGDET_P2_RXLFPS (0x1<<6) //6:6
2977 +#define RG_SSUSB_P_SIGDET_NON_BK_AD (0x1<<5) //5:5
2978 +#define RG_SSUSB_P_SIGDET_BK_B_RXEQ (0x1<<4) //4:4
2979 +#define RG_SSUSB_P_SIGDET_G2_KO_SEL (0x3<<2) //3:2
2980 +#define RG_SSUSB_P_SIGDET_G1_KO_SEL (0x3<<0) //1:0
2981 +
2982 +//U3D_B2_PHYD_P_SIGDET_CAL1
2983 +#define RG_SSUSB_P_SIGDET_CAL_OFFSET (0x1f<<24) //28:24
2984 +#define RG_SSUSB_P_FORCE_SIGDET_CAL_OFFSET (0x1<<16) //16:16
2985 +#define RG_SSUSB_P_SIGDET_CAL_EN (0x1<<8) //8:8
2986 +#define RG_SSUSB_P_FORCE_SIGDET_CAL_EN (0x1<<3) //3:3
2987 +#define RG_SSUSB_P_SIGDET_FLT_EN (0x1<<2) //2:2
2988 +#define RG_SSUSB_P_SIGDET_SAMPLE_PRD (0x1<<1) //1:1
2989 +#define RG_SSUSB_P_SIGDET_REK (0x1<<0) //0:0
2990 +
2991 +//U3D_B2_PHYD_RXDET1
2992 +#define RG_SSUSB_RXDET_PRB_SEL (0x1<<31) //31:31
2993 +#define RG_SSUSB_FORCE_CMDET (0x1<<30) //30:30
2994 +#define RG_SSUSB_RXDET_EN (0x1<<29) //29:29
2995 +#define RG_SSUSB_FORCE_RXDET_EN (0x1<<28) //28:28
2996 +#define RG_SSUSB_RXDET_K_TWICE (0x1<<27) //27:27
2997 +#define RG_SSUSB_RXDET_STB3_SET (0x1ff<<18) //26:18
2998 +#define RG_SSUSB_RXDET_STB2_SET (0x1ff<<9) //17:9
2999 +#define RG_SSUSB_RXDET_STB1_SET (0x1ff<<0) //8:0
3000 +
3001 +//U3D_B2_PHYD_RXDET2
3002 +#define RG_SSUSB_PHYD_TRAINDEC_FORCE_CGEN (0x1<<31) //31:31
3003 +#define RG_SSUSB_PHYD_BERTLB_FORCE_CGEN (0x1<<30) //30:30
3004 +#define RG_SSUSB_PHYD_T2RLB_FORCE_CGEN (0x1<<29) //29:29
3005 +#define RG_SSUSB_PDN_T_SEL (0x3<<18) //19:18
3006 +#define RG_SSUSB_RXDET_STB3_SET_P3 (0x1ff<<9) //17:9
3007 +#define RG_SSUSB_RXDET_STB2_SET_P3 (0x1ff<<0) //8:0
3008 +
3009 +//U3D_B2_PHYD_MISC0
3010 +#define RG_SSUSB_FORCE_PLL_DDS_HF_EN (0x1<<22) //22:22
3011 +#define RG_SSUSB_PLL_DDS_HF_EN_MAN (0x1<<21) //21:21
3012 +#define RG_SSUSB_RXLFPS_ENTXDRV (0x1<<20) //20:20
3013 +#define RG_SSUSB_RX_FL_UNLOCKTH (0xf<<16) //19:16
3014 +#define RG_SSUSB_LFPS_PSEL (0x1<<15) //15:15
3015 +#define RG_SSUSB_RX_SIGDET_EN (0x1<<14) //14:14
3016 +#define RG_SSUSB_RX_SIGDET_EN_SEL (0x1<<13) //13:13
3017 +#define RG_SSUSB_RX_PI_CAL_EN (0x1<<12) //12:12
3018 +#define RG_SSUSB_RX_PI_CAL_EN_SEL (0x1<<11) //11:11
3019 +#define RG_SSUSB_P3_CLS_CK_SEL (0x1<<10) //10:10
3020 +#define RG_SSUSB_T2RLB_PSEL (0x3<<8) //9:8
3021 +#define RG_SSUSB_PPCTL_PSEL (0x7<<5) //7:5
3022 +#define RG_SSUSB_PHYD_TX_DATA_INV (0x1<<4) //4:4
3023 +#define RG_SSUSB_BERTLB_PSEL (0x3<<2) //3:2
3024 +#define RG_SSUSB_RETRACK_DIS (0x1<<1) //1:1
3025 +#define RG_SSUSB_PPERRCNT_CLR (0x1<<0) //0:0
3026 +
3027 +//U3D_B2_PHYD_MISC2
3028 +#define RG_SSUSB_FRC_PLL_DDS_PREDIV2 (0x1<<31) //31:31
3029 +#define RG_SSUSB_FRC_PLL_DDS_IADJ (0xf<<27) //30:27
3030 +#define RG_SSUSB_P_SIGDET_125FILTER (0x1<<26) //26:26
3031 +#define RG_SSUSB_P_SIGDET_RST_FILTER (0x1<<25) //25:25
3032 +#define RG_SSUSB_P_SIGDET_EID_USE_RAW (0x1<<24) //24:24
3033 +#define RG_SSUSB_P_SIGDET_LTD_USE_RAW (0x1<<23) //23:23
3034 +#define RG_SSUSB_EIDLE_BF_RXDET (0x1<<22) //22:22
3035 +#define RG_SSUSB_EIDLE_LP_STBCYC (0x1ff<<13) //21:13
3036 +#define RG_SSUSB_TX_EIDLE_LP_POSTDLY (0x3f<<7) //12:7
3037 +#define RG_SSUSB_TX_EIDLE_LP_PREDLY (0x3f<<1) //6:1
3038 +#define RG_SSUSB_TX_EIDLE_LP_EN_ADV (0x1<<0) //0:0
3039 +
3040 +//U3D_B2_PHYD_MISC3
3041 +#define RGS_SSUSB_DDS_CALIB_C_STATE (0x7<<16) //18:16
3042 +#define RGS_SSUSB_PPERRCNT (0xffff<<0) //15:0
3043 +
3044 +//U3D_B2_ROSC_0
3045 +#define RG_SSUSB_RING_OSC_CNTEND (0x1ff<<23) //31:23
3046 +#define RG_SSUSB_XTAL_OSC_CNTEND (0x7f<<16) //22:16
3047 +#define RG_SSUSB_RING_OSC_EN (0x1<<3) //3:3
3048 +#define RG_SSUSB_RING_OSC_FORCE_EN (0x1<<2) //2:2
3049 +#define RG_SSUSB_FRC_RING_BYPASS_DET (0x1<<1) //1:1
3050 +#define RG_SSUSB_RING_BYPASS_DET (0x1<<0) //0:0
3051 +
3052 +//U3D_B2_ROSC_1
3053 +#define RG_SSUSB_RING_OSC_FRC_P3 (0x1<<20) //20:20
3054 +#define RG_SSUSB_RING_OSC_P3 (0x1<<19) //19:19
3055 +#define RG_SSUSB_RING_OSC_FRC_RECAL (0x3<<17) //18:17
3056 +#define RG_SSUSB_RING_OSC_RECAL (0x1<<16) //16:16
3057 +#define RG_SSUSB_RING_OSC_SEL (0xff<<8) //15:8
3058 +#define RG_SSUSB_RING_OSC_FRC_SEL (0x1<<0) //0:0
3059 +
3060 +//U3D_B2_ROSC_2
3061 +#define RG_SSUSB_RING_DET_STRCYC2 (0xffff<<16) //31:16
3062 +#define RG_SSUSB_RING_DET_STRCYC1 (0xffff<<0) //15:0
3063 +
3064 +//U3D_B2_ROSC_3
3065 +#define RG_SSUSB_RING_DET_DETWIN1 (0xffff<<16) //31:16
3066 +#define RG_SSUSB_RING_DET_STRCYC3 (0xffff<<0) //15:0
3067 +
3068 +//U3D_B2_ROSC_4
3069 +#define RG_SSUSB_RING_DET_DETWIN3 (0xffff<<16) //31:16
3070 +#define RG_SSUSB_RING_DET_DETWIN2 (0xffff<<0) //15:0
3071 +
3072 +//U3D_B2_ROSC_5
3073 +#define RG_SSUSB_RING_DET_LBOND1 (0xffff<<16) //31:16
3074 +#define RG_SSUSB_RING_DET_UBOND1 (0xffff<<0) //15:0
3075 +
3076 +//U3D_B2_ROSC_6
3077 +#define RG_SSUSB_RING_DET_LBOND2 (0xffff<<16) //31:16
3078 +#define RG_SSUSB_RING_DET_UBOND2 (0xffff<<0) //15:0
3079 +
3080 +//U3D_B2_ROSC_7
3081 +#define RG_SSUSB_RING_DET_LBOND3 (0xffff<<16) //31:16
3082 +#define RG_SSUSB_RING_DET_UBOND3 (0xffff<<0) //15:0
3083 +
3084 +//U3D_B2_ROSC_8
3085 +#define RG_SSUSB_RING_RESERVE (0xffff<<16) //31:16
3086 +#define RG_SSUSB_ROSC_PROB_SEL (0xf<<2) //5:2
3087 +#define RG_SSUSB_RING_FREQMETER_EN (0x1<<1) //1:1
3088 +#define RG_SSUSB_RING_DET_BPS_UBOND (0x1<<0) //0:0
3089 +
3090 +//U3D_B2_ROSC_9
3091 +#define RGS_FM_RING_CNT (0xffff<<16) //31:16
3092 +#define RGS_SSUSB_RING_OSC_STATE (0x3<<10) //11:10
3093 +#define RGS_SSUSB_RING_OSC_STABLE (0x1<<9) //9:9
3094 +#define RGS_SSUSB_RING_OSC_CAL_FAIL (0x1<<8) //8:8
3095 +#define RGS_SSUSB_RING_OSC_CAL (0xff<<0) //7:0
3096 +
3097 +//U3D_B2_ROSC_A
3098 +#define RGS_SSUSB_ROSC_PROB_OUT (0xff<<0) //7:0
3099 +
3100 +//U3D_PHYD_VERSION
3101 +#define RGS_SSUSB_PHYD_VERSION (0xffffffff<<0) //31:0
3102 +
3103 +//U3D_PHYD_MODEL
3104 +#define RGS_SSUSB_PHYD_MODEL (0xffffffff<<0) //31:0
3105 +
3106 +
3107 +/* OFFSET */
3108 +
3109 +//U3D_B2_PHYD_TOP1
3110 +#define RG_SSUSB_PCIE2_K_EMP_OFST (28)
3111 +#define RG_SSUSB_PCIE2_K_FUL_OFST (24)
3112 +#define RG_SSUSB_TX_EIDLE_LP_EN_OFST (17)
3113 +#define RG_SSUSB_FORCE_TX_EIDLE_LP_EN_OFST (16)
3114 +#define RG_SSUSB_SIGDET_EN_OFST (15)
3115 +#define RG_SSUSB_FORCE_SIGDET_EN_OFST (14)
3116 +#define RG_SSUSB_CLKRX_EN_OFST (13)
3117 +#define RG_SSUSB_FORCE_CLKRX_EN_OFST (12)
3118 +#define RG_SSUSB_CLKTX_EN_OFST (11)
3119 +#define RG_SSUSB_FORCE_CLKTX_EN_OFST (10)
3120 +#define RG_SSUSB_CLK_REQ_N_I_OFST (9)
3121 +#define RG_SSUSB_FORCE_CLK_REQ_N_I_OFST (8)
3122 +#define RG_SSUSB_RATE_OFST (6)
3123 +#define RG_SSUSB_FORCE_RATE_OFST (5)
3124 +#define RG_SSUSB_PCIE_MODE_SEL_OFST (4)
3125 +#define RG_SSUSB_FORCE_PCIE_MODE_SEL_OFST (3)
3126 +#define RG_SSUSB_PHY_MODE_OFST (1)
3127 +#define RG_SSUSB_FORCE_PHY_MODE_OFST (0)
3128 +
3129 +//U3D_B2_PHYD_TOP2
3130 +#define RG_SSUSB_FORCE_IDRV_6DB_OFST (30)
3131 +#define RG_SSUSB_IDRV_6DB_OFST (24)
3132 +#define RG_SSUSB_FORCE_IDEM_3P5DB_OFST (22)
3133 +#define RG_SSUSB_IDEM_3P5DB_OFST (16)
3134 +#define RG_SSUSB_FORCE_IDRV_3P5DB_OFST (14)
3135 +#define RG_SSUSB_IDRV_3P5DB_OFST (8)
3136 +#define RG_SSUSB_FORCE_IDRV_0DB_OFST (6)
3137 +#define RG_SSUSB_IDRV_0DB_OFST (0)
3138 +
3139 +//U3D_B2_PHYD_TOP3
3140 +#define RG_SSUSB_TX_BIASI_OFST (25)
3141 +#define RG_SSUSB_FORCE_TX_BIASI_EN_OFST (24)
3142 +#define RG_SSUSB_TX_BIASI_EN_OFST (16)
3143 +#define RG_SSUSB_FORCE_TX_BIASI_OFST (13)
3144 +#define RG_SSUSB_FORCE_IDEM_6DB_OFST (8)
3145 +#define RG_SSUSB_IDEM_6DB_OFST (0)
3146 +
3147 +//U3D_B2_PHYD_TOP4
3148 +#define RG_SSUSB_G1_CDR_BIC_LTR_OFST (28)
3149 +#define RG_SSUSB_G1_CDR_BIC_LTD0_OFST (24)
3150 +#define RG_SSUSB_G1_CDR_BC_LTD1_OFST (16)
3151 +#define RG_SSUSB_G1_CDR_BC_LTR_OFST (8)
3152 +#define RG_SSUSB_G1_CDR_BC_LTD0_OFST (0)
3153 +
3154 +//U3D_B2_PHYD_TOP5
3155 +#define RG_SSUSB_G1_CDR_BIR_LTD1_OFST (24)
3156 +#define RG_SSUSB_G1_CDR_BIR_LTR_OFST (16)
3157 +#define RG_SSUSB_G1_CDR_BIR_LTD0_OFST (8)
3158 +#define RG_SSUSB_G1_CDR_BIC_LTD1_OFST (0)
3159 +
3160 +//U3D_B2_PHYD_TOP6
3161 +#define RG_SSUSB_G2_CDR_BIC_LTR_OFST (28)
3162 +#define RG_SSUSB_G2_CDR_BIC_LTD0_OFST (24)
3163 +#define RG_SSUSB_G2_CDR_BC_LTD1_OFST (16)
3164 +#define RG_SSUSB_G2_CDR_BC_LTR_OFST (8)
3165 +#define RG_SSUSB_G2_CDR_BC_LTD0_OFST (0)
3166 +
3167 +//U3D_B2_PHYD_TOP7
3168 +#define RG_SSUSB_G2_CDR_BIR_LTD1_OFST (24)
3169 +#define RG_SSUSB_G2_CDR_BIR_LTR_OFST (16)
3170 +#define RG_SSUSB_G2_CDR_BIR_LTD0_OFST (8)
3171 +#define RG_SSUSB_G2_CDR_BIC_LTD1_OFST (0)
3172 +
3173 +//U3D_B2_PHYD_P_SIGDET1
3174 +#define RG_SSUSB_P_SIGDET_FLT_DIS_OFST (31)
3175 +#define RG_SSUSB_P_SIGDET_FLT_G2_DEAST_SEL_OFST (24)
3176 +#define RG_SSUSB_P_SIGDET_FLT_G1_DEAST_SEL_OFST (16)
3177 +#define RG_SSUSB_P_SIGDET_FLT_P2_AST_SEL_OFST (8)
3178 +#define RG_SSUSB_P_SIGDET_FLT_PX_AST_SEL_OFST (0)
3179 +
3180 +//U3D_B2_PHYD_P_SIGDET2
3181 +#define RG_SSUSB_P_SIGDET_RX_VAL_S_OFST (29)
3182 +#define RG_SSUSB_P_SIGDET_L0S_DEAS_SEL_OFST (28)
3183 +#define RG_SSUSB_P_SIGDET_L0_EXIT_S_OFST (27)
3184 +#define RG_SSUSB_P_SIGDET_L0S_EXIT_T_S_OFST (25)
3185 +#define RG_SSUSB_P_SIGDET_L0S_EXIT_S_OFST (24)
3186 +#define RG_SSUSB_P_SIGDET_L0S_ENTRY_S_OFST (16)
3187 +#define RG_SSUSB_P_SIGDET_PRB_SEL_OFST (10)
3188 +#define RG_SSUSB_P_SIGDET_BK_SIG_T_OFST (8)
3189 +#define RG_SSUSB_P_SIGDET_P2_RXLFPS_OFST (6)
3190 +#define RG_SSUSB_P_SIGDET_NON_BK_AD_OFST (5)
3191 +#define RG_SSUSB_P_SIGDET_BK_B_RXEQ_OFST (4)
3192 +#define RG_SSUSB_P_SIGDET_G2_KO_SEL_OFST (2)
3193 +#define RG_SSUSB_P_SIGDET_G1_KO_SEL_OFST (0)
3194 +
3195 +//U3D_B2_PHYD_P_SIGDET_CAL1
3196 +#define RG_SSUSB_P_SIGDET_CAL_OFFSET_OFST (24)
3197 +#define RG_SSUSB_P_FORCE_SIGDET_CAL_OFFSET_OFST (16)
3198 +#define RG_SSUSB_P_SIGDET_CAL_EN_OFST (8)
3199 +#define RG_SSUSB_P_FORCE_SIGDET_CAL_EN_OFST (3)
3200 +#define RG_SSUSB_P_SIGDET_FLT_EN_OFST (2)
3201 +#define RG_SSUSB_P_SIGDET_SAMPLE_PRD_OFST (1)
3202 +#define RG_SSUSB_P_SIGDET_REK_OFST (0)
3203 +
3204 +//U3D_B2_PHYD_RXDET1
3205 +#define RG_SSUSB_RXDET_PRB_SEL_OFST (31)
3206 +#define RG_SSUSB_FORCE_CMDET_OFST (30)
3207 +#define RG_SSUSB_RXDET_EN_OFST (29)
3208 +#define RG_SSUSB_FORCE_RXDET_EN_OFST (28)
3209 +#define RG_SSUSB_RXDET_K_TWICE_OFST (27)
3210 +#define RG_SSUSB_RXDET_STB3_SET_OFST (18)
3211 +#define RG_SSUSB_RXDET_STB2_SET_OFST (9)
3212 +#define RG_SSUSB_RXDET_STB1_SET_OFST (0)
3213 +
3214 +//U3D_B2_PHYD_RXDET2
3215 +#define RG_SSUSB_PHYD_TRAINDEC_FORCE_CGEN_OFST (31)
3216 +#define RG_SSUSB_PHYD_BERTLB_FORCE_CGEN_OFST (30)
3217 +#define RG_SSUSB_PHYD_T2RLB_FORCE_CGEN_OFST (29)
3218 +#define RG_SSUSB_PDN_T_SEL_OFST (18)
3219 +#define RG_SSUSB_RXDET_STB3_SET_P3_OFST (9)
3220 +#define RG_SSUSB_RXDET_STB2_SET_P3_OFST (0)
3221 +
3222 +//U3D_B2_PHYD_MISC0
3223 +#define RG_SSUSB_FORCE_PLL_DDS_HF_EN_OFST (22)
3224 +#define RG_SSUSB_PLL_DDS_HF_EN_MAN_OFST (21)
3225 +#define RG_SSUSB_RXLFPS_ENTXDRV_OFST (20)
3226 +#define RG_SSUSB_RX_FL_UNLOCKTH_OFST (16)
3227 +#define RG_SSUSB_LFPS_PSEL_OFST (15)
3228 +#define RG_SSUSB_RX_SIGDET_EN_OFST (14)
3229 +#define RG_SSUSB_RX_SIGDET_EN_SEL_OFST (13)
3230 +#define RG_SSUSB_RX_PI_CAL_EN_OFST (12)
3231 +#define RG_SSUSB_RX_PI_CAL_EN_SEL_OFST (11)
3232 +#define RG_SSUSB_P3_CLS_CK_SEL_OFST (10)
3233 +#define RG_SSUSB_T2RLB_PSEL_OFST (8)
3234 +#define RG_SSUSB_PPCTL_PSEL_OFST (5)
3235 +#define RG_SSUSB_PHYD_TX_DATA_INV_OFST (4)
3236 +#define RG_SSUSB_BERTLB_PSEL_OFST (2)
3237 +#define RG_SSUSB_RETRACK_DIS_OFST (1)
3238 +#define RG_SSUSB_PPERRCNT_CLR_OFST (0)
3239 +
3240 +//U3D_B2_PHYD_MISC2
3241 +#define RG_SSUSB_FRC_PLL_DDS_PREDIV2_OFST (31)
3242 +#define RG_SSUSB_FRC_PLL_DDS_IADJ_OFST (27)
3243 +#define RG_SSUSB_P_SIGDET_125FILTER_OFST (26)
3244 +#define RG_SSUSB_P_SIGDET_RST_FILTER_OFST (25)
3245 +#define RG_SSUSB_P_SIGDET_EID_USE_RAW_OFST (24)
3246 +#define RG_SSUSB_P_SIGDET_LTD_USE_RAW_OFST (23)
3247 +#define RG_SSUSB_EIDLE_BF_RXDET_OFST (22)
3248 +#define RG_SSUSB_EIDLE_LP_STBCYC_OFST (13)
3249 +#define RG_SSUSB_TX_EIDLE_LP_POSTDLY_OFST (7)
3250 +#define RG_SSUSB_TX_EIDLE_LP_PREDLY_OFST (1)
3251 +#define RG_SSUSB_TX_EIDLE_LP_EN_ADV_OFST (0)
3252 +
3253 +//U3D_B2_PHYD_MISC3
3254 +#define RGS_SSUSB_DDS_CALIB_C_STATE_OFST (16)
3255 +#define RGS_SSUSB_PPERRCNT_OFST (0)
3256 +
3257 +//U3D_B2_ROSC_0
3258 +#define RG_SSUSB_RING_OSC_CNTEND_OFST (23)
3259 +#define RG_SSUSB_XTAL_OSC_CNTEND_OFST (16)
3260 +#define RG_SSUSB_RING_OSC_EN_OFST (3)
3261 +#define RG_SSUSB_RING_OSC_FORCE_EN_OFST (2)
3262 +#define RG_SSUSB_FRC_RING_BYPASS_DET_OFST (1)
3263 +#define RG_SSUSB_RING_BYPASS_DET_OFST (0)
3264 +
3265 +//U3D_B2_ROSC_1
3266 +#define RG_SSUSB_RING_OSC_FRC_P3_OFST (20)
3267 +#define RG_SSUSB_RING_OSC_P3_OFST (19)
3268 +#define RG_SSUSB_RING_OSC_FRC_RECAL_OFST (17)
3269 +#define RG_SSUSB_RING_OSC_RECAL_OFST (16)
3270 +#define RG_SSUSB_RING_OSC_SEL_OFST (8)
3271 +#define RG_SSUSB_RING_OSC_FRC_SEL_OFST (0)
3272 +
3273 +//U3D_B2_ROSC_2
3274 +#define RG_SSUSB_RING_DET_STRCYC2_OFST (16)
3275 +#define RG_SSUSB_RING_DET_STRCYC1_OFST (0)
3276 +
3277 +//U3D_B2_ROSC_3
3278 +#define RG_SSUSB_RING_DET_DETWIN1_OFST (16)
3279 +#define RG_SSUSB_RING_DET_STRCYC3_OFST (0)
3280 +
3281 +//U3D_B2_ROSC_4
3282 +#define RG_SSUSB_RING_DET_DETWIN3_OFST (16)
3283 +#define RG_SSUSB_RING_DET_DETWIN2_OFST (0)
3284 +
3285 +//U3D_B2_ROSC_5
3286 +#define RG_SSUSB_RING_DET_LBOND1_OFST (16)
3287 +#define RG_SSUSB_RING_DET_UBOND1_OFST (0)
3288 +
3289 +//U3D_B2_ROSC_6
3290 +#define RG_SSUSB_RING_DET_LBOND2_OFST (16)
3291 +#define RG_SSUSB_RING_DET_UBOND2_OFST (0)
3292 +
3293 +//U3D_B2_ROSC_7
3294 +#define RG_SSUSB_RING_DET_LBOND3_OFST (16)
3295 +#define RG_SSUSB_RING_DET_UBOND3_OFST (0)
3296 +
3297 +//U3D_B2_ROSC_8
3298 +#define RG_SSUSB_RING_RESERVE_OFST (16)
3299 +#define RG_SSUSB_ROSC_PROB_SEL_OFST (2)
3300 +#define RG_SSUSB_RING_FREQMETER_EN_OFST (1)
3301 +#define RG_SSUSB_RING_DET_BPS_UBOND_OFST (0)
3302 +
3303 +//U3D_B2_ROSC_9
3304 +#define RGS_FM_RING_CNT_OFST (16)
3305 +#define RGS_SSUSB_RING_OSC_STATE_OFST (10)
3306 +#define RGS_SSUSB_RING_OSC_STABLE_OFST (9)
3307 +#define RGS_SSUSB_RING_OSC_CAL_FAIL_OFST (8)
3308 +#define RGS_SSUSB_RING_OSC_CAL_OFST (0)
3309 +
3310 +//U3D_B2_ROSC_A
3311 +#define RGS_SSUSB_ROSC_PROB_OUT_OFST (0)
3312 +
3313 +//U3D_PHYD_VERSION
3314 +#define RGS_SSUSB_PHYD_VERSION_OFST (0)
3315 +
3316 +//U3D_PHYD_MODEL
3317 +#define RGS_SSUSB_PHYD_MODEL_OFST (0)
3318 +
3319 +
3320 +///////////////////////////////////////////////////////////////////////////////
3321 +
3322 +struct sifslv_chip_reg {
3323 + PHY_LE32 xtalbias;
3324 + PHY_LE32 syspll1;
3325 + PHY_LE32 gpio_ctla;
3326 + PHY_LE32 gpio_ctlb;
3327 + PHY_LE32 gpio_ctlc;
3328 +};
3329 +
3330 +//U3D_GPIO_CTLA
3331 +#define RG_C60802_GPIO_CTLA (0xffffffff<<0) //31:0
3332 +
3333 +//U3D_GPIO_CTLB
3334 +#define RG_C60802_GPIO_CTLB (0xffffffff<<0) //31:0
3335 +
3336 +//U3D_GPIO_CTLC
3337 +#define RG_C60802_GPIO_CTLC (0xffffffff<<0) //31:0
3338 +
3339 +/* OFFSET */
3340 +
3341 +//U3D_GPIO_CTLA
3342 +#define RG_C60802_GPIO_CTLA_OFST (0)
3343 +
3344 +//U3D_GPIO_CTLB
3345 +#define RG_C60802_GPIO_CTLB_OFST (0)
3346 +
3347 +//U3D_GPIO_CTLC
3348 +#define RG_C60802_GPIO_CTLC_OFST (0)
3349 +
3350 +///////////////////////////////////////////////////////////////////////////////
3351 +
3352 +struct sifslv_fm_feg {
3353 + //0x0
3354 + PHY_LE32 fmcr0;
3355 + PHY_LE32 fmcr1;
3356 + PHY_LE32 fmcr2;
3357 + PHY_LE32 fmmonr0;
3358 + //0x10
3359 + PHY_LE32 fmmonr1;
3360 +};
3361 +
3362 +//U3D_FMCR0
3363 +#define RG_LOCKTH (0xf<<28) //31:28
3364 +#define RG_MONCLK_SEL (0x3<<26) //27:26
3365 +#define RG_FM_MODE (0x1<<25) //25:25
3366 +#define RG_FREQDET_EN (0x1<<24) //24:24
3367 +#define RG_CYCLECNT (0xffffff<<0) //23:0
3368 +
3369 +//U3D_FMCR1
3370 +#define RG_TARGET (0xffffffff<<0) //31:0
3371 +
3372 +//U3D_FMCR2
3373 +#define RG_OFFSET (0xffffffff<<0) //31:0
3374 +
3375 +//U3D_FMMONR0
3376 +#define USB_FM_OUT (0xffffffff<<0) //31:0
3377 +
3378 +//U3D_FMMONR1
3379 +#define RG_MONCLK_SEL_3 (0x1<<9) //9:9
3380 +#define RG_FRCK_EN (0x1<<8) //8:8
3381 +#define USBPLL_LOCK (0x1<<1) //1:1
3382 +#define USB_FM_VLD (0x1<<0) //0:0
3383 +
3384 +
3385 +/* OFFSET */
3386 +
3387 +//U3D_FMCR0
3388 +#define RG_LOCKTH_OFST (28)
3389 +#define RG_MONCLK_SEL_OFST (26)
3390 +#define RG_FM_MODE_OFST (25)
3391 +#define RG_FREQDET_EN_OFST (24)
3392 +#define RG_CYCLECNT_OFST (0)
3393 +
3394 +//U3D_FMCR1
3395 +#define RG_TARGET_OFST (0)
3396 +
3397 +//U3D_FMCR2
3398 +#define RG_OFFSET_OFST (0)
3399 +
3400 +//U3D_FMMONR0
3401 +#define USB_FM_OUT_OFST (0)
3402 +
3403 +//U3D_FMMONR1
3404 +#define RG_MONCLK_SEL_3_OFST (9)
3405 +#define RG_FRCK_EN_OFST (8)
3406 +#define USBPLL_LOCK_OFST (1)
3407 +#define USB_FM_VLD_OFST (0)
3408 +
3409 +
3410 +///////////////////////////////////////////////////////////////////////////////
3411 +
3412 +PHY_INT32 phy_init(struct u3phy_info *info);
3413 +PHY_INT32 phy_change_pipe_phase(struct u3phy_info *info, PHY_INT32 phy_drv, PHY_INT32 pipe_phase);
3414 +PHY_INT32 eyescan_init(struct u3phy_info *info);
3415 +PHY_INT32 phy_eyescan(struct u3phy_info *info, PHY_INT32 x_t1, PHY_INT32 y_t1, PHY_INT32 x_br, PHY_INT32 y_br, PHY_INT32 delta_x, PHY_INT32 delta_y
3416 + , PHY_INT32 eye_cnt, PHY_INT32 num_cnt, PHY_INT32 PI_cal_en, PHY_INT32 num_ignore_cnt);
3417 +PHY_INT32 u2_save_cur_en(struct u3phy_info *info);
3418 +PHY_INT32 u2_save_cur_re(struct u3phy_info *info);
3419 +PHY_INT32 u2_slew_rate_calibration(struct u3phy_info *info);
3420 +
3421 +#endif
3422 +#endif
3423 --- /dev/null
3424 +++ b/drivers/usb/host/mtk-phy-ahb.c
3425 @@ -0,0 +1,58 @@
3426 +#include "mtk-phy.h"
3427 +#ifdef CONFIG_U3D_HAL_SUPPORT
3428 +#include "mu3d_hal_osal.h"
3429 +#endif
3430 +
3431 +#ifdef CONFIG_U3_PHY_AHB_SUPPORT
3432 +#include <linux/gfp.h>
3433 +#include <linux/kernel.h>
3434 +#include <linux/slab.h>
3435 +
3436 +#ifndef CONFIG_U3D_HAL_SUPPORT
3437 +#define os_writel(addr,data) {\
3438 + (*((volatile PHY_UINT32*)(addr)) = data);\
3439 + }
3440 +#define os_readl(addr) *((volatile PHY_UINT32*)(addr))
3441 +#define os_writelmsk(addr, data, msk) \
3442 + { os_writel(addr, ((os_readl(addr) & ~(msk)) | ((data) & (msk)))); \
3443 + }
3444 +#define os_setmsk(addr, msk) \
3445 + { os_writel(addr, os_readl(addr) | msk); \
3446 + }
3447 +#define os_clrmsk(addr, msk) \
3448 + { os_writel(addr, os_readl(addr) &~ msk); \
3449 + }
3450 +/*msk the data first, then umsk with the umsk.*/
3451 +#define os_writelmskumsk(addr, data, msk, umsk) \
3452 +{\
3453 + os_writel(addr, ((os_readl(addr) & ~(msk)) | ((data) & (msk))) & (umsk));\
3454 +}
3455 +
3456 +#endif
3457 +
3458 +PHY_INT32 U3PhyWriteReg32(PHY_UINT32 addr, PHY_UINT32 data)
3459 +{
3460 + os_writel(addr, data);
3461 +
3462 + return 0;
3463 +}
3464 +
3465 +PHY_INT32 U3PhyReadReg32(PHY_UINT32 addr)
3466 +{
3467 + return os_readl(addr);
3468 +}
3469 +
3470 +PHY_INT32 U3PhyWriteReg8(PHY_UINT32 addr, PHY_UINT8 data)
3471 +{
3472 + os_writelmsk(addr&0xfffffffc, data<<((addr%4)*8), 0xff<<((addr%4)*8));
3473 +
3474 + return 0;
3475 +}
3476 +
3477 +PHY_INT8 U3PhyReadReg8(PHY_UINT32 addr)
3478 +{
3479 + return ((os_readl(addr)>>((addr%4)*8))&0xff);
3480 +}
3481 +
3482 +#endif
3483 +
3484 --- /dev/null
3485 +++ b/drivers/usb/host/mtk-phy.c
3486 @@ -0,0 +1,102 @@
3487 +#include <linux/gfp.h>
3488 +#include <linux/kernel.h>
3489 +#include <linux/slab.h>
3490 +#define U3_PHY_LIB
3491 +#include "mtk-phy.h"
3492 +#ifdef CONFIG_PROJECT_7621
3493 +#include "mtk-phy-7621.h"
3494 +#endif
3495 +#ifdef CONFIG_PROJECT_PHY
3496 +static struct u3phy_operator project_operators = {
3497 + .init = phy_init,
3498 + .change_pipe_phase = phy_change_pipe_phase,
3499 + .eyescan_init = eyescan_init,
3500 + .eyescan = phy_eyescan,
3501 + .u2_slew_rate_calibration = u2_slew_rate_calibration,
3502 +};
3503 +#endif
3504 +
3505 +
3506 +PHY_INT32 u3phy_init(){
3507 +#ifndef CONFIG_PROJECT_PHY
3508 + PHY_INT32 u3phy_version;
3509 +#endif
3510 +
3511 + if(u3phy != NULL){
3512 + return PHY_TRUE;
3513 + }
3514 +
3515 + u3phy = kmalloc(sizeof(struct u3phy_info), GFP_NOIO);
3516 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
3517 + u3phy_p1 = kmalloc(sizeof(struct u3phy_info), GFP_NOIO);
3518 +#endif
3519 +#ifdef CONFIG_U3_PHY_GPIO_SUPPORT
3520 + u3phy->phyd_version_addr = 0x2000e4;
3521 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
3522 + u3phy_p1->phyd_version_addr = 0x2000e4;
3523 +#endif
3524 +#else
3525 + u3phy->phyd_version_addr = U3_PHYD_B2_BASE + 0xe4;
3526 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
3527 + u3phy_p1->phyd_version_addr = U3_PHYD_B2_BASE_P1 + 0xe4;
3528 +#endif
3529 +#endif
3530 +
3531 +#ifdef CONFIG_PROJECT_PHY
3532 +
3533 + u3phy->u2phy_regs = (struct u2phy_reg *)U2_PHY_BASE;
3534 + u3phy->u3phyd_regs = (struct u3phyd_reg *)U3_PHYD_BASE;
3535 + u3phy->u3phyd_bank2_regs = (struct u3phyd_bank2_reg *)U3_PHYD_B2_BASE;
3536 + u3phy->u3phya_regs = (struct u3phya_reg *)U3_PHYA_BASE;
3537 + u3phy->u3phya_da_regs = (struct u3phya_da_reg *)U3_PHYA_DA_BASE;
3538 + u3phy->sifslv_chip_regs = (struct sifslv_chip_reg *)SIFSLV_CHIP_BASE;
3539 + u3phy->sifslv_fm_regs = (struct sifslv_fm_feg *)SIFSLV_FM_FEG_BASE;
3540 + u3phy_ops = &project_operators;
3541 +
3542 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
3543 + u3phy_p1->u2phy_regs = (struct u2phy_reg *)U2_PHY_BASE_P1;
3544 + u3phy_p1->u3phyd_regs = (struct u3phyd_reg *)U3_PHYD_BASE_P1;
3545 + u3phy_p1->u3phyd_bank2_regs = (struct u3phyd_bank2_reg *)U3_PHYD_B2_BASE_P1;
3546 + u3phy_p1->u3phya_regs = (struct u3phya_reg *)U3_PHYA_BASE_P1;
3547 + u3phy_p1->u3phya_da_regs = (struct u3phya_da_reg *)U3_PHYA_DA_BASE_P1;
3548 + u3phy_p1->sifslv_chip_regs = (struct sifslv_chip_reg *)SIFSLV_CHIP_BASE;
3549 + u3phy_p1->sifslv_fm_regs = (struct sifslv_fm_feg *)SIFSLV_FM_FEG_BASE;
3550 +#endif
3551 +#endif
3552 +
3553 + return PHY_TRUE;
3554 +}
3555 +
3556 +PHY_INT32 U3PhyWriteField8(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask, PHY_INT32 value){
3557 + PHY_INT8 cur_value;
3558 + PHY_INT8 new_value;
3559 +
3560 + cur_value = U3PhyReadReg8(addr);
3561 + new_value = (cur_value & (~mask)) | (value << offset);
3562 + //udelay(i2cdelayus);
3563 + U3PhyWriteReg8(addr, new_value);
3564 + return PHY_TRUE;
3565 +}
3566 +
3567 +PHY_INT32 U3PhyWriteField32(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask, PHY_INT32 value){
3568 + PHY_INT32 cur_value;
3569 + PHY_INT32 new_value;
3570 +
3571 + cur_value = U3PhyReadReg32(addr);
3572 + new_value = (cur_value & (~mask)) | ((value << offset) & mask);
3573 + U3PhyWriteReg32(addr, new_value);
3574 + //DRV_MDELAY(100);
3575 +
3576 + return PHY_TRUE;
3577 +}
3578 +
3579 +PHY_INT32 U3PhyReadField8(PHY_INT32 addr,PHY_INT32 offset,PHY_INT32 mask){
3580 +
3581 + return ((U3PhyReadReg8(addr) & mask) >> offset);
3582 +}
3583 +
3584 +PHY_INT32 U3PhyReadField32(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask){
3585 +
3586 + return ((U3PhyReadReg32(addr) & mask) >> offset);
3587 +}
3588 +
3589 --- /dev/null
3590 +++ b/drivers/usb/host/mtk-phy.h
3591 @@ -0,0 +1,179 @@
3592 +#ifndef __MTK_PHY_NEW_H
3593 +#define __MTK_PHY_NEW_H
3594 +
3595 +//#define CONFIG_U3D_HAL_SUPPORT
3596 +
3597 +/* include system library */
3598 +#include <linux/gfp.h>
3599 +#include <linux/kernel.h>
3600 +#include <linux/slab.h>
3601 +#include <linux/delay.h>
3602 +
3603 +/* Choose PHY R/W implementation */
3604 +//#define CONFIG_U3_PHY_GPIO_SUPPORT //SW I2C implemented by GPIO
3605 +#define CONFIG_U3_PHY_AHB_SUPPORT //AHB, only on SoC
3606 +
3607 +/* Choose PHY version */
3608 +//Select your project by defining one of the followings
3609 +#define CONFIG_PROJECT_7621 //7621
3610 +#define CONFIG_PROJECT_PHY
3611 +
3612 +/* BASE ADDRESS DEFINE, should define this on ASIC */
3613 +#define PHY_BASE 0xBE1D0000
3614 +#define SIFSLV_FM_FEG_BASE (PHY_BASE+0x100)
3615 +#define SIFSLV_CHIP_BASE (PHY_BASE+0x700)
3616 +#define U2_PHY_BASE (PHY_BASE+0x800)
3617 +#define U3_PHYD_BASE (PHY_BASE+0x900)
3618 +#define U3_PHYD_B2_BASE (PHY_BASE+0xa00)
3619 +#define U3_PHYA_BASE (PHY_BASE+0xb00)
3620 +#define U3_PHYA_DA_BASE (PHY_BASE+0xc00)
3621 +
3622 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
3623 +#define SIFSLV_FM_FEG_BASE_P1 (PHY_BASE+0x100)
3624 +#define SIFSLV_CHIP_BASE_P1 (PHY_BASE+0x700)
3625 +#define U2_PHY_BASE_P1 (PHY_BASE+0x1000)
3626 +#define U3_PHYD_BASE_P1 (PHY_BASE+0x1100)
3627 +#define U3_PHYD_B2_BASE_P1 (PHY_BASE+0x1200)
3628 +#define U3_PHYA_BASE_P1 (PHY_BASE+0x1300)
3629 +#define U3_PHYA_DA_BASE_P1 (PHY_BASE+0x1400)
3630 +#endif
3631 +
3632 +/*
3633 +
3634 +0x00000100 MODULE ssusb_sifslv_fmreg ssusb_sifslv_fmreg
3635 +0x00000700 MODULE ssusb_sifslv_ippc ssusb_sifslv_ippc
3636 +0x00000800 MODULE ssusb_sifslv_u2phy_com ssusb_sifslv_u2_phy_com_T28
3637 +0x00000900 MODULE ssusb_sifslv_u3phyd ssusb_sifslv_u3phyd_T28
3638 +0x00000a00 MODULE ssusb_sifslv_u3phyd_bank2 ssusb_sifslv_u3phyd_bank2_T28
3639 +0x00000b00 MODULE ssusb_sifslv_u3phya ssusb_sifslv_u3phya_T28
3640 +0x00000c00 MODULE ssusb_sifslv_u3phya_da ssusb_sifslv_u3phya_da_T28
3641 +*/
3642 +
3643 +
3644 +/* TYPE DEFINE */
3645 +typedef unsigned int PHY_UINT32;
3646 +typedef int PHY_INT32;
3647 +typedef unsigned short PHY_UINT16;
3648 +typedef short PHY_INT16;
3649 +typedef unsigned char PHY_UINT8;
3650 +typedef char PHY_INT8;
3651 +
3652 +typedef PHY_UINT32 __bitwise PHY_LE32;
3653 +
3654 +/* CONSTANT DEFINE */
3655 +#define PHY_FALSE 0
3656 +#define PHY_TRUE 1
3657 +
3658 +/* MACRO DEFINE */
3659 +#define DRV_WriteReg32(addr,data) ((*(volatile PHY_UINT32 *)(addr)) = (unsigned long)(data))
3660 +#define DRV_Reg32(addr) (*(volatile PHY_UINT32 *)(addr))
3661 +
3662 +#define DRV_MDELAY mdelay
3663 +#define DRV_MSLEEP msleep
3664 +#define DRV_UDELAY udelay
3665 +#define DRV_USLEEP usleep
3666 +
3667 +/* PHY FUNCTION DEFINE, implemented in platform files, ex. ahb, gpio */
3668 +PHY_INT32 U3PhyWriteReg32(PHY_UINT32 addr, PHY_UINT32 data);
3669 +PHY_INT32 U3PhyReadReg32(PHY_UINT32 addr);
3670 +PHY_INT32 U3PhyWriteReg8(PHY_UINT32 addr, PHY_UINT8 data);
3671 +PHY_INT8 U3PhyReadReg8(PHY_UINT32 addr);
3672 +
3673 +/* PHY GENERAL USAGE FUNC, implemented in mtk-phy.c */
3674 +PHY_INT32 U3PhyWriteField8(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask, PHY_INT32 value);
3675 +PHY_INT32 U3PhyWriteField32(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask, PHY_INT32 value);
3676 +PHY_INT32 U3PhyReadField8(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask);
3677 +PHY_INT32 U3PhyReadField32(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask);
3678 +
3679 +struct u3phy_info {
3680 + PHY_INT32 phy_version;
3681 + PHY_INT32 phyd_version_addr;
3682 +
3683 +#ifdef CONFIG_PROJECT_PHY
3684 + struct u2phy_reg *u2phy_regs;
3685 + struct u3phya_reg *u3phya_regs;
3686 + struct u3phya_da_reg *u3phya_da_regs;
3687 + struct u3phyd_reg *u3phyd_regs;
3688 + struct u3phyd_bank2_reg *u3phyd_bank2_regs;
3689 + struct sifslv_chip_reg *sifslv_chip_regs;
3690 + struct sifslv_fm_feg *sifslv_fm_regs;
3691 +#endif
3692 +};
3693 +
3694 +struct u3phy_operator {
3695 + PHY_INT32 (*init) (struct u3phy_info *info);
3696 + PHY_INT32 (*change_pipe_phase) (struct u3phy_info *info, PHY_INT32 phy_drv, PHY_INT32 pipe_phase);
3697 + PHY_INT32 (*eyescan_init) (struct u3phy_info *info);
3698 + PHY_INT32 (*eyescan) (struct u3phy_info *info, PHY_INT32 x_t1, PHY_INT32 y_t1, PHY_INT32 x_br, PHY_INT32 y_br, PHY_INT32 delta_x, PHY_INT32 delta_y, PHY_INT32 eye_cnt, PHY_INT32 num_cnt, PHY_INT32 PI_cal_en, PHY_INT32 num_ignore_cnt);
3699 + PHY_INT32 (*u2_save_current_entry) (struct u3phy_info *info);
3700 + PHY_INT32 (*u2_save_current_recovery) (struct u3phy_info *info);
3701 + PHY_INT32 (*u2_slew_rate_calibration) (struct u3phy_info *info);
3702 +};
3703 +
3704 +#ifdef U3_PHY_LIB
3705 +#define AUTOEXT
3706 +#else
3707 +#define AUTOEXT extern
3708 +#endif
3709 +
3710 +AUTOEXT struct u3phy_info *u3phy;
3711 +AUTOEXT struct u3phy_info *u3phy_p1;
3712 +AUTOEXT struct u3phy_operator *u3phy_ops;
3713 +
3714 +/*********eye scan required*********/
3715 +
3716 +#define LO_BYTE(x) ((PHY_UINT8)((x) & 0xFF))
3717 +#define HI_BYTE(x) ((PHY_UINT8)(((x) & 0xFF00) >> 8))
3718 +
3719 +typedef enum
3720 +{
3721 + SCAN_UP,
3722 + SCAN_DN
3723 +} enumScanDir;
3724 +
3725 +struct strucScanRegion
3726 +{
3727 + PHY_INT8 bX_tl;
3728 + PHY_INT8 bY_tl;
3729 + PHY_INT8 bX_br;
3730 + PHY_INT8 bY_br;
3731 + PHY_INT8 bDeltaX;
3732 + PHY_INT8 bDeltaY;
3733 +};
3734 +
3735 +struct strucTestCycle
3736 +{
3737 + PHY_UINT16 wEyeCnt;
3738 + PHY_INT8 bNumOfEyeCnt;
3739 + PHY_INT8 bPICalEn;
3740 + PHY_INT8 bNumOfIgnoreCnt;
3741 +};
3742 +
3743 +#define ERRCNT_MAX 128
3744 +#define CYCLE_COUNT_MAX 15
3745 +
3746 +/// the map resolution is 128 x 128 pts
3747 +#define MAX_X 127
3748 +#define MAX_Y 127
3749 +#define MIN_X 0
3750 +#define MIN_Y 0
3751 +
3752 +PHY_INT32 u3phy_init(void);
3753 +
3754 +AUTOEXT struct strucScanRegion _rEye1;
3755 +AUTOEXT struct strucScanRegion _rEye2;
3756 +AUTOEXT struct strucTestCycle _rTestCycle;
3757 +AUTOEXT PHY_UINT8 _bXcurr;
3758 +AUTOEXT PHY_UINT8 _bYcurr;
3759 +AUTOEXT enumScanDir _eScanDir;
3760 +AUTOEXT PHY_INT8 _fgXChged;
3761 +AUTOEXT PHY_INT8 _bPIResult;
3762 +/* use local variable instead to save memory use */
3763 +#if 0
3764 +AUTOEXT PHY_UINT32 pwErrCnt0[CYCLE_COUNT_MAX][ERRCNT_MAX][ERRCNT_MAX];
3765 +AUTOEXT PHY_UINT32 pwErrCnt1[CYCLE_COUNT_MAX][ERRCNT_MAX][ERRCNT_MAX];
3766 +#endif
3767 +
3768 +/***********************************/
3769 +#endif
3770 +
3771 --- a/drivers/usb/host/pci-quirks.h
3772 +++ b/drivers/usb/host/pci-quirks.h
3773 @@ -1,7 +1,7 @@
3774 #ifndef __LINUX_USB_PCI_QUIRKS_H
3775 #define __LINUX_USB_PCI_QUIRKS_H
3776
3777 -#ifdef CONFIG_PCI
3778 +#if defined (CONFIG_PCI) && !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
3779 void uhci_reset_hc(struct pci_dev *pdev, unsigned long base);
3780 int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base);
3781 #endif /* CONFIG_PCI */
3782 --- a/drivers/usb/host/xhci-dbg.c
3783 +++ b/drivers/usb/host/xhci-dbg.c
3784 @@ -21,6 +21,9 @@
3785 */
3786
3787 #include "xhci.h"
3788 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
3789 +#include "xhci-mtk.h"
3790 +#endif
3791
3792 #define XHCI_INIT_VALUE 0x0
3793
3794 --- a/drivers/usb/host/xhci-mem.c
3795 +++ b/drivers/usb/host/xhci-mem.c
3796 @@ -67,6 +67,9 @@
3797
3798 static void xhci_segment_free(struct xhci_hcd *xhci, struct xhci_segment *seg)
3799 {
3800 + if (!seg)
3801 + return;
3802 +
3803 if (seg->trbs) {
3804 dma_pool_free(xhci->segment_pool, seg->trbs, seg->dma);
3805 seg->trbs = NULL;
3806 @@ -1475,9 +1478,17 @@
3807 max_burst = (usb_endpoint_maxp(&ep->desc)
3808 & 0x1800) >> 11;
3809 }
3810 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
3811 + if ((max_packet % 4 == 2) && (max_packet % 16 != 14) && (max_burst == 0) && usb_endpoint_dir_in(&ep->desc))
3812 + max_packet += 2;
3813 +#endif
3814 break;
3815 case USB_SPEED_FULL:
3816 case USB_SPEED_LOW:
3817 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
3818 + if ((max_packet % 4 == 2) && (max_packet % 16 != 14) && (max_burst == 0) && usb_endpoint_dir_in(&ep->desc))
3819 + max_packet += 2;
3820 +#endif
3821 break;
3822 default:
3823 BUG();
3824 --- /dev/null
3825 +++ b/drivers/usb/host/xhci-mtk-power.c
3826 @@ -0,0 +1,115 @@
3827 +#include "xhci-mtk.h"
3828 +#include "xhci-mtk-power.h"
3829 +#include "xhci.h"
3830 +#include <linux/kernel.h> /* printk() */
3831 +#include <linux/slab.h>
3832 +#include <linux/delay.h>
3833 +
3834 +static int g_num_u3_port;
3835 +static int g_num_u2_port;
3836 +
3837 +
3838 +void enableXhciAllPortPower(struct xhci_hcd *xhci){
3839 + int i;
3840 + u32 port_id, temp;
3841 + u32 __iomem *addr;
3842 +
3843 + g_num_u3_port = SSUSB_U3_PORT_NUM(readl(SSUSB_IP_CAP));
3844 + g_num_u2_port = SSUSB_U2_PORT_NUM(readl(SSUSB_IP_CAP));
3845 +
3846 + for(i=1; i<=g_num_u3_port; i++){
3847 + port_id=i;
3848 + addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(port_id-1 & 0xff);
3849 + temp = readl(addr);
3850 + temp = xhci_port_state_to_neutral(temp);
3851 + temp |= PORT_POWER;
3852 + writel(temp, addr);
3853 + }
3854 + for(i=1; i<=g_num_u2_port; i++){
3855 + port_id=i+g_num_u3_port;
3856 + addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(port_id-1 & 0xff);
3857 + temp = readl(addr);
3858 + temp = xhci_port_state_to_neutral(temp);
3859 + temp |= PORT_POWER;
3860 + writel(temp, addr);
3861 + }
3862 +}
3863 +
3864 +void enableAllClockPower(){
3865 +
3866 + int i;
3867 + u32 temp;
3868 +
3869 + g_num_u3_port = SSUSB_U3_PORT_NUM(readl(SSUSB_IP_CAP));
3870 + g_num_u2_port = SSUSB_U2_PORT_NUM(readl(SSUSB_IP_CAP));
3871 +
3872 + //2. Enable xHC
3873 + writel(readl(SSUSB_IP_PW_CTRL) | (SSUSB_IP_SW_RST), SSUSB_IP_PW_CTRL);
3874 + writel(readl(SSUSB_IP_PW_CTRL) & (~SSUSB_IP_SW_RST), SSUSB_IP_PW_CTRL);
3875 + writel(readl(SSUSB_IP_PW_CTRL_1) & (~SSUSB_IP_PDN), SSUSB_IP_PW_CTRL_1);
3876 +
3877 + //1. Enable target ports
3878 + for(i=0; i<g_num_u3_port; i++){
3879 + temp = readl(SSUSB_U3_CTRL(i));
3880 + temp = temp & (~SSUSB_U3_PORT_PDN) & (~SSUSB_U3_PORT_DIS);
3881 + writel(temp, SSUSB_U3_CTRL(i));
3882 + }
3883 + for(i=0; i<g_num_u2_port; i++){
3884 + temp = readl(SSUSB_U2_CTRL(i));
3885 + temp = temp & (~SSUSB_U2_PORT_PDN) & (~SSUSB_U2_PORT_DIS);
3886 + writel(temp, SSUSB_U2_CTRL(i));
3887 + }
3888 + msleep(100);
3889 +}
3890 +
3891 +
3892 +//(X)disable clock/power of a port
3893 +//(X)if all ports are disabled, disable IP ctrl power
3894 +//disable all ports and IP clock/power, this is just mention HW that the power/clock of port
3895 +//and IP could be disable if suspended.
3896 +//If doesn't not disable all ports at first, the IP clock/power will never be disabled
3897 +//(some U2 and U3 ports are binded to the same connection, that is, they will never enter suspend at the same time
3898 +//port_index: port number
3899 +//port_rev: 0x2 - USB2.0, 0x3 - USB3.0 (SuperSpeed)
3900 +void disablePortClockPower(void){
3901 + int i;
3902 + u32 temp;
3903 +
3904 + g_num_u3_port = SSUSB_U3_PORT_NUM(readl(SSUSB_IP_CAP));
3905 + g_num_u2_port = SSUSB_U2_PORT_NUM(readl(SSUSB_IP_CAP));
3906 +
3907 + for(i=0; i<g_num_u3_port; i++){
3908 + temp = readl(SSUSB_U3_CTRL(i));
3909 + temp = temp | (SSUSB_U3_PORT_PDN);
3910 + writel(temp, SSUSB_U3_CTRL(i));
3911 + }
3912 + for(i=0; i<g_num_u2_port; i++){
3913 + temp = readl(SSUSB_U2_CTRL(i));
3914 + temp = temp | (SSUSB_U2_PORT_PDN);
3915 + writel(temp, SSUSB_U2_CTRL(i));
3916 + }
3917 + writel(readl(SSUSB_IP_PW_CTRL_1) | (SSUSB_IP_PDN), SSUSB_IP_PW_CTRL_1);
3918 +}
3919 +
3920 +//if IP ctrl power is disabled, enable it
3921 +//enable clock/power of a port
3922 +//port_index: port number
3923 +//port_rev: 0x2 - USB2.0, 0x3 - USB3.0 (SuperSpeed)
3924 +void enablePortClockPower(int port_index, int port_rev){
3925 + int i;
3926 + u32 temp;
3927 +
3928 + writel(readl(SSUSB_IP_PW_CTRL_1) & (~SSUSB_IP_PDN), SSUSB_IP_PW_CTRL_1);
3929 +
3930 + if(port_rev == 0x3){
3931 + temp = readl(SSUSB_U3_CTRL(port_index));
3932 + temp = temp & (~SSUSB_U3_PORT_PDN);
3933 + writel(temp, SSUSB_U3_CTRL(port_index));
3934 + }
3935 + else if(port_rev == 0x2){
3936 + temp = readl(SSUSB_U2_CTRL(port_index));
3937 + temp = temp & (~SSUSB_U2_PORT_PDN);
3938 + writel(temp, SSUSB_U2_CTRL(port_index));
3939 + }
3940 +}
3941 +
3942 --- /dev/null
3943 +++ b/drivers/usb/host/xhci-mtk-power.h
3944 @@ -0,0 +1,13 @@
3945 +#ifndef _XHCI_MTK_POWER_H
3946 +#define _XHCI_MTK_POWER_H
3947 +
3948 +#include <linux/usb.h>
3949 +#include "xhci.h"
3950 +#include "xhci-mtk.h"
3951 +
3952 +void enableXhciAllPortPower(struct xhci_hcd *xhci);
3953 +void enableAllClockPower(void);
3954 +void disablePortClockPower(void);
3955 +void enablePortClockPower(int port_index, int port_rev);
3956 +
3957 +#endif
3958 --- /dev/null
3959 +++ b/drivers/usb/host/xhci-mtk-scheduler.c
3960 @@ -0,0 +1,608 @@
3961 +#include "xhci-mtk-scheduler.h"
3962 +#include <linux/kernel.h> /* printk() */
3963 +
3964 +static struct sch_ep **ss_out_eps[MAX_EP_NUM];
3965 +static struct sch_ep **ss_in_eps[MAX_EP_NUM];
3966 +static struct sch_ep **hs_eps[MAX_EP_NUM]; //including tt isoc
3967 +static struct sch_ep **tt_intr_eps[MAX_EP_NUM];
3968 +
3969 +
3970 +int mtk_xhci_scheduler_init(void){
3971 + int i;
3972 +
3973 + for(i=0; i<MAX_EP_NUM; i++){
3974 + ss_out_eps[i] = NULL;
3975 + }
3976 + for(i=0; i<MAX_EP_NUM; i++){
3977 + ss_in_eps[i] = NULL;
3978 + }
3979 + for(i=0; i<MAX_EP_NUM; i++){
3980 + hs_eps[i] = NULL;
3981 + }
3982 + for(i=0; i<MAX_EP_NUM; i++){
3983 + tt_intr_eps[i] = NULL;
3984 + }
3985 + return 0;
3986 +}
3987 +
3988 +int add_sch_ep(int dev_speed, int is_in, int isTT, int ep_type, int maxp, int interval, int burst
3989 + , int mult, int offset, int repeat, int pkts, int cs_count, int burst_mode
3990 + , int bw_cost, mtk_u32 *ep, struct sch_ep *tmp_ep){
3991 +
3992 + struct sch_ep **ep_array;
3993 + int i;
3994 +
3995 + if(is_in && dev_speed == USB_SPEED_SUPER ){
3996 + ep_array = (struct sch_ep **)ss_in_eps;
3997 + }
3998 + else if(dev_speed == USB_SPEED_SUPER){
3999 + ep_array = (struct sch_ep **)ss_out_eps;
4000 + }
4001 + else if(dev_speed == USB_SPEED_HIGH || (isTT && ep_type == USB_EP_ISOC)){
4002 + ep_array = (struct sch_ep **)hs_eps;
4003 + }
4004 + else{
4005 + ep_array = (struct sch_ep **)tt_intr_eps;
4006 + }
4007 + for(i=0; i<MAX_EP_NUM; i++){
4008 + if(ep_array[i] == NULL){
4009 + tmp_ep->dev_speed = dev_speed;
4010 + tmp_ep->isTT = isTT;
4011 + tmp_ep->is_in = is_in;
4012 + tmp_ep->ep_type = ep_type;
4013 + tmp_ep->maxp = maxp;
4014 + tmp_ep->interval = interval;
4015 + tmp_ep->burst = burst;
4016 + tmp_ep->mult = mult;
4017 + tmp_ep->offset = offset;
4018 + tmp_ep->repeat = repeat;
4019 + tmp_ep->pkts = pkts;
4020 + tmp_ep->cs_count = cs_count;
4021 + tmp_ep->burst_mode = burst_mode;
4022 + tmp_ep->bw_cost = bw_cost;
4023 + tmp_ep->ep = ep;
4024 + ep_array[i] = tmp_ep;
4025 + return SCH_SUCCESS;
4026 + }
4027 + }
4028 + return SCH_FAIL;
4029 +}
4030 +
4031 +int count_ss_bw(int is_in, int ep_type, int maxp, int interval, int burst, int mult, int offset, int repeat
4032 + , int td_size){
4033 + int i, j, k;
4034 + int bw_required[3];
4035 + int final_bw_required;
4036 + int bw_required_per_repeat;
4037 + int tmp_bw_required;
4038 + struct sch_ep *cur_sch_ep;
4039 + struct sch_ep **ep_array;
4040 + int cur_offset;
4041 + int cur_ep_offset;
4042 + int tmp_offset;
4043 + int tmp_interval;
4044 + int ep_offset;
4045 + int ep_interval;
4046 + int ep_repeat;
4047 + int ep_mult;
4048 +
4049 + if(is_in){
4050 + ep_array = (struct sch_ep **)ss_in_eps;
4051 + }
4052 + else{
4053 + ep_array = (struct sch_ep **)ss_out_eps;
4054 + }
4055 +
4056 + bw_required[0] = 0;
4057 + bw_required[1] = 0;
4058 + bw_required[2] = 0;
4059 +
4060 + if(repeat == 0){
4061 + final_bw_required = 0;
4062 + for(i=0; i<MAX_EP_NUM; i++){
4063 + cur_sch_ep = ep_array[i];
4064 + if(cur_sch_ep == NULL){
4065 + continue;
4066 + }
4067 + ep_interval = cur_sch_ep->interval;
4068 + ep_offset = cur_sch_ep->offset;
4069 + if(cur_sch_ep->repeat == 0){
4070 + if(ep_interval >= interval){
4071 + tmp_offset = ep_offset + ep_interval - offset;
4072 + tmp_interval = interval;
4073 + }
4074 + else{
4075 + tmp_offset = offset + interval - ep_offset;
4076 + tmp_interval = ep_interval;
4077 + }
4078 + if(tmp_offset % tmp_interval == 0){
4079 + final_bw_required += cur_sch_ep->bw_cost;
4080 + }
4081 + }
4082 + else{
4083 + ep_repeat = cur_sch_ep->repeat;
4084 + ep_mult = cur_sch_ep->mult;
4085 + for(k=0; k<=ep_mult; k++){
4086 + cur_ep_offset = ep_offset+(k*ep_mult);
4087 + if(ep_interval >= interval){
4088 + tmp_offset = cur_ep_offset + ep_interval - offset;
4089 + tmp_interval = interval;
4090 + }
4091 + else{
4092 + tmp_offset = offset + interval - cur_ep_offset;
4093 + tmp_interval = ep_interval;
4094 + }
4095 + if(tmp_offset % tmp_interval == 0){
4096 + final_bw_required += cur_sch_ep->bw_cost;
4097 + break;
4098 + }
4099 + }
4100 + }
4101 + }
4102 + final_bw_required += td_size;
4103 + }
4104 + else{
4105 + bw_required_per_repeat = maxp * (burst+1);
4106 + for(j=0; j<=mult; j++){
4107 + tmp_bw_required = 0;
4108 + cur_offset = offset+(j*repeat);
4109 + for(i=0; i<MAX_EP_NUM; i++){
4110 + cur_sch_ep = ep_array[i];
4111 + if(cur_sch_ep == NULL){
4112 + continue;
4113 + }
4114 + ep_interval = cur_sch_ep->interval;
4115 + ep_offset = cur_sch_ep->offset;
4116 + if(cur_sch_ep->repeat == 0){
4117 + if(ep_interval >= interval){
4118 + tmp_offset = ep_offset + ep_interval - cur_offset;
4119 + tmp_interval = interval;
4120 + }
4121 + else{
4122 + tmp_offset = cur_offset + interval - ep_offset;
4123 + tmp_interval = ep_interval;
4124 + }
4125 + if(tmp_offset % tmp_interval == 0){
4126 + tmp_bw_required += cur_sch_ep->bw_cost;
4127 + }
4128 + }
4129 + else{
4130 + ep_repeat = cur_sch_ep->repeat;
4131 + ep_mult = cur_sch_ep->mult;
4132 + for(k=0; k<=ep_mult; k++){
4133 + cur_ep_offset = ep_offset+(k*ep_repeat);
4134 + if(ep_interval >= interval){
4135 + tmp_offset = cur_ep_offset + ep_interval - cur_offset;
4136 + tmp_interval = interval;
4137 + }
4138 + else{
4139 + tmp_offset = cur_offset + interval - cur_ep_offset;
4140 + tmp_interval = ep_interval;
4141 + }
4142 + if(tmp_offset % tmp_interval == 0){
4143 + tmp_bw_required += cur_sch_ep->bw_cost;
4144 + break;
4145 + }
4146 + }
4147 + }
4148 + }
4149 + bw_required[j] = tmp_bw_required;
4150 + }
4151 + final_bw_required = SS_BW_BOUND;
4152 + for(j=0; j<=mult; j++){
4153 + if(bw_required[j] < final_bw_required){
4154 + final_bw_required = bw_required[j];
4155 + }
4156 + }
4157 + final_bw_required += bw_required_per_repeat;
4158 + }
4159 + return final_bw_required;
4160 +}
4161 +
4162 +int count_hs_bw(int ep_type, int maxp, int interval, int offset, int td_size){
4163 + int i;
4164 + int bw_required;
4165 + struct sch_ep *cur_sch_ep;
4166 + int tmp_offset;
4167 + int tmp_interval;
4168 + int ep_offset;
4169 + int ep_interval;
4170 + int cur_tt_isoc_interval; //for isoc tt check
4171 +
4172 + bw_required = 0;
4173 + for(i=0; i<MAX_EP_NUM; i++){
4174 +
4175 + cur_sch_ep = (struct sch_ep *)hs_eps[i];
4176 + if(cur_sch_ep == NULL){
4177 + continue;
4178 + }
4179 + ep_offset = cur_sch_ep->offset;
4180 + ep_interval = cur_sch_ep->interval;
4181 +
4182 + if(cur_sch_ep->isTT && cur_sch_ep->ep_type == USB_EP_ISOC){
4183 + cur_tt_isoc_interval = ep_interval<<3;
4184 + if(ep_interval >= interval){
4185 + tmp_offset = ep_offset + cur_tt_isoc_interval - offset;
4186 + tmp_interval = interval;
4187 + }
4188 + else{
4189 + tmp_offset = offset + interval - ep_offset;
4190 + tmp_interval = cur_tt_isoc_interval;
4191 + }
4192 + if(cur_sch_ep->is_in){
4193 + if((tmp_offset%tmp_interval >=2) && (tmp_offset%tmp_interval <= cur_sch_ep->cs_count)){
4194 + bw_required += 188;
4195 + }
4196 + }
4197 + else{
4198 + if(tmp_offset%tmp_interval <= cur_sch_ep->cs_count){
4199 + bw_required += 188;
4200 + }
4201 + }
4202 + }
4203 + else{
4204 + if(ep_interval >= interval){
4205 + tmp_offset = ep_offset + ep_interval - offset;
4206 + tmp_interval = interval;
4207 + }
4208 + else{
4209 + tmp_offset = offset + interval - ep_offset;
4210 + tmp_interval = ep_interval;
4211 + }
4212 + if(tmp_offset%tmp_interval == 0){
4213 + bw_required += cur_sch_ep->bw_cost;
4214 + }
4215 + }
4216 + }
4217 + bw_required += td_size;
4218 + return bw_required;
4219 +}
4220 +
4221 +int count_tt_isoc_bw(int is_in, int maxp, int interval, int offset, int td_size){
4222 + char is_cs;
4223 + int mframe_idx, frame_idx, s_frame, s_mframe, cur_mframe;
4224 + int bw_required, max_bw;
4225 + int ss_cs_count;
4226 + int cs_mframe;
4227 + int max_frame;
4228 + int i,j;
4229 + struct sch_ep *cur_sch_ep;
4230 + int ep_offset;
4231 + int ep_interval;
4232 + int ep_cs_count;
4233 + int tt_isoc_interval; //for isoc tt check
4234 + int cur_tt_isoc_interval; //for isoc tt check
4235 + int tmp_offset;
4236 + int tmp_interval;
4237 +
4238 + is_cs = 0;
4239 +
4240 + tt_isoc_interval = interval<<3; //frame to mframe
4241 + if(is_in){
4242 + is_cs = 1;
4243 + }
4244 + s_frame = offset/8;
4245 + s_mframe = offset%8;
4246 + ss_cs_count = (maxp + (188 - 1))/188;
4247 + if(is_cs){
4248 + cs_mframe = offset%8 + 2 + ss_cs_count;
4249 + if (cs_mframe <= 6)
4250 + ss_cs_count += 2;
4251 + else if (cs_mframe == 7)
4252 + ss_cs_count++;
4253 + else if (cs_mframe > 8)
4254 + return -1;
4255 + }
4256 + max_bw = 0;
4257 + if(is_in){
4258 + i=2;
4259 + }
4260 + for(cur_mframe = offset+i; i<ss_cs_count; cur_mframe++, i++){
4261 + bw_required = 0;
4262 + for(j=0; j<MAX_EP_NUM; j++){
4263 + cur_sch_ep = (struct sch_ep *)hs_eps[j];
4264 + if(cur_sch_ep == NULL){
4265 + continue;
4266 + }
4267 + ep_offset = cur_sch_ep->offset;
4268 + ep_interval = cur_sch_ep->interval;
4269 + if(cur_sch_ep->isTT && cur_sch_ep->ep_type == USB_EP_ISOC){
4270 + //isoc tt
4271 + //check if mframe offset overlap
4272 + //if overlap, add 188 to the bw
4273 + cur_tt_isoc_interval = ep_interval<<3;
4274 + if(cur_tt_isoc_interval >= tt_isoc_interval){
4275 + tmp_offset = (ep_offset+cur_tt_isoc_interval) - cur_mframe;
4276 + tmp_interval = tt_isoc_interval;
4277 + }
4278 + else{
4279 + tmp_offset = (cur_mframe+tt_isoc_interval) - ep_offset;
4280 + tmp_interval = cur_tt_isoc_interval;
4281 + }
4282 + if(cur_sch_ep->is_in){
4283 + if((tmp_offset%tmp_interval >=2) && (tmp_offset%tmp_interval <= cur_sch_ep->cs_count)){
4284 + bw_required += 188;
4285 + }
4286 + }
4287 + else{
4288 + if(tmp_offset%tmp_interval <= cur_sch_ep->cs_count){
4289 + bw_required += 188;
4290 + }
4291 + }
4292 +
4293 + }
4294 + else if(cur_sch_ep->ep_type == USB_EP_INT || cur_sch_ep->ep_type == USB_EP_ISOC){
4295 + //check if mframe
4296 + if(ep_interval >= tt_isoc_interval){
4297 + tmp_offset = (ep_offset+ep_interval) - cur_mframe;
4298 + tmp_interval = tt_isoc_interval;
4299 + }
4300 + else{
4301 + tmp_offset = (cur_mframe+tt_isoc_interval) - ep_offset;
4302 + tmp_interval = ep_interval;
4303 + }
4304 + if(tmp_offset%tmp_interval == 0){
4305 + bw_required += cur_sch_ep->bw_cost;
4306 + }
4307 + }
4308 + }
4309 + bw_required += 188;
4310 + if(bw_required > max_bw){
4311 + max_bw = bw_required;
4312 + }
4313 + }
4314 + return max_bw;
4315 +}
4316 +
4317 +int count_tt_intr_bw(int interval, int frame_offset){
4318 + //check all eps in tt_intr_eps
4319 + int ret;
4320 + int i,j;
4321 + int ep_offset;
4322 + int ep_interval;
4323 + int tmp_offset;
4324 + int tmp_interval;
4325 + ret = SCH_SUCCESS;
4326 + struct sch_ep *cur_sch_ep;
4327 +
4328 + for(i=0; i<MAX_EP_NUM; i++){
4329 + cur_sch_ep = (struct sch_ep *)tt_intr_eps[i];
4330 + if(cur_sch_ep == NULL){
4331 + continue;
4332 + }
4333 + ep_offset = cur_sch_ep->offset;
4334 + ep_interval = cur_sch_ep->interval;
4335 + if(ep_interval >= interval){
4336 + tmp_offset = ep_offset + ep_interval - frame_offset;
4337 + tmp_interval = interval;
4338 + }
4339 + else{
4340 + tmp_offset = frame_offset + interval - ep_offset;
4341 + tmp_interval = ep_interval;
4342 + }
4343 +
4344 + if(tmp_offset%tmp_interval==0){
4345 + return SCH_FAIL;
4346 + }
4347 + }
4348 + return SCH_SUCCESS;
4349 +}
4350 +
4351 +struct sch_ep * mtk_xhci_scheduler_remove_ep(int dev_speed, int is_in, int isTT, int ep_type, mtk_u32 *ep){
4352 + int i;
4353 + struct sch_ep **ep_array;
4354 + struct sch_ep *cur_ep;
4355 +
4356 + if (is_in && dev_speed == USB_SPEED_SUPER) {
4357 + ep_array = (struct sch_ep **)ss_in_eps;
4358 + }
4359 + else if (dev_speed == USB_SPEED_SUPER) {
4360 + ep_array = (struct sch_ep **)ss_out_eps;
4361 + }
4362 + else if (dev_speed == USB_SPEED_HIGH || (isTT && ep_type == USB_EP_ISOC)) {
4363 + ep_array = (struct sch_ep **)hs_eps;
4364 + }
4365 + else {
4366 + ep_array = (struct sch_ep **)tt_intr_eps;
4367 + }
4368 + for (i = 0; i < MAX_EP_NUM; i++) {
4369 + cur_ep = (struct sch_ep *)ep_array[i];
4370 + if(cur_ep != NULL && cur_ep->ep == ep){
4371 + ep_array[i] = NULL;
4372 + return cur_ep;
4373 + }
4374 + }
4375 + return NULL;
4376 +}
4377 +
4378 +int mtk_xhci_scheduler_add_ep(int dev_speed, int is_in, int isTT, int ep_type, int maxp, int interval, int burst
4379 + , int mult, mtk_u32 *ep, mtk_u32 *ep_ctx, struct sch_ep *sch_ep){
4380 + mtk_u32 bPkts = 0;
4381 + mtk_u32 bCsCount = 0;
4382 + mtk_u32 bBm = 1;
4383 + mtk_u32 bOffset = 0;
4384 + mtk_u32 bRepeat = 0;
4385 + int ret;
4386 + struct mtk_xhci_ep_ctx *temp_ep_ctx;
4387 + int td_size;
4388 + int mframe_idx, frame_idx;
4389 + int bw_cost;
4390 + int cur_bw, best_bw, best_bw_idx,repeat, max_repeat, best_bw_repeat;
4391 + int cur_offset, cs_mframe;
4392 + int break_out;
4393 + int frame_interval;
4394 +
4395 + printk(KERN_ERR "add_ep parameters, dev_speed %d, is_in %d, isTT %d, ep_type %d, maxp %d, interval %d, burst %d, mult %d, ep 0x%x, ep_ctx 0x%x, sch_ep 0x%x\n", dev_speed, is_in, isTT, ep_type, maxp
4396 + , interval, burst, mult, ep, ep_ctx, sch_ep);
4397 + if(isTT && ep_type == USB_EP_INT && ((dev_speed == USB_SPEED_LOW) || (dev_speed == USB_SPEED_FULL))){
4398 + frame_interval = interval >> 3;
4399 + for(frame_idx=0; frame_idx<frame_interval; frame_idx++){
4400 + printk(KERN_ERR "check tt_intr_bw interval %d, frame_idx %d\n", frame_interval, frame_idx);
4401 + if(count_tt_intr_bw(frame_interval, frame_idx) == SCH_SUCCESS){
4402 + printk(KERN_ERR "check OK............\n");
4403 + bOffset = frame_idx<<3;
4404 + bPkts = 1;
4405 + bCsCount = 3;
4406 + bw_cost = maxp;
4407 + bRepeat = 0;
4408 + if(add_sch_ep(dev_speed, is_in, isTT, ep_type, maxp, frame_interval, burst, mult
4409 + , bOffset, bRepeat, bPkts, bCsCount, bBm, maxp, ep, sch_ep) == SCH_FAIL){
4410 + return SCH_FAIL;
4411 + }
4412 + ret = SCH_SUCCESS;
4413 + break;
4414 + }
4415 + }
4416 + }
4417 + else if(isTT && ep_type == USB_EP_ISOC){
4418 + best_bw = HS_BW_BOUND;
4419 + best_bw_idx = -1;
4420 + cur_bw = 0;
4421 + td_size = maxp;
4422 + break_out = 0;
4423 + frame_interval = interval>>3;
4424 + for(frame_idx=0; frame_idx<frame_interval && !break_out; frame_idx++){
4425 + for(mframe_idx=0; mframe_idx<8; mframe_idx++){
4426 + cur_offset = (frame_idx*8) + mframe_idx;
4427 + cur_bw = count_tt_isoc_bw(is_in, maxp, frame_interval, cur_offset, td_size);
4428 + if(cur_bw > 0 && cur_bw < best_bw){
4429 + best_bw_idx = cur_offset;
4430 + best_bw = cur_bw;
4431 + if(cur_bw == td_size || cur_bw < (HS_BW_BOUND>>1)){
4432 + break_out = 1;
4433 + break;
4434 + }
4435 + }
4436 + }
4437 + }
4438 + if(best_bw_idx == -1){
4439 + return SCH_FAIL;
4440 + }
4441 + else{
4442 + bOffset = best_bw_idx;
4443 + bPkts = 1;
4444 + bCsCount = (maxp + (188 - 1)) / 188;
4445 + if(is_in){
4446 + cs_mframe = bOffset%8 + 2 + bCsCount;
4447 + if (cs_mframe <= 6)
4448 + bCsCount += 2;
4449 + else if (cs_mframe == 7)
4450 + bCsCount++;
4451 + }
4452 + bw_cost = 188;
4453 + bRepeat = 0;
4454 + if(add_sch_ep( dev_speed, is_in, isTT, ep_type, maxp, interval, burst, mult
4455 + , bOffset, bRepeat, bPkts, bCsCount, bBm, bw_cost, ep, sch_ep) == SCH_FAIL){
4456 + return SCH_FAIL;
4457 + }
4458 + ret = SCH_SUCCESS;
4459 + }
4460 + }
4461 + else if((dev_speed == USB_SPEED_FULL || dev_speed == USB_SPEED_LOW) && ep_type == USB_EP_INT){
4462 + bPkts = 1;
4463 + ret = SCH_SUCCESS;
4464 + }
4465 + else if(dev_speed == USB_SPEED_FULL && ep_type == USB_EP_ISOC){
4466 + bPkts = 1;
4467 + ret = SCH_SUCCESS;
4468 + }
4469 + else if(dev_speed == USB_SPEED_HIGH && (ep_type == USB_EP_INT || ep_type == USB_EP_ISOC)){
4470 + best_bw = HS_BW_BOUND;
4471 + best_bw_idx = -1;
4472 + cur_bw = 0;
4473 + td_size = maxp*(burst+1);
4474 + for(cur_offset = 0; cur_offset<interval; cur_offset++){
4475 + cur_bw = count_hs_bw(ep_type, maxp, interval, cur_offset, td_size);
4476 + if(cur_bw > 0 && cur_bw < best_bw){
4477 + best_bw_idx = cur_offset;
4478 + best_bw = cur_bw;
4479 + if(cur_bw == td_size || cur_bw < (HS_BW_BOUND>>1)){
4480 + break;
4481 + }
4482 + }
4483 + }
4484 + if(best_bw_idx == -1){
4485 + return SCH_FAIL;
4486 + }
4487 + else{
4488 + bOffset = best_bw_idx;
4489 + bPkts = burst + 1;
4490 + bCsCount = 0;
4491 + bw_cost = td_size;
4492 + bRepeat = 0;
4493 + if(add_sch_ep(dev_speed, is_in, isTT, ep_type, maxp, interval, burst, mult
4494 + , bOffset, bRepeat, bPkts, bCsCount, bBm, bw_cost, ep, sch_ep) == SCH_FAIL){
4495 + return SCH_FAIL;
4496 + }
4497 + ret = SCH_SUCCESS;
4498 + }
4499 + }
4500 + else if(dev_speed == USB_SPEED_SUPER && (ep_type == USB_EP_INT || ep_type == USB_EP_ISOC)){
4501 + best_bw = SS_BW_BOUND;
4502 + best_bw_idx = -1;
4503 + cur_bw = 0;
4504 + td_size = maxp * (mult+1) * (burst+1);
4505 + if(mult == 0){
4506 + max_repeat = 0;
4507 + }
4508 + else{
4509 + max_repeat = (interval-1)/(mult+1);
4510 + }
4511 + break_out = 0;
4512 + for(frame_idx = 0; (frame_idx < interval) && !break_out; frame_idx++){
4513 + for(repeat = max_repeat; repeat >= 0; repeat--){
4514 + cur_bw = count_ss_bw(is_in, ep_type, maxp, interval, burst, mult, frame_idx
4515 + , repeat, td_size);
4516 + printk(KERN_ERR "count_ss_bw, frame_idx %d, repeat %d, td_size %d, result bw %d\n"
4517 + , frame_idx, repeat, td_size, cur_bw);
4518 + if(cur_bw > 0 && cur_bw < best_bw){
4519 + best_bw_idx = frame_idx;
4520 + best_bw_repeat = repeat;
4521 + best_bw = cur_bw;
4522 + if(cur_bw <= td_size || cur_bw < (HS_BW_BOUND>>1)){
4523 + break_out = 1;
4524 + break;
4525 + }
4526 + }
4527 + }
4528 + }
4529 + printk(KERN_ERR "final best idx %d, best repeat %d\n", best_bw_idx, best_bw_repeat);
4530 + if(best_bw_idx == -1){
4531 + return SCH_FAIL;
4532 + }
4533 + else{
4534 + bOffset = best_bw_idx;
4535 + bCsCount = 0;
4536 + bRepeat = best_bw_repeat;
4537 + if(bRepeat == 0){
4538 + bw_cost = (burst+1)*(mult+1)*maxp;
4539 + bPkts = (burst+1)*(mult+1);
4540 + }
4541 + else{
4542 + bw_cost = (burst+1)*maxp;
4543 + bPkts = (burst+1);
4544 + }
4545 + if(add_sch_ep(dev_speed, is_in, isTT, ep_type, maxp, interval, burst, mult
4546 + , bOffset, bRepeat, bPkts, bCsCount, bBm, bw_cost, ep, sch_ep) == SCH_FAIL){
4547 + return SCH_FAIL;
4548 + }
4549 + ret = SCH_SUCCESS;
4550 + }
4551 + }
4552 + else{
4553 + bPkts = 1;
4554 + ret = SCH_SUCCESS;
4555 + }
4556 + if(ret == SCH_SUCCESS){
4557 + temp_ep_ctx = (struct mtk_xhci_ep_ctx *)ep_ctx;
4558 + temp_ep_ctx->reserved[0] |= (BPKTS(bPkts) | BCSCOUNT(bCsCount) | BBM(bBm));
4559 + temp_ep_ctx->reserved[1] |= (BOFFSET(bOffset) | BREPEAT(bRepeat));
4560 +
4561 + printk(KERN_DEBUG "[DBG] BPKTS: %x, BCSCOUNT: %x, BBM: %x\n", bPkts, bCsCount, bBm);
4562 + printk(KERN_DEBUG "[DBG] BOFFSET: %x, BREPEAT: %x\n", bOffset, bRepeat);
4563 + return SCH_SUCCESS;
4564 + }
4565 + else{
4566 + return SCH_FAIL;
4567 + }
4568 +}
4569 --- /dev/null
4570 +++ b/drivers/usb/host/xhci-mtk-scheduler.h
4571 @@ -0,0 +1,77 @@
4572 +#ifndef _XHCI_MTK_SCHEDULER_H
4573 +#define _XHCI_MTK_SCHEDULER_H
4574 +
4575 +#define MTK_SCH_NEW 1
4576 +
4577 +#define SCH_SUCCESS 1
4578 +#define SCH_FAIL 0
4579 +
4580 +#define MAX_EP_NUM 64
4581 +#define SS_BW_BOUND 51000
4582 +#define HS_BW_BOUND 6144
4583 +
4584 +#define USB_EP_CONTROL 0
4585 +#define USB_EP_ISOC 1
4586 +#define USB_EP_BULK 2
4587 +#define USB_EP_INT 3
4588 +
4589 +#define USB_SPEED_LOW 1
4590 +#define USB_SPEED_FULL 2
4591 +#define USB_SPEED_HIGH 3
4592 +#define USB_SPEED_SUPER 5
4593 +
4594 +/* mtk scheduler bitmasks */
4595 +#define BPKTS(p) ((p) & 0x3f)
4596 +#define BCSCOUNT(p) (((p) & 0x7) << 8)
4597 +#define BBM(p) ((p) << 11)
4598 +#define BOFFSET(p) ((p) & 0x3fff)
4599 +#define BREPEAT(p) (((p) & 0x7fff) << 16)
4600 +
4601 +
4602 +#if 1
4603 +typedef unsigned int mtk_u32;
4604 +typedef unsigned long long mtk_u64;
4605 +#endif
4606 +
4607 +#define NULL ((void *)0)
4608 +
4609 +struct mtk_xhci_ep_ctx {
4610 + mtk_u32 ep_info;
4611 + mtk_u32 ep_info2;
4612 + mtk_u64 deq;
4613 + mtk_u32 tx_info;
4614 + /* offset 0x14 - 0x1f reserved for HC internal use */
4615 + mtk_u32 reserved[3];
4616 +};
4617 +
4618 +
4619 +struct sch_ep
4620 +{
4621 + //device info
4622 + int dev_speed;
4623 + int isTT;
4624 + //ep info
4625 + int is_in;
4626 + int ep_type;
4627 + int maxp;
4628 + int interval;
4629 + int burst;
4630 + int mult;
4631 + //scheduling info
4632 + int offset;
4633 + int repeat;
4634 + int pkts;
4635 + int cs_count;
4636 + int burst_mode;
4637 + //other
4638 + int bw_cost; //bandwidth cost in each repeat; including overhead
4639 + mtk_u32 *ep; //address of usb_endpoint pointer
4640 +};
4641 +
4642 +int mtk_xhci_scheduler_init(void);
4643 +int mtk_xhci_scheduler_add_ep(int dev_speed, int is_in, int isTT, int ep_type, int maxp, int interval, int burst
4644 + , int mult, mtk_u32 *ep, mtk_u32 *ep_ctx, struct sch_ep *sch_ep);
4645 +struct sch_ep * mtk_xhci_scheduler_remove_ep(int dev_speed, int is_in, int isTT, int ep_type, mtk_u32 *ep);
4646 +
4647 +
4648 +#endif
4649 --- /dev/null
4650 +++ b/drivers/usb/host/xhci-mtk.c
4651 @@ -0,0 +1,265 @@
4652 +#include "xhci-mtk.h"
4653 +#include "xhci-mtk-power.h"
4654 +#include "xhci.h"
4655 +#include "mtk-phy.h"
4656 +#ifdef CONFIG_C60802_SUPPORT
4657 +#include "mtk-phy-c60802.h"
4658 +#endif
4659 +#include "xhci-mtk-scheduler.h"
4660 +#include <linux/kernel.h> /* printk() */
4661 +#include <linux/slab.h>
4662 +#include <linux/delay.h>
4663 +#include <asm/uaccess.h>
4664 +#include <linux/dma-mapping.h>
4665 +#include <linux/platform_device.h>
4666 +
4667 +void setInitialReg(void )
4668 +{
4669 + __u32 __iomem *addr;
4670 + u32 temp;
4671 +
4672 + /* set SSUSB DMA burst size to 128B */
4673 + addr = SSUSB_U3_XHCI_BASE + SSUSB_HDMA_CFG;
4674 + temp = SSUSB_HDMA_CFG_MT7621_VALUE;
4675 + writel(temp, addr);
4676 +
4677 + /* extend U3 LTSSM Polling.LFPS timeout value */
4678 + addr = SSUSB_U3_XHCI_BASE + U3_LTSSM_TIMING_PARAMETER3;
4679 + temp = U3_LTSSM_TIMING_PARAMETER3_VALUE;
4680 + writel(temp, addr);
4681 +
4682 + /* EOF */
4683 + addr = SSUSB_U3_XHCI_BASE + SYNC_HS_EOF;
4684 + temp = SYNC_HS_EOF_VALUE;
4685 + writel(temp, addr);
4686 +
4687 +#if defined (CONFIG_PERIODIC_ENP)
4688 + /* HSCH_CFG1: SCH2_FIFO_DEPTH */
4689 + addr = SSUSB_U3_XHCI_BASE + HSCH_CFG1;
4690 + temp = readl(addr);
4691 + temp &= ~(0x3 << SCH2_FIFO_DEPTH_OFFSET);
4692 + writel(temp, addr);
4693 +#endif
4694 +
4695 + /* Doorbell handling */
4696 + addr = SIFSLV_IPPC + SSUSB_IP_SPAR0;
4697 + temp = 0x1;
4698 + writel(temp, addr);
4699 +
4700 + /* Set SW PLL Stable mode to 1 for U2 LPM device remote wakeup */
4701 + /* Port 0 */
4702 + addr = U2_PHY_BASE + U2_PHYD_CR1;
4703 + temp = readl(addr);
4704 + temp &= ~(0x3 << 18);
4705 + temp |= (1 << 18);
4706 + writel(temp, addr);
4707 +
4708 + /* Port 1 */
4709 + addr = U2_PHY_BASE_P1 + U2_PHYD_CR1;
4710 + temp = readl(addr);
4711 + temp &= ~(0x3 << 18);
4712 + temp |= (1 << 18);
4713 + writel(temp, addr);
4714 +}
4715 +
4716 +
4717 +void setLatchSel(void){
4718 + __u32 __iomem *latch_sel_addr;
4719 + u32 latch_sel_value;
4720 + latch_sel_addr = U3_PIPE_LATCH_SEL_ADD;
4721 + latch_sel_value = ((U3_PIPE_LATCH_TX)<<2) | (U3_PIPE_LATCH_RX);
4722 + writel(latch_sel_value, latch_sel_addr);
4723 +}
4724 +
4725 +void reinitIP(void){
4726 + __u32 __iomem *ip_reset_addr;
4727 + u32 ip_reset_value;
4728 +
4729 + enableAllClockPower();
4730 + mtk_xhci_scheduler_init();
4731 +}
4732 +
4733 +void dbg_prb_out(void){
4734 + mtk_probe_init(0x0f0f0f0f);
4735 + mtk_probe_out(0xffffffff);
4736 + mtk_probe_out(0x01010101);
4737 + mtk_probe_out(0x02020202);
4738 + mtk_probe_out(0x04040404);
4739 + mtk_probe_out(0x08080808);
4740 + mtk_probe_out(0x10101010);
4741 + mtk_probe_out(0x20202020);
4742 + mtk_probe_out(0x40404040);
4743 + mtk_probe_out(0x80808080);
4744 + mtk_probe_out(0x55555555);
4745 + mtk_probe_out(0xaaaaaaaa);
4746 +}
4747 +
4748 +
4749 +
4750 +///////////////////////////////////////////////////////////////////////////////
4751 +
4752 +#define RET_SUCCESS 0
4753 +#define RET_FAIL 1
4754 +
4755 +static int dbg_u3w(int argc, char**argv)
4756 +{
4757 + int u4TimingValue;
4758 + char u1TimingValue;
4759 + int u4TimingAddress;
4760 +
4761 + if (argc<3)
4762 + {
4763 + printk(KERN_ERR "Arg: address value\n");
4764 + return RET_FAIL;
4765 + }
4766 + u3phy_init();
4767 +
4768 + u4TimingAddress = (int)simple_strtol(argv[1], &argv[1], 16);
4769 + u4TimingValue = (int)simple_strtol(argv[2], &argv[2], 16);
4770 + u1TimingValue = u4TimingValue & 0xff;
4771 + /* access MMIO directly */
4772 + writel(u1TimingValue, u4TimingAddress);
4773 + printk(KERN_ERR "Write done\n");
4774 + return RET_SUCCESS;
4775 +
4776 +}
4777 +
4778 +static int dbg_u3r(int argc, char**argv)
4779 +{
4780 + char u1ReadTimingValue;
4781 + int u4TimingAddress;
4782 + if (argc<2)
4783 + {
4784 + printk(KERN_ERR "Arg: address\n");
4785 + return 0;
4786 + }
4787 + u3phy_init();
4788 + mdelay(500);
4789 + u4TimingAddress = (int)simple_strtol(argv[1], &argv[1], 16);
4790 + /* access MMIO directly */
4791 + u1ReadTimingValue = readl(u4TimingAddress);
4792 + printk(KERN_ERR "Value = 0x%x\n", u1ReadTimingValue);
4793 + return 0;
4794 +}
4795 +
4796 +static int dbg_u3init(int argc, char**argv)
4797 +{
4798 + int ret;
4799 + ret = u3phy_init();
4800 + printk(KERN_ERR "phy registers and operations initial done\n");
4801 + if(u3phy_ops->u2_slew_rate_calibration){
4802 + u3phy_ops->u2_slew_rate_calibration(u3phy);
4803 + }
4804 + else{
4805 + printk(KERN_ERR "WARN: PHY doesn't implement u2 slew rate calibration function\n");
4806 + }
4807 + if(u3phy_ops->init(u3phy) == PHY_TRUE)
4808 + return RET_SUCCESS;
4809 + return RET_FAIL;
4810 +}
4811 +
4812 +void dbg_setU1U2(int argc, char**argv){
4813 + struct xhci_hcd *xhci;
4814 + int u1_value;
4815 + int u2_value;
4816 + u32 port_id, temp;
4817 + u32 __iomem *addr;
4818 +
4819 + if (argc<3)
4820 + {
4821 + printk(KERN_ERR "Arg: u1value u2value\n");
4822 + return RET_FAIL;
4823 + }
4824 +
4825 + u1_value = (int)simple_strtol(argv[1], &argv[1], 10);
4826 + u2_value = (int)simple_strtol(argv[2], &argv[2], 10);
4827 + addr = (SSUSB_U3_XHCI_BASE + 0x424);
4828 + temp = readl(addr);
4829 + temp = temp & (~(0x0000ffff));
4830 + temp = temp | u1_value | (u2_value<<8);
4831 + writel(temp, addr);
4832 +}
4833 +///////////////////////////////////////////////////////////////////////////////
4834 +
4835 +int call_function(char *buf)
4836 +{
4837 + int i;
4838 + int argc;
4839 + char *argv[80];
4840 +
4841 + argc = 0;
4842 + do
4843 + {
4844 + argv[argc] = strsep(&buf, " ");
4845 + printk(KERN_DEBUG "[%d] %s\r\n", argc, argv[argc]);
4846 + argc++;
4847 + } while (buf);
4848 + if (!strcmp("dbg.r", argv[0]))
4849 + dbg_prb_out();
4850 + else if (!strcmp("dbg.u3w", argv[0]))
4851 + dbg_u3w(argc, argv);
4852 + else if (!strcmp("dbg.u3r", argv[0]))
4853 + dbg_u3r(argc, argv);
4854 + else if (!strcmp("dbg.u3i", argv[0]))
4855 + dbg_u3init(argc, argv);
4856 + else if (!strcmp("pw.u1u2", argv[0]))
4857 + dbg_setU1U2(argc, argv);
4858 + return 0;
4859 +}
4860 +
4861 +long xhci_mtk_test_unlock_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
4862 +{
4863 + char w_buf[200];
4864 + char r_buf[200] = "this is a test";
4865 + int len = 200;
4866 +
4867 + switch (cmd) {
4868 + case IOCTL_READ:
4869 + copy_to_user((char *) arg, r_buf, len);
4870 + printk(KERN_DEBUG "IOCTL_READ: %s\r\n", r_buf);
4871 + break;
4872 + case IOCTL_WRITE:
4873 + copy_from_user(w_buf, (char *) arg, len);
4874 + printk(KERN_DEBUG "IOCTL_WRITE: %s\r\n", w_buf);
4875 +
4876 + //invoke function
4877 + return call_function(w_buf);
4878 + break;
4879 + default:
4880 + return -ENOTTY;
4881 + }
4882 +
4883 + return len;
4884 +}
4885 +
4886 +int xhci_mtk_test_open(struct inode *inode, struct file *file)
4887 +{
4888 +
4889 + printk(KERN_DEBUG "xhci_mtk_test open: successful\n");
4890 + return 0;
4891 +}
4892 +
4893 +int xhci_mtk_test_release(struct inode *inode, struct file *file)
4894 +{
4895 +
4896 + printk(KERN_DEBUG "xhci_mtk_test release: successful\n");
4897 + return 0;
4898 +}
4899 +
4900 +ssize_t xhci_mtk_test_read(struct file *file, char *buf, size_t count, loff_t *ptr)
4901 +{
4902 +
4903 + printk(KERN_DEBUG "xhci_mtk_test read: returning zero bytes\n");
4904 + return 0;
4905 +}
4906 +
4907 +ssize_t xhci_mtk_test_write(struct file *file, const char *buf, size_t count, loff_t * ppos)
4908 +{
4909 +
4910 + printk(KERN_DEBUG "xhci_mtk_test write: accepting zero bytes\n");
4911 + return 0;
4912 +}
4913 +
4914 +
4915 +
4916 +
4917 --- /dev/null
4918 +++ b/drivers/usb/host/xhci-mtk.h
4919 @@ -0,0 +1,120 @@
4920 +#ifndef _XHCI_MTK_H
4921 +#define _XHCI_MTK_H
4922 +
4923 +#include <linux/usb.h>
4924 +#include "xhci.h"
4925 +
4926 +#define SSUSB_U3_XHCI_BASE 0xBE1C0000
4927 +#define SSUSB_U3_MAC_BASE 0xBE1C2400
4928 +#define SSUSB_U3_SYS_BASE 0xBE1C2600
4929 +#define SSUSB_U2_SYS_BASE 0xBE1C3400
4930 +#define SSUB_SIF_SLV_TOP 0xBE1D0000
4931 +#define SIFSLV_IPPC (SSUB_SIF_SLV_TOP + 0x700)
4932 +
4933 +#define U3_PIPE_LATCH_SEL_ADD SSUSB_U3_MAC_BASE + 0x130
4934 +#define U3_PIPE_LATCH_TX 0
4935 +#define U3_PIPE_LATCH_RX 0
4936 +
4937 +#define U3_UX_EXIT_LFPS_TIMING_PAR 0xa0
4938 +#define U3_REF_CK_PAR 0xb0
4939 +#define U3_RX_UX_EXIT_LFPS_REF_OFFSET 8
4940 +#define U3_RX_UX_EXIT_LFPS_REF 3
4941 +#define U3_REF_CK_VAL 10
4942 +
4943 +#define U3_TIMING_PULSE_CTRL 0xb4
4944 +#define CNT_1US_VALUE 63 //62.5MHz:63, 70MHz:70, 80MHz:80, 100MHz:100, 125MHz:125
4945 +
4946 +#define USB20_TIMING_PARAMETER 0x40
4947 +#define TIME_VALUE_1US 63 //62.5MHz:63, 80MHz:80, 100MHz:100, 125MHz:125
4948 +
4949 +#define LINK_PM_TIMER 0x8
4950 +#define PM_LC_TIMEOUT_VALUE 3
4951 +
4952 +#define XHCI_IMOD 0x624
4953 +#define XHCI_IMOD_MT7621_VALUE 0x10
4954 +
4955 +#define SSUSB_HDMA_CFG 0x950
4956 +#define SSUSB_HDMA_CFG_MT7621_VALUE 0x10E0E0C
4957 +
4958 +#define U3_LTSSM_TIMING_PARAMETER3 0x2514
4959 +#define U3_LTSSM_TIMING_PARAMETER3_VALUE 0x3E8012C
4960 +
4961 +#define U2_PHYD_CR1 0x64
4962 +
4963 +#define SSUSB_IP_SPAR0 0xC8
4964 +
4965 +#define SYNC_HS_EOF 0x938
4966 +#define SYNC_HS_EOF_VALUE 0x201F3
4967 +
4968 +#define HSCH_CFG1 0x960
4969 +#define SCH2_FIFO_DEPTH_OFFSET 16
4970 +
4971 +
4972 +#define SSUSB_IP_PW_CTRL (SIFSLV_IPPC+0x0)
4973 +#define SSUSB_IP_SW_RST (1<<0)
4974 +#define SSUSB_IP_PW_CTRL_1 (SIFSLV_IPPC+0x4)
4975 +#define SSUSB_IP_PDN (1<<0)
4976 +#define SSUSB_U3_CTRL(p) (SIFSLV_IPPC+0x30+(p*0x08))
4977 +#define SSUSB_U3_PORT_DIS (1<<0)
4978 +#define SSUSB_U3_PORT_PDN (1<<1)
4979 +#define SSUSB_U3_PORT_HOST_SEL (1<<2)
4980 +#define SSUSB_U3_PORT_CKBG_EN (1<<3)
4981 +#define SSUSB_U3_PORT_MAC_RST (1<<4)
4982 +#define SSUSB_U3_PORT_PHYD_RST (1<<5)
4983 +#define SSUSB_U2_CTRL(p) (SIFSLV_IPPC+(0x50)+(p*0x08))
4984 +#define SSUSB_U2_PORT_DIS (1<<0)
4985 +#define SSUSB_U2_PORT_PDN (1<<1)
4986 +#define SSUSB_U2_PORT_HOST_SEL (1<<2)
4987 +#define SSUSB_U2_PORT_CKBG_EN (1<<3)
4988 +#define SSUSB_U2_PORT_MAC_RST (1<<4)
4989 +#define SSUSB_U2_PORT_PHYD_RST (1<<5)
4990 +#define SSUSB_IP_CAP (SIFSLV_IPPC+0x024)
4991 +
4992 +#define SSUSB_U3_PORT_NUM(p) (p & 0xff)
4993 +#define SSUSB_U2_PORT_NUM(p) ((p>>8) & 0xff)
4994 +
4995 +
4996 +#define XHCI_MTK_TEST_MAJOR 234
4997 +#define DEVICE_NAME "xhci_mtk_test"
4998 +
4999 +#define CLI_MAGIC 'CLI'
5000 +#define IOCTL_READ _IOR(CLI_MAGIC, 0, int)
5001 +#define IOCTL_WRITE _IOW(CLI_MAGIC, 1, int)
5002 +
5003 +void reinitIP(void);
5004 +void setInitialReg(void);
5005 +void dbg_prb_out(void);
5006 +int call_function(char *buf);
5007 +
5008 +long xhci_mtk_test_unlock_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
5009 +int xhci_mtk_test_open(struct inode *inode, struct file *file);
5010 +int xhci_mtk_test_release(struct inode *inode, struct file *file);
5011 +ssize_t xhci_mtk_test_read(struct file *file, char *buf, size_t count, loff_t *ptr);
5012 +ssize_t xhci_mtk_test_write(struct file *file, const char *buf, size_t count, loff_t * ppos);
5013 +
5014 +/*
5015 + mediatek probe out
5016 +*/
5017 +/************************************************************************************/
5018 +
5019 +#define SW_PRB_OUT_ADDR (SIFSLV_IPPC+0xc0)
5020 +#define PRB_MODULE_SEL_ADDR (SIFSLV_IPPC+0xbc)
5021 +
5022 +static inline void mtk_probe_init(const u32 byte){
5023 + __u32 __iomem *ptr = (__u32 __iomem *) PRB_MODULE_SEL_ADDR;
5024 + writel(byte, ptr);
5025 +}
5026 +
5027 +static inline void mtk_probe_out(const u32 value){
5028 + __u32 __iomem *ptr = (__u32 __iomem *) SW_PRB_OUT_ADDR;
5029 + writel(value, ptr);
5030 +}
5031 +
5032 +static inline u32 mtk_probe_value(void){
5033 + __u32 __iomem *ptr = (__u32 __iomem *) SW_PRB_OUT_ADDR;
5034 +
5035 + return readl(ptr);
5036 +}
5037 +
5038 +
5039 +#endif
5040 --- a/drivers/usb/host/xhci-plat.c
5041 +++ b/drivers/usb/host/xhci-plat.c
5042 @@ -33,6 +33,13 @@
5043 * dev struct in order to setup MSI
5044 */
5045 xhci->quirks |= XHCI_PLAT;
5046 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5047 + /* MTK host controller gives a spurious successful event after a
5048 + * short transfer. Ignore it.
5049 + */
5050 + xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
5051 + xhci->quirks |= XHCI_LPM_SUPPORT;
5052 +#endif
5053 }
5054
5055 /* called during probe() after chip reset completes */
5056 @@ -79,7 +86,11 @@
5057
5058 driver = &xhci_plat_hc_driver;
5059
5060 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5061 + irq = XHC_IRQ;
5062 +#else
5063 irq = platform_get_irq(pdev, 0);
5064 +#endif
5065 if (irq < 0)
5066 return -ENODEV;
5067
5068 --- a/drivers/usb/host/xhci-ring.c
5069 +++ b/drivers/usb/host/xhci-ring.c
5070 @@ -254,16 +254,20 @@
5071 static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
5072 unsigned int num_trbs)
5073 {
5074 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5075 int num_trbs_in_deq_seg;
5076 +#endif
5077
5078 if (ring->num_trbs_free < num_trbs)
5079 return 0;
5080
5081 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5082 if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) {
5083 num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs;
5084 if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg)
5085 return 0;
5086 }
5087 +#endif
5088
5089 return 1;
5090 }
5091 @@ -2799,6 +2803,7 @@
5092 next = ring->enqueue;
5093
5094 while (last_trb(xhci, ring, ring->enq_seg, next)) {
5095 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5096 /* If we're not dealing with 0.95 hardware or isoc rings
5097 * on AMD 0.96 host, clear the chain bit.
5098 */
5099 @@ -2808,6 +2813,9 @@
5100 next->link.control &= cpu_to_le32(~TRB_CHAIN);
5101 else
5102 next->link.control |= cpu_to_le32(TRB_CHAIN);
5103 +#else
5104 + next->link.control &= cpu_to_le32(~TRB_CHAIN);
5105 +#endif
5106
5107 wmb();
5108 next->link.control ^= cpu_to_le32(TRB_CYCLE);
5109 @@ -2938,6 +2946,9 @@
5110 start_trb->field[3] |= cpu_to_le32(start_cycle);
5111 else
5112 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
5113 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5114 + wmb();
5115 +#endif
5116 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
5117 }
5118
5119 @@ -2993,6 +3004,29 @@
5120 return (remainder >> 10) << 17;
5121 }
5122
5123 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5124 +static u32 mtk_xhci_td_remainder(unsigned int td_transfer_size, unsigned int td_running_total, unsigned int maxp, unsigned trb_buffer_length)
5125 +{
5126 + u32 max = 31;
5127 + int remainder, td_packet_count, packet_transferred;
5128 +
5129 + //0 for the last TRB
5130 + //FIXME: need to workaround if there is ZLP in this TD
5131 + if (td_running_total + trb_buffer_length == td_transfer_size)
5132 + return 0;
5133 +
5134 + //FIXME: need to take care of high-bandwidth (MAX_ESIT)
5135 + packet_transferred = (td_running_total /*+ trb_buffer_length*/) / maxp;
5136 + td_packet_count = DIV_ROUND_UP(td_transfer_size, maxp);
5137 + remainder = td_packet_count - packet_transferred;
5138 +
5139 + if (remainder > max)
5140 + return max << 17;
5141 + else
5142 + return remainder << 17;
5143 +}
5144 +#endif
5145 +
5146 /*
5147 * For xHCI 1.0 host controllers, TD size is the number of max packet sized
5148 * packets remaining in the TD (*not* including this TRB).
5149 @@ -3130,6 +3164,7 @@
5150 }
5151
5152 /* Set the TRB length, TD size, and interrupter fields. */
5153 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5154 if (xhci->hci_version < 0x100) {
5155 remainder = xhci_td_remainder(
5156 urb->transfer_buffer_length -
5157 @@ -3139,6 +3174,12 @@
5158 trb_buff_len, total_packet_count, urb,
5159 num_trbs - 1);
5160 }
5161 +#else
5162 + if (num_trbs > 1)
5163 + remainder = mtk_xhci_td_remainder(urb->transfer_buffer_length,
5164 + running_total, urb->ep->desc.wMaxPacketSize, trb_buff_len);
5165 +#endif
5166 +
5167 length_field = TRB_LEN(trb_buff_len) |
5168 remainder |
5169 TRB_INTR_TARGET(0);
5170 @@ -3201,6 +3242,9 @@
5171 int running_total, trb_buff_len, ret;
5172 unsigned int total_packet_count;
5173 u64 addr;
5174 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5175 + int max_packet;
5176 +#endif
5177
5178 if (urb->num_sgs)
5179 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
5180 @@ -3226,6 +3270,25 @@
5181 running_total += TRB_MAX_BUFF_SIZE;
5182 }
5183 /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
5184 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5185 + switch(urb->dev->speed){
5186 + case USB_SPEED_SUPER:
5187 + max_packet = urb->ep->desc.wMaxPacketSize;
5188 + break;
5189 + case USB_SPEED_HIGH:
5190 + case USB_SPEED_FULL:
5191 + case USB_SPEED_LOW:
5192 + case USB_SPEED_WIRELESS:
5193 + case USB_SPEED_UNKNOWN:
5194 + default:
5195 + max_packet = urb->ep->desc.wMaxPacketSize & 0x7ff;
5196 + break;
5197 + }
5198 + if((urb->transfer_flags & URB_ZERO_PACKET)
5199 + && ((urb->transfer_buffer_length % max_packet) == 0)){
5200 + num_trbs++;
5201 + }
5202 +#endif
5203
5204 ret = prepare_transfer(xhci, xhci->devs[slot_id],
5205 ep_index, urb->stream_id,
5206 @@ -3285,6 +3348,7 @@
5207 field |= TRB_ISP;
5208
5209 /* Set the TRB length, TD size, and interrupter fields. */
5210 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5211 if (xhci->hci_version < 0x100) {
5212 remainder = xhci_td_remainder(
5213 urb->transfer_buffer_length -
5214 @@ -3294,6 +3358,10 @@
5215 trb_buff_len, total_packet_count, urb,
5216 num_trbs - 1);
5217 }
5218 +#else
5219 + remainder = mtk_xhci_td_remainder(urb->transfer_buffer_length, running_total, max_packet, trb_buff_len);
5220 +#endif
5221 +
5222 length_field = TRB_LEN(trb_buff_len) |
5223 remainder |
5224 TRB_INTR_TARGET(0);
5225 @@ -3383,7 +3451,11 @@
5226 field |= 0x1;
5227
5228 /* xHCI 1.0 6.4.1.2.1: Transfer Type field */
5229 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5230 + if (1) {
5231 +#else
5232 if (xhci->hci_version == 0x100) {
5233 +#endif
5234 if (urb->transfer_buffer_length > 0) {
5235 if (setup->bRequestType & USB_DIR_IN)
5236 field |= TRB_TX_TYPE(TRB_DATA_IN);
5237 @@ -3407,7 +3479,12 @@
5238 field = TRB_TYPE(TRB_DATA);
5239
5240 length_field = TRB_LEN(urb->transfer_buffer_length) |
5241 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5242 xhci_td_remainder(urb->transfer_buffer_length) |
5243 +#else
5244 + //CC: MTK style, no scatter-gather for control transfer
5245 + 0 |
5246 +#endif
5247 TRB_INTR_TARGET(0);
5248 if (urb->transfer_buffer_length > 0) {
5249 if (setup->bRequestType & USB_DIR_IN)
5250 @@ -3530,6 +3607,9 @@
5251 u64 start_addr, addr;
5252 int i, j;
5253 bool more_trbs_coming;
5254 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5255 + int max_packet;
5256 +#endif
5257
5258 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
5259
5260 @@ -3543,6 +3623,21 @@
5261 start_trb = &ep_ring->enqueue->generic;
5262 start_cycle = ep_ring->cycle_state;
5263
5264 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5265 + switch(urb->dev->speed){
5266 + case USB_SPEED_SUPER:
5267 + max_packet = urb->ep->desc.wMaxPacketSize;
5268 + break;
5269 + case USB_SPEED_HIGH:
5270 + case USB_SPEED_FULL:
5271 + case USB_SPEED_LOW:
5272 + case USB_SPEED_WIRELESS:
5273 + case USB_SPEED_UNKNOWN:
5274 + max_packet = urb->ep->desc.wMaxPacketSize & 0x7ff;
5275 + break;
5276 + }
5277 +#endif
5278 +
5279 urb_priv = urb->hcpriv;
5280 /* Queue the first TRB, even if it's zero-length */
5281 for (i = 0; i < num_tds; i++) {
5282 @@ -3614,9 +3709,13 @@
5283 } else {
5284 td->last_trb = ep_ring->enqueue;
5285 field |= TRB_IOC;
5286 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5287 + if (!(xhci->quirks & XHCI_AVOID_BEI)) {
5288 +#else
5289 if (xhci->hci_version == 0x100 &&
5290 !(xhci->quirks &
5291 XHCI_AVOID_BEI)) {
5292 +#endif
5293 /* Set BEI bit except for the last td */
5294 if (i < num_tds - 1)
5295 field |= TRB_BEI;
5296 @@ -3631,6 +3730,7 @@
5297 trb_buff_len = td_remain_len;
5298
5299 /* Set the TRB length, TD size, & interrupter fields. */
5300 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5301 if (xhci->hci_version < 0x100) {
5302 remainder = xhci_td_remainder(
5303 td_len - running_total);
5304 @@ -3640,6 +3740,10 @@
5305 total_packet_count, urb,
5306 (trbs_per_td - j - 1));
5307 }
5308 +#else
5309 + remainder = mtk_xhci_td_remainder(urb->transfer_buffer_length, running_total, max_packet, trb_buff_len);
5310 +#endif
5311 +
5312 length_field = TRB_LEN(trb_buff_len) |
5313 remainder |
5314 TRB_INTR_TARGET(0);
5315 --- a/drivers/usb/host/xhci.c
5316 +++ b/drivers/usb/host/xhci.c
5317 @@ -32,6 +32,16 @@
5318 #include "xhci.h"
5319 #include "xhci-trace.h"
5320
5321 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5322 +#include <asm/uaccess.h>
5323 +#include <linux/dma-mapping.h>
5324 +#include <linux/platform_device.h>
5325 +#include "mtk-phy.h"
5326 +#include "xhci-mtk-scheduler.h"
5327 +#include "xhci-mtk-power.h"
5328 +#include "xhci-mtk.h"
5329 +#endif
5330 +
5331 #define DRIVER_AUTHOR "Sarah Sharp"
5332 #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
5333
5334 @@ -46,6 +56,18 @@
5335 module_param(quirks, uint, S_IRUGO);
5336 MODULE_PARM_DESC(quirks, "Bit flags for quirks to be enabled as default");
5337
5338 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5339 +long xhci_mtk_test_unlock_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
5340 +static struct file_operations xhci_mtk_test_fops = {
5341 + .owner = THIS_MODULE,
5342 + .read = xhci_mtk_test_read,
5343 + .write = xhci_mtk_test_write,
5344 + .unlocked_ioctl = xhci_mtk_test_unlock_ioctl,
5345 + .open = xhci_mtk_test_open,
5346 + .release = xhci_mtk_test_release,
5347 +};
5348 +#endif
5349 +
5350 /* TODO: copied from ehci-hcd.c - can this be refactored? */
5351 /*
5352 * xhci_handshake - spin reading hc until handshake completes or fails
5353 @@ -198,7 +220,7 @@
5354 return ret;
5355 }
5356
5357 -#ifdef CONFIG_PCI
5358 +#if defined (CONFIG_PCI) && !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5359 static int xhci_free_msi(struct xhci_hcd *xhci)
5360 {
5361 int i;
5362 @@ -448,6 +470,11 @@
5363 "Attempting compliance mode recovery");
5364 hcd = xhci->shared_hcd;
5365
5366 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5367 + temp |= (1 << 31);
5368 + writel(temp, xhci->usb3_ports[i]);
5369 +#endif
5370 +
5371 if (hcd->state == HC_STATE_SUSPENDED)
5372 usb_hcd_resume_root_hub(hcd);
5373
5374 @@ -497,6 +524,9 @@
5375 {
5376 const char *dmi_product_name, *dmi_sys_vendor;
5377
5378 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5379 + return true;
5380 +#endif
5381 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
5382 dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
5383 if (!dmi_product_name || !dmi_sys_vendor)
5384 @@ -542,6 +572,10 @@
5385 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
5386 "xHCI doesn't need link TRB QUIRK");
5387 }
5388 +
5389 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5390 + mtk_xhci_scheduler_init();
5391 +#endif
5392 retval = xhci_mem_init(xhci, GFP_KERNEL);
5393 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Finished xhci_init");
5394
5395 @@ -626,7 +660,11 @@
5396 "// Set the interrupt modulation register");
5397 temp = readl(&xhci->ir_set->irq_control);
5398 temp &= ~ER_IRQ_INTERVAL_MASK;
5399 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5400 + temp |= (u32) 16;
5401 +#else
5402 temp |= (u32) 160;
5403 +#endif
5404 writel(temp, &xhci->ir_set->irq_control);
5405
5406 /* Set the HCD state before we enable the irqs */
5407 @@ -651,6 +689,9 @@
5408 xhci_queue_vendor_command(xhci, command, 0, 0, 0,
5409 TRB_TYPE(TRB_NEC_GET_FW));
5410 }
5411 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5412 + enableXhciAllPortPower(xhci);
5413 +#endif
5414 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
5415 "Finished xhci_run for USB2 roothub");
5416 return 0;
5417 @@ -1642,6 +1683,14 @@
5418 u32 drop_flag;
5419 u32 new_add_flags, new_drop_flags;
5420 int ret;
5421 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5422 +#if MTK_SCH_NEW
5423 + struct xhci_slot_ctx *slot_ctx;
5424 + struct sch_ep *sch_ep = NULL;
5425 + int isTT;
5426 + int ep_type;
5427 +#endif
5428 +#endif
5429
5430 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
5431 if (ret <= 0)
5432 @@ -1689,6 +1738,40 @@
5433
5434 xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
5435
5436 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5437 +#if MTK_SCH_NEW
5438 + slot_ctx = xhci_get_slot_ctx(xhci, xhci->devs[udev->slot_id]->out_ctx);
5439 + if ((slot_ctx->tt_info & 0xff) > 0) {
5440 + isTT = 1;
5441 + }
5442 + else {
5443 + isTT = 0;
5444 + }
5445 + if (usb_endpoint_xfer_int(&ep->desc)) {
5446 + ep_type = USB_EP_INT;
5447 + }
5448 + else if (usb_endpoint_xfer_isoc(&ep->desc)) {
5449 + ep_type = USB_EP_ISOC;
5450 + }
5451 + else if (usb_endpoint_xfer_bulk(&ep->desc)) {
5452 + ep_type = USB_EP_BULK;
5453 + }
5454 + else
5455 + ep_type = USB_EP_CONTROL;
5456 +
5457 + sch_ep = mtk_xhci_scheduler_remove_ep(udev->speed, usb_endpoint_dir_in(&ep->desc)
5458 + , isTT, ep_type, (mtk_u32 *)ep);
5459 + if (sch_ep != NULL) {
5460 + kfree(sch_ep);
5461 + }
5462 + else {
5463 + xhci_dbg(xhci, "[MTK]Doesn't find ep_sch instance when removing endpoint\n");
5464 + }
5465 +#else
5466 + mtk_xhci_scheduler_remove_ep(xhci, udev, ep);
5467 +#endif
5468 +#endif
5469 +
5470 xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
5471 (unsigned int) ep->desc.bEndpointAddress,
5472 udev->slot_id,
5473 @@ -1721,6 +1804,19 @@
5474 u32 new_add_flags, new_drop_flags;
5475 struct xhci_virt_device *virt_dev;
5476 int ret = 0;
5477 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5478 + struct xhci_ep_ctx *in_ep_ctx;
5479 +#if MTK_SCH_NEW
5480 + struct xhci_slot_ctx *slot_ctx;
5481 + struct sch_ep *sch_ep;
5482 + int isTT;
5483 + int ep_type;
5484 + int maxp = 0;
5485 + int burst = 0;
5486 + int mult = 0;
5487 + int interval;
5488 +#endif
5489 +#endif
5490
5491 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
5492 if (ret <= 0) {
5493 @@ -1787,6 +1883,56 @@
5494 return -ENOMEM;
5495 }
5496
5497 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5498 + in_ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
5499 +#if MTK_SCH_NEW
5500 + slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
5501 + if ((slot_ctx->tt_info & 0xff) > 0) {
5502 + isTT = 1;
5503 + }
5504 + else {
5505 + isTT = 0;
5506 + }
5507 + if (usb_endpoint_xfer_int(&ep->desc)) {
5508 + ep_type = USB_EP_INT;
5509 + }
5510 + else if (usb_endpoint_xfer_isoc(&ep->desc)) {
5511 + ep_type = USB_EP_ISOC;
5512 + }
5513 + else if (usb_endpoint_xfer_bulk(&ep->desc)) {
5514 + ep_type = USB_EP_BULK;
5515 + }
5516 + else
5517 + ep_type = USB_EP_CONTROL;
5518 +
5519 + if (udev->speed == USB_SPEED_FULL || udev->speed == USB_SPEED_HIGH
5520 + || udev->speed == USB_SPEED_LOW) {
5521 + maxp = ep->desc.wMaxPacketSize & 0x7FF;
5522 + burst = ep->desc.wMaxPacketSize >> 11;
5523 + mult = 0;
5524 + }
5525 + else if (udev->speed == USB_SPEED_SUPER) {
5526 + maxp = ep->desc.wMaxPacketSize & 0x7FF;
5527 + burst = ep->ss_ep_comp.bMaxBurst;
5528 + mult = ep->ss_ep_comp.bmAttributes & 0x3;
5529 + }
5530 + interval = (1 << ((in_ep_ctx->ep_info >> 16) & 0xff));
5531 + sch_ep = kmalloc(sizeof(struct sch_ep), GFP_KERNEL);
5532 + if (mtk_xhci_scheduler_add_ep(udev->speed, usb_endpoint_dir_in(&ep->desc),
5533 + isTT, ep_type, maxp, interval, burst, mult, (mtk_u32 *)ep
5534 + , (mtk_u32 *)in_ep_ctx, sch_ep) != SCH_SUCCESS) {
5535 + xhci_err(xhci, "[MTK] not enough bandwidth\n");
5536 +
5537 + return -ENOSPC;
5538 + }
5539 +#else
5540 + if (mtk_xhci_scheduler_add_ep(xhci, udev, ep, in_ep_ctx) != SCH_SUCCESS) {
5541 + xhci_err(xhci, "[MTK] not enough bandwidth\n");
5542 +
5543 + return -ENOSPC;
5544 + }
5545 +#endif
5546 +#endif
5547 ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
5548 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
5549
5550 @@ -4451,8 +4597,14 @@
5551 u16 *timeout)
5552 {
5553 if (state == USB3_LPM_U1)
5554 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5555 + if (xhci->quirks & XHCI_INTEL_HOST)
5556 +#endif
5557 return xhci_calculate_u1_timeout(xhci, udev, desc);
5558 else if (state == USB3_LPM_U2)
5559 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5560 + if (xhci->quirks & XHCI_INTEL_HOST)
5561 +#endif
5562 return xhci_calculate_u2_timeout(xhci, udev, desc);
5563
5564 return USB3_LPM_DISABLED;
5565 @@ -4837,7 +4989,9 @@
5566 hcd->self.no_sg_constraint = 1;
5567
5568 /* XHCI controllers don't stop the ep queue on short packets :| */
5569 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5570 hcd->self.no_stop_on_short = 1;
5571 +#endif
5572
5573 if (usb_hcd_is_primary_hcd(hcd)) {
5574 xhci = kzalloc(sizeof(struct xhci_hcd), GFP_KERNEL);
5575 @@ -4900,6 +5054,10 @@
5576 goto error;
5577 xhci_dbg(xhci, "Reset complete\n");
5578
5579 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5580 + setInitialReg();
5581 +#endif
5582 +
5583 /* Set dma_mask and coherent_dma_mask to 64-bits,
5584 * if xHC supports 64-bit addressing */
5585 if (HCC_64BIT_ADDR(xhci->hcc_params) &&
5586 @@ -4994,8 +5152,57 @@
5587 MODULE_AUTHOR(DRIVER_AUTHOR);
5588 MODULE_LICENSE("GPL");
5589
5590 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5591 +static struct resource xhci_resouce[] = {
5592 + {
5593 + .name = "xhci-hcd",
5594 + .start = XHC_IO_START,
5595 + .end = XHC_IO_START + XHC_IO_LENGTH -1,
5596 + .flags = IORESOURCE_MEM,
5597 + }
5598 +};
5599 +
5600 +static struct platform_device xhci_platform_dev = {
5601 + .name = "xhci-hcd",
5602 + .id = -1,
5603 + .dev = {
5604 + .coherent_dma_mask = 0xffffffff,
5605 + },
5606 + .resource = xhci_resouce,
5607 +};
5608 +#endif
5609 +
5610 static int __init xhci_hcd_init(void)
5611 {
5612 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5613 + struct platform_device *pPlatformDev;
5614 +
5615 + register_chrdev(XHCI_MTK_TEST_MAJOR, DEVICE_NAME, &xhci_mtk_test_fops);
5616 +
5617 + u3phy_init();
5618 + if (u3phy_ops->u2_slew_rate_calibration) {
5619 + u3phy_ops->u2_slew_rate_calibration(u3phy);
5620 + u3phy_ops->u2_slew_rate_calibration(u3phy_p1);
5621 + }
5622 + else{
5623 + printk(KERN_ERR "WARN: PHY doesn't implement u2 slew rate calibration function\n");
5624 + }
5625 + u3phy_ops->init(u3phy);
5626 + reinitIP();
5627 +
5628 + pPlatformDev = &xhci_platform_dev;
5629 + memset(pPlatformDev, 0, sizeof(struct platform_device));
5630 + pPlatformDev->name = "xhci-hcd";
5631 + pPlatformDev->id = -1;
5632 + pPlatformDev->dev.coherent_dma_mask = 0xffffffff;
5633 + pPlatformDev->dev.dma_mask = &pPlatformDev->dev.coherent_dma_mask;
5634 + pPlatformDev->resource = xhci_resouce;
5635 + pPlatformDev->num_resources = ARRAY_SIZE(xhci_resouce);
5636 +
5637 + platform_device_register(&xhci_platform_dev);
5638 +
5639 +#endif
5640 +
5641 /*
5642 * Check the compiler generated sizes of structures that must be laid
5643 * out in specific ways for hardware access.
5644 --- a/drivers/usb/host/xhci.h
5645 +++ b/drivers/usb/host/xhci.h
5646 @@ -32,6 +32,21 @@
5647 #include "xhci-ext-caps.h"
5648 #include "pci-quirks.h"
5649
5650 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5651 +#define XHC_IRQ (22 + 8)
5652 +#define XHC_IO_START 0x1E1C0000
5653 +#define XHC_IO_LENGTH 0x10000
5654 +/* mtk scheduler bitmasks */
5655 +#define BPKTS(p) ((p) & 0x3f)
5656 +#define BCSCOUNT(p) (((p) & 0x7) << 8)
5657 +#define BBM(p) ((p) << 11)
5658 +#define BOFFSET(p) ((p) & 0x3fff)
5659 +#define BREPEAT(p) (((p) & 0x7fff) << 16)
5660 +#endif
5661 +
5662 +
5663 +
5664 +
5665 /* xHCI PCI Configuration Registers */
5666 #define XHCI_SBRN_OFFSET (0x60)
5667
5668 @@ -1582,8 +1597,12 @@
5669 /* Compliance Mode Recovery Data */
5670 struct timer_list comp_mode_recovery_timer;
5671 u32 port_status_u0;
5672 +#ifdef CONFIG_USB_MT7621_XHCI_PLATFORM
5673 +#define COMP_MODE_RCVRY_MSECS 5000
5674 +#else
5675 /* Compliance Mode Timer Triggered every 2 seconds */
5676 #define COMP_MODE_RCVRY_MSECS 2000
5677 +#endif
5678 };
5679
5680 /* convert between an HCD pointer and the corresponding EHCI_HCD */
5681 @@ -1731,6 +1750,26 @@
5682 void xhci_free_command(struct xhci_hcd *xhci,
5683 struct xhci_command *command);
5684
5685 +#if defined (CONFIG_PCI) && !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5686 +/* xHCI PCI glue */
5687 +int xhci_register_pci(void);
5688 +void xhci_unregister_pci(void);
5689 +#else
5690 +static inline int xhci_register_pci(void) { return 0; }
5691 +static inline void xhci_unregister_pci(void) {}
5692 +#endif
5693 +
5694 +#if defined(CONFIG_USB_XHCI_PLATFORM) \
5695 + || defined(CONFIG_USB_XHCI_PLATFORM_MODULE)
5696 +int xhci_register_plat(void);
5697 +void xhci_unregister_plat(void);
5698 +#else
5699 +static inline int xhci_register_plat(void)
5700 +{ return 0; }
5701 +static inline void xhci_unregister_plat(void)
5702 +{ }
5703 +#endif
5704 +
5705 /* xHCI host controller glue */
5706 typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *);
5707 int xhci_handshake(struct xhci_hcd *xhci, void __iomem *ptr,
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