target/linux/ramips/patches-3.8/0002-MIPS-ralink-adds-irq-code.patch

   1 From 833836f47b4191e93267b91fcab38dd15affcd28 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Sun, 20 Jan 2013 22:00:50 +0100
   4 Subject: [PATCH 02/79] MIPS: ralink: adds irq code
   5
   6 All of the Ralink Wifi SoC currently supported by this series share the same
   7 interrupt controller (INTC).
   8
   9 Signed-off-by: John Crispin <blogic@openwrt.org>
  10 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
  11 Patchwork: http://patchwork.linux-mips.org/patch/4890/
  12 ---
  13  arch/mips/ralink/irq.c |  176 ++++++++++++++++++++++++++++++++++++++++++++++++
  14  1 file changed, 176 insertions(+)
  15  create mode 100644 arch/mips/ralink/irq.c
  16
  17 diff --git a/arch/mips/ralink/irq.c b/arch/mips/ralink/irq.c
  18 new file mode 100644
  19 index 0000000..e62c975
  20 --- /dev/null
  21 +++ b/arch/mips/ralink/irq.c
  22 @@ -0,0 +1,176 @@
  23 +/*
  24 + * This program is free software; you can redistribute it and/or modify it
  25 + * under the terms of the GNU General Public License version 2 as published
  26 + * by the Free Software Foundation.
  27 + *
  28 + * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
  29 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
  30 + */
  31 +
  32 +#include <linux/io.h>
  33 +#include <linux/bitops.h>
  34 +#include <linux/of_platform.h>
  35 +#include <linux/of_address.h>
  36 +#include <linux/of_irq.h>
  37 +#include <linux/irqdomain.h>
  38 +#include <linux/interrupt.h>
  39 +
  40 +#include <asm/irq_cpu.h>
  41 +#include <asm/mipsregs.h>
  42 +
  43 +#include "common.h"
  44 +
  45 +/* INTC register offsets */
  46 +#define INTC_REG_STATUS0       0x00
  47 +#define INTC_REG_STATUS1       0x04
  48 +#define INTC_REG_TYPE          0x20
  49 +#define INTC_REG_RAW_STATUS    0x30
  50 +#define INTC_REG_ENABLE                0x34
  51 +#define INTC_REG_DISABLE       0x38
  52 +
  53 +#define INTC_INT_GLOBAL                BIT(31)
  54 +
  55 +#define RALINK_CPU_IRQ_INTC    (MIPS_CPU_IRQ_BASE + 2)
  56 +#define RALINK_CPU_IRQ_FE      (MIPS_CPU_IRQ_BASE + 5)
  57 +#define RALINK_CPU_IRQ_WIFI    (MIPS_CPU_IRQ_BASE + 6)
  58 +#define RALINK_CPU_IRQ_COUNTER (MIPS_CPU_IRQ_BASE + 7)
  59 +
  60 +/* we have a cascade of 8 irqs */
  61 +#define RALINK_INTC_IRQ_BASE   8
  62 +
  63 +/* we have 32 SoC irqs */
  64 +#define RALINK_INTC_IRQ_COUNT  32
  65 +
  66 +#define RALINK_INTC_IRQ_PERFC   (RALINK_INTC_IRQ_BASE + 9)
  67 +
  68 +static void __iomem *rt_intc_membase;
  69 +
  70 +static inline void rt_intc_w32(u32 val, unsigned reg)
  71 +{
  72 +       __raw_writel(val, rt_intc_membase + reg);
  73 +}
  74 +
  75 +static inline u32 rt_intc_r32(unsigned reg)
  76 +{
  77 +       return __raw_readl(rt_intc_membase + reg);
  78 +}
  79 +
  80 +static void ralink_intc_irq_unmask(struct irq_data *d)
  81 +{
  82 +       rt_intc_w32(BIT(d->hwirq), INTC_REG_ENABLE);
  83 +}
  84 +
  85 +static void ralink_intc_irq_mask(struct irq_data *d)
  86 +{
  87 +       rt_intc_w32(BIT(d->hwirq), INTC_REG_DISABLE);
  88 +}
  89 +
  90 +static struct irq_chip ralink_intc_irq_chip = {
  91 +       .name           = "INTC",
  92 +       .irq_unmask     = ralink_intc_irq_unmask,
  93 +       .irq_mask       = ralink_intc_irq_mask,
  94 +       .irq_mask_ack   = ralink_intc_irq_mask,
  95 +};
  96 +
  97 +unsigned int __cpuinit get_c0_compare_int(void)
  98 +{
  99 +       return CP0_LEGACY_COMPARE_IRQ;
 100 +}
 101 +
 102 +static void ralink_intc_irq_handler(unsigned int irq, struct irq_desc *desc)
 103 +{
 104 +       u32 pending = rt_intc_r32(INTC_REG_STATUS0);
 105 +
 106 +       if (pending) {
 107 +               struct irq_domain *domain = irq_get_handler_data(irq);
 108 +               generic_handle_irq(irq_find_mapping(domain, __ffs(pending)));
 109 +       } else {
 110 +               spurious_interrupt();
 111 +       }
 112 +}
 113 +
 114 +asmlinkage void plat_irq_dispatch(void)
 115 +{
 116 +       unsigned long pending;
 117 +
 118 +       pending = read_c0_status() & read_c0_cause() & ST0_IM;
 119 +
 120 +       if (pending & STATUSF_IP7)
 121 +               do_IRQ(RALINK_CPU_IRQ_COUNTER);
 122 +
 123 +       else if (pending & STATUSF_IP5)
 124 +               do_IRQ(RALINK_CPU_IRQ_FE);
 125 +
 126 +       else if (pending & STATUSF_IP6)
 127 +               do_IRQ(RALINK_CPU_IRQ_WIFI);
 128 +
 129 +       else if (pending & STATUSF_IP2)
 130 +               do_IRQ(RALINK_CPU_IRQ_INTC);
 131 +
 132 +       else
 133 +               spurious_interrupt();
 134 +}
 135 +
 136 +static int intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
 137 +{
 138 +       irq_set_chip_and_handler(irq, &ralink_intc_irq_chip, handle_level_irq);
 139 +
 140 +       return 0;
 141 +}
 142 +
 143 +static const struct irq_domain_ops irq_domain_ops = {
 144 +       .xlate = irq_domain_xlate_onecell,
 145 +       .map = intc_map,
 146 +};
 147 +
 148 +static int __init intc_of_init(struct device_node *node,
 149 +                              struct device_node *parent)
 150 +{
 151 +       struct resource res;
 152 +       struct irq_domain *domain;
 153 +
 154 +       mips_cpu_irq_init();
 155 +
 156 +       if (of_address_to_resource(node, 0, &res))
 157 +               panic("Failed to get intc memory range");
 158 +
 159 +       if (request_mem_region(res.start, resource_size(&res),
 160 +                               res.name) < 0)
 161 +               pr_err("Failed to request intc memory");
 162 +
 163 +       rt_intc_membase = ioremap_nocache(res.start,
 164 +                                       resource_size(&res));
 165 +       if (!rt_intc_membase)
 166 +               panic("Failed to remap intc memory");
 167 +
 168 +       /* disable all interrupts */
 169 +       rt_intc_w32(~0, INTC_REG_DISABLE);
 170 +
 171 +       /* route all INTC interrupts to MIPS HW0 interrupt */
 172 +       rt_intc_w32(0, INTC_REG_TYPE);
 173 +
 174 +       domain = irq_domain_add_legacy(node, RALINK_INTC_IRQ_COUNT,
 175 +                       RALINK_INTC_IRQ_BASE, 0, &irq_domain_ops, NULL);
 176 +       if (!domain)
 177 +               panic("Failed to add irqdomain");
 178 +
 179 +       rt_intc_w32(INTC_INT_GLOBAL, INTC_REG_ENABLE);
 180 +
 181 +       irq_set_chained_handler(RALINK_CPU_IRQ_INTC, ralink_intc_irq_handler);
 182 +       irq_set_handler_data(RALINK_CPU_IRQ_INTC, domain);
 183 +
 184 +       cp0_perfcount_irq = irq_create_mapping(domain, 9);
 185 +
 186 +       return 0;
 187 +}
 188 +
 189 +static struct of_device_id __initdata of_irq_ids[] = {
 190 +       { .compatible = "ralink,rt2880-intc", .data = intc_of_init },
 191 +       {},
 192 +};
 193 +
 194 +void __init arch_init_irq(void)
 195 +{
 196 +       of_irq_init(of_irq_ids);
 197 +}
 198 +
 199 --
 200 1.7.10.4
 201