target/linux/ramips/patches-3.8/0007-MIPS-ralink-adds-early_printk-support.patch

   1 From 4efba82d0e4059588f2b2fc0ac2576eaf37f1d22 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Sun, 20 Jan 2013 22:02:55 +0100
   4 Subject: [PATCH 07/79] MIPS: ralink: adds early_printk support
   5
   6 Add the code needed to make early printk work.
   7
   8 Signed-off-by: John Crispin <blogic@openwrt.org>
   9 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
  10 Patchwork: http://patchwork.linux-mips.org/patch/4897/
  11 ---
  12  arch/mips/ralink/early_printk.c |   44 +++++++++++++++++++++++++++++++++++++++
  13  1 file changed, 44 insertions(+)
  14  create mode 100644 arch/mips/ralink/early_printk.c
  15
  16 diff --git a/arch/mips/ralink/early_printk.c b/arch/mips/ralink/early_printk.c
  17 new file mode 100644
  18 index 0000000..c4ae47e
  19 --- /dev/null
  20 +++ b/arch/mips/ralink/early_printk.c
  21 @@ -0,0 +1,44 @@
  22 +/*
  23 + *  This program is free software; you can redistribute it and/or modify it
  24 + *  under the terms of the GNU General Public License version 2 as published
  25 + *  by the Free Software Foundation.
  26 + *
  27 + *  Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
  28 + */
  29 +
  30 +#include <linux/io.h>
  31 +#include <linux/serial_reg.h>
  32 +
  33 +#include <asm/addrspace.h>
  34 +
  35 +#define EARLY_UART_BASE         0x10000c00
  36 +
  37 +#define UART_REG_RX             0x00
  38 +#define UART_REG_TX             0x04
  39 +#define UART_REG_IER            0x08
  40 +#define UART_REG_IIR            0x0c
  41 +#define UART_REG_FCR            0x10
  42 +#define UART_REG_LCR            0x14
  43 +#define UART_REG_MCR            0x18
  44 +#define UART_REG_LSR            0x1c
  45 +
  46 +static __iomem void *uart_membase = (__iomem void *) KSEG1ADDR(EARLY_UART_BASE);
  47 +
  48 +static inline void uart_w32(u32 val, unsigned reg)
  49 +{
  50 +       __raw_writel(val, uart_membase + reg);
  51 +}
  52 +
  53 +static inline u32 uart_r32(unsigned reg)
  54 +{
  55 +       return __raw_readl(uart_membase + reg);
  56 +}
  57 +
  58 +void prom_putchar(unsigned char ch)
  59 +{
  60 +       while ((uart_r32(UART_REG_LSR) & UART_LSR_THRE) == 0)
  61 +               ;
  62 +       uart_w32(ch, UART_REG_TX);
  63 +       while ((uart_r32(UART_REG_LSR) & UART_LSR_THRE) == 0)
  64 +               ;
  65 +}
  66 --
  67 1.7.10.4
  68