target/linux/ramips/patches-3.8/0019-MIPS-ralink-fix-RT305x-clock-setup.patch

   1 From 853823a469a8123657bf32bc5e1843c40529a20d Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Fri, 22 Mar 2013 19:25:59 +0100
   4 Subject: [PATCH 19/79] MIPS: ralink: fix RT305x clock setup
   5
   6 Add a few missing clocks.
   7
   8 Signed-off-by: John Crispin <blogic@openwrt.org>
   9 Acked-by: Gabor Juhos <juhosg@openwrt.org>
  10 Patchwork: http://patchwork.linux-mips.org/patch/5167/
  11 ---
  12  arch/mips/ralink/rt305x.c |   12 ++++++++++++
  13  1 file changed, 12 insertions(+)
  14
  15 diff --git a/arch/mips/ralink/rt305x.c b/arch/mips/ralink/rt305x.c
  16 index 0a4bbdc..5d49a54 100644
  17 --- a/arch/mips/ralink/rt305x.c
  18 +++ b/arch/mips/ralink/rt305x.c
  19 @@ -124,6 +124,8 @@ struct ralink_pinmux gpio_pinmux = {
  20  void __init ralink_clk_init(void)
  21  {
  22         unsigned long cpu_rate, sys_rate, wdt_rate, uart_rate;
  23 +       unsigned long wmac_rate = 40000000;
  24 +
  25         u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
  26
  27         if (soc_is_rt305x() || soc_is_rt3350()) {
  28 @@ -176,11 +178,21 @@ void __init ralink_clk_init(void)
  29                 BUG();
  30         }
  31
  32 +       if (soc_is_rt3352() || soc_is_rt5350()) {
  33 +               u32 val = rt_sysc_r32(RT3352_SYSC_REG_SYSCFG0);
  34 +
  35 +               if (!(val & RT3352_CLKCFG0_XTAL_SEL))
  36 +                       wmac_rate = 20000000;
  37 +       }
  38 +
  39         ralink_clk_add("cpu", cpu_rate);
  40         ralink_clk_add("10000b00.spi", sys_rate);
  41         ralink_clk_add("10000100.timer", wdt_rate);
  42 +       ralink_clk_add("10000120.watchdog", wdt_rate);
  43         ralink_clk_add("10000500.uart", uart_rate);
  44         ralink_clk_add("10000c00.uartlite", uart_rate);
  45 +       ralink_clk_add("10100000.ethernet", sys_rate);
  46 +       ralink_clk_add("10180000.wmac", wmac_rate);
  47  }
  48
  49  void __init ralink_of_remap(void)
  50 --
  51 1.7.10.4
  52