target/linux/ramips/patches-3.8/0028-MIPS-ralink-adds-support-for-RT3883-SoC-family.patch

   1 From c75f4a5af758494595fded27efb95732365d10db Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Sun, 27 Jan 2013 09:39:02 +0100
   4 Subject: [PATCH 28/79] MIPS: ralink: adds support for RT3883 SoC family
   5
   6 Add support code for rt3883 SOC.
   7
   8 The code detects the SoC and registers the clk / pinmux settings.
   9
  10 Signed-off-by: John Crispin <blogic@openwrt.org>
  11 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
  12 Patchwork: http://patchwork.linux-mips.org/patch/5185/
  13 ---
  14  arch/mips/include/asm/mach-ralink/rt3883.h |  247 ++++++++++++++++++++++++++++
  15  arch/mips/ralink/Kconfig                   |    5 +
  16  arch/mips/ralink/Makefile                  |    1 +
  17  arch/mips/ralink/Platform                  |    5 +
  18  arch/mips/ralink/rt3883.c                  |  242 +++++++++++++++++++++++++++
  19  5 files changed, 500 insertions(+)
  20  create mode 100644 arch/mips/include/asm/mach-ralink/rt3883.h
  21  create mode 100644 arch/mips/ralink/rt3883.c
  22
  23 diff --git a/arch/mips/include/asm/mach-ralink/rt3883.h b/arch/mips/include/asm/mach-ralink/rt3883.h
  24 new file mode 100644
  25 index 0000000..b91c6c1
  26 --- /dev/null
  27 +++ b/arch/mips/include/asm/mach-ralink/rt3883.h
  28 @@ -0,0 +1,247 @@
  29 +/*
  30 + * Ralink RT3662/RT3883 SoC register definitions
  31 + *
  32 + * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
  33 + *
  34 + * This program is free software; you can redistribute it and/or modify it
  35 + * under the terms of the GNU General Public License version 2 as published
  36 + * by the Free Software Foundation.
  37 + */
  38 +
  39 +#ifndef _RT3883_REGS_H_
  40 +#define _RT3883_REGS_H_
  41 +
  42 +#include <linux/bitops.h>
  43 +
  44 +#define RT3883_SDRAM_BASE      0x00000000
  45 +#define RT3883_SYSC_BASE       0x10000000
  46 +#define RT3883_TIMER_BASE      0x10000100
  47 +#define RT3883_INTC_BASE       0x10000200
  48 +#define RT3883_MEMC_BASE       0x10000300
  49 +#define RT3883_UART0_BASE      0x10000500
  50 +#define RT3883_PIO_BASE                0x10000600
  51 +#define RT3883_FSCC_BASE       0x10000700
  52 +#define RT3883_NANDC_BASE      0x10000810
  53 +#define RT3883_I2C_BASE                0x10000900
  54 +#define RT3883_I2S_BASE                0x10000a00
  55 +#define RT3883_SPI_BASE                0x10000b00
  56 +#define RT3883_UART1_BASE      0x10000c00
  57 +#define RT3883_PCM_BASE                0x10002000
  58 +#define RT3883_GDMA_BASE       0x10002800
  59 +#define RT3883_CODEC1_BASE     0x10003000
  60 +#define RT3883_CODEC2_BASE     0x10003800
  61 +#define RT3883_FE_BASE         0x10100000
  62 +#define RT3883_ROM_BASE                0x10118000
  63 +#define RT3883_USBDEV_BASE     0x10112000
  64 +#define RT3883_PCI_BASE                0x10140000
  65 +#define RT3883_WLAN_BASE       0x10180000
  66 +#define RT3883_USBHOST_BASE    0x101c0000
  67 +#define RT3883_BOOT_BASE       0x1c000000
  68 +#define RT3883_SRAM_BASE       0x1e000000
  69 +#define RT3883_PCIMEM_BASE     0x20000000
  70 +
  71 +#define RT3883_EHCI_BASE       (RT3883_USBHOST_BASE)
  72 +#define RT3883_OHCI_BASE       (RT3883_USBHOST_BASE + 0x1000)
  73 +
  74 +#define RT3883_SYSC_SIZE       0x100
  75 +#define RT3883_TIMER_SIZE      0x100
  76 +#define RT3883_INTC_SIZE       0x100
  77 +#define RT3883_MEMC_SIZE       0x100
  78 +#define RT3883_UART0_SIZE      0x100
  79 +#define RT3883_UART1_SIZE      0x100
  80 +#define RT3883_PIO_SIZE                0x100
  81 +#define RT3883_FSCC_SIZE       0x100
  82 +#define RT3883_NANDC_SIZE      0x0f0
  83 +#define RT3883_I2C_SIZE                0x100
  84 +#define RT3883_I2S_SIZE                0x100
  85 +#define RT3883_SPI_SIZE                0x100
  86 +#define RT3883_PCM_SIZE                0x800
  87 +#define RT3883_GDMA_SIZE       0x800
  88 +#define RT3883_CODEC1_SIZE     0x800
  89 +#define RT3883_CODEC2_SIZE     0x800
  90 +#define RT3883_FE_SIZE         0x10000
  91 +#define RT3883_ROM_SIZE                0x4000
  92 +#define RT3883_USBDEV_SIZE     0x4000
  93 +#define RT3883_PCI_SIZE                0x40000
  94 +#define RT3883_WLAN_SIZE       0x40000
  95 +#define RT3883_USBHOST_SIZE    0x40000
  96 +#define RT3883_BOOT_SIZE       (32 * 1024 * 1024)
  97 +#define RT3883_SRAM_SIZE       (32 * 1024 * 1024)
  98 +
  99 +/* SYSC registers */
 100 +#define RT3883_SYSC_REG_CHIPID0_3      0x00    /* Chip ID 0 */
 101 +#define RT3883_SYSC_REG_CHIPID4_7      0x04    /* Chip ID 1 */
 102 +#define RT3883_SYSC_REG_REVID          0x0c    /* Chip Revision Identification */
 103 +#define RT3883_SYSC_REG_SYSCFG0                0x10    /* System Configuration 0 */
 104 +#define RT3883_SYSC_REG_SYSCFG1                0x14    /* System Configuration 1 */
 105 +#define RT3883_SYSC_REG_CLKCFG0                0x2c    /* Clock Configuration 0 */
 106 +#define RT3883_SYSC_REG_CLKCFG1                0x30    /* Clock Configuration 1 */
 107 +#define RT3883_SYSC_REG_RSTCTRL                0x34    /* Reset Control*/
 108 +#define RT3883_SYSC_REG_RSTSTAT                0x38    /* Reset Status*/
 109 +#define RT3883_SYSC_REG_USB_PS         0x5c    /* USB Power saving control */
 110 +#define RT3883_SYSC_REG_GPIO_MODE      0x60    /* GPIO Purpose Select */
 111 +#define RT3883_SYSC_REG_PCIE_CLK_GEN0  0x7c
 112 +#define RT3883_SYSC_REG_PCIE_CLK_GEN1  0x80
 113 +#define RT3883_SYSC_REG_PCIE_CLK_GEN2  0x84
 114 +#define RT3883_SYSC_REG_PMU            0x88
 115 +#define RT3883_SYSC_REG_PMU1           0x8c
 116 +
 117 +#define RT3883_CHIP_NAME0              0x38335452
 118 +#define RT3883_CHIP_NAME1              0x20203338
 119 +
 120 +#define RT3883_REVID_VER_ID_MASK       0x0f
 121 +#define RT3883_REVID_VER_ID_SHIFT      8
 122 +#define RT3883_REVID_ECO_ID_MASK       0x0f
 123 +
 124 +#define RT3883_SYSCFG0_DRAM_TYPE_DDR2  BIT(17)
 125 +#define RT3883_SYSCFG0_CPUCLK_SHIFT    8
 126 +#define RT3883_SYSCFG0_CPUCLK_MASK     0x3
 127 +#define RT3883_SYSCFG0_CPUCLK_250      0x0
 128 +#define RT3883_SYSCFG0_CPUCLK_384      0x1
 129 +#define RT3883_SYSCFG0_CPUCLK_480      0x2
 130 +#define RT3883_SYSCFG0_CPUCLK_500      0x3
 131 +
 132 +#define RT3883_SYSCFG1_USB0_HOST_MODE  BIT(10)
 133 +#define RT3883_SYSCFG1_PCIE_RC_MODE    BIT(8)
 134 +#define RT3883_SYSCFG1_PCI_HOST_MODE   BIT(7)
 135 +#define RT3883_SYSCFG1_PCI_66M_MODE    BIT(6)
 136 +#define RT3883_SYSCFG1_GPIO2_AS_WDT_OUT        BIT(2)
 137 +
 138 +#define RT3883_CLKCFG1_PCIE_CLK_EN     BIT(21)
 139 +#define RT3883_CLKCFG1_UPHY1_CLK_EN    BIT(20)
 140 +#define RT3883_CLKCFG1_PCI_CLK_EN      BIT(19)
 141 +#define RT3883_CLKCFG1_UPHY0_CLK_EN    BIT(18)
 142 +
 143 +#define RT3883_GPIO_MODE_I2C           BIT(0)
 144 +#define RT3883_GPIO_MODE_SPI           BIT(1)
 145 +#define RT3883_GPIO_MODE_UART0_SHIFT   2
 146 +#define RT3883_GPIO_MODE_UART0_MASK    0x7
 147 +#define RT3883_GPIO_MODE_UART0(x)      ((x) << RT3883_GPIO_MODE_UART0_SHIFT)
 148 +#define RT3883_GPIO_MODE_UARTF         0x0
 149 +#define RT3883_GPIO_MODE_PCM_UARTF     0x1
 150 +#define RT3883_GPIO_MODE_PCM_I2S       0x2
 151 +#define RT3883_GPIO_MODE_I2S_UARTF     0x3
 152 +#define RT3883_GPIO_MODE_PCM_GPIO      0x4
 153 +#define RT3883_GPIO_MODE_GPIO_UARTF    0x5
 154 +#define RT3883_GPIO_MODE_GPIO_I2S      0x6
 155 +#define RT3883_GPIO_MODE_GPIO          0x7
 156 +#define RT3883_GPIO_MODE_UART1         BIT(5)
 157 +#define RT3883_GPIO_MODE_JTAG          BIT(6)
 158 +#define RT3883_GPIO_MODE_MDIO          BIT(7)
 159 +#define RT3883_GPIO_MODE_GE1           BIT(9)
 160 +#define RT3883_GPIO_MODE_GE2           BIT(10)
 161 +#define RT3883_GPIO_MODE_PCI_SHIFT     11
 162 +#define RT3883_GPIO_MODE_PCI_MASK      0x7
 163 +#define RT3883_GPIO_MODE_PCI           (RT3883_GPIO_MODE_PCI_MASK << RT3883_GPIO_MODE_PCI_SHIFT)
 164 +#define RT3883_GPIO_MODE_LNA_A_SHIFT   16
 165 +#define RT3883_GPIO_MODE_LNA_A_MASK    0x3
 166 +#define _RT3883_GPIO_MODE_LNA_A(_x)    ((_x) << RT3883_GPIO_MODE_LNA_A_SHIFT)
 167 +#define RT3883_GPIO_MODE_LNA_A_GPIO    0x3
 168 +#define RT3883_GPIO_MODE_LNA_A         _RT3883_GPIO_MODE_LNA_A(RT3883_GPIO_MODE_LNA_A_MASK)
 169 +#define RT3883_GPIO_MODE_LNA_G_SHIFT   18
 170 +#define RT3883_GPIO_MODE_LNA_G_MASK    0x3
 171 +#define _RT3883_GPIO_MODE_LNA_G(_x)    ((_x) << RT3883_GPIO_MODE_LNA_G_SHIFT)
 172 +#define RT3883_GPIO_MODE_LNA_G_GPIO    0x3
 173 +#define RT3883_GPIO_MODE_LNA_G         _RT3883_GPIO_MODE_LNA_G(RT3883_GPIO_MODE_LNA_G_MASK)
 174 +
 175 +#define RT3883_GPIO_I2C_SD             1
 176 +#define RT3883_GPIO_I2C_SCLK           2
 177 +#define RT3883_GPIO_SPI_CS0            3
 178 +#define RT3883_GPIO_SPI_CLK            4
 179 +#define RT3883_GPIO_SPI_MOSI           5
 180 +#define RT3883_GPIO_SPI_MISO           6
 181 +#define RT3883_GPIO_7                  7
 182 +#define RT3883_GPIO_10                 10
 183 +#define RT3883_GPIO_14                 14
 184 +#define RT3883_GPIO_UART1_TXD          15
 185 +#define RT3883_GPIO_UART1_RXD          16
 186 +#define RT3883_GPIO_JTAG_TDO           17
 187 +#define RT3883_GPIO_JTAG_TDI           18
 188 +#define RT3883_GPIO_JTAG_TMS           19
 189 +#define RT3883_GPIO_JTAG_TCLK          20
 190 +#define RT3883_GPIO_JTAG_TRST_N                21
 191 +#define RT3883_GPIO_MDIO_MDC           22
 192 +#define RT3883_GPIO_MDIO_MDIO          23
 193 +#define RT3883_GPIO_LNA_PE_A0          32
 194 +#define RT3883_GPIO_LNA_PE_A1          33
 195 +#define RT3883_GPIO_LNA_PE_A2          34
 196 +#define RT3883_GPIO_LNA_PE_G0          35
 197 +#define RT3883_GPIO_LNA_PE_G1          36
 198 +#define RT3883_GPIO_LNA_PE_G2          37
 199 +#define RT3883_GPIO_PCI_AD0            40
 200 +#define RT3883_GPIO_PCI_AD31           71
 201 +#define RT3883_GPIO_GE2_TXD0           72
 202 +#define RT3883_GPIO_GE2_TXD1           73
 203 +#define RT3883_GPIO_GE2_TXD2           74
 204 +#define RT3883_GPIO_GE2_TXD3           75
 205 +#define RT3883_GPIO_GE2_TXEN           76
 206 +#define RT3883_GPIO_GE2_TXCLK          77
 207 +#define RT3883_GPIO_GE2_RXD0           78
 208 +#define RT3883_GPIO_GE2_RXD1           79
 209 +#define RT3883_GPIO_GE2_RXD2           80
 210 +#define RT3883_GPIO_GE2_RXD3           81
 211 +#define RT3883_GPIO_GE2_RXDV           82
 212 +#define RT3883_GPIO_GE2_RXCLK          83
 213 +#define RT3883_GPIO_GE1_TXD0           84
 214 +#define RT3883_GPIO_GE1_TXD1           85
 215 +#define RT3883_GPIO_GE1_TXD2           86
 216 +#define RT3883_GPIO_GE1_TXD3           87
 217 +#define RT3883_GPIO_GE1_TXEN           88
 218 +#define RT3883_GPIO_GE1_TXCLK          89
 219 +#define RT3883_GPIO_GE1_RXD0           90
 220 +#define RT3883_GPIO_GE1_RXD1           91
 221 +#define RT3883_GPIO_GE1_RXD2           92
 222 +#define RT3883_GPIO_GE1_RXD3           93
 223 +#define RT3883_GPIO_GE1_RXDV           94
 224 +#define RT3883_GPIO_GE1_RXCLK  95
 225 +
 226 +#define RT3883_RSTCTRL_PCIE_PCI_PDM    BIT(27)
 227 +#define RT3883_RSTCTRL_FLASH           BIT(26)
 228 +#define RT3883_RSTCTRL_UDEV            BIT(25)
 229 +#define RT3883_RSTCTRL_PCI             BIT(24)
 230 +#define RT3883_RSTCTRL_PCIE            BIT(23)
 231 +#define RT3883_RSTCTRL_UHST            BIT(22)
 232 +#define RT3883_RSTCTRL_FE              BIT(21)
 233 +#define RT3883_RSTCTRL_WLAN            BIT(20)
 234 +#define RT3883_RSTCTRL_UART1           BIT(29)
 235 +#define RT3883_RSTCTRL_SPI             BIT(18)
 236 +#define RT3883_RSTCTRL_I2S             BIT(17)
 237 +#define RT3883_RSTCTRL_I2C             BIT(16)
 238 +#define RT3883_RSTCTRL_NAND            BIT(15)
 239 +#define RT3883_RSTCTRL_DMA             BIT(14)
 240 +#define RT3883_RSTCTRL_PIO             BIT(13)
 241 +#define RT3883_RSTCTRL_UART            BIT(12)
 242 +#define RT3883_RSTCTRL_PCM             BIT(11)
 243 +#define RT3883_RSTCTRL_MC              BIT(10)
 244 +#define RT3883_RSTCTRL_INTC            BIT(9)
 245 +#define RT3883_RSTCTRL_TIMER           BIT(8)
 246 +#define RT3883_RSTCTRL_SYS             BIT(0)
 247 +
 248 +#define RT3883_INTC_INT_SYSCTL BIT(0)
 249 +#define RT3883_INTC_INT_TIMER0 BIT(1)
 250 +#define RT3883_INTC_INT_TIMER1 BIT(2)
 251 +#define RT3883_INTC_INT_IA     BIT(3)
 252 +#define RT3883_INTC_INT_PCM    BIT(4)
 253 +#define RT3883_INTC_INT_UART0  BIT(5)
 254 +#define RT3883_INTC_INT_PIO    BIT(6)
 255 +#define RT3883_INTC_INT_DMA    BIT(7)
 256 +#define RT3883_INTC_INT_NAND   BIT(8)
 257 +#define RT3883_INTC_INT_PERFC  BIT(9)
 258 +#define RT3883_INTC_INT_I2S    BIT(10)
 259 +#define RT3883_INTC_INT_UART1  BIT(12)
 260 +#define RT3883_INTC_INT_UHST   BIT(18)
 261 +#define RT3883_INTC_INT_UDEV   BIT(19)
 262 +
 263 +/* FLASH/SRAM/Codec Controller registers */
 264 +#define RT3883_FSCC_REG_FLASH_CFG0     0x00
 265 +#define RT3883_FSCC_REG_FLASH_CFG1     0x04
 266 +#define RT3883_FSCC_REG_CODEC_CFG0     0x40
 267 +#define RT3883_FSCC_REG_CODEC_CFG1     0x44
 268 +
 269 +#define RT3883_FLASH_CFG_WIDTH_SHIFT   26
 270 +#define RT3883_FLASH_CFG_WIDTH_MASK    0x3
 271 +#define RT3883_FLASH_CFG_WIDTH_8BIT    0x0
 272 +#define RT3883_FLASH_CFG_WIDTH_16BIT   0x1
 273 +#define RT3883_FLASH_CFG_WIDTH_32BIT   0x2
 274 +
 275 +#endif /* _RT3883_REGS_H_ */
 276 diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig
 277 index 6723b94..ce57d3e 100644
 278 --- a/arch/mips/ralink/Kconfig
 279 +++ b/arch/mips/ralink/Kconfig
 280 @@ -15,6 +15,11 @@ choice
 281                 select USB_ARCH_HAS_OHCI
 282                 select USB_ARCH_HAS_EHCI
 283
 284 +       config SOC_RT3883
 285 +               bool "RT3883"
 286 +               select USB_ARCH_HAS_OHCI
 287 +               select USB_ARCH_HAS_EHCI
 288 +
 289  endchoice
 290
 291  choice
 292 diff --git a/arch/mips/ralink/Makefile b/arch/mips/ralink/Makefile
 293 index 6d826f2..ba9669c 100644
 294 --- a/arch/mips/ralink/Makefile
 295 +++ b/arch/mips/ralink/Makefile
 296 @@ -10,6 +10,7 @@ obj-y := prom.o of.o reset.o clk.o irq.o
 297
 298  obj-$(CONFIG_SOC_RT288X) += rt288x.o
 299  obj-$(CONFIG_SOC_RT305X) += rt305x.o
 300 +obj-$(CONFIG_SOC_RT3883) += rt3883.o
 301
 302  obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
 303
 304 diff --git a/arch/mips/ralink/Platform b/arch/mips/ralink/Platform
 305 index 3f49e51..f67c08d 100644
 306 --- a/arch/mips/ralink/Platform
 307 +++ b/arch/mips/ralink/Platform
 308 @@ -13,3 +13,8 @@ load-$(CONFIG_SOC_RT288X)     += 0xffffffff88000000
 309  # Ralink RT305x
 310  #
 311  load-$(CONFIG_SOC_RT305X)      += 0xffffffff80000000
 312 +
 313 +#
 314 +# Ralink RT3883
 315 +#
 316 +load-$(CONFIG_SOC_RT3883)      += 0xffffffff80000000
 317 diff --git a/arch/mips/ralink/rt3883.c b/arch/mips/ralink/rt3883.c
 318 new file mode 100644
 319 index 0000000..2d90aa9
 320 --- /dev/null
 321 +++ b/arch/mips/ralink/rt3883.c
 322 @@ -0,0 +1,242 @@
 323 +/*
 324 + * This program is free software; you can redistribute it and/or modify it
 325 + * under the terms of the GNU General Public License version 2 as published
 326 + * by the Free Software Foundation.
 327 + *
 328 + * Parts of this file are based on Ralink's 2.6.21 BSP
 329 + *
 330 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
 331 + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
 332 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
 333 + */
 334 +
 335 +#include <linux/kernel.h>
 336 +#include <linux/init.h>
 337 +#include <linux/module.h>
 338 +
 339 +#include <asm/mipsregs.h>
 340 +#include <asm/mach-ralink/ralink_regs.h>
 341 +#include <asm/mach-ralink/rt3883.h>
 342 +
 343 +#include "common.h"
 344 +
 345 +static struct ralink_pinmux_grp mode_mux[] = {
 346 +       {
 347 +               .name = "i2c",
 348 +               .mask = RT3883_GPIO_MODE_I2C,
 349 +               .gpio_first = RT3883_GPIO_I2C_SD,
 350 +               .gpio_last = RT3883_GPIO_I2C_SCLK,
 351 +       }, {
 352 +               .name = "spi",
 353 +               .mask = RT3883_GPIO_MODE_SPI,
 354 +               .gpio_first = RT3883_GPIO_SPI_CS0,
 355 +               .gpio_last = RT3883_GPIO_SPI_MISO,
 356 +       }, {
 357 +               .name = "uartlite",
 358 +               .mask = RT3883_GPIO_MODE_UART1,
 359 +               .gpio_first = RT3883_GPIO_UART1_TXD,
 360 +               .gpio_last = RT3883_GPIO_UART1_RXD,
 361 +       }, {
 362 +               .name = "jtag",
 363 +               .mask = RT3883_GPIO_MODE_JTAG,
 364 +               .gpio_first = RT3883_GPIO_JTAG_TDO,
 365 +               .gpio_last = RT3883_GPIO_JTAG_TCLK,
 366 +       }, {
 367 +               .name = "mdio",
 368 +               .mask = RT3883_GPIO_MODE_MDIO,
 369 +               .gpio_first = RT3883_GPIO_MDIO_MDC,
 370 +               .gpio_last = RT3883_GPIO_MDIO_MDIO,
 371 +       }, {
 372 +               .name = "ge1",
 373 +               .mask = RT3883_GPIO_MODE_GE1,
 374 +               .gpio_first = RT3883_GPIO_GE1_TXD0,
 375 +               .gpio_last = RT3883_GPIO_GE1_RXCLK,
 376 +       }, {
 377 +               .name = "ge2",
 378 +               .mask = RT3883_GPIO_MODE_GE2,
 379 +               .gpio_first = RT3883_GPIO_GE2_TXD0,
 380 +               .gpio_last = RT3883_GPIO_GE2_RXCLK,
 381 +       }, {
 382 +               .name = "pci",
 383 +               .mask = RT3883_GPIO_MODE_PCI,
 384 +               .gpio_first = RT3883_GPIO_PCI_AD0,
 385 +               .gpio_last = RT3883_GPIO_PCI_AD31,
 386 +       }, {
 387 +               .name = "lna a",
 388 +               .mask = RT3883_GPIO_MODE_LNA_A,
 389 +               .gpio_first = RT3883_GPIO_LNA_PE_A0,
 390 +               .gpio_last = RT3883_GPIO_LNA_PE_A2,
 391 +       }, {
 392 +               .name = "lna g",
 393 +               .mask = RT3883_GPIO_MODE_LNA_G,
 394 +               .gpio_first = RT3883_GPIO_LNA_PE_G0,
 395 +               .gpio_last = RT3883_GPIO_LNA_PE_G2,
 396 +       }, {0}
 397 +};
 398 +
 399 +static struct ralink_pinmux_grp uart_mux[] = {
 400 +       {
 401 +               .name = "uartf",
 402 +               .mask = RT3883_GPIO_MODE_UARTF,
 403 +               .gpio_first = RT3883_GPIO_7,
 404 +               .gpio_last = RT3883_GPIO_14,
 405 +       }, {
 406 +               .name = "pcm uartf",
 407 +               .mask = RT3883_GPIO_MODE_PCM_UARTF,
 408 +               .gpio_first = RT3883_GPIO_7,
 409 +               .gpio_last = RT3883_GPIO_14,
 410 +       }, {
 411 +               .name = "pcm i2s",
 412 +               .mask = RT3883_GPIO_MODE_PCM_I2S,
 413 +               .gpio_first = RT3883_GPIO_7,
 414 +               .gpio_last = RT3883_GPIO_14,
 415 +       }, {
 416 +               .name = "i2s uartf",
 417 +               .mask = RT3883_GPIO_MODE_I2S_UARTF,
 418 +               .gpio_first = RT3883_GPIO_7,
 419 +               .gpio_last = RT3883_GPIO_14,
 420 +       }, {
 421 +               .name = "pcm gpio",
 422 +               .mask = RT3883_GPIO_MODE_PCM_GPIO,
 423 +               .gpio_first = RT3883_GPIO_11,
 424 +               .gpio_last = RT3883_GPIO_14,
 425 +       }, {
 426 +               .name = "gpio uartf",
 427 +               .mask = RT3883_GPIO_MODE_GPIO_UARTF,
 428 +               .gpio_first = RT3883_GPIO_7,
 429 +               .gpio_last = RT3883_GPIO_10,
 430 +       }, {
 431 +               .name = "gpio i2s",
 432 +               .mask = RT3883_GPIO_MODE_GPIO_I2S,
 433 +               .gpio_first = RT3883_GPIO_7,
 434 +               .gpio_last = RT3883_GPIO_10,
 435 +       }, {
 436 +               .name = "gpio",
 437 +               .mask = RT3883_GPIO_MODE_GPIO,
 438 +       }, {0}
 439 +};
 440 +
 441 +static struct ralink_pinmux_grp pci_mux[] = {
 442 +       {
 443 +               .name = "pci-dev",
 444 +               .mask = 0,
 445 +               .gpio_first = RT3883_GPIO_PCI_AD0,
 446 +               .gpio_last = RT3883_GPIO_PCI_AD31,
 447 +       }, {
 448 +               .name = "pci-host2",
 449 +               .mask = 1,
 450 +               .gpio_first = RT3883_GPIO_PCI_AD0,
 451 +               .gpio_last = RT3883_GPIO_PCI_AD31,
 452 +       }, {
 453 +               .name = "pci-host1",
 454 +               .mask = 2,
 455 +               .gpio_first = RT3883_GPIO_PCI_AD0,
 456 +               .gpio_last = RT3883_GPIO_PCI_AD31,
 457 +       }, {
 458 +               .name = "pci-fnc",
 459 +               .mask = 3,
 460 +               .gpio_first = RT3883_GPIO_PCI_AD0,
 461 +               .gpio_last = RT3883_GPIO_PCI_AD31,
 462 +       }, {
 463 +               .name = "pci-gpio",
 464 +               .mask = 7,
 465 +               .gpio_first = RT3883_GPIO_PCI_AD0,
 466 +               .gpio_last = RT3883_GPIO_PCI_AD31,
 467 +       }, {0}
 468 +};
 469 +
 470 +static void rt3883_wdt_reset(void)
 471 +{
 472 +       u32 t;
 473 +
 474 +       /* enable WDT reset output on GPIO 2 */
 475 +       t = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG1);
 476 +       t |= RT3883_SYSCFG1_GPIO2_AS_WDT_OUT;
 477 +       rt_sysc_w32(t, RT3883_SYSC_REG_SYSCFG1);
 478 +}
 479 +
 480 +struct ralink_pinmux rt_gpio_pinmux = {
 481 +       .mode = mode_mux,
 482 +       .uart = uart_mux,
 483 +       .uart_shift = RT3883_GPIO_MODE_UART0_SHIFT,
 484 +       .uart_mask = RT3883_GPIO_MODE_GPIO,
 485 +       .wdt_reset = rt3883_wdt_reset,
 486 +       .pci = pci_mux,
 487 +       .pci_shift = RT3883_GPIO_MODE_PCI_SHIFT,
 488 +       .pci_mask = RT3883_GPIO_MODE_PCI_MASK,
 489 +};
 490 +
 491 +void __init ralink_clk_init(void)
 492 +{
 493 +       unsigned long cpu_rate, sys_rate;
 494 +       u32 syscfg0;
 495 +       u32 clksel;
 496 +       u32 ddr2;
 497 +
 498 +       syscfg0 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG0);
 499 +       clksel = ((syscfg0 >> RT3883_SYSCFG0_CPUCLK_SHIFT) &
 500 +               RT3883_SYSCFG0_CPUCLK_MASK);
 501 +       ddr2 = syscfg0 & RT3883_SYSCFG0_DRAM_TYPE_DDR2;
 502 +
 503 +       switch (clksel) {
 504 +       case RT3883_SYSCFG0_CPUCLK_250:
 505 +               cpu_rate = 250000000;
 506 +               sys_rate = (ddr2) ? 125000000 : 83000000;
 507 +               break;
 508 +       case RT3883_SYSCFG0_CPUCLK_384:
 509 +               cpu_rate = 384000000;
 510 +               sys_rate = (ddr2) ? 128000000 : 96000000;
 511 +               break;
 512 +       case RT3883_SYSCFG0_CPUCLK_480:
 513 +               cpu_rate = 480000000;
 514 +               sys_rate = (ddr2) ? 160000000 : 120000000;
 515 +               break;
 516 +       case RT3883_SYSCFG0_CPUCLK_500:
 517 +               cpu_rate = 500000000;
 518 +               sys_rate = (ddr2) ? 166000000 : 125000000;
 519 +               break;
 520 +       }
 521 +
 522 +       ralink_clk_add("cpu", cpu_rate);
 523 +       ralink_clk_add("10000100.timer", sys_rate);
 524 +       ralink_clk_add("10000120.watchdog", sys_rate);
 525 +       ralink_clk_add("10000500.uart", 40000000);
 526 +       ralink_clk_add("10000b00.spi", sys_rate);
 527 +       ralink_clk_add("10000c00.uartlite", 40000000);
 528 +       ralink_clk_add("10100000.ethernet", sys_rate);
 529 +}
 530 +
 531 +void __init ralink_of_remap(void)
 532 +{
 533 +       rt_sysc_membase = plat_of_remap_node("ralink,rt3883-sysc");
 534 +       rt_memc_membase = plat_of_remap_node("ralink,rt3883-memc");
 535 +
 536 +       if (!rt_sysc_membase || !rt_memc_membase)
 537 +               panic("Failed to remap core resources");
 538 +}
 539 +
 540 +void prom_soc_init(struct ralink_soc_info *soc_info)
 541 +{
 542 +       void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT3883_SYSC_BASE);
 543 +       const char *name;
 544 +       u32 n0;
 545 +       u32 n1;
 546 +       u32 id;
 547 +
 548 +       n0 = __raw_readl(sysc + RT3883_SYSC_REG_CHIPID0_3);
 549 +       n1 = __raw_readl(sysc + RT3883_SYSC_REG_CHIPID4_7);
 550 +       id = __raw_readl(sysc + RT3883_SYSC_REG_REVID);
 551 +
 552 +       if (n0 == RT3883_CHIP_NAME0 && n1 == RT3883_CHIP_NAME1) {
 553 +               soc_info->compatible = "ralink,rt3883-soc";
 554 +               name = "RT3883";
 555 +       } else {
 556 +               panic("rt3883: unknown SoC, n0:%08x n1:%08x", n0, n1);
 557 +       }
 558 +
 559 +       snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
 560 +               "Ralink %s ver:%u eco:%u",
 561 +               name,
 562 +               (id >> RT3883_REVID_VER_ID_SHIFT) & RT3883_REVID_VER_ID_MASK,
 563 +               (id & RT3883_REVID_ECO_ID_MASK));
 564 +}
 565 --
 566 1.7.10.4
 567