target/linux/ramips/patches-3.8/0103-MIPS-ralink-fix-RT305x-clock-setup.patch

   1 From 845f786c561c0991d9b4088a2d77b8fd4831d487 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Fri, 22 Mar 2013 19:25:59 +0100
   4 Subject: [PATCH 103/137] MIPS: ralink: fix RT305x clock setup
   5
   6 Add a few missing clocks.
   7
   8 Signed-off-by: John Crispin <blogic@openwrt.org>
   9 Acked-by: Gabor Juhos <juhosg@openwrt.org>
  10 Patchwork: http://patchwork.linux-mips.org/patch/5167/
  11 ---
  12  arch/mips/ralink/rt305x.c |   12 ++++++++++++
  13  1 file changed, 12 insertions(+)
  14
  15 --- a/arch/mips/ralink/rt305x.c
  16 +++ b/arch/mips/ralink/rt305x.c
  17 @@ -124,6 +124,8 @@ struct ralink_pinmux gpio_pinmux = {
  18  void __init ralink_clk_init(void)
  19  {
  20         unsigned long cpu_rate, sys_rate, wdt_rate, uart_rate;
  21 +       unsigned long wmac_rate = 40000000;
  22 +
  23         u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
  24
  25         if (soc_is_rt305x() || soc_is_rt3350()) {
  26 @@ -176,11 +178,21 @@ void __init ralink_clk_init(void)
  27                 BUG();
  28         }
  29
  30 +       if (soc_is_rt3352() || soc_is_rt5350()) {
  31 +               u32 val = rt_sysc_r32(RT3352_SYSC_REG_SYSCFG0);
  32 +
  33 +               if (!(val & RT3352_CLKCFG0_XTAL_SEL))
  34 +                       wmac_rate = 20000000;
  35 +       }
  36 +
  37         ralink_clk_add("cpu", cpu_rate);
  38         ralink_clk_add("10000b00.spi", sys_rate);
  39         ralink_clk_add("10000100.timer", wdt_rate);
  40 +       ralink_clk_add("10000120.watchdog", wdt_rate);
  41         ralink_clk_add("10000500.uart", uart_rate);
  42         ralink_clk_add("10000c00.uartlite", uart_rate);
  43 +       ralink_clk_add("10100000.ethernet", sys_rate);
  44 +       ralink_clk_add("10180000.wmac", wmac_rate);
  45  }
  46
  47  void __init ralink_of_remap(void)