target/linux/ramips/patches-3.8/0111-MIPS-ralink-adds-support-for-RT2880-SoC-family.patch

   1 From cccb9a7b42227a442ca42d590c838c8b6fa0eba1 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Sun, 27 Jan 2013 09:17:20 +0100
   4 Subject: [PATCH 111/137] MIPS: ralink: adds support for RT2880 SoC family
   5
   6 Add support code for rt2880 SOC.
   7
   8 The code detects the SoC and registers the clk / pinmux settings.
   9
  10 Signed-off-by: John Crispin <blogic@openwrt.org>
  11 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
  12 Patchwork: http://patchwork.linux-mips.org/patch/5176/
  13 ---
  14  arch/mips/Kconfig                          |    2 +-
  15  arch/mips/include/asm/mach-ralink/rt288x.h |   49 ++++++++++
  16  arch/mips/ralink/Kconfig                   |    3 +
  17  arch/mips/ralink/Makefile                  |    1 +
  18  arch/mips/ralink/Platform                  |    5 +
  19  arch/mips/ralink/rt288x.c                  |  139 ++++++++++++++++++++++++++++
  20  6 files changed, 198 insertions(+), 1 deletion(-)
  21  create mode 100644 arch/mips/include/asm/mach-ralink/rt288x.h
  22  create mode 100644 arch/mips/ralink/rt288x.c
  23
  24 --- a/arch/mips/Kconfig
  25 +++ b/arch/mips/Kconfig
  26 @@ -1189,7 +1189,7 @@ config BOOT_ELF32
  27
  28  config MIPS_L1_CACHE_SHIFT
  29         int
  30 -       default "4" if MACH_DECSTATION || MIKROTIK_RB532 || PMC_MSP4200_EVAL
  31 +       default "4" if MACH_DECSTATION || MIKROTIK_RB532 || PMC_MSP4200_EVAL || SOC_RT288X
  32         default "6" if MIPS_CPU_SCACHE
  33         default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM || CPU_CAVIUM_OCTEON
  34         default "5"
  35 --- /dev/null
  36 +++ b/arch/mips/include/asm/mach-ralink/rt288x.h
  37 @@ -0,0 +1,49 @@
  38 +/*
  39 + * This program is free software; you can redistribute it and/or modify it
  40 + * under the terms of the GNU General Public License version 2 as published
  41 + * by the Free Software Foundation.
  42 + *
  43 + * Parts of this file are based on Ralink's 2.6.21 BSP
  44 + *
  45 + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
  46 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  47 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
  48 + */
  49 +
  50 +#ifndef _RT288X_REGS_H_
  51 +#define _RT288X_REGS_H_
  52 +
  53 +#define RT2880_SYSC_BASE               0x00300000
  54 +
  55 +#define SYSC_REG_CHIP_NAME0            0x00
  56 +#define SYSC_REG_CHIP_NAME1            0x04
  57 +#define SYSC_REG_CHIP_ID               0x0c
  58 +#define SYSC_REG_SYSTEM_CONFIG         0x10
  59 +#define SYSC_REG_CLKCFG                        0x30
  60 +
  61 +#define RT2880_CHIP_NAME0              0x38325452
  62 +#define RT2880_CHIP_NAME1              0x20203038
  63 +
  64 +#define CHIP_ID_ID_MASK                        0xff
  65 +#define CHIP_ID_ID_SHIFT               8
  66 +#define CHIP_ID_REV_MASK               0xff
  67 +
  68 +#define SYSTEM_CONFIG_CPUCLK_SHIFT     20
  69 +#define SYSTEM_CONFIG_CPUCLK_MASK      0x3
  70 +#define SYSTEM_CONFIG_CPUCLK_250       0x0
  71 +#define SYSTEM_CONFIG_CPUCLK_266       0x1
  72 +#define SYSTEM_CONFIG_CPUCLK_280       0x2
  73 +#define SYSTEM_CONFIG_CPUCLK_300       0x3
  74 +
  75 +#define RT2880_GPIO_MODE_I2C           BIT(0)
  76 +#define RT2880_GPIO_MODE_UART0         BIT(1)
  77 +#define RT2880_GPIO_MODE_SPI           BIT(2)
  78 +#define RT2880_GPIO_MODE_UART1         BIT(3)
  79 +#define RT2880_GPIO_MODE_JTAG          BIT(4)
  80 +#define RT2880_GPIO_MODE_MDIO          BIT(5)
  81 +#define RT2880_GPIO_MODE_SDRAM         BIT(6)
  82 +#define RT2880_GPIO_MODE_PCI           BIT(7)
  83 +
  84 +#define CLKCFG_SRAM_CS_N_WDT           BIT(9)
  85 +
  86 +#endif
  87 --- a/arch/mips/ralink/Kconfig
  88 +++ b/arch/mips/ralink/Kconfig
  89 @@ -6,6 +6,9 @@ choice
  90         help
  91           Select Ralink MIPS SoC type.
  92
  93 +       config SOC_RT288X
  94 +               bool "RT288x"
  95 +
  96         config SOC_RT305X
  97                 bool "RT305x"
  98                 select USB_ARCH_HAS_HCD
  99 --- a/arch/mips/ralink/Makefile
 100 +++ b/arch/mips/ralink/Makefile
 101 @@ -8,6 +8,7 @@
 102
 103  obj-y := prom.o of.o reset.o clk.o irq.o
 104
 105 +obj-$(CONFIG_SOC_RT288X) += rt288x.o
 106  obj-$(CONFIG_SOC_RT305X) += rt305x.o
 107
 108  obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
 109 --- a/arch/mips/ralink/Platform
 110 +++ b/arch/mips/ralink/Platform
 111 @@ -5,6 +5,11 @@ core-$(CONFIG_RALINK)          += arch/mips/rali
 112  cflags-$(CONFIG_RALINK)                += -I$(srctree)/arch/mips/include/asm/mach-ralink
 113
 114  #
 115 +# Ralink RT288x
 116 +#
 117 +load-$(CONFIG_SOC_RT288X)      += 0xffffffff88000000
 118 +
 119 +#
 120  # Ralink RT305x
 121  #
 122  load-$(CONFIG_SOC_RT305X)      += 0xffffffff80000000
 123 --- /dev/null
 124 +++ b/arch/mips/ralink/rt288x.c
 125 @@ -0,0 +1,139 @@
 126 +/*
 127 + * This program is free software; you can redistribute it and/or modify it
 128 + * under the terms of the GNU General Public License version 2 as published
 129 + * by the Free Software Foundation.
 130 + *
 131 + * Parts of this file are based on Ralink's 2.6.21 BSP
 132 + *
 133 + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
 134 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
 135 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
 136 + */
 137 +
 138 +#include <linux/kernel.h>
 139 +#include <linux/init.h>
 140 +#include <linux/module.h>
 141 +
 142 +#include <asm/mipsregs.h>
 143 +#include <asm/mach-ralink/ralink_regs.h>
 144 +#include <asm/mach-ralink/rt288x.h>
 145 +
 146 +#include "common.h"
 147 +
 148 +static struct ralink_pinmux_grp mode_mux[] = {
 149 +       {
 150 +               .name = "i2c",
 151 +               .mask = RT2880_GPIO_MODE_I2C,
 152 +               .gpio_first = 1,
 153 +               .gpio_last = 2,
 154 +       }, {
 155 +               .name = "spi",
 156 +               .mask = RT2880_GPIO_MODE_SPI,
 157 +               .gpio_first = 3,
 158 +               .gpio_last = 6,
 159 +       }, {
 160 +               .name = "uartlite",
 161 +               .mask = RT2880_GPIO_MODE_UART0,
 162 +               .gpio_first = 7,
 163 +               .gpio_last = 14,
 164 +       }, {
 165 +               .name = "jtag",
 166 +               .mask = RT2880_GPIO_MODE_JTAG,
 167 +               .gpio_first = 17,
 168 +               .gpio_last = 21,
 169 +       }, {
 170 +               .name = "mdio",
 171 +               .mask = RT2880_GPIO_MODE_MDIO,
 172 +               .gpio_first = 22,
 173 +               .gpio_last = 23,
 174 +       }, {
 175 +               .name = "sdram",
 176 +               .mask = RT2880_GPIO_MODE_SDRAM,
 177 +               .gpio_first = 24,
 178 +               .gpio_last = 39,
 179 +       }, {
 180 +               .name = "pci",
 181 +               .mask = RT2880_GPIO_MODE_PCI,
 182 +               .gpio_first = 40,
 183 +               .gpio_last = 71,
 184 +       }, {0}
 185 +};
 186 +
 187 +static void rt288x_wdt_reset(void)
 188 +{
 189 +       u32 t;
 190 +
 191 +       /* enable WDT reset output on pin SRAM_CS_N */
 192 +       t = rt_sysc_r32(SYSC_REG_CLKCFG);
 193 +       t |= CLKCFG_SRAM_CS_N_WDT;
 194 +       rt_sysc_w32(t, SYSC_REG_CLKCFG);
 195 +}
 196 +
 197 +struct ralink_pinmux rt_gpio_pinmux = {
 198 +       .mode = mode_mux,
 199 +       .wdt_reset = rt288x_wdt_reset,
 200 +};
 201 +
 202 +void __init ralink_clk_init(void)
 203 +{
 204 +       unsigned long cpu_rate;
 205 +       u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
 206 +       t = ((t >> SYSTEM_CONFIG_CPUCLK_SHIFT) & SYSTEM_CONFIG_CPUCLK_MASK);
 207 +
 208 +       switch (t) {
 209 +       case SYSTEM_CONFIG_CPUCLK_250:
 210 +               cpu_rate = 250000000;
 211 +               break;
 212 +       case SYSTEM_CONFIG_CPUCLK_266:
 213 +               cpu_rate = 266666667;
 214 +               break;
 215 +       case SYSTEM_CONFIG_CPUCLK_280:
 216 +               cpu_rate = 280000000;
 217 +               break;
 218 +       case SYSTEM_CONFIG_CPUCLK_300:
 219 +               cpu_rate = 300000000;
 220 +               break;
 221 +       }
 222 +
 223 +       ralink_clk_add("cpu", cpu_rate);
 224 +       ralink_clk_add("300100.timer", cpu_rate / 2);
 225 +       ralink_clk_add("300120.watchdog", cpu_rate / 2);
 226 +       ralink_clk_add("300500.uart", cpu_rate / 2);
 227 +       ralink_clk_add("300c00.uartlite", cpu_rate / 2);
 228 +       ralink_clk_add("400000.ethernet", cpu_rate / 2);
 229 +}
 230 +
 231 +void __init ralink_of_remap(void)
 232 +{
 233 +       rt_sysc_membase = plat_of_remap_node("ralink,rt2880-sysc");
 234 +       rt_memc_membase = plat_of_remap_node("ralink,rt2880-memc");
 235 +
 236 +       if (!rt_sysc_membase || !rt_memc_membase)
 237 +               panic("Failed to remap core resources");
 238 +}
 239 +
 240 +void prom_soc_init(struct ralink_soc_info *soc_info)
 241 +{
 242 +       void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT2880_SYSC_BASE);
 243 +       const char *name;
 244 +       u32 n0;
 245 +       u32 n1;
 246 +       u32 id;
 247 +
 248 +       n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
 249 +       n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
 250 +       id = __raw_readl(sysc + SYSC_REG_CHIP_ID);
 251 +
 252 +       if (n0 == RT2880_CHIP_NAME0 && n1 == RT2880_CHIP_NAME1) {
 253 +               soc_info->compatible = "ralink,r2880-soc";
 254 +               name = "RT2880";
 255 +       } else {
 256 +               panic("rt288x: unknown SoC, n0:%08x n1:%08x", n0, n1);
 257 +       }
 258 +
 259 +       snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
 260 +               "Ralink %s id:%u rev:%u",
 261 +               name,
 262 +               (id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK,
 263 +               (id & CHIP_ID_REV_MASK));
 264 +}