target/linux/ramips/patches-3.8/0123-MIPS-ralink-add-memory-definition-for-RT305x.patch

   1 From 016f1f659cf70cc78e72e12a2130d8f3e1a6e0d3 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Sat, 13 Apr 2013 15:13:40 +0200
   4 Subject: [PATCH 123/137] MIPS: ralink: add memory definition for RT305x
   5
   6 Populate struct soc_info with the data that describes our RAM window.
   7
   8 As memory detection fails on RT5350 we read the amount of available memory
   9 from the system controller.
  10
  11 Signed-off-by: John Crispin <blogic@openwrt.org>
  12 Patchwork: http://patchwork.linux-mips.org/patch/5180/
  13 ---
  14  arch/mips/include/asm/mach-ralink/rt305x.h |    6 ++++
  15  arch/mips/ralink/rt305x.c                  |   45 ++++++++++++++++++++++++++++
  16  2 files changed, 51 insertions(+)
  17
  18 --- a/arch/mips/include/asm/mach-ralink/rt305x.h
  19 +++ b/arch/mips/include/asm/mach-ralink/rt305x.h
  20 @@ -157,4 +157,10 @@ static inline int soc_is_rt5350(void)
  21  #define RT3352_RSTCTRL_UDEV            BIT(25)
  22  #define RT3352_SYSCFG1_USB0_HOST_MODE  BIT(10)
  23
  24 +#define RT305X_SDRAM_BASE              0x00000000
  25 +#define RT305X_MEM_SIZE_MIN            2
  26 +#define RT305X_MEM_SIZE_MAX            64
  27 +#define RT3352_MEM_SIZE_MIN            2
  28 +#define RT3352_MEM_SIZE_MAX            256
  29 +
  30  #endif
  31 --- a/arch/mips/ralink/rt305x.c
  32 +++ b/arch/mips/ralink/rt305x.c
  33 @@ -122,6 +122,40 @@ struct ralink_pinmux rt_gpio_pinmux = {
  34         .wdt_reset = rt305x_wdt_reset,
  35  };
  36
  37 +static unsigned long rt5350_get_mem_size(void)
  38 +{
  39 +       void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE);
  40 +       unsigned long ret;
  41 +       u32 t;
  42 +
  43 +       t = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG);
  44 +       t = (t >> RT5350_SYSCFG0_DRAM_SIZE_SHIFT) &
  45 +               RT5350_SYSCFG0_DRAM_SIZE_MASK;
  46 +
  47 +       switch (t) {
  48 +       case RT5350_SYSCFG0_DRAM_SIZE_2M:
  49 +               ret = 2;
  50 +               break;
  51 +       case RT5350_SYSCFG0_DRAM_SIZE_8M:
  52 +               ret = 8;
  53 +               break;
  54 +       case RT5350_SYSCFG0_DRAM_SIZE_16M:
  55 +               ret = 16;
  56 +               break;
  57 +       case RT5350_SYSCFG0_DRAM_SIZE_32M:
  58 +               ret = 32;
  59 +               break;
  60 +       case RT5350_SYSCFG0_DRAM_SIZE_64M:
  61 +               ret = 64;
  62 +               break;
  63 +       default:
  64 +               panic("rt5350: invalid DRAM size: %u", t);
  65 +               break;
  66 +       }
  67 +
  68 +       return ret * 1024 * 1024;
  69 +}
  70 +
  71  void __init ralink_clk_init(void)
  72  {
  73         unsigned long cpu_rate, sys_rate, wdt_rate, uart_rate;
  74 @@ -252,4 +286,15 @@ void prom_soc_init(struct ralink_soc_inf
  75                 name,
  76                 (id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK,
  77                 (id & CHIP_ID_REV_MASK));
  78 +
  79 +       soc_info->mem_base = RT305X_SDRAM_BASE;
  80 +       if (soc_is_rt5350()) {
  81 +               soc_info->mem_size = rt5350_get_mem_size();
  82 +       } else if (soc_is_rt305x() || soc_is_rt3350()) {
  83 +               soc_info->mem_size_min = RT305X_MEM_SIZE_MIN;
  84 +               soc_info->mem_size_max = RT305X_MEM_SIZE_MAX;
  85 +       } else if (soc_is_rt3352()) {
  86 +               soc_info->mem_size_min = RT3352_MEM_SIZE_MIN;
  87 +               soc_info->mem_size_max = RT3352_MEM_SIZE_MAX;
  88 +       }
  89  }