target/linux/ramips/patches-3.8/0126-MIPS-ralink-add-memory-definition-for-MT7620.patch

   1 From c1d35c42d697e9c28c817921a79c5f814529a4c6 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Sun, 14 Apr 2013 09:55:29 +0200
   4 Subject: [PATCH 126/137] MIPS: ralink: add memory definition for MT7620
   5
   6 Populate struct soc_info with the data that describes our RAM window.
   7
   8 Signed-off-by: John Crispin <blogic@openwrt.org>
   9 Patchwork: http://patchwork.linux-mips.org/patch/5183/
  10 ---
  11  arch/mips/include/asm/mach-ralink/mt7620.h |    8 ++++++++
  12  arch/mips/ralink/mt7620.c                  |   20 ++++++++++++++++++++
  13  2 files changed, 28 insertions(+)
  14
  15 --- a/arch/mips/include/asm/mach-ralink/mt7620.h
  16 +++ b/arch/mips/include/asm/mach-ralink/mt7620.h
  17 @@ -50,6 +50,14 @@
  18  #define SYSCFG0_DRAM_TYPE_DDR1         1
  19  #define SYSCFG0_DRAM_TYPE_DDR2         2
  20
  21 +#define MT7620_DRAM_BASE               0x0
  22 +#define MT7620_SDRAM_SIZE_MIN          2
  23 +#define MT7620_SDRAM_SIZE_MAX          64
  24 +#define MT7620_DDR1_SIZE_MIN           32
  25 +#define MT7620_DDR1_SIZE_MAX           128
  26 +#define MT7620_DDR2_SIZE_MIN           32
  27 +#define MT7620_DDR2_SIZE_MAX           256
  28 +
  29  #define MT7620_GPIO_MODE_I2C           BIT(0)
  30  #define MT7620_GPIO_MODE_UART0_SHIFT   2
  31  #define MT7620_GPIO_MODE_UART0_MASK    0x7
  32 --- a/arch/mips/ralink/mt7620.c
  33 +++ b/arch/mips/ralink/mt7620.c
  34 @@ -211,4 +211,24 @@ void prom_soc_init(struct ralink_soc_inf
  35
  36         cfg0 = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG0);
  37         dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & SYSCFG0_DRAM_TYPE_MASK;
  38 +
  39 +       switch (dram_type) {
  40 +       case SYSCFG0_DRAM_TYPE_SDRAM:
  41 +               soc_info->mem_size_min = MT7620_SDRAM_SIZE_MIN;
  42 +               soc_info->mem_size_max = MT7620_SDRAM_SIZE_MAX;
  43 +               break;
  44 +
  45 +       case SYSCFG0_DRAM_TYPE_DDR1:
  46 +               soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;
  47 +               soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;
  48 +               break;
  49 +
  50 +       case SYSCFG0_DRAM_TYPE_DDR2:
  51 +               soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;
  52 +               soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;
  53 +               break;
  54 +       default:
  55 +               BUG();
  56 +       }
  57 +       soc_info->mem_base = MT7620_DRAM_BASE;
  58  }