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kernel/4.3: update to version 4.3.3
[openwrt/openwrt.git] / target / linux / ramips / patches-4.3 / 0033-USB-add-xhci-hooks.patch
1 From 71fbde37e60c11f5a715c105d25b9c6cee8dae6c Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Mon, 7 Dec 2015 17:14:03 +0100
4 Subject: [PATCH 33/53] USB: add xhci hooks
5
6 Signed-off-by: John Crispin <blogic@openwrt.org>
7 ---
8 drivers/usb/core/hcd-pci.c | 5 +
9 drivers/usb/core/hub.c | 2 +-
10 drivers/usb/core/port.c | 10 +-
11 drivers/usb/host/Kconfig | 9 +-
12 drivers/usb/host/Makefile | 10 +-
13 drivers/usb/host/mtk-phy-7621.c | 445 +++++
14 drivers/usb/host/mtk-phy-7621.h | 2871 +++++++++++++++++++++++++++++++++
15 drivers/usb/host/mtk-phy-ahb.c | 58 +
16 drivers/usb/host/mtk-phy.c | 102 ++
17 drivers/usb/host/mtk-phy.h | 179 ++
18 drivers/usb/host/pci-quirks.h | 2 +-
19 drivers/usb/host/xhci-dbg.c | 3 +
20 drivers/usb/host/xhci-mem.c | 11 +
21 drivers/usb/host/xhci-mtk-power.c | 115 ++
22 drivers/usb/host/xhci-mtk-power.h | 13 +
23 drivers/usb/host/xhci-mtk-scheduler.c | 608 +++++++
24 drivers/usb/host/xhci-mtk-scheduler.h | 77 +
25 drivers/usb/host/xhci-mtk.c | 265 +++
26 drivers/usb/host/xhci-mtk.h | 120 ++
27 drivers/usb/host/xhci-plat.c | 11 +
28 drivers/usb/host/xhci-ring.c | 104 ++
29 drivers/usb/host/xhci.c | 209 ++-
30 drivers/usb/host/xhci.h | 39 +
31 23 files changed, 5257 insertions(+), 11 deletions(-)
32 create mode 100644 drivers/usb/host/mtk-phy-7621.c
33 create mode 100644 drivers/usb/host/mtk-phy-7621.h
34 create mode 100644 drivers/usb/host/mtk-phy-ahb.c
35 create mode 100644 drivers/usb/host/mtk-phy.c
36 create mode 100644 drivers/usb/host/mtk-phy.h
37 create mode 100644 drivers/usb/host/xhci-mtk-power.c
38 create mode 100644 drivers/usb/host/xhci-mtk-power.h
39 create mode 100644 drivers/usb/host/xhci-mtk-scheduler.c
40 create mode 100644 drivers/usb/host/xhci-mtk-scheduler.h
41 create mode 100644 drivers/usb/host/xhci-mtk.c
42 create mode 100644 drivers/usb/host/xhci-mtk.h
43
44 --- a/drivers/usb/core/hcd-pci.c
45 +++ b/drivers/usb/core/hcd-pci.c
46 @@ -214,8 +214,13 @@ int usb_hcd_pci_probe(struct pci_dev *de
47 goto disable_pci;
48 }
49
50 +
51 +#ifdef CONFIG_USB_MT7621_XHCI_PLATFORM
52 + hcd->amd_resume_bug = 0;
53 +#else
54 hcd->amd_resume_bug = (usb_hcd_amd_remote_wakeup_quirk(dev) &&
55 driver->flags & (HCD_USB11 | HCD_USB3)) ? 1 : 0;
56 +#endif
57
58 if (driver->flags & HCD_MEMORY) {
59 /* EHCI, OHCI */
60 --- a/drivers/usb/core/hub.c
61 +++ b/drivers/usb/core/hub.c
62 @@ -1287,7 +1287,7 @@ static void hub_quiesce(struct usb_hub *
63 if (type != HUB_SUSPEND) {
64 /* Disconnect all the children */
65 for (i = 0; i < hdev->maxchild; ++i) {
66 - if (hub->ports[i]->child)
67 + if (hub->ports[i] && hub->ports[i]->child)
68 usb_disconnect(&hub->ports[i]->child);
69 }
70 }
71 --- a/drivers/usb/core/port.c
72 +++ b/drivers/usb/core/port.c
73 @@ -480,8 +480,10 @@ void usb_hub_remove_port_device(struct u
74 struct usb_port *port_dev = hub->ports[port1 - 1];
75 struct usb_port *peer;
76
77 - peer = port_dev->peer;
78 - if (peer)
79 - unlink_peers(port_dev, peer);
80 - device_unregister(&port_dev->dev);
81 + if(port_dev) {
82 + peer = port_dev->peer;
83 + if (peer)
84 + unlink_peers(port_dev, peer);
85 + device_unregister(&port_dev->dev);
86 + }
87 }
88 --- a/drivers/usb/host/Kconfig
89 +++ b/drivers/usb/host/Kconfig
90 @@ -41,6 +41,13 @@ config USB_XHCI_PLATFORM
91
92 If unsure, say N.
93
94 +config USB_MT7621_XHCI_PLATFORM
95 + bool
96 + depends on USB_XHCI_PLATFORM
97 + depends on SOC_MT7621
98 + select USB_PHY
99 + default y
100 +
101 config USB_XHCI_MVEBU
102 tristate "xHCI support for Marvell Armada 375/38x"
103 select USB_XHCI_PLATFORM
104 @@ -590,7 +597,7 @@ endif # USB_OHCI_HCD
105
106 config USB_UHCI_HCD
107 tristate "UHCI HCD (most Intel and VIA) support"
108 - depends on PCI || USB_UHCI_SUPPORT_NON_PCI_HC
109 + depends on BROKEN && (PCI || USB_UHCI_SUPPORT_NON_PCI_HC)
110 ---help---
111 The Universal Host Controller Interface is a standard by Intel for
112 accessing the USB hardware in the PC (which is also called the USB
113 --- a/drivers/usb/host/Makefile
114 +++ b/drivers/usb/host/Makefile
115 @@ -14,7 +14,12 @@ xhci-hcd-y := xhci.o xhci-mem.o
116 xhci-hcd-y += xhci-ring.o xhci-hub.o xhci-dbg.o
117 xhci-hcd-y += xhci-trace.o
118
119 +ifdef CONFIG_USB_MT7621_XHCI_PLATFORM
120 +xhci-hcd-y += mtk-phy.o xhci-mtk-scheduler.o xhci-mtk-power.o xhci-mtk.o mtk-phy-7621.o mtk-phy-ahb.o
121 +endif
122 +
123 xhci-plat-hcd-y := xhci-plat.o
124 +
125 ifneq ($(CONFIG_USB_XHCI_MVEBU), )
126 xhci-plat-hcd-y += xhci-mvebu.o
127 endif
128 @@ -24,11 +29,10 @@ endif
129
130 obj-$(CONFIG_USB_WHCI_HCD) += whci/
131
132 -ifneq ($(CONFIG_USB), )
133 +ifndef CONFIG_USB_MT7621_XHCI_PLATFORM
134 obj-$(CONFIG_PCI) += pci-quirks.o
135 + obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o
136 endif
137 -
138 -obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o
139 obj-$(CONFIG_USB_XHCI_PLATFORM) += xhci-plat-hcd.o
140
141 obj-$(CONFIG_USB_EHCI_HCD) += ehci-hcd.o
142 --- /dev/null
143 +++ b/drivers/usb/host/mtk-phy-7621.c
144 @@ -0,0 +1,445 @@
145 +#include "mtk-phy.h"
146 +
147 +#ifdef CONFIG_PROJECT_7621
148 +#include "mtk-phy-7621.h"
149 +
150 +//not used on SoC
151 +PHY_INT32 phy_init(struct u3phy_info *info){
152 + return PHY_TRUE;
153 +}
154 +
155 +//not used on SoC
156 +PHY_INT32 phy_change_pipe_phase(struct u3phy_info *info, PHY_INT32 phy_drv, PHY_INT32 pipe_phase){
157 + return PHY_TRUE;
158 +}
159 +
160 +//--------------------------------------------------------
161 +// Function : fgEyeScanHelper_CheckPtInRegion()
162 +// Description : Check if the test point is in a rectangle region.
163 +// If it is in the rectangle, also check if this point
164 +// is on the multiple of deltaX and deltaY.
165 +// Parameter : strucScanRegion * prEye - the region
166 +// BYTE bX
167 +// BYTE bY
168 +// Return : BYTE - TRUE : This point needs to be tested
169 +// FALSE: This point will be omitted
170 +// Note : First check within the rectangle.
171 +// Secondly, use modulous to check if the point will be tested.
172 +//--------------------------------------------------------
173 +static PHY_INT8 fgEyeScanHelper_CheckPtInRegion(struct strucScanRegion * prEye, PHY_INT8 bX, PHY_INT8 bY)
174 +{
175 + PHY_INT8 fgValid = true;
176 +
177 +
178 + /// Be careful, the axis origin is on the TOP-LEFT corner.
179 + /// Therefore the top-left point has the minimum X and Y
180 + /// Botton-right point is the maximum X and Y
181 + if ( (prEye->bX_tl <= bX) && (bX <= prEye->bX_br)
182 + && (prEye->bY_tl <= bY) && (bY <= prEye->bX_br))
183 + {
184 + // With the region, now check whether or not the input test point is
185 + // on the multiples of X and Y
186 + // Do not have to worry about negative value, because we have already
187 + // check the input bX, and bY is within the region.
188 + if ( ((bX - prEye->bX_tl) % (prEye->bDeltaX))
189 + || ((bY - prEye->bY_tl) % (prEye->bDeltaY)) )
190 + {
191 + // if the division will have remainder, that means
192 + // the input test point is on the multiples of X and Y
193 + fgValid = false;
194 + }
195 + else
196 + {
197 + }
198 + }
199 + else
200 + {
201 +
202 + fgValid = false;
203 + }
204 + return fgValid;
205 +}
206 +
207 +//--------------------------------------------------------
208 +// Function : EyeScanHelper_RunTest()
209 +// Description : Enable the test, and wait til it is completed
210 +// Parameter : None
211 +// Return : None
212 +// Note : None
213 +//--------------------------------------------------------
214 +static void EyeScanHelper_RunTest(struct u3phy_info *info)
215 +{
216 + DRV_UDELAY(100);
217 + // Disable the test
218 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
219 + , RG_SSUSB_EQ_EYE_CNT_EN_OFST, RG_SSUSB_EQ_EYE_CNT_EN, 0); //RG_SSUSB_RX_EYE_CNT_EN = 0
220 + DRV_UDELAY(100);
221 + // Run the test
222 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
223 + , RG_SSUSB_EQ_EYE_CNT_EN_OFST, RG_SSUSB_EQ_EYE_CNT_EN, 1); //RG_SSUSB_RX_EYE_CNT_EN = 1
224 + DRV_UDELAY(100);
225 + // Wait til it's done
226 + //RGS_SSUSB_RX_EYE_CNT_RDY
227 + while(!U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->phya_rx_mon5)
228 + , RGS_SSUSB_EQ_EYE_CNT_RDY_OFST, RGS_SSUSB_EQ_EYE_CNT_RDY));
229 +}
230 +
231 +//--------------------------------------------------------
232 +// Function : fgEyeScanHelper_CalNextPoint()
233 +// Description : Calcualte the test point for the measurement
234 +// Parameter : None
235 +// Return : BOOL - TRUE : the next point is within the
236 +// boundaryof HW limit
237 +// FALSE: the next point is out of the HW limit
238 +// Note : The next point is obtained by calculating
239 +// from the bottom left of the region rectangle
240 +// and then scanning up until it reaches the upper
241 +// limit. At this time, the x will increment, and
242 +// start scanning downwards until the y hits the
243 +// zero.
244 +//--------------------------------------------------------
245 +static PHY_INT8 fgEyeScanHelper_CalNextPoint(void)
246 +{
247 + if ( ((_bYcurr == MAX_Y) && (_eScanDir == SCAN_DN))
248 + || ((_bYcurr == MIN_Y) && (_eScanDir == SCAN_UP))
249 + )
250 + {
251 + /// Reaches the limit of Y axis
252 + /// Increment X
253 + _bXcurr++;
254 + _fgXChged = true;
255 + _eScanDir = (_eScanDir == SCAN_UP) ? SCAN_DN : SCAN_UP;
256 +
257 + if (_bXcurr > MAX_X)
258 + {
259 + return false;
260 + }
261 + }
262 + else
263 + {
264 + _bYcurr = (_eScanDir == SCAN_DN) ? _bYcurr + 1 : _bYcurr - 1;
265 + _fgXChged = false;
266 + }
267 + return PHY_TRUE;
268 +}
269 +
270 +PHY_INT32 eyescan_init(struct u3phy_info *info){
271 + //initial PHY setting
272 + U3PhyWriteField32(((PHY_UINT32)&info->u3phya_regs->rega)
273 + , RG_SSUSB_CDR_EPEN_OFST, RG_SSUSB_CDR_EPEN, 1);
274 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->phyd_mix3)
275 + , RG_SSUSB_FORCE_CDR_PI_PWD_OFST, RG_SSUSB_FORCE_CDR_PI_PWD, 1);
276 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
277 + , RG_SSUSB_RX_PI_CAL_EN_SEL_OFST, RG_SSUSB_RX_PI_CAL_EN_SEL, 1); //RG_SSUSB_RX_PI_CAL_MANUAL_SEL = 1
278 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
279 + , RG_SSUSB_RX_PI_CAL_EN_OFST, RG_SSUSB_RX_PI_CAL_EN, 1); //RG_SSUSB_RX_PI_CAL_MANUAL_EN = 1
280 + return PHY_TRUE;
281 +}
282 +
283 +PHY_INT32 phy_eyescan(struct u3phy_info *info, PHY_INT32 x_t1, PHY_INT32 y_t1, PHY_INT32 x_br, PHY_INT32 y_br, PHY_INT32 delta_x, PHY_INT32 delta_y
284 + , PHY_INT32 eye_cnt, PHY_INT32 num_cnt, PHY_INT32 PI_cal_en, PHY_INT32 num_ignore_cnt){
285 + PHY_INT32 cOfst = 0;
286 + PHY_UINT8 bIdxX = 0;
287 + PHY_UINT8 bIdxY = 0;
288 + //PHY_INT8 bCnt = 0;
289 + PHY_UINT8 bIdxCycCnt = 0;
290 + PHY_INT8 fgValid;
291 + PHY_INT8 cX;
292 + PHY_INT8 cY;
293 + PHY_UINT8 bExtendCnt;
294 + PHY_INT8 isContinue;
295 + //PHY_INT8 isBreak;
296 + PHY_UINT32 wErr0 = 0, wErr1 = 0;
297 + //PHY_UINT32 temp;
298 +
299 + PHY_UINT32 pwErrCnt0[CYCLE_COUNT_MAX][ERRCNT_MAX][ERRCNT_MAX];
300 + PHY_UINT32 pwErrCnt1[CYCLE_COUNT_MAX][ERRCNT_MAX][ERRCNT_MAX];
301 +
302 + _rEye1.bX_tl = x_t1;
303 + _rEye1.bY_tl = y_t1;
304 + _rEye1.bX_br = x_br;
305 + _rEye1.bY_br = y_br;
306 + _rEye1.bDeltaX = delta_x;
307 + _rEye1.bDeltaY = delta_y;
308 +
309 + _rEye2.bX_tl = x_t1;
310 + _rEye2.bY_tl = y_t1;
311 + _rEye2.bX_br = x_br;
312 + _rEye2.bY_br = y_br;
313 + _rEye2.bDeltaX = delta_x;
314 + _rEye2.bDeltaY = delta_y;
315 +
316 + _rTestCycle.wEyeCnt = eye_cnt;
317 + _rTestCycle.bNumOfEyeCnt = num_cnt;
318 + _rTestCycle.bNumOfIgnoreCnt = num_ignore_cnt;
319 + _rTestCycle.bPICalEn = PI_cal_en;
320 +
321 + _bXcurr = 0;
322 + _bYcurr = 0;
323 + _eScanDir = SCAN_DN;
324 + _fgXChged = false;
325 +
326 + printk("x_t1: %x, y_t1: %x, x_br: %x, y_br: %x, delta_x: %x, delta_y: %x, \
327 + eye_cnt: %x, num_cnt: %x, PI_cal_en: %x, num_ignore_cnt: %x\n", \
328 + x_t1, y_t1, x_br, y_br, delta_x, delta_y, eye_cnt, num_cnt, PI_cal_en, num_ignore_cnt);
329 +
330 + //force SIGDET to OFF
331 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
332 + , RG_SSUSB_RX_SIGDET_EN_SEL_OFST, RG_SSUSB_RX_SIGDET_EN_SEL, 1); //RG_SSUSB_RX_SIGDET_SEL = 1
333 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
334 + , RG_SSUSB_RX_SIGDET_EN_OFST, RG_SSUSB_RX_SIGDET_EN, 0); //RG_SSUSB_RX_SIGDET_EN = 0
335 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye1)
336 + , RG_SSUSB_EQ_SIGDET_OFST, RG_SSUSB_EQ_SIGDET, 0); //RG_SSUSB_RX_SIGDET = 0
337 +
338 + // RX_TRI_DET_EN to Disable
339 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq3)
340 + , RG_SSUSB_EQ_TRI_DET_EN_OFST, RG_SSUSB_EQ_TRI_DET_EN, 0); //RG_SSUSB_RX_TRI_DET_EN = 0
341 +
342 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
343 + , RG_SSUSB_EQ_EYE_MON_EN_OFST, RG_SSUSB_EQ_EYE_MON_EN, 1); //RG_SSUSB_EYE_MON_EN = 1
344 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
345 + , RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET, 0); //RG_SSUSB_RX_EYE_XOFFSET = 0
346 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
347 + , RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y, 0); //RG_SSUSB_RX_EYE0_Y = 0
348 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
349 + , RG_SSUSB_EQ_EYE1_Y_OFST, RG_SSUSB_EQ_EYE1_Y, 0); //RG_SSUSB_RX_EYE1_Y = 0
350 +
351 +
352 + if (PI_cal_en){
353 + // PI Calibration
354 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
355 + , RG_SSUSB_RX_PI_CAL_EN_SEL_OFST, RG_SSUSB_RX_PI_CAL_EN_SEL, 1); //RG_SSUSB_RX_PI_CAL_MANUAL_SEL = 1
356 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
357 + , RG_SSUSB_RX_PI_CAL_EN_OFST, RG_SSUSB_RX_PI_CAL_EN, 0); //RG_SSUSB_RX_PI_CAL_MANUAL_EN = 0
358 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
359 + , RG_SSUSB_RX_PI_CAL_EN_OFST, RG_SSUSB_RX_PI_CAL_EN, 1); //RG_SSUSB_RX_PI_CAL_MANUAL_EN = 1
360 +
361 + DRV_UDELAY(20);
362 +
363 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
364 + , RG_SSUSB_RX_PI_CAL_EN_OFST, RG_SSUSB_RX_PI_CAL_EN, 0); //RG_SSUSB_RX_PI_CAL_MANUAL_EN = 0
365 + _bPIResult = U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->phya_rx_mon5)
366 + , RGS_SSUSB_EQ_PILPO_OFST, RGS_SSUSB_EQ_PILPO); //read RGS_SSUSB_RX_PILPO
367 +
368 + printk(KERN_ERR "PI result: %d\n", _bPIResult);
369 + }
370 + // Read Initial DAC
371 + // Set CYCLE
372 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye3)
373 + ,RG_SSUSB_EQ_EYE_CNT_OFST, RG_SSUSB_EQ_EYE_CNT, eye_cnt); //RG_SSUSB_RX_EYE_CNT
374 +
375 + // Eye Monitor Feature
376 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye1)
377 + , RG_SSUSB_EQ_EYE_MASK_OFST, RG_SSUSB_EQ_EYE_MASK, 0x3ff); //RG_SSUSB_RX_EYE_MASK = 0x3ff
378 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
379 + , RG_SSUSB_EQ_EYE_MON_EN_OFST, RG_SSUSB_EQ_EYE_MON_EN, 1); //RG_SSUSB_EYE_MON_EN = 1
380 +
381 + // Move X,Y to the top-left corner
382 + for (cOfst = 0; cOfst >= -64; cOfst--)
383 + {
384 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
385 + ,RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET, cOfst); //RG_SSUSB_RX_EYE_XOFFSET
386 + }
387 + for (cOfst = 0; cOfst < 64; cOfst++)
388 + {
389 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
390 + , RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y, cOfst); //RG_SSUSB_RX_EYE0_Y
391 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
392 + , RG_SSUSB_EQ_EYE1_Y_OFST, RG_SSUSB_EQ_EYE1_Y, cOfst); //RG_SSUSB_RX_EYE1_Y
393 + }
394 + //ClearErrorResult
395 + for(bIdxCycCnt = 0; bIdxCycCnt < CYCLE_COUNT_MAX; bIdxCycCnt++){
396 + for(bIdxX = 0; bIdxX < ERRCNT_MAX; bIdxX++)
397 + {
398 + for(bIdxY = 0; bIdxY < ERRCNT_MAX; bIdxY++){
399 + pwErrCnt0[bIdxCycCnt][bIdxX][bIdxY] = 0;
400 + pwErrCnt1[bIdxCycCnt][bIdxX][bIdxY] = 0;
401 + }
402 + }
403 + }
404 + isContinue = true;
405 + while(isContinue){
406 + //printk(KERN_ERR "_bXcurr: %d, _bYcurr: %d\n", _bXcurr, _bYcurr);
407 + // The point is within the boundary, then let's check if it is within
408 + // the testing region.
409 + // The point is only test-able if one of the eye region
410 + // includes this point.
411 + fgValid = fgEyeScanHelper_CheckPtInRegion(&_rEye1, _bXcurr, _bYcurr)
412 + || fgEyeScanHelper_CheckPtInRegion(&_rEye2, _bXcurr, _bYcurr);
413 + // Translate bX and bY to 2's complement from where the origin was on the
414 + // top left corner.
415 + // 0x40 and 0x3F needs a bit of thinking!!!! >"<
416 + cX = (_bXcurr ^ 0x40);
417 + cY = (_bYcurr ^ 0x3F);
418 +
419 + // Set X if necessary
420 + if (_fgXChged == true)
421 + {
422 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
423 + , RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET, cX); //RG_SSUSB_RX_EYE_XOFFSET
424 + }
425 + // Set Y
426 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
427 + , RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y, cY); //RG_SSUSB_RX_EYE0_Y
428 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
429 + , RG_SSUSB_EQ_EYE1_Y_OFST, RG_SSUSB_EQ_EYE1_Y, cY); //RG_SSUSB_RX_EYE1_Y
430 +
431 + /// Test this point!
432 + if (fgValid){
433 + for (bExtendCnt = 0; bExtendCnt < num_ignore_cnt; bExtendCnt++)
434 + {
435 + //run test
436 + EyeScanHelper_RunTest(info);
437 + }
438 + for (bExtendCnt = 0; bExtendCnt < num_cnt; bExtendCnt++)
439 + {
440 + EyeScanHelper_RunTest(info);
441 + wErr0 = U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->phya_rx_mon3)
442 + , RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_0_OFST, RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_0);
443 + wErr1 = U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->phya_rx_mon4)
444 + , RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_1_OFST, RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_1);
445 +
446 + pwErrCnt0[bExtendCnt][_bXcurr][_bYcurr] = wErr0;
447 + pwErrCnt1[bExtendCnt][_bXcurr][_bYcurr] = wErr1;
448 +
449 + //EyeScanHelper_GetResult(&_rRes.pwErrCnt0[bCnt], &_rRes.pwErrCnt1[bCnt]);
450 +// printk(KERN_ERR "cnt[%d] cur_x,y [0x%x][0x%x], cX,cY [0x%x][0x%x], ErrCnt[%d][%d]\n"
451 +// , bExtendCnt, _bXcurr, _bYcurr, cX, cY, pwErrCnt0[bExtendCnt][_bXcurr][_bYcurr], pwErrCnt1[bExtendCnt][_bXcurr][_bYcurr]);
452 + }
453 + //printk(KERN_ERR "cur_x,y [0x%x][0x%x], cX,cY [0x%x][0x%x], ErrCnt[%d][%d]\n", _bXcurr, _bYcurr, cX, cY, pwErrCnt0[0][_bXcurr][_bYcurr], pwErrCnt1[0][_bXcurr][_bYcurr]);
454 + }
455 + else{
456 +
457 + }
458 + if (fgEyeScanHelper_CalNextPoint() == false){
459 +#if 0
460 + printk(KERN_ERR "Xcurr [0x%x] Ycurr [0x%x]\n", _bXcurr, _bYcurr);
461 + printk(KERN_ERR "XcurrREG [0x%x] YcurrREG [0x%x]\n", cX, cY);
462 +#endif
463 + printk(KERN_ERR "end of eye scan\n");
464 + isContinue = false;
465 + }
466 + }
467 + printk(KERN_ERR "CurX [0x%x] CurY [0x%x]\n"
468 + , U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0), RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET)
469 + , U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0), RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y));
470 +
471 + // Move X,Y to the top-left corner
472 + for (cOfst = 63; cOfst >= 0; cOfst--)
473 + {
474 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
475 + , RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET, cOfst); //RG_SSUSB_RX_EYE_XOFFSET
476 + }
477 + for (cOfst = 63; cOfst >= 0; cOfst--)
478 + {
479 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
480 + , RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y, cOfst);
481 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
482 + , RG_SSUSB_EQ_EYE1_Y_OFST, RG_SSUSB_EQ_EYE1_Y, cOfst);
483 +
484 + }
485 + printk(KERN_ERR "CurX [0x%x] CurY [0x%x]\n"
486 + , U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0), RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET)
487 + , U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0), RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y));
488 +
489 + printk(KERN_ERR "PI result: %d\n", _bPIResult);
490 + printk(KERN_ERR "pwErrCnt0 addr: 0x%x\n", (PHY_UINT32)pwErrCnt0);
491 + printk(KERN_ERR "pwErrCnt1 addr: 0x%x\n", (PHY_UINT32)pwErrCnt1);
492 +
493 + return PHY_TRUE;
494 +}
495 +
496 +//not used on SoC
497 +PHY_INT32 u2_save_cur_en(struct u3phy_info *info){
498 + return PHY_TRUE;
499 +}
500 +
501 +//not used on SoC
502 +PHY_INT32 u2_save_cur_re(struct u3phy_info *info){
503 + return PHY_TRUE;
504 +}
505 +
506 +PHY_INT32 u2_slew_rate_calibration(struct u3phy_info *info){
507 + PHY_INT32 i=0;
508 + //PHY_INT32 j=0;
509 + //PHY_INT8 u1SrCalVal = 0;
510 + //PHY_INT8 u1Reg_addr_HSTX_SRCAL_EN;
511 + PHY_INT32 fgRet = 0;
512 + PHY_INT32 u4FmOut = 0;
513 + PHY_INT32 u4Tmp = 0;
514 + //PHY_INT32 temp;
515 +
516 + // => RG_USB20_HSTX_SRCAL_EN = 1
517 + // enable HS TX SR calibration
518 + U3PhyWriteField32(((PHY_UINT32)&info->u2phy_regs->u2phyacr0)
519 + , RG_USB20_HSTX_SRCAL_EN_OFST, RG_USB20_HSTX_SRCAL_EN, 0x1);
520 + DRV_MSLEEP(1);
521 +
522 + // => RG_FRCK_EN = 1
523 + // Enable free run clock
524 + U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmmonr1)
525 + , RG_FRCK_EN_OFST, RG_FRCK_EN, 1);
526 +
527 + // MT6290 HS signal quality patch
528 + // => RG_CYCLECNT = 400
529 + // Setting cyclecnt =400
530 + U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmcr0)
531 + , RG_CYCLECNT_OFST, RG_CYCLECNT, 0x400);
532 +
533 + // => RG_FREQDET_EN = 1
534 + // Enable frequency meter
535 + U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmcr0)
536 + , RG_FREQDET_EN_OFST, RG_FREQDET_EN, 0x1);
537 +
538 + // wait for FM detection done, set 10ms timeout
539 + for(i=0; i<10; i++){
540 + // => u4FmOut = USB_FM_OUT
541 + // read FM_OUT
542 + u4FmOut = U3PhyReadReg32(((PHY_UINT32)&info->sifslv_fm_regs->fmmonr0));
543 + printk("FM_OUT value: u4FmOut = %d(0x%08X)\n", u4FmOut, u4FmOut);
544 +
545 + // check if FM detection done
546 + if (u4FmOut != 0)
547 + {
548 + fgRet = 0;
549 + printk("FM detection done! loop = %d\n", i);
550 +
551 + break;
552 + }
553 +
554 + fgRet = 1;
555 + DRV_MSLEEP(1);
556 + }
557 + // => RG_FREQDET_EN = 0
558 + // disable frequency meter
559 + U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmcr0)
560 + , RG_FREQDET_EN_OFST, RG_FREQDET_EN, 0);
561 +
562 + // => RG_FRCK_EN = 0
563 + // disable free run clock
564 + U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmmonr1)
565 + , RG_FRCK_EN_OFST, RG_FRCK_EN, 0);
566 +
567 + // => RG_USB20_HSTX_SRCAL_EN = 0
568 + // disable HS TX SR calibration
569 + U3PhyWriteField32(((PHY_UINT32)&info->u2phy_regs->u2phyacr0)
570 + , RG_USB20_HSTX_SRCAL_EN_OFST, RG_USB20_HSTX_SRCAL_EN, 0);
571 + DRV_MSLEEP(1);
572 +
573 + if(u4FmOut == 0){
574 + U3PhyWriteField32(((PHY_UINT32)&info->u2phy_regs->u2phyacr0)
575 + , RG_USB20_HSTX_SRCTRL_OFST, RG_USB20_HSTX_SRCTRL, 0x4);
576 +
577 + fgRet = 1;
578 + }
579 + else{
580 + // set reg = (1024/FM_OUT) * 25 * 0.028 (round to the nearest digits)
581 + u4Tmp = (((1024 * 25 * U2_SR_COEF_7621) / u4FmOut) + 500) / 1000;
582 + printk("SR calibration value u1SrCalVal = %d\n", (PHY_UINT8)u4Tmp);
583 + U3PhyWriteField32(((PHY_UINT32)&info->u2phy_regs->u2phyacr0)
584 + , RG_USB20_HSTX_SRCTRL_OFST, RG_USB20_HSTX_SRCTRL, u4Tmp);
585 + }
586 + return fgRet;
587 +}
588 +
589 +#endif
590 --- /dev/null
591 +++ b/drivers/usb/host/mtk-phy-7621.h
592 @@ -0,0 +1,2871 @@
593 +#ifdef CONFIG_PROJECT_7621
594 +#ifndef __MTK_PHY_7621_H
595 +#define __MTK_PHY_7621_H
596 +
597 +#define U2_SR_COEF_7621 28
598 +
599 +///////////////////////////////////////////////////////////////////////////////
600 +
601 +struct u2phy_reg {
602 + //0x0
603 + PHY_LE32 u2phyac0;
604 + PHY_LE32 u2phyac1;
605 + PHY_LE32 u2phyac2;
606 + PHY_LE32 reserve0;
607 + //0x10
608 + PHY_LE32 u2phyacr0;
609 + PHY_LE32 u2phyacr1;
610 + PHY_LE32 u2phyacr2;
611 + PHY_LE32 u2phyacr3;
612 + //0x20
613 + PHY_LE32 u2phyacr4;
614 + PHY_LE32 u2phyamon0;
615 + PHY_LE32 reserve1[2];
616 + //0x30~0x50
617 + PHY_LE32 reserve2[12];
618 + //0x60
619 + PHY_LE32 u2phydcr0;
620 + PHY_LE32 u2phydcr1;
621 + PHY_LE32 u2phydtm0;
622 + PHY_LE32 u2phydtm1;
623 + //0x70
624 + PHY_LE32 u2phydmon0;
625 + PHY_LE32 u2phydmon1;
626 + PHY_LE32 u2phydmon2;
627 + PHY_LE32 u2phydmon3;
628 + //0x80
629 + PHY_LE32 u2phybc12c;
630 + PHY_LE32 u2phybc12c1;
631 + PHY_LE32 reserve3[2];
632 + //0x90~0xe0
633 + PHY_LE32 reserve4[24];
634 + //0xf0
635 + PHY_LE32 reserve6[3];
636 + PHY_LE32 regfcom;
637 +};
638 +
639 +//U3D_U2PHYAC0
640 +#define RG_USB20_USBPLL_DIVEN (0x7<<28) //30:28
641 +#define RG_USB20_USBPLL_CKCTRL (0x3<<26) //27:26
642 +#define RG_USB20_USBPLL_PREDIV (0x3<<24) //25:24
643 +#define RG_USB20_USBPLL_FORCE_ON (0x1<<23) //23:23
644 +#define RG_USB20_USBPLL_FBDIV (0x7f<<16) //22:16
645 +#define RG_USB20_REF_EN (0x1<<15) //15:15
646 +#define RG_USB20_INTR_EN (0x1<<14) //14:14
647 +#define RG_USB20_BG_TRIM (0xf<<8) //11:8
648 +#define RG_USB20_BG_RBSEL (0x3<<6) //7:6
649 +#define RG_USB20_BG_RASEL (0x3<<4) //5:4
650 +#define RG_USB20_BGR_DIV (0x3<<2) //3:2
651 +#define RG_SIFSLV_CHP_EN (0x1<<1) //1:1
652 +#define RG_SIFSLV_BGR_EN (0x1<<0) //0:0
653 +
654 +//U3D_U2PHYAC1
655 +#define RG_USB20_VRT_VREF_SEL (0x7<<28) //30:28
656 +#define RG_USB20_TERM_VREF_SEL (0x7<<24) //26:24
657 +#define RG_USB20_MPX_SEL (0xff<<16) //23:16
658 +#define RG_USB20_MPX_OUT_SEL (0x3<<12) //13:12
659 +#define RG_USB20_TX_PH_ROT_SEL (0x7<<8) //10:8
660 +#define RG_USB20_USBPLL_ACCEN (0x1<<3) //3:3
661 +#define RG_USB20_USBPLL_LF (0x1<<2) //2:2
662 +#define RG_USB20_USBPLL_BR (0x1<<1) //1:1
663 +#define RG_USB20_USBPLL_BP (0x1<<0) //0:0
664 +
665 +//U3D_U2PHYAC2
666 +#define RG_SIFSLV_MAC_BANDGAP_EN (0x1<<17) //17:17
667 +#define RG_SIFSLV_MAC_CHOPPER_EN (0x1<<16) //16:16
668 +#define RG_USB20_CLKREF_REV (0xff<<0) //7:0
669 +
670 +//U3D_U2PHYACR0
671 +#define RG_USB20_ICUSB_EN (0x1<<24) //24:24
672 +#define RG_USB20_HSTX_SRCAL_EN (0x1<<23) //23:23
673 +#define RG_USB20_HSTX_SRCTRL (0x7<<16) //18:16
674 +#define RG_USB20_LS_CR (0x7<<12) //14:12
675 +#define RG_USB20_FS_CR (0x7<<8) //10:8
676 +#define RG_USB20_LS_SR (0x7<<4) //6:4
677 +#define RG_USB20_FS_SR (0x7<<0) //2:0
678 +
679 +//U3D_U2PHYACR1
680 +#define RG_USB20_INIT_SQ_EN_DG (0x3<<28) //29:28
681 +#define RG_USB20_SQD (0x3<<24) //25:24
682 +#define RG_USB20_HSTX_TMODE_SEL (0x3<<20) //21:20
683 +#define RG_USB20_HSTX_TMODE_EN (0x1<<19) //19:19
684 +#define RG_USB20_PHYD_MONEN (0x1<<18) //18:18
685 +#define RG_USB20_INLPBK_EN (0x1<<17) //17:17
686 +#define RG_USB20_CHIRP_EN (0x1<<16) //16:16
687 +#define RG_USB20_DM_ABIST_SOURCE_EN (0x1<<15) //15:15
688 +#define RG_USB20_DM_ABIST_SELE (0xf<<8) //11:8
689 +#define RG_USB20_DP_ABIST_SOURCE_EN (0x1<<7) //7:7
690 +#define RG_USB20_DP_ABIST_SELE (0xf<<0) //3:0
691 +
692 +//U3D_U2PHYACR2
693 +#define RG_USB20_OTG_ABIST_SELE (0x7<<29) //31:29
694 +#define RG_USB20_OTG_ABIST_EN (0x1<<28) //28:28
695 +#define RG_USB20_OTG_VBUSCMP_EN (0x1<<27) //27:27
696 +#define RG_USB20_OTG_VBUSTH (0x7<<24) //26:24
697 +#define RG_USB20_DISC_FIT_EN (0x1<<22) //22:22
698 +#define RG_USB20_DISCD (0x3<<20) //21:20
699 +#define RG_USB20_DISCTH (0xf<<16) //19:16
700 +#define RG_USB20_SQCAL_EN (0x1<<15) //15:15
701 +#define RG_USB20_SQCAL (0xf<<8) //11:8
702 +#define RG_USB20_SQTH (0xf<<0) //3:0
703 +
704 +//U3D_U2PHYACR3
705 +#define RG_USB20_HSTX_DBIST (0xf<<28) //31:28
706 +#define RG_USB20_HSTX_BIST_EN (0x1<<26) //26:26
707 +#define RG_USB20_HSTX_I_EN_MODE (0x3<<24) //25:24
708 +#define RG_USB20_HSRX_TMODE_EN (0x1<<23) //23:23
709 +#define RG_USB20_HSRX_BIAS_EN_SEL (0x3<<20) //21:20
710 +#define RG_USB20_USB11_TMODE_EN (0x1<<19) //19:19
711 +#define RG_USB20_TMODE_FS_LS_TX_EN (0x1<<18) //18:18
712 +#define RG_USB20_TMODE_FS_LS_RCV_EN (0x1<<17) //17:17
713 +#define RG_USB20_TMODE_FS_LS_MODE (0x1<<16) //16:16
714 +#define RG_USB20_HS_TERM_EN_MODE (0x3<<13) //14:13
715 +#define RG_USB20_PUPD_BIST_EN (0x1<<12) //12:12
716 +#define RG_USB20_EN_PU_DM (0x1<<11) //11:11
717 +#define RG_USB20_EN_PD_DM (0x1<<10) //10:10
718 +#define RG_USB20_EN_PU_DP (0x1<<9) //9:9
719 +#define RG_USB20_EN_PD_DP (0x1<<8) //8:8
720 +#define RG_USB20_PHY_REV (0xff<<0) //7:0
721 +
722 +//U3D_U2PHYACR4
723 +#define RG_USB20_DP_100K_MODE (0x1<<18) //18:18
724 +#define RG_USB20_DM_100K_EN (0x1<<17) //17:17
725 +#define USB20_DP_100K_EN (0x1<<16) //16:16
726 +#define USB20_GPIO_DM_I (0x1<<15) //15:15
727 +#define USB20_GPIO_DP_I (0x1<<14) //14:14
728 +#define USB20_GPIO_DM_OE (0x1<<13) //13:13
729 +#define USB20_GPIO_DP_OE (0x1<<12) //12:12
730 +#define RG_USB20_GPIO_CTL (0x1<<9) //9:9
731 +#define USB20_GPIO_MODE (0x1<<8) //8:8
732 +#define RG_USB20_TX_BIAS_EN (0x1<<5) //5:5
733 +#define RG_USB20_TX_VCMPDN_EN (0x1<<4) //4:4
734 +#define RG_USB20_HS_SQ_EN_MODE (0x3<<2) //3:2
735 +#define RG_USB20_HS_RCV_EN_MODE (0x3<<0) //1:0
736 +
737 +//U3D_U2PHYAMON0
738 +#define RGO_USB20_GPIO_DM_O (0x1<<1) //1:1
739 +#define RGO_USB20_GPIO_DP_O (0x1<<0) //0:0
740 +
741 +//U3D_U2PHYDCR0
742 +#define RG_USB20_CDR_TST (0x3<<30) //31:30
743 +#define RG_USB20_GATED_ENB (0x1<<29) //29:29
744 +#define RG_USB20_TESTMODE (0x3<<26) //27:26
745 +#define RG_USB20_PLL_STABLE (0x1<<25) //25:25
746 +#define RG_USB20_PLL_FORCE_ON (0x1<<24) //24:24
747 +#define RG_USB20_PHYD_RESERVE (0xffff<<8) //23:8
748 +#define RG_USB20_EBTHRLD (0x1<<7) //7:7
749 +#define RG_USB20_EARLY_HSTX_I (0x1<<6) //6:6
750 +#define RG_USB20_TX_TST (0x1<<5) //5:5
751 +#define RG_USB20_NEGEDGE_ENB (0x1<<4) //4:4
752 +#define RG_USB20_CDR_FILT (0xf<<0) //3:0
753 +
754 +//U3D_U2PHYDCR1
755 +#define RG_USB20_PROBE_SEL (0xff<<24) //31:24
756 +#define RG_USB20_DRVVBUS (0x1<<23) //23:23
757 +#define RG_DEBUG_EN (0x1<<22) //22:22
758 +#define RG_USB20_OTG_PROBE (0x3<<20) //21:20
759 +#define RG_USB20_SW_PLLMODE (0x3<<18) //19:18
760 +#define RG_USB20_BERTH (0x3<<16) //17:16
761 +#define RG_USB20_LBMODE (0x3<<13) //14:13
762 +#define RG_USB20_FORCE_TAP (0x1<<12) //12:12
763 +#define RG_USB20_TAPSEL (0xfff<<0) //11:0
764 +
765 +//U3D_U2PHYDTM0
766 +#define RG_UART_MODE (0x3<<30) //31:30
767 +#define FORCE_UART_I (0x1<<29) //29:29
768 +#define FORCE_UART_BIAS_EN (0x1<<28) //28:28
769 +#define FORCE_UART_TX_OE (0x1<<27) //27:27
770 +#define FORCE_UART_EN (0x1<<26) //26:26
771 +#define FORCE_USB_CLKEN (0x1<<25) //25:25
772 +#define FORCE_DRVVBUS (0x1<<24) //24:24
773 +#define FORCE_DATAIN (0x1<<23) //23:23
774 +#define FORCE_TXVALID (0x1<<22) //22:22
775 +#define FORCE_DM_PULLDOWN (0x1<<21) //21:21
776 +#define FORCE_DP_PULLDOWN (0x1<<20) //20:20
777 +#define FORCE_XCVRSEL (0x1<<19) //19:19
778 +#define FORCE_SUSPENDM (0x1<<18) //18:18
779 +#define FORCE_TERMSEL (0x1<<17) //17:17
780 +#define FORCE_OPMODE (0x1<<16) //16:16
781 +#define UTMI_MUXSEL (0x1<<15) //15:15
782 +#define RG_RESET (0x1<<14) //14:14
783 +#define RG_DATAIN (0xf<<10) //13:10
784 +#define RG_TXVALIDH (0x1<<9) //9:9
785 +#define RG_TXVALID (0x1<<8) //8:8
786 +#define RG_DMPULLDOWN (0x1<<7) //7:7
787 +#define RG_DPPULLDOWN (0x1<<6) //6:6
788 +#define RG_XCVRSEL (0x3<<4) //5:4
789 +#define RG_SUSPENDM (0x1<<3) //3:3
790 +#define RG_TERMSEL (0x1<<2) //2:2
791 +#define RG_OPMODE (0x3<<0) //1:0
792 +
793 +//U3D_U2PHYDTM1
794 +#define RG_USB20_PRBS7_EN (0x1<<31) //31:31
795 +#define RG_USB20_PRBS7_BITCNT (0x3f<<24) //29:24
796 +#define RG_USB20_CLK48M_EN (0x1<<23) //23:23
797 +#define RG_USB20_CLK60M_EN (0x1<<22) //22:22
798 +#define RG_UART_I (0x1<<19) //19:19
799 +#define RG_UART_BIAS_EN (0x1<<18) //18:18
800 +#define RG_UART_TX_OE (0x1<<17) //17:17
801 +#define RG_UART_EN (0x1<<16) //16:16
802 +#define FORCE_VBUSVALID (0x1<<13) //13:13
803 +#define FORCE_SESSEND (0x1<<12) //12:12
804 +#define FORCE_BVALID (0x1<<11) //11:11
805 +#define FORCE_AVALID (0x1<<10) //10:10
806 +#define FORCE_IDDIG (0x1<<9) //9:9
807 +#define FORCE_IDPULLUP (0x1<<8) //8:8
808 +#define RG_VBUSVALID (0x1<<5) //5:5
809 +#define RG_SESSEND (0x1<<4) //4:4
810 +#define RG_BVALID (0x1<<3) //3:3
811 +#define RG_AVALID (0x1<<2) //2:2
812 +#define RG_IDDIG (0x1<<1) //1:1
813 +#define RG_IDPULLUP (0x1<<0) //0:0
814 +
815 +//U3D_U2PHYDMON0
816 +#define RG_USB20_PRBS7_BERTH (0xff<<0) //7:0
817 +
818 +//U3D_U2PHYDMON1
819 +#define USB20_UART_O (0x1<<31) //31:31
820 +#define RGO_USB20_LB_PASS (0x1<<30) //30:30
821 +#define RGO_USB20_LB_DONE (0x1<<29) //29:29
822 +#define AD_USB20_BVALID (0x1<<28) //28:28
823 +#define USB20_IDDIG (0x1<<27) //27:27
824 +#define AD_USB20_VBUSVALID (0x1<<26) //26:26
825 +#define AD_USB20_SESSEND (0x1<<25) //25:25
826 +#define AD_USB20_AVALID (0x1<<24) //24:24
827 +#define USB20_LINE_STATE (0x3<<22) //23:22
828 +#define USB20_HST_DISCON (0x1<<21) //21:21
829 +#define USB20_TX_READY (0x1<<20) //20:20
830 +#define USB20_RX_ERROR (0x1<<19) //19:19
831 +#define USB20_RX_ACTIVE (0x1<<18) //18:18
832 +#define USB20_RX_VALIDH (0x1<<17) //17:17
833 +#define USB20_RX_VALID (0x1<<16) //16:16
834 +#define USB20_DATA_OUT (0xffff<<0) //15:0
835 +
836 +//U3D_U2PHYDMON2
837 +#define RGO_TXVALID_CNT (0xff<<24) //31:24
838 +#define RGO_RXACTIVE_CNT (0xff<<16) //23:16
839 +#define RGO_USB20_LB_BERCNT (0xff<<8) //15:8
840 +#define USB20_PROBE_OUT (0xff<<0) //7:0
841 +
842 +//U3D_U2PHYDMON3
843 +#define RGO_USB20_PRBS7_ERRCNT (0xffff<<16) //31:16
844 +#define RGO_USB20_PRBS7_DONE (0x1<<3) //3:3
845 +#define RGO_USB20_PRBS7_LOCK (0x1<<2) //2:2
846 +#define RGO_USB20_PRBS7_PASS (0x1<<1) //1:1
847 +#define RGO_USB20_PRBS7_PASSTH (0x1<<0) //0:0
848 +
849 +//U3D_U2PHYBC12C
850 +#define RG_SIFSLV_CHGDT_DEGLCH_CNT (0xf<<28) //31:28
851 +#define RG_SIFSLV_CHGDT_CTRL_CNT (0xf<<24) //27:24
852 +#define RG_SIFSLV_CHGDT_FORCE_MODE (0x1<<16) //16:16
853 +#define RG_CHGDT_ISRC_LEV (0x3<<14) //15:14
854 +#define RG_CHGDT_VDATSRC (0x1<<13) //13:13
855 +#define RG_CHGDT_BGVREF_SEL (0x7<<10) //12:10
856 +#define RG_CHGDT_RDVREF_SEL (0x3<<8) //9:8
857 +#define RG_CHGDT_ISRC_DP (0x1<<7) //7:7
858 +#define RG_SIFSLV_CHGDT_OPOUT_DM (0x1<<6) //6:6
859 +#define RG_CHGDT_VDAT_DM (0x1<<5) //5:5
860 +#define RG_CHGDT_OPOUT_DP (0x1<<4) //4:4
861 +#define RG_SIFSLV_CHGDT_VDAT_DP (0x1<<3) //3:3
862 +#define RG_SIFSLV_CHGDT_COMP_EN (0x1<<2) //2:2
863 +#define RG_SIFSLV_CHGDT_OPDRV_EN (0x1<<1) //1:1
864 +#define RG_CHGDT_EN (0x1<<0) //0:0
865 +
866 +//U3D_U2PHYBC12C1
867 +#define RG_CHGDT_REV (0xff<<0) //7:0
868 +
869 +//U3D_REGFCOM
870 +#define RG_PAGE (0xff<<24) //31:24
871 +#define I2C_MODE (0x1<<16) //16:16
872 +
873 +
874 +/* OFFSET */
875 +
876 +//U3D_U2PHYAC0
877 +#define RG_USB20_USBPLL_DIVEN_OFST (28)
878 +#define RG_USB20_USBPLL_CKCTRL_OFST (26)
879 +#define RG_USB20_USBPLL_PREDIV_OFST (24)
880 +#define RG_USB20_USBPLL_FORCE_ON_OFST (23)
881 +#define RG_USB20_USBPLL_FBDIV_OFST (16)
882 +#define RG_USB20_REF_EN_OFST (15)
883 +#define RG_USB20_INTR_EN_OFST (14)
884 +#define RG_USB20_BG_TRIM_OFST (8)
885 +#define RG_USB20_BG_RBSEL_OFST (6)
886 +#define RG_USB20_BG_RASEL_OFST (4)
887 +#define RG_USB20_BGR_DIV_OFST (2)
888 +#define RG_SIFSLV_CHP_EN_OFST (1)
889 +#define RG_SIFSLV_BGR_EN_OFST (0)
890 +
891 +//U3D_U2PHYAC1
892 +#define RG_USB20_VRT_VREF_SEL_OFST (28)
893 +#define RG_USB20_TERM_VREF_SEL_OFST (24)
894 +#define RG_USB20_MPX_SEL_OFST (16)
895 +#define RG_USB20_MPX_OUT_SEL_OFST (12)
896 +#define RG_USB20_TX_PH_ROT_SEL_OFST (8)
897 +#define RG_USB20_USBPLL_ACCEN_OFST (3)
898 +#define RG_USB20_USBPLL_LF_OFST (2)
899 +#define RG_USB20_USBPLL_BR_OFST (1)
900 +#define RG_USB20_USBPLL_BP_OFST (0)
901 +
902 +//U3D_U2PHYAC2
903 +#define RG_SIFSLV_MAC_BANDGAP_EN_OFST (17)
904 +#define RG_SIFSLV_MAC_CHOPPER_EN_OFST (16)
905 +#define RG_USB20_CLKREF_REV_OFST (0)
906 +
907 +//U3D_U2PHYACR0
908 +#define RG_USB20_ICUSB_EN_OFST (24)
909 +#define RG_USB20_HSTX_SRCAL_EN_OFST (23)
910 +#define RG_USB20_HSTX_SRCTRL_OFST (16)
911 +#define RG_USB20_LS_CR_OFST (12)
912 +#define RG_USB20_FS_CR_OFST (8)
913 +#define RG_USB20_LS_SR_OFST (4)
914 +#define RG_USB20_FS_SR_OFST (0)
915 +
916 +//U3D_U2PHYACR1
917 +#define RG_USB20_INIT_SQ_EN_DG_OFST (28)
918 +#define RG_USB20_SQD_OFST (24)
919 +#define RG_USB20_HSTX_TMODE_SEL_OFST (20)
920 +#define RG_USB20_HSTX_TMODE_EN_OFST (19)
921 +#define RG_USB20_PHYD_MONEN_OFST (18)
922 +#define RG_USB20_INLPBK_EN_OFST (17)
923 +#define RG_USB20_CHIRP_EN_OFST (16)
924 +#define RG_USB20_DM_ABIST_SOURCE_EN_OFST (15)
925 +#define RG_USB20_DM_ABIST_SELE_OFST (8)
926 +#define RG_USB20_DP_ABIST_SOURCE_EN_OFST (7)
927 +#define RG_USB20_DP_ABIST_SELE_OFST (0)
928 +
929 +//U3D_U2PHYACR2
930 +#define RG_USB20_OTG_ABIST_SELE_OFST (29)
931 +#define RG_USB20_OTG_ABIST_EN_OFST (28)
932 +#define RG_USB20_OTG_VBUSCMP_EN_OFST (27)
933 +#define RG_USB20_OTG_VBUSTH_OFST (24)
934 +#define RG_USB20_DISC_FIT_EN_OFST (22)
935 +#define RG_USB20_DISCD_OFST (20)
936 +#define RG_USB20_DISCTH_OFST (16)
937 +#define RG_USB20_SQCAL_EN_OFST (15)
938 +#define RG_USB20_SQCAL_OFST (8)
939 +#define RG_USB20_SQTH_OFST (0)
940 +
941 +//U3D_U2PHYACR3
942 +#define RG_USB20_HSTX_DBIST_OFST (28)
943 +#define RG_USB20_HSTX_BIST_EN_OFST (26)
944 +#define RG_USB20_HSTX_I_EN_MODE_OFST (24)
945 +#define RG_USB20_HSRX_TMODE_EN_OFST (23)
946 +#define RG_USB20_HSRX_BIAS_EN_SEL_OFST (20)
947 +#define RG_USB20_USB11_TMODE_EN_OFST (19)
948 +#define RG_USB20_TMODE_FS_LS_TX_EN_OFST (18)
949 +#define RG_USB20_TMODE_FS_LS_RCV_EN_OFST (17)
950 +#define RG_USB20_TMODE_FS_LS_MODE_OFST (16)
951 +#define RG_USB20_HS_TERM_EN_MODE_OFST (13)
952 +#define RG_USB20_PUPD_BIST_EN_OFST (12)
953 +#define RG_USB20_EN_PU_DM_OFST (11)
954 +#define RG_USB20_EN_PD_DM_OFST (10)
955 +#define RG_USB20_EN_PU_DP_OFST (9)
956 +#define RG_USB20_EN_PD_DP_OFST (8)
957 +#define RG_USB20_PHY_REV_OFST (0)
958 +
959 +//U3D_U2PHYACR4
960 +#define RG_USB20_DP_100K_MODE_OFST (18)
961 +#define RG_USB20_DM_100K_EN_OFST (17)
962 +#define USB20_DP_100K_EN_OFST (16)
963 +#define USB20_GPIO_DM_I_OFST (15)
964 +#define USB20_GPIO_DP_I_OFST (14)
965 +#define USB20_GPIO_DM_OE_OFST (13)
966 +#define USB20_GPIO_DP_OE_OFST (12)
967 +#define RG_USB20_GPIO_CTL_OFST (9)
968 +#define USB20_GPIO_MODE_OFST (8)
969 +#define RG_USB20_TX_BIAS_EN_OFST (5)
970 +#define RG_USB20_TX_VCMPDN_EN_OFST (4)
971 +#define RG_USB20_HS_SQ_EN_MODE_OFST (2)
972 +#define RG_USB20_HS_RCV_EN_MODE_OFST (0)
973 +
974 +//U3D_U2PHYAMON0
975 +#define RGO_USB20_GPIO_DM_O_OFST (1)
976 +#define RGO_USB20_GPIO_DP_O_OFST (0)
977 +
978 +//U3D_U2PHYDCR0
979 +#define RG_USB20_CDR_TST_OFST (30)
980 +#define RG_USB20_GATED_ENB_OFST (29)
981 +#define RG_USB20_TESTMODE_OFST (26)
982 +#define RG_USB20_PLL_STABLE_OFST (25)
983 +#define RG_USB20_PLL_FORCE_ON_OFST (24)
984 +#define RG_USB20_PHYD_RESERVE_OFST (8)
985 +#define RG_USB20_EBTHRLD_OFST (7)
986 +#define RG_USB20_EARLY_HSTX_I_OFST (6)
987 +#define RG_USB20_TX_TST_OFST (5)
988 +#define RG_USB20_NEGEDGE_ENB_OFST (4)
989 +#define RG_USB20_CDR_FILT_OFST (0)
990 +
991 +//U3D_U2PHYDCR1
992 +#define RG_USB20_PROBE_SEL_OFST (24)
993 +#define RG_USB20_DRVVBUS_OFST (23)
994 +#define RG_DEBUG_EN_OFST (22)
995 +#define RG_USB20_OTG_PROBE_OFST (20)
996 +#define RG_USB20_SW_PLLMODE_OFST (18)
997 +#define RG_USB20_BERTH_OFST (16)
998 +#define RG_USB20_LBMODE_OFST (13)
999 +#define RG_USB20_FORCE_TAP_OFST (12)
1000 +#define RG_USB20_TAPSEL_OFST (0)
1001 +
1002 +//U3D_U2PHYDTM0
1003 +#define RG_UART_MODE_OFST (30)
1004 +#define FORCE_UART_I_OFST (29)
1005 +#define FORCE_UART_BIAS_EN_OFST (28)
1006 +#define FORCE_UART_TX_OE_OFST (27)
1007 +#define FORCE_UART_EN_OFST (26)
1008 +#define FORCE_USB_CLKEN_OFST (25)
1009 +#define FORCE_DRVVBUS_OFST (24)
1010 +#define FORCE_DATAIN_OFST (23)
1011 +#define FORCE_TXVALID_OFST (22)
1012 +#define FORCE_DM_PULLDOWN_OFST (21)
1013 +#define FORCE_DP_PULLDOWN_OFST (20)
1014 +#define FORCE_XCVRSEL_OFST (19)
1015 +#define FORCE_SUSPENDM_OFST (18)
1016 +#define FORCE_TERMSEL_OFST (17)
1017 +#define FORCE_OPMODE_OFST (16)
1018 +#define UTMI_MUXSEL_OFST (15)
1019 +#define RG_RESET_OFST (14)
1020 +#define RG_DATAIN_OFST (10)
1021 +#define RG_TXVALIDH_OFST (9)
1022 +#define RG_TXVALID_OFST (8)
1023 +#define RG_DMPULLDOWN_OFST (7)
1024 +#define RG_DPPULLDOWN_OFST (6)
1025 +#define RG_XCVRSEL_OFST (4)
1026 +#define RG_SUSPENDM_OFST (3)
1027 +#define RG_TERMSEL_OFST (2)
1028 +#define RG_OPMODE_OFST (0)
1029 +
1030 +//U3D_U2PHYDTM1
1031 +#define RG_USB20_PRBS7_EN_OFST (31)
1032 +#define RG_USB20_PRBS7_BITCNT_OFST (24)
1033 +#define RG_USB20_CLK48M_EN_OFST (23)
1034 +#define RG_USB20_CLK60M_EN_OFST (22)
1035 +#define RG_UART_I_OFST (19)
1036 +#define RG_UART_BIAS_EN_OFST (18)
1037 +#define RG_UART_TX_OE_OFST (17)
1038 +#define RG_UART_EN_OFST (16)
1039 +#define FORCE_VBUSVALID_OFST (13)
1040 +#define FORCE_SESSEND_OFST (12)
1041 +#define FORCE_BVALID_OFST (11)
1042 +#define FORCE_AVALID_OFST (10)
1043 +#define FORCE_IDDIG_OFST (9)
1044 +#define FORCE_IDPULLUP_OFST (8)
1045 +#define RG_VBUSVALID_OFST (5)
1046 +#define RG_SESSEND_OFST (4)
1047 +#define RG_BVALID_OFST (3)
1048 +#define RG_AVALID_OFST (2)
1049 +#define RG_IDDIG_OFST (1)
1050 +#define RG_IDPULLUP_OFST (0)
1051 +
1052 +//U3D_U2PHYDMON0
1053 +#define RG_USB20_PRBS7_BERTH_OFST (0)
1054 +
1055 +//U3D_U2PHYDMON1
1056 +#define USB20_UART_O_OFST (31)
1057 +#define RGO_USB20_LB_PASS_OFST (30)
1058 +#define RGO_USB20_LB_DONE_OFST (29)
1059 +#define AD_USB20_BVALID_OFST (28)
1060 +#define USB20_IDDIG_OFST (27)
1061 +#define AD_USB20_VBUSVALID_OFST (26)
1062 +#define AD_USB20_SESSEND_OFST (25)
1063 +#define AD_USB20_AVALID_OFST (24)
1064 +#define USB20_LINE_STATE_OFST (22)
1065 +#define USB20_HST_DISCON_OFST (21)
1066 +#define USB20_TX_READY_OFST (20)
1067 +#define USB20_RX_ERROR_OFST (19)
1068 +#define USB20_RX_ACTIVE_OFST (18)
1069 +#define USB20_RX_VALIDH_OFST (17)
1070 +#define USB20_RX_VALID_OFST (16)
1071 +#define USB20_DATA_OUT_OFST (0)
1072 +
1073 +//U3D_U2PHYDMON2
1074 +#define RGO_TXVALID_CNT_OFST (24)
1075 +#define RGO_RXACTIVE_CNT_OFST (16)
1076 +#define RGO_USB20_LB_BERCNT_OFST (8)
1077 +#define USB20_PROBE_OUT_OFST (0)
1078 +
1079 +//U3D_U2PHYDMON3
1080 +#define RGO_USB20_PRBS7_ERRCNT_OFST (16)
1081 +#define RGO_USB20_PRBS7_DONE_OFST (3)
1082 +#define RGO_USB20_PRBS7_LOCK_OFST (2)
1083 +#define RGO_USB20_PRBS7_PASS_OFST (1)
1084 +#define RGO_USB20_PRBS7_PASSTH_OFST (0)
1085 +
1086 +//U3D_U2PHYBC12C
1087 +#define RG_SIFSLV_CHGDT_DEGLCH_CNT_OFST (28)
1088 +#define RG_SIFSLV_CHGDT_CTRL_CNT_OFST (24)
1089 +#define RG_SIFSLV_CHGDT_FORCE_MODE_OFST (16)
1090 +#define RG_CHGDT_ISRC_LEV_OFST (14)
1091 +#define RG_CHGDT_VDATSRC_OFST (13)
1092 +#define RG_CHGDT_BGVREF_SEL_OFST (10)
1093 +#define RG_CHGDT_RDVREF_SEL_OFST (8)
1094 +#define RG_CHGDT_ISRC_DP_OFST (7)
1095 +#define RG_SIFSLV_CHGDT_OPOUT_DM_OFST (6)
1096 +#define RG_CHGDT_VDAT_DM_OFST (5)
1097 +#define RG_CHGDT_OPOUT_DP_OFST (4)
1098 +#define RG_SIFSLV_CHGDT_VDAT_DP_OFST (3)
1099 +#define RG_SIFSLV_CHGDT_COMP_EN_OFST (2)
1100 +#define RG_SIFSLV_CHGDT_OPDRV_EN_OFST (1)
1101 +#define RG_CHGDT_EN_OFST (0)
1102 +
1103 +//U3D_U2PHYBC12C1
1104 +#define RG_CHGDT_REV_OFST (0)
1105 +
1106 +//U3D_REGFCOM
1107 +#define RG_PAGE_OFST (24)
1108 +#define I2C_MODE_OFST (16)
1109 +
1110 +
1111 +///////////////////////////////////////////////////////////////////////////////
1112 +
1113 +struct u3phya_reg {
1114 + //0x0
1115 + PHY_LE32 reg0;
1116 + PHY_LE32 reg1;
1117 + PHY_LE32 reg2;
1118 + PHY_LE32 reg3;
1119 + //0x10
1120 + PHY_LE32 reg4;
1121 + PHY_LE32 reg5;
1122 + PHY_LE32 reg6;
1123 + PHY_LE32 reg7;
1124 + //0x20
1125 + PHY_LE32 reg8;
1126 + PHY_LE32 reg9;
1127 + PHY_LE32 rega;
1128 + PHY_LE32 regb;
1129 + //0x30
1130 + PHY_LE32 regc;
1131 + PHY_LE32 regd;
1132 + PHY_LE32 rege;
1133 +};
1134 +
1135 +//U3D_reg0
1136 +#define RG_SSUSB_BGR_EN (0x1<<31) //31:31
1137 +#define RG_SSUSB_CHPEN (0x1<<30) //30:30
1138 +#define RG_SSUSB_BG_DIV (0x3<<28) //29:28
1139 +#define RG_SSUSB_INTR_EN (0x1<<26) //26:26
1140 +#define RG_SSUSB_MPX_OUT_SEL (0x3<<24) //25:24
1141 +#define RG_SSUSB_MPX_SEL (0xff<<16) //23:16
1142 +#define RG_SSUSB_REF_EN (0x1<<15) //15:15
1143 +#define RG_SSUSB_VRT_VREF_SEL (0xf<<11) //14:11
1144 +#define RG_SSUSB_BG_RASEL (0x3<<9) //10:9
1145 +#define RG_SSUSB_BG_RBSEL (0x3<<7) //8:7
1146 +#define RG_SSUSB_BG_MONEN (0x1<<6) //6:6
1147 +#define RG_PCIE_CLKDRV_OFFSET (0x3<<0) //1:0
1148 +
1149 +//U3D_reg1
1150 +#define RG_PCIE_CLKDRV_SLEW (0x3<<30) //31:30
1151 +#define RG_PCIE_CLKDRV_AMP (0x7<<27) //29:27
1152 +#define RG_SSUSB_XTAL_TST_A2DCK_EN (0x1<<26) //26:26
1153 +#define RG_SSUSB_XTAL_MON_EN (0x1<<25) //25:25
1154 +#define RG_SSUSB_XTAL_HYS (0x1<<24) //24:24
1155 +#define RG_SSUSB_XTAL_TOP_RESERVE (0xffff<<8) //23:8
1156 +#define RG_SSUSB_SYSPLL_RESERVE (0xf<<4) //7:4
1157 +#define RG_SSUSB_SYSPLL_FBSEL (0x3<<2) //3:2
1158 +#define RG_SSUSB_SYSPLL_PREDIV (0x3<<0) //1:0
1159 +
1160 +//U3D_reg2
1161 +#define RG_SSUSB_SYSPLL_LF (0x1<<31) //31:31
1162 +#define RG_SSUSB_SYSPLL_FBDIV (0x7f<<24) //30:24
1163 +#define RG_SSUSB_SYSPLL_POSDIV (0x3<<22) //23:22
1164 +#define RG_SSUSB_SYSPLL_VCO_DIV_SEL (0x1<<21) //21:21
1165 +#define RG_SSUSB_SYSPLL_BLP (0x1<<20) //20:20
1166 +#define RG_SSUSB_SYSPLL_BP (0x1<<19) //19:19
1167 +#define RG_SSUSB_SYSPLL_BR (0x1<<18) //18:18
1168 +#define RG_SSUSB_SYSPLL_BC (0x1<<17) //17:17
1169 +#define RG_SSUSB_SYSPLL_DIVEN (0x7<<14) //16:14
1170 +#define RG_SSUSB_SYSPLL_FPEN (0x1<<13) //13:13
1171 +#define RG_SSUSB_SYSPLL_MONCK_EN (0x1<<12) //12:12
1172 +#define RG_SSUSB_SYSPLL_MONVC_EN (0x1<<11) //11:11
1173 +#define RG_SSUSB_SYSPLL_MONREF_EN (0x1<<10) //10:10
1174 +#define RG_SSUSB_SYSPLL_VOD_EN (0x1<<9) //9:9
1175 +#define RG_SSUSB_SYSPLL_CK_SEL (0x1<<8) //8:8
1176 +
1177 +//U3D_reg3
1178 +#define RG_SSUSB_SYSPLL_TOP_RESERVE (0xffff<<16) //31:16
1179 +
1180 +//U3D_reg4
1181 +#define RG_SSUSB_SYSPLL_PCW_NCPO (0x7fffffff<<1) //31:1
1182 +
1183 +//U3D_reg5
1184 +#define RG_SSUSB_SYSPLL_DDS_PI_C (0x7<<29) //31:29
1185 +#define RG_SSUSB_SYSPLL_DDS_HF_EN (0x1<<28) //28:28
1186 +#define RG_SSUSB_SYSPLL_DDS_PREDIV2 (0x1<<27) //27:27
1187 +#define RG_SSUSB_SYSPLL_DDS_POSTDIV2 (0x1<<26) //26:26
1188 +#define RG_SSUSB_SYSPLL_DDS_PI_PL_EN (0x1<<25) //25:25
1189 +#define RG_SSUSB_SYSPLL_DDS_PI_RST_SEL (0x1<<24) //24:24
1190 +#define RG_SSUSB_SYSPLL_DDS_MONEN (0x1<<23) //23:23
1191 +#define RG_SSUSB_SYSPLL_DDS_LPF_EN (0x1<<22) //22:22
1192 +#define RG_SSUSB_SYSPLL_CLK_PH_INV (0x1<<21) //21:21
1193 +#define RG_SSUSB_SYSPLL_DDS_SEL_EXT (0x1<<20) //20:20
1194 +#define RG_SSUSB_SYSPLL_DDS_DMY (0xffff<<0) //15:0
1195 +
1196 +//U3D_reg6
1197 +#define RG_SSUSB_TX250MCK_INVB (0x1<<31) //31:31
1198 +#define RG_SSUSB_IDRV_ITAILOP_EN (0x1<<30) //30:30
1199 +#define RG_SSUSB_IDRV_CALIB (0x3f<<24) //29:24
1200 +#define RG_SSUSB_TX_R50_FON (0x1<<23) //23:23
1201 +#define RG_SSUSB_TX_SR (0x7<<20) //22:20
1202 +#define RG_SSUSB_TX_EIDLE_CM (0xf<<16) //19:16
1203 +#define RG_SSUSB_RXDET_RSEL (0x3<<14) //15:14
1204 +#define RG_SSUSB_RXDET_VTHSEL (0x3<<12) //13:12
1205 +#define RG_SSUSB_CKMON_EN (0x1<<11) //11:11
1206 +#define RG_SSUSB_CKMON_SEL (0x7<<8) //10:8
1207 +#define RG_SSUSB_TX_VLMON_EN (0x1<<7) //7:7
1208 +#define RG_SSUSB_TX_VLMON_SEL (0x1<<6) //6:6
1209 +#define RG_SSUSB_RXLBTX_EN (0x1<<5) //5:5
1210 +#define RG_SSUSB_TXLBRX_EN (0x1<<4) //4:4
1211 +
1212 +//U3D_reg7
1213 +#define RG_SSUSB_RESERVE (0xfffff<<12) //31:12
1214 +#define RG_SSUSB_PLL_CKCTRL (0x3<<10) //11:10
1215 +#define RG_SSUSB_PLL_POSDIV (0x3<<8) //9:8
1216 +#define RG_SSUSB_PLL_AUTOK_LOAD (0x1<<7) //7:7
1217 +#define RG_SSUSB_PLL_LOAD_RSTB (0x1<<6) //6:6
1218 +#define RG_SSUSB_PLL_EP_EN (0x1<<5) //5:5
1219 +#define RG_SSUSB_PLL_VOD_EN (0x1<<4) //4:4
1220 +#define RG_SSUSB_PLL_V11_EN (0x1<<3) //3:3
1221 +#define RG_SSUSB_PLL_MONREF_EN (0x1<<2) //2:2
1222 +#define RG_SSUSB_PLL_MONCK_EN (0x1<<1) //1:1
1223 +#define RG_SSUSB_PLL_MONVC_EN (0x1<<0) //0:0
1224 +
1225 +//U3D_reg8
1226 +#define RG_SSUSB_PLL_RESERVE (0xffff<<0) //15:0
1227 +
1228 +//U3D_reg9
1229 +#define RG_SSUSB_PLL_DDS_DMY (0xffff<<16) //31:16
1230 +#define RG_SSUSB_PLL_SSC_PRD (0xffff<<0) //15:0
1231 +
1232 +//U3D_regA
1233 +#define RG_SSUSB_PLL_SSC_PHASE_INI (0x1<<31) //31:31
1234 +#define RG_SSUSB_PLL_SSC_TRI_EN (0x1<<30) //30:30
1235 +#define RG_SSUSB_PLL_CLK_PH_INV (0x1<<29) //29:29
1236 +#define RG_SSUSB_PLL_DDS_LPF_EN (0x1<<28) //28:28
1237 +#define RG_SSUSB_PLL_DDS_VADJ (0x7<<21) //23:21
1238 +#define RG_SSUSB_PLL_DDS_MONEN (0x1<<20) //20:20
1239 +#define RG_SSUSB_PLL_DDS_PS_VADJ (0x7<<17) //19:17
1240 +#define RG_SSUSB_PLL_DDS_SEL_EXT (0x1<<16) //16:16
1241 +#define RG_SSUSB_CDR_PD_DIV_BYPASS (0x1<<15) //15:15
1242 +#define RG_SSUSB_CDR_PD_DIV_SEL (0x1<<14) //14:14
1243 +#define RG_SSUSB_CDR_CPBIAS_SEL (0x1<<13) //13:13
1244 +#define RG_SSUSB_CDR_OSCDET_EN (0x1<<12) //12:12
1245 +#define RG_SSUSB_CDR_MONMUX (0x1<<11) //11:11
1246 +#define RG_SSUSB_CDR_CKCTRL (0x3<<9) //10:9
1247 +#define RG_SSUSB_CDR_ACCEN (0x1<<8) //8:8
1248 +#define RG_SSUSB_CDR_BYPASS (0x3<<6) //7:6
1249 +#define RG_SSUSB_CDR_PI_SLEW (0x3<<4) //5:4
1250 +#define RG_SSUSB_CDR_EPEN (0x1<<3) //3:3
1251 +#define RG_SSUSB_CDR_AUTOK_LOAD (0x1<<2) //2:2
1252 +#define RG_SSUSB_CDR_LOAD_RSTB (0x1<<1) //1:1
1253 +#define RG_SSUSB_CDR_MONEN (0x1<<0) //0:0
1254 +
1255 +//U3D_regB
1256 +#define RG_SSUSB_CDR_MONEN_DIG (0x1<<31) //31:31
1257 +#define RG_SSUSB_CDR_REGOD (0x3<<29) //30:29
1258 +#define RG_SSUSB_RX_DAC_EN (0x1<<26) //26:26
1259 +#define RG_SSUSB_RX_DAC_PWD (0x1<<25) //25:25
1260 +#define RG_SSUSB_EQ_CURSEL (0x1<<24) //24:24
1261 +#define RG_SSUSB_RX_DAC_MUX (0x1f<<19) //23:19
1262 +#define RG_SSUSB_RX_R2T_EN (0x1<<18) //18:18
1263 +#define RG_SSUSB_RX_T2R_EN (0x1<<17) //17:17
1264 +#define RG_SSUSB_RX_50_LOWER (0x7<<14) //16:14
1265 +#define RG_SSUSB_RX_50_TAR (0x3<<12) //13:12
1266 +#define RG_SSUSB_RX_SW_CTRL (0xf<<7) //10:7
1267 +#define RG_PCIE_SIGDET_VTH (0x3<<5) //6:5
1268 +#define RG_PCIE_SIGDET_LPF (0x3<<3) //4:3
1269 +#define RG_SSUSB_LFPS_MON_EN (0x1<<2) //2:2
1270 +
1271 +//U3D_regC
1272 +#define RG_SSUSB_RXAFE_DCMON_SEL (0xf<<28) //31:28
1273 +#define RG_SSUSB_CDR_RESERVE (0xff<<16) //23:16
1274 +#define RG_SSUSB_RXAFE_RESERVE (0xff<<8) //15:8
1275 +#define RG_PCIE_RX_RESERVE (0xff<<0) //7:0
1276 +
1277 +//U3D_redD
1278 +#define RGS_SSUSB_CDR_NO_OSC (0x1<<8) //8:8
1279 +#define RGS_SSUSB_RX_DEBUG_RESERVE (0xff<<0) //7:0
1280 +
1281 +//U3D_regE
1282 +#define RG_SSUSB_INT_BIAS_SEL (0x1<<4) //4:4
1283 +#define RG_SSUSB_EXT_BIAS_SEL (0x1<<3) //3:3
1284 +#define RG_SSUSB_RX_P1_ENTRY_PASS (0x1<<2) //2:2
1285 +#define RG_SSUSB_RX_PD_RST (0x1<<1) //1:1
1286 +#define RG_SSUSB_RX_PD_RST_PASS (0x1<<0) //0:0
1287 +
1288 +
1289 +/* OFFSET */
1290 +
1291 +//U3D_reg0
1292 +#define RG_SSUSB_BGR_EN_OFST (31)
1293 +#define RG_SSUSB_CHPEN_OFST (30)
1294 +#define RG_SSUSB_BG_DIV_OFST (28)
1295 +#define RG_SSUSB_INTR_EN_OFST (26)
1296 +#define RG_SSUSB_MPX_OUT_SEL_OFST (24)
1297 +#define RG_SSUSB_MPX_SEL_OFST (16)
1298 +#define RG_SSUSB_REF_EN_OFST (15)
1299 +#define RG_SSUSB_VRT_VREF_SEL_OFST (11)
1300 +#define RG_SSUSB_BG_RASEL_OFST (9)
1301 +#define RG_SSUSB_BG_RBSEL_OFST (7)
1302 +#define RG_SSUSB_BG_MONEN_OFST (6)
1303 +#define RG_PCIE_CLKDRV_OFFSET_OFST (0)
1304 +
1305 +//U3D_reg1
1306 +#define RG_PCIE_CLKDRV_SLEW_OFST (30)
1307 +#define RG_PCIE_CLKDRV_AMP_OFST (27)
1308 +#define RG_SSUSB_XTAL_TST_A2DCK_EN_OFST (26)
1309 +#define RG_SSUSB_XTAL_MON_EN_OFST (25)
1310 +#define RG_SSUSB_XTAL_HYS_OFST (24)
1311 +#define RG_SSUSB_XTAL_TOP_RESERVE_OFST (8)
1312 +#define RG_SSUSB_SYSPLL_RESERVE_OFST (4)
1313 +#define RG_SSUSB_SYSPLL_FBSEL_OFST (2)
1314 +#define RG_SSUSB_SYSPLL_PREDIV_OFST (0)
1315 +
1316 +//U3D_reg2
1317 +#define RG_SSUSB_SYSPLL_LF_OFST (31)
1318 +#define RG_SSUSB_SYSPLL_FBDIV_OFST (24)
1319 +#define RG_SSUSB_SYSPLL_POSDIV_OFST (22)
1320 +#define RG_SSUSB_SYSPLL_VCO_DIV_SEL_OFST (21)
1321 +#define RG_SSUSB_SYSPLL_BLP_OFST (20)
1322 +#define RG_SSUSB_SYSPLL_BP_OFST (19)
1323 +#define RG_SSUSB_SYSPLL_BR_OFST (18)
1324 +#define RG_SSUSB_SYSPLL_BC_OFST (17)
1325 +#define RG_SSUSB_SYSPLL_DIVEN_OFST (14)
1326 +#define RG_SSUSB_SYSPLL_FPEN_OFST (13)
1327 +#define RG_SSUSB_SYSPLL_MONCK_EN_OFST (12)
1328 +#define RG_SSUSB_SYSPLL_MONVC_EN_OFST (11)
1329 +#define RG_SSUSB_SYSPLL_MONREF_EN_OFST (10)
1330 +#define RG_SSUSB_SYSPLL_VOD_EN_OFST (9)
1331 +#define RG_SSUSB_SYSPLL_CK_SEL_OFST (8)
1332 +
1333 +//U3D_reg3
1334 +#define RG_SSUSB_SYSPLL_TOP_RESERVE_OFST (16)
1335 +
1336 +//U3D_reg4
1337 +#define RG_SSUSB_SYSPLL_PCW_NCPO_OFST (1)
1338 +
1339 +//U3D_reg5
1340 +#define RG_SSUSB_SYSPLL_DDS_PI_C_OFST (29)
1341 +#define RG_SSUSB_SYSPLL_DDS_HF_EN_OFST (28)
1342 +#define RG_SSUSB_SYSPLL_DDS_PREDIV2_OFST (27)
1343 +#define RG_SSUSB_SYSPLL_DDS_POSTDIV2_OFST (26)
1344 +#define RG_SSUSB_SYSPLL_DDS_PI_PL_EN_OFST (25)
1345 +#define RG_SSUSB_SYSPLL_DDS_PI_RST_SEL_OFST (24)
1346 +#define RG_SSUSB_SYSPLL_DDS_MONEN_OFST (23)
1347 +#define RG_SSUSB_SYSPLL_DDS_LPF_EN_OFST (22)
1348 +#define RG_SSUSB_SYSPLL_CLK_PH_INV_OFST (21)
1349 +#define RG_SSUSB_SYSPLL_DDS_SEL_EXT_OFST (20)
1350 +#define RG_SSUSB_SYSPLL_DDS_DMY_OFST (0)
1351 +
1352 +//U3D_reg6
1353 +#define RG_SSUSB_TX250MCK_INVB_OFST (31)
1354 +#define RG_SSUSB_IDRV_ITAILOP_EN_OFST (30)
1355 +#define RG_SSUSB_IDRV_CALIB_OFST (24)
1356 +#define RG_SSUSB_TX_R50_FON_OFST (23)
1357 +#define RG_SSUSB_TX_SR_OFST (20)
1358 +#define RG_SSUSB_TX_EIDLE_CM_OFST (16)
1359 +#define RG_SSUSB_RXDET_RSEL_OFST (14)
1360 +#define RG_SSUSB_RXDET_VTHSEL_OFST (12)
1361 +#define RG_SSUSB_CKMON_EN_OFST (11)
1362 +#define RG_SSUSB_CKMON_SEL_OFST (8)
1363 +#define RG_SSUSB_TX_VLMON_EN_OFST (7)
1364 +#define RG_SSUSB_TX_VLMON_SEL_OFST (6)
1365 +#define RG_SSUSB_RXLBTX_EN_OFST (5)
1366 +#define RG_SSUSB_TXLBRX_EN_OFST (4)
1367 +
1368 +//U3D_reg7
1369 +#define RG_SSUSB_RESERVE_OFST (12)
1370 +#define RG_SSUSB_PLL_CKCTRL_OFST (10)
1371 +#define RG_SSUSB_PLL_POSDIV_OFST (8)
1372 +#define RG_SSUSB_PLL_AUTOK_LOAD_OFST (7)
1373 +#define RG_SSUSB_PLL_LOAD_RSTB_OFST (6)
1374 +#define RG_SSUSB_PLL_EP_EN_OFST (5)
1375 +#define RG_SSUSB_PLL_VOD_EN_OFST (4)
1376 +#define RG_SSUSB_PLL_V11_EN_OFST (3)
1377 +#define RG_SSUSB_PLL_MONREF_EN_OFST (2)
1378 +#define RG_SSUSB_PLL_MONCK_EN_OFST (1)
1379 +#define RG_SSUSB_PLL_MONVC_EN_OFST (0)
1380 +
1381 +//U3D_reg8
1382 +#define RG_SSUSB_PLL_RESERVE_OFST (0)
1383 +
1384 +//U3D_reg9
1385 +#define RG_SSUSB_PLL_DDS_DMY_OFST (16)
1386 +#define RG_SSUSB_PLL_SSC_PRD_OFST (0)
1387 +
1388 +//U3D_regA
1389 +#define RG_SSUSB_PLL_SSC_PHASE_INI_OFST (31)
1390 +#define RG_SSUSB_PLL_SSC_TRI_EN_OFST (30)
1391 +#define RG_SSUSB_PLL_CLK_PH_INV_OFST (29)
1392 +#define RG_SSUSB_PLL_DDS_LPF_EN_OFST (28)
1393 +#define RG_SSUSB_PLL_DDS_VADJ_OFST (21)
1394 +#define RG_SSUSB_PLL_DDS_MONEN_OFST (20)
1395 +#define RG_SSUSB_PLL_DDS_PS_VADJ_OFST (17)
1396 +#define RG_SSUSB_PLL_DDS_SEL_EXT_OFST (16)
1397 +#define RG_SSUSB_CDR_PD_DIV_BYPASS_OFST (15)
1398 +#define RG_SSUSB_CDR_PD_DIV_SEL_OFST (14)
1399 +#define RG_SSUSB_CDR_CPBIAS_SEL_OFST (13)
1400 +#define RG_SSUSB_CDR_OSCDET_EN_OFST (12)
1401 +#define RG_SSUSB_CDR_MONMUX_OFST (11)
1402 +#define RG_SSUSB_CDR_CKCTRL_OFST (9)
1403 +#define RG_SSUSB_CDR_ACCEN_OFST (8)
1404 +#define RG_SSUSB_CDR_BYPASS_OFST (6)
1405 +#define RG_SSUSB_CDR_PI_SLEW_OFST (4)
1406 +#define RG_SSUSB_CDR_EPEN_OFST (3)
1407 +#define RG_SSUSB_CDR_AUTOK_LOAD_OFST (2)
1408 +#define RG_SSUSB_CDR_LOAD_RSTB_OFST (1)
1409 +#define RG_SSUSB_CDR_MONEN_OFST (0)
1410 +
1411 +//U3D_regB
1412 +#define RG_SSUSB_CDR_MONEN_DIG_OFST (31)
1413 +#define RG_SSUSB_CDR_REGOD_OFST (29)
1414 +#define RG_SSUSB_RX_DAC_EN_OFST (26)
1415 +#define RG_SSUSB_RX_DAC_PWD_OFST (25)
1416 +#define RG_SSUSB_EQ_CURSEL_OFST (24)
1417 +#define RG_SSUSB_RX_DAC_MUX_OFST (19)
1418 +#define RG_SSUSB_RX_R2T_EN_OFST (18)
1419 +#define RG_SSUSB_RX_T2R_EN_OFST (17)
1420 +#define RG_SSUSB_RX_50_LOWER_OFST (14)
1421 +#define RG_SSUSB_RX_50_TAR_OFST (12)
1422 +#define RG_SSUSB_RX_SW_CTRL_OFST (7)
1423 +#define RG_PCIE_SIGDET_VTH_OFST (5)
1424 +#define RG_PCIE_SIGDET_LPF_OFST (3)
1425 +#define RG_SSUSB_LFPS_MON_EN_OFST (2)
1426 +
1427 +//U3D_regC
1428 +#define RG_SSUSB_RXAFE_DCMON_SEL_OFST (28)
1429 +#define RG_SSUSB_CDR_RESERVE_OFST (16)
1430 +#define RG_SSUSB_RXAFE_RESERVE_OFST (8)
1431 +#define RG_PCIE_RX_RESERVE_OFST (0)
1432 +
1433 +//U3D_redD
1434 +#define RGS_SSUSB_CDR_NO_OSC_OFST (8)
1435 +#define RGS_SSUSB_RX_DEBUG_RESERVE_OFST (0)
1436 +
1437 +//U3D_regE
1438 +#define RG_SSUSB_INT_BIAS_SEL_OFST (4)
1439 +#define RG_SSUSB_EXT_BIAS_SEL_OFST (3)
1440 +#define RG_SSUSB_RX_P1_ENTRY_PASS_OFST (2)
1441 +#define RG_SSUSB_RX_PD_RST_OFST (1)
1442 +#define RG_SSUSB_RX_PD_RST_PASS_OFST (0)
1443 +
1444 +///////////////////////////////////////////////////////////////////////////////
1445 +
1446 +struct u3phya_da_reg {
1447 + //0x0
1448 + PHY_LE32 reg0;
1449 + PHY_LE32 reg1;
1450 + PHY_LE32 reg4;
1451 + PHY_LE32 reg5;
1452 + //0x10
1453 + PHY_LE32 reg6;
1454 + PHY_LE32 reg7;
1455 + PHY_LE32 reg8;
1456 + PHY_LE32 reg9;
1457 + //0x20
1458 + PHY_LE32 reg10;
1459 + PHY_LE32 reg12;
1460 + PHY_LE32 reg13;
1461 + PHY_LE32 reg14;
1462 + //0x30
1463 + PHY_LE32 reg15;
1464 + PHY_LE32 reg16;
1465 + PHY_LE32 reg19;
1466 + PHY_LE32 reg20;
1467 + //0x40
1468 + PHY_LE32 reg21;
1469 + PHY_LE32 reg23;
1470 + PHY_LE32 reg25;
1471 + PHY_LE32 reg26;
1472 + //0x50
1473 + PHY_LE32 reg28;
1474 + PHY_LE32 reg29;
1475 + PHY_LE32 reg30;
1476 + PHY_LE32 reg31;
1477 + //0x60
1478 + PHY_LE32 reg32;
1479 + PHY_LE32 reg33;
1480 +};
1481 +
1482 +//U3D_reg0
1483 +#define RG_PCIE_SPEED_PE2D (0x1<<24) //24:24
1484 +#define RG_PCIE_SPEED_PE2H (0x1<<23) //23:23
1485 +#define RG_PCIE_SPEED_PE1D (0x1<<22) //22:22
1486 +#define RG_PCIE_SPEED_PE1H (0x1<<21) //21:21
1487 +#define RG_PCIE_SPEED_U3 (0x1<<20) //20:20
1488 +#define RG_SSUSB_XTAL_EXT_EN_PE2D (0x3<<18) //19:18
1489 +#define RG_SSUSB_XTAL_EXT_EN_PE2H (0x3<<16) //17:16
1490 +#define RG_SSUSB_XTAL_EXT_EN_PE1D (0x3<<14) //15:14
1491 +#define RG_SSUSB_XTAL_EXT_EN_PE1H (0x3<<12) //13:12
1492 +#define RG_SSUSB_XTAL_EXT_EN_U3 (0x3<<10) //11:10
1493 +#define RG_SSUSB_CDR_REFCK_SEL_PE2D (0x3<<8) //9:8
1494 +#define RG_SSUSB_CDR_REFCK_SEL_PE2H (0x3<<6) //7:6
1495 +#define RG_SSUSB_CDR_REFCK_SEL_PE1D (0x3<<4) //5:4
1496 +#define RG_SSUSB_CDR_REFCK_SEL_PE1H (0x3<<2) //3:2
1497 +#define RG_SSUSB_CDR_REFCK_SEL_U3 (0x3<<0) //1:0
1498 +
1499 +//U3D_reg1
1500 +#define RG_USB20_REFCK_SEL_PE2D (0x1<<30) //30:30
1501 +#define RG_USB20_REFCK_SEL_PE2H (0x1<<29) //29:29
1502 +#define RG_USB20_REFCK_SEL_PE1D (0x1<<28) //28:28
1503 +#define RG_USB20_REFCK_SEL_PE1H (0x1<<27) //27:27
1504 +#define RG_USB20_REFCK_SEL_U3 (0x1<<26) //26:26
1505 +#define RG_PCIE_REFCK_DIV4_PE2D (0x1<<25) //25:25
1506 +#define RG_PCIE_REFCK_DIV4_PE2H (0x1<<24) //24:24
1507 +#define RG_PCIE_REFCK_DIV4_PE1D (0x1<<18) //18:18
1508 +#define RG_PCIE_REFCK_DIV4_PE1H (0x1<<17) //17:17
1509 +#define RG_PCIE_REFCK_DIV4_U3 (0x1<<16) //16:16
1510 +#define RG_PCIE_MODE_PE2D (0x1<<8) //8:8
1511 +#define RG_PCIE_MODE_PE2H (0x1<<3) //3:3
1512 +#define RG_PCIE_MODE_PE1D (0x1<<2) //2:2
1513 +#define RG_PCIE_MODE_PE1H (0x1<<1) //1:1
1514 +#define RG_PCIE_MODE_U3 (0x1<<0) //0:0
1515 +
1516 +//U3D_reg4
1517 +#define RG_SSUSB_PLL_DIVEN_PE2D (0x7<<22) //24:22
1518 +#define RG_SSUSB_PLL_DIVEN_PE2H (0x7<<19) //21:19
1519 +#define RG_SSUSB_PLL_DIVEN_PE1D (0x7<<16) //18:16
1520 +#define RG_SSUSB_PLL_DIVEN_PE1H (0x7<<13) //15:13
1521 +#define RG_SSUSB_PLL_DIVEN_U3 (0x7<<10) //12:10
1522 +#define RG_SSUSB_PLL_BC_PE2D (0x3<<8) //9:8
1523 +#define RG_SSUSB_PLL_BC_PE2H (0x3<<6) //7:6
1524 +#define RG_SSUSB_PLL_BC_PE1D (0x3<<4) //5:4
1525 +#define RG_SSUSB_PLL_BC_PE1H (0x3<<2) //3:2
1526 +#define RG_SSUSB_PLL_BC_U3 (0x3<<0) //1:0
1527 +
1528 +//U3D_reg5
1529 +#define RG_SSUSB_PLL_BR_PE2D (0x7<<27) //29:27
1530 +#define RG_SSUSB_PLL_BR_PE2H (0x7<<24) //26:24
1531 +#define RG_SSUSB_PLL_BR_PE1D (0x7<<21) //23:21
1532 +#define RG_SSUSB_PLL_BR_PE1H (0x7<<18) //20:18
1533 +#define RG_SSUSB_PLL_BR_U3 (0x7<<15) //17:15
1534 +#define RG_SSUSB_PLL_IC_PE2D (0x7<<12) //14:12
1535 +#define RG_SSUSB_PLL_IC_PE2H (0x7<<9) //11:9
1536 +#define RG_SSUSB_PLL_IC_PE1D (0x7<<6) //8:6
1537 +#define RG_SSUSB_PLL_IC_PE1H (0x7<<3) //5:3
1538 +#define RG_SSUSB_PLL_IC_U3 (0x7<<0) //2:0
1539 +
1540 +//U3D_reg6
1541 +#define RG_SSUSB_PLL_IR_PE2D (0xf<<24) //27:24
1542 +#define RG_SSUSB_PLL_IR_PE2H (0xf<<16) //19:16
1543 +#define RG_SSUSB_PLL_IR_PE1D (0xf<<8) //11:8
1544 +#define RG_SSUSB_PLL_IR_PE1H (0xf<<4) //7:4
1545 +#define RG_SSUSB_PLL_IR_U3 (0xf<<0) //3:0
1546 +
1547 +//U3D_reg7
1548 +#define RG_SSUSB_PLL_BP_PE2D (0xf<<24) //27:24
1549 +#define RG_SSUSB_PLL_BP_PE2H (0xf<<16) //19:16
1550 +#define RG_SSUSB_PLL_BP_PE1D (0xf<<8) //11:8
1551 +#define RG_SSUSB_PLL_BP_PE1H (0xf<<4) //7:4
1552 +#define RG_SSUSB_PLL_BP_U3 (0xf<<0) //3:0
1553 +
1554 +//U3D_reg8
1555 +#define RG_SSUSB_PLL_FBKSEL_PE2D (0x3<<24) //25:24
1556 +#define RG_SSUSB_PLL_FBKSEL_PE2H (0x3<<16) //17:16
1557 +#define RG_SSUSB_PLL_FBKSEL_PE1D (0x3<<8) //9:8
1558 +#define RG_SSUSB_PLL_FBKSEL_PE1H (0x3<<2) //3:2
1559 +#define RG_SSUSB_PLL_FBKSEL_U3 (0x3<<0) //1:0
1560 +
1561 +//U3D_reg9
1562 +#define RG_SSUSB_PLL_FBKDIV_PE2H (0x7f<<24) //30:24
1563 +#define RG_SSUSB_PLL_FBKDIV_PE1D (0x7f<<16) //22:16
1564 +#define RG_SSUSB_PLL_FBKDIV_PE1H (0x7f<<8) //14:8
1565 +#define RG_SSUSB_PLL_FBKDIV_U3 (0x7f<<0) //6:0
1566 +
1567 +//U3D_reg10
1568 +#define RG_SSUSB_PLL_PREDIV_PE2D (0x3<<26) //27:26
1569 +#define RG_SSUSB_PLL_PREDIV_PE2H (0x3<<24) //25:24
1570 +#define RG_SSUSB_PLL_PREDIV_PE1D (0x3<<18) //19:18
1571 +#define RG_SSUSB_PLL_PREDIV_PE1H (0x3<<16) //17:16
1572 +#define RG_SSUSB_PLL_PREDIV_U3 (0x3<<8) //9:8
1573 +#define RG_SSUSB_PLL_FBKDIV_PE2D (0x7f<<0) //6:0
1574 +
1575 +//U3D_reg12
1576 +#define RG_SSUSB_PLL_PCW_NCPO_U3 (0x7fffffff<<0) //30:0
1577 +
1578 +//U3D_reg13
1579 +#define RG_SSUSB_PLL_PCW_NCPO_PE1H (0x7fffffff<<0) //30:0
1580 +
1581 +//U3D_reg14
1582 +#define RG_SSUSB_PLL_PCW_NCPO_PE1D (0x7fffffff<<0) //30:0
1583 +
1584 +//U3D_reg15
1585 +#define RG_SSUSB_PLL_PCW_NCPO_PE2H (0x7fffffff<<0) //30:0
1586 +
1587 +//U3D_reg16
1588 +#define RG_SSUSB_PLL_PCW_NCPO_PE2D (0x7fffffff<<0) //30:0
1589 +
1590 +//U3D_reg19
1591 +#define RG_SSUSB_PLL_SSC_DELTA1_PE1H (0xffff<<16) //31:16
1592 +#define RG_SSUSB_PLL_SSC_DELTA1_U3 (0xffff<<0) //15:0
1593 +
1594 +//U3D_reg20
1595 +#define RG_SSUSB_PLL_SSC_DELTA1_PE2H (0xffff<<16) //31:16
1596 +#define RG_SSUSB_PLL_SSC_DELTA1_PE1D (0xffff<<0) //15:0
1597 +
1598 +//U3D_reg21
1599 +#define RG_SSUSB_PLL_SSC_DELTA_U3 (0xffff<<16) //31:16
1600 +#define RG_SSUSB_PLL_SSC_DELTA1_PE2D (0xffff<<0) //15:0
1601 +
1602 +//U3D_reg23
1603 +#define RG_SSUSB_PLL_SSC_DELTA_PE1D (0xffff<<16) //31:16
1604 +#define RG_SSUSB_PLL_SSC_DELTA_PE1H (0xffff<<0) //15:0
1605 +
1606 +//U3D_reg25
1607 +#define RG_SSUSB_PLL_SSC_DELTA_PE2D (0xffff<<16) //31:16
1608 +#define RG_SSUSB_PLL_SSC_DELTA_PE2H (0xffff<<0) //15:0
1609 +
1610 +//U3D_reg26
1611 +#define RG_SSUSB_PLL_REFCKDIV_PE2D (0x1<<25) //25:25
1612 +#define RG_SSUSB_PLL_REFCKDIV_PE2H (0x1<<24) //24:24
1613 +#define RG_SSUSB_PLL_REFCKDIV_PE1D (0x1<<16) //16:16
1614 +#define RG_SSUSB_PLL_REFCKDIV_PE1H (0x1<<8) //8:8
1615 +#define RG_SSUSB_PLL_REFCKDIV_U3 (0x1<<0) //0:0
1616 +
1617 +//U3D_reg28
1618 +#define RG_SSUSB_CDR_BPA_PE2D (0x3<<24) //25:24
1619 +#define RG_SSUSB_CDR_BPA_PE2H (0x3<<16) //17:16
1620 +#define RG_SSUSB_CDR_BPA_PE1D (0x3<<10) //11:10
1621 +#define RG_SSUSB_CDR_BPA_PE1H (0x3<<8) //9:8
1622 +#define RG_SSUSB_CDR_BPA_U3 (0x3<<0) //1:0
1623 +
1624 +//U3D_reg29
1625 +#define RG_SSUSB_CDR_BPB_PE2D (0x7<<24) //26:24
1626 +#define RG_SSUSB_CDR_BPB_PE2H (0x7<<16) //18:16
1627 +#define RG_SSUSB_CDR_BPB_PE1D (0x7<<6) //8:6
1628 +#define RG_SSUSB_CDR_BPB_PE1H (0x7<<3) //5:3
1629 +#define RG_SSUSB_CDR_BPB_U3 (0x7<<0) //2:0
1630 +
1631 +//U3D_reg30
1632 +#define RG_SSUSB_CDR_BR_PE2D (0x7<<24) //26:24
1633 +#define RG_SSUSB_CDR_BR_PE2H (0x7<<16) //18:16
1634 +#define RG_SSUSB_CDR_BR_PE1D (0x7<<6) //8:6
1635 +#define RG_SSUSB_CDR_BR_PE1H (0x7<<3) //5:3
1636 +#define RG_SSUSB_CDR_BR_U3 (0x7<<0) //2:0
1637 +
1638 +//U3D_reg31
1639 +#define RG_SSUSB_CDR_FBDIV_PE2H (0x7f<<24) //30:24
1640 +#define RG_SSUSB_CDR_FBDIV_PE1D (0x7f<<16) //22:16
1641 +#define RG_SSUSB_CDR_FBDIV_PE1H (0x7f<<8) //14:8
1642 +#define RG_SSUSB_CDR_FBDIV_U3 (0x7f<<0) //6:0
1643 +
1644 +//U3D_reg32
1645 +#define RG_SSUSB_EQ_RSTEP1_PE2D (0x3<<30) //31:30
1646 +#define RG_SSUSB_EQ_RSTEP1_PE2H (0x3<<28) //29:28
1647 +#define RG_SSUSB_EQ_RSTEP1_PE1D (0x3<<26) //27:26
1648 +#define RG_SSUSB_EQ_RSTEP1_PE1H (0x3<<24) //25:24
1649 +#define RG_SSUSB_EQ_RSTEP1_U3 (0x3<<22) //23:22
1650 +#define RG_SSUSB_LFPS_DEGLITCH_PE2D (0x3<<20) //21:20
1651 +#define RG_SSUSB_LFPS_DEGLITCH_PE2H (0x3<<18) //19:18
1652 +#define RG_SSUSB_LFPS_DEGLITCH_PE1D (0x3<<16) //17:16
1653 +#define RG_SSUSB_LFPS_DEGLITCH_PE1H (0x3<<14) //15:14
1654 +#define RG_SSUSB_LFPS_DEGLITCH_U3 (0x3<<12) //13:12
1655 +#define RG_SSUSB_CDR_KVSEL_PE2D (0x1<<11) //11:11
1656 +#define RG_SSUSB_CDR_KVSEL_PE2H (0x1<<10) //10:10
1657 +#define RG_SSUSB_CDR_KVSEL_PE1D (0x1<<9) //9:9
1658 +#define RG_SSUSB_CDR_KVSEL_PE1H (0x1<<8) //8:8
1659 +#define RG_SSUSB_CDR_KVSEL_U3 (0x1<<7) //7:7
1660 +#define RG_SSUSB_CDR_FBDIV_PE2D (0x7f<<0) //6:0
1661 +
1662 +//U3D_reg33
1663 +#define RG_SSUSB_RX_CMPWD_PE2D (0x1<<26) //26:26
1664 +#define RG_SSUSB_RX_CMPWD_PE2H (0x1<<25) //25:25
1665 +#define RG_SSUSB_RX_CMPWD_PE1D (0x1<<24) //24:24
1666 +#define RG_SSUSB_RX_CMPWD_PE1H (0x1<<23) //23:23
1667 +#define RG_SSUSB_RX_CMPWD_U3 (0x1<<16) //16:16
1668 +#define RG_SSUSB_EQ_RSTEP2_PE2D (0x3<<8) //9:8
1669 +#define RG_SSUSB_EQ_RSTEP2_PE2H (0x3<<6) //7:6
1670 +#define RG_SSUSB_EQ_RSTEP2_PE1D (0x3<<4) //5:4
1671 +#define RG_SSUSB_EQ_RSTEP2_PE1H (0x3<<2) //3:2
1672 +#define RG_SSUSB_EQ_RSTEP2_U3 (0x3<<0) //1:0
1673 +
1674 +
1675 +/* OFFSET */
1676 +
1677 +//U3D_reg0
1678 +#define RG_PCIE_SPEED_PE2D_OFST (24)
1679 +#define RG_PCIE_SPEED_PE2H_OFST (23)
1680 +#define RG_PCIE_SPEED_PE1D_OFST (22)
1681 +#define RG_PCIE_SPEED_PE1H_OFST (21)
1682 +#define RG_PCIE_SPEED_U3_OFST (20)
1683 +#define RG_SSUSB_XTAL_EXT_EN_PE2D_OFST (18)
1684 +#define RG_SSUSB_XTAL_EXT_EN_PE2H_OFST (16)
1685 +#define RG_SSUSB_XTAL_EXT_EN_PE1D_OFST (14)
1686 +#define RG_SSUSB_XTAL_EXT_EN_PE1H_OFST (12)
1687 +#define RG_SSUSB_XTAL_EXT_EN_U3_OFST (10)
1688 +#define RG_SSUSB_CDR_REFCK_SEL_PE2D_OFST (8)
1689 +#define RG_SSUSB_CDR_REFCK_SEL_PE2H_OFST (6)
1690 +#define RG_SSUSB_CDR_REFCK_SEL_PE1D_OFST (4)
1691 +#define RG_SSUSB_CDR_REFCK_SEL_PE1H_OFST (2)
1692 +#define RG_SSUSB_CDR_REFCK_SEL_U3_OFST (0)
1693 +
1694 +//U3D_reg1
1695 +#define RG_USB20_REFCK_SEL_PE2D_OFST (30)
1696 +#define RG_USB20_REFCK_SEL_PE2H_OFST (29)
1697 +#define RG_USB20_REFCK_SEL_PE1D_OFST (28)
1698 +#define RG_USB20_REFCK_SEL_PE1H_OFST (27)
1699 +#define RG_USB20_REFCK_SEL_U3_OFST (26)
1700 +#define RG_PCIE_REFCK_DIV4_PE2D_OFST (25)
1701 +#define RG_PCIE_REFCK_DIV4_PE2H_OFST (24)
1702 +#define RG_PCIE_REFCK_DIV4_PE1D_OFST (18)
1703 +#define RG_PCIE_REFCK_DIV4_PE1H_OFST (17)
1704 +#define RG_PCIE_REFCK_DIV4_U3_OFST (16)
1705 +#define RG_PCIE_MODE_PE2D_OFST (8)
1706 +#define RG_PCIE_MODE_PE2H_OFST (3)
1707 +#define RG_PCIE_MODE_PE1D_OFST (2)
1708 +#define RG_PCIE_MODE_PE1H_OFST (1)
1709 +#define RG_PCIE_MODE_U3_OFST (0)
1710 +
1711 +//U3D_reg4
1712 +#define RG_SSUSB_PLL_DIVEN_PE2D_OFST (22)
1713 +#define RG_SSUSB_PLL_DIVEN_PE2H_OFST (19)
1714 +#define RG_SSUSB_PLL_DIVEN_PE1D_OFST (16)
1715 +#define RG_SSUSB_PLL_DIVEN_PE1H_OFST (13)
1716 +#define RG_SSUSB_PLL_DIVEN_U3_OFST (10)
1717 +#define RG_SSUSB_PLL_BC_PE2D_OFST (8)
1718 +#define RG_SSUSB_PLL_BC_PE2H_OFST (6)
1719 +#define RG_SSUSB_PLL_BC_PE1D_OFST (4)
1720 +#define RG_SSUSB_PLL_BC_PE1H_OFST (2)
1721 +#define RG_SSUSB_PLL_BC_U3_OFST (0)
1722 +
1723 +//U3D_reg5
1724 +#define RG_SSUSB_PLL_BR_PE2D_OFST (27)
1725 +#define RG_SSUSB_PLL_BR_PE2H_OFST (24)
1726 +#define RG_SSUSB_PLL_BR_PE1D_OFST (21)
1727 +#define RG_SSUSB_PLL_BR_PE1H_OFST (18)
1728 +#define RG_SSUSB_PLL_BR_U3_OFST (15)
1729 +#define RG_SSUSB_PLL_IC_PE2D_OFST (12)
1730 +#define RG_SSUSB_PLL_IC_PE2H_OFST (9)
1731 +#define RG_SSUSB_PLL_IC_PE1D_OFST (6)
1732 +#define RG_SSUSB_PLL_IC_PE1H_OFST (3)
1733 +#define RG_SSUSB_PLL_IC_U3_OFST (0)
1734 +
1735 +//U3D_reg6
1736 +#define RG_SSUSB_PLL_IR_PE2D_OFST (24)
1737 +#define RG_SSUSB_PLL_IR_PE2H_OFST (16)
1738 +#define RG_SSUSB_PLL_IR_PE1D_OFST (8)
1739 +#define RG_SSUSB_PLL_IR_PE1H_OFST (4)
1740 +#define RG_SSUSB_PLL_IR_U3_OFST (0)
1741 +
1742 +//U3D_reg7
1743 +#define RG_SSUSB_PLL_BP_PE2D_OFST (24)
1744 +#define RG_SSUSB_PLL_BP_PE2H_OFST (16)
1745 +#define RG_SSUSB_PLL_BP_PE1D_OFST (8)
1746 +#define RG_SSUSB_PLL_BP_PE1H_OFST (4)
1747 +#define RG_SSUSB_PLL_BP_U3_OFST (0)
1748 +
1749 +//U3D_reg8
1750 +#define RG_SSUSB_PLL_FBKSEL_PE2D_OFST (24)
1751 +#define RG_SSUSB_PLL_FBKSEL_PE2H_OFST (16)
1752 +#define RG_SSUSB_PLL_FBKSEL_PE1D_OFST (8)
1753 +#define RG_SSUSB_PLL_FBKSEL_PE1H_OFST (2)
1754 +#define RG_SSUSB_PLL_FBKSEL_U3_OFST (0)
1755 +
1756 +//U3D_reg9
1757 +#define RG_SSUSB_PLL_FBKDIV_PE2H_OFST (24)
1758 +#define RG_SSUSB_PLL_FBKDIV_PE1D_OFST (16)
1759 +#define RG_SSUSB_PLL_FBKDIV_PE1H_OFST (8)
1760 +#define RG_SSUSB_PLL_FBKDIV_U3_OFST (0)
1761 +
1762 +//U3D_reg10
1763 +#define RG_SSUSB_PLL_PREDIV_PE2D_OFST (26)
1764 +#define RG_SSUSB_PLL_PREDIV_PE2H_OFST (24)
1765 +#define RG_SSUSB_PLL_PREDIV_PE1D_OFST (18)
1766 +#define RG_SSUSB_PLL_PREDIV_PE1H_OFST (16)
1767 +#define RG_SSUSB_PLL_PREDIV_U3_OFST (8)
1768 +#define RG_SSUSB_PLL_FBKDIV_PE2D_OFST (0)
1769 +
1770 +//U3D_reg12
1771 +#define RG_SSUSB_PLL_PCW_NCPO_U3_OFST (0)
1772 +
1773 +//U3D_reg13
1774 +#define RG_SSUSB_PLL_PCW_NCPO_PE1H_OFST (0)
1775 +
1776 +//U3D_reg14
1777 +#define RG_SSUSB_PLL_PCW_NCPO_PE1D_OFST (0)
1778 +
1779 +//U3D_reg15
1780 +#define RG_SSUSB_PLL_PCW_NCPO_PE2H_OFST (0)
1781 +
1782 +//U3D_reg16
1783 +#define RG_SSUSB_PLL_PCW_NCPO_PE2D_OFST (0)
1784 +
1785 +//U3D_reg19
1786 +#define RG_SSUSB_PLL_SSC_DELTA1_PE1H_OFST (16)
1787 +#define RG_SSUSB_PLL_SSC_DELTA1_U3_OFST (0)
1788 +
1789 +//U3D_reg20
1790 +#define RG_SSUSB_PLL_SSC_DELTA1_PE2H_OFST (16)
1791 +#define RG_SSUSB_PLL_SSC_DELTA1_PE1D_OFST (0)
1792 +
1793 +//U3D_reg21
1794 +#define RG_SSUSB_PLL_SSC_DELTA_U3_OFST (16)
1795 +#define RG_SSUSB_PLL_SSC_DELTA1_PE2D_OFST (0)
1796 +
1797 +//U3D_reg23
1798 +#define RG_SSUSB_PLL_SSC_DELTA_PE1D_OFST (16)
1799 +#define RG_SSUSB_PLL_SSC_DELTA_PE1H_OFST (0)
1800 +
1801 +//U3D_reg25
1802 +#define RG_SSUSB_PLL_SSC_DELTA_PE2D_OFST (16)
1803 +#define RG_SSUSB_PLL_SSC_DELTA_PE2H_OFST (0)
1804 +
1805 +//U3D_reg26
1806 +#define RG_SSUSB_PLL_REFCKDIV_PE2D_OFST (25)
1807 +#define RG_SSUSB_PLL_REFCKDIV_PE2H_OFST (24)
1808 +#define RG_SSUSB_PLL_REFCKDIV_PE1D_OFST (16)
1809 +#define RG_SSUSB_PLL_REFCKDIV_PE1H_OFST (8)
1810 +#define RG_SSUSB_PLL_REFCKDIV_U3_OFST (0)
1811 +
1812 +//U3D_reg28
1813 +#define RG_SSUSB_CDR_BPA_PE2D_OFST (24)
1814 +#define RG_SSUSB_CDR_BPA_PE2H_OFST (16)
1815 +#define RG_SSUSB_CDR_BPA_PE1D_OFST (10)
1816 +#define RG_SSUSB_CDR_BPA_PE1H_OFST (8)
1817 +#define RG_SSUSB_CDR_BPA_U3_OFST (0)
1818 +
1819 +//U3D_reg29
1820 +#define RG_SSUSB_CDR_BPB_PE2D_OFST (24)
1821 +#define RG_SSUSB_CDR_BPB_PE2H_OFST (16)
1822 +#define RG_SSUSB_CDR_BPB_PE1D_OFST (6)
1823 +#define RG_SSUSB_CDR_BPB_PE1H_OFST (3)
1824 +#define RG_SSUSB_CDR_BPB_U3_OFST (0)
1825 +
1826 +//U3D_reg30
1827 +#define RG_SSUSB_CDR_BR_PE2D_OFST (24)
1828 +#define RG_SSUSB_CDR_BR_PE2H_OFST (16)
1829 +#define RG_SSUSB_CDR_BR_PE1D_OFST (6)
1830 +#define RG_SSUSB_CDR_BR_PE1H_OFST (3)
1831 +#define RG_SSUSB_CDR_BR_U3_OFST (0)
1832 +
1833 +//U3D_reg31
1834 +#define RG_SSUSB_CDR_FBDIV_PE2H_OFST (24)
1835 +#define RG_SSUSB_CDR_FBDIV_PE1D_OFST (16)
1836 +#define RG_SSUSB_CDR_FBDIV_PE1H_OFST (8)
1837 +#define RG_SSUSB_CDR_FBDIV_U3_OFST (0)
1838 +
1839 +//U3D_reg32
1840 +#define RG_SSUSB_EQ_RSTEP1_PE2D_OFST (30)
1841 +#define RG_SSUSB_EQ_RSTEP1_PE2H_OFST (28)
1842 +#define RG_SSUSB_EQ_RSTEP1_PE1D_OFST (26)
1843 +#define RG_SSUSB_EQ_RSTEP1_PE1H_OFST (24)
1844 +#define RG_SSUSB_EQ_RSTEP1_U3_OFST (22)
1845 +#define RG_SSUSB_LFPS_DEGLITCH_PE2D_OFST (20)
1846 +#define RG_SSUSB_LFPS_DEGLITCH_PE2H_OFST (18)
1847 +#define RG_SSUSB_LFPS_DEGLITCH_PE1D_OFST (16)
1848 +#define RG_SSUSB_LFPS_DEGLITCH_PE1H_OFST (14)
1849 +#define RG_SSUSB_LFPS_DEGLITCH_U3_OFST (12)
1850 +#define RG_SSUSB_CDR_KVSEL_PE2D_OFST (11)
1851 +#define RG_SSUSB_CDR_KVSEL_PE2H_OFST (10)
1852 +#define RG_SSUSB_CDR_KVSEL_PE1D_OFST (9)
1853 +#define RG_SSUSB_CDR_KVSEL_PE1H_OFST (8)
1854 +#define RG_SSUSB_CDR_KVSEL_U3_OFST (7)
1855 +#define RG_SSUSB_CDR_FBDIV_PE2D_OFST (0)
1856 +
1857 +//U3D_reg33
1858 +#define RG_SSUSB_RX_CMPWD_PE2D_OFST (26)
1859 +#define RG_SSUSB_RX_CMPWD_PE2H_OFST (25)
1860 +#define RG_SSUSB_RX_CMPWD_PE1D_OFST (24)
1861 +#define RG_SSUSB_RX_CMPWD_PE1H_OFST (23)
1862 +#define RG_SSUSB_RX_CMPWD_U3_OFST (16)
1863 +#define RG_SSUSB_EQ_RSTEP2_PE2D_OFST (8)
1864 +#define RG_SSUSB_EQ_RSTEP2_PE2H_OFST (6)
1865 +#define RG_SSUSB_EQ_RSTEP2_PE1D_OFST (4)
1866 +#define RG_SSUSB_EQ_RSTEP2_PE1H_OFST (2)
1867 +#define RG_SSUSB_EQ_RSTEP2_U3_OFST (0)
1868 +
1869 +
1870 +///////////////////////////////////////////////////////////////////////////////
1871 +
1872 +struct u3phyd_reg {
1873 + //0x0
1874 + PHY_LE32 phyd_mix0;
1875 + PHY_LE32 phyd_mix1;
1876 + PHY_LE32 phyd_lfps0;
1877 + PHY_LE32 phyd_lfps1;
1878 + //0x10
1879 + PHY_LE32 phyd_impcal0;
1880 + PHY_LE32 phyd_impcal1;
1881 + PHY_LE32 phyd_txpll0;
1882 + PHY_LE32 phyd_txpll1;
1883 + //0x20
1884 + PHY_LE32 phyd_txpll2;
1885 + PHY_LE32 phyd_fl0;
1886 + PHY_LE32 phyd_mix2;
1887 + PHY_LE32 phyd_rx0;
1888 + //0x30
1889 + PHY_LE32 phyd_t2rlb;
1890 + PHY_LE32 phyd_cppat;
1891 + PHY_LE32 phyd_mix3;
1892 + PHY_LE32 phyd_ebufctl;
1893 + //0x40
1894 + PHY_LE32 phyd_pipe0;
1895 + PHY_LE32 phyd_pipe1;
1896 + PHY_LE32 phyd_mix4;
1897 + PHY_LE32 phyd_ckgen0;
1898 + //0x50
1899 + PHY_LE32 phyd_mix5;
1900 + PHY_LE32 phyd_reserved;
1901 + PHY_LE32 phyd_cdr0;
1902 + PHY_LE32 phyd_cdr1;
1903 + //0x60
1904 + PHY_LE32 phyd_pll_0;
1905 + PHY_LE32 phyd_pll_1;
1906 + PHY_LE32 phyd_bcn_det_1;
1907 + PHY_LE32 phyd_bcn_det_2;
1908 + //0x70
1909 + PHY_LE32 eq0;
1910 + PHY_LE32 eq1;
1911 + PHY_LE32 eq2;
1912 + PHY_LE32 eq3;
1913 + //0x80
1914 + PHY_LE32 eq_eye0;
1915 + PHY_LE32 eq_eye1;
1916 + PHY_LE32 eq_eye2;
1917 + PHY_LE32 eq_dfe0;
1918 + //0x90
1919 + PHY_LE32 eq_dfe1;
1920 + PHY_LE32 eq_dfe2;
1921 + PHY_LE32 eq_dfe3;
1922 + PHY_LE32 reserve0;
1923 + //0xa0
1924 + PHY_LE32 phyd_mon0;
1925 + PHY_LE32 phyd_mon1;
1926 + PHY_LE32 phyd_mon2;
1927 + PHY_LE32 phyd_mon3;
1928 + //0xb0
1929 + PHY_LE32 phyd_mon4;
1930 + PHY_LE32 phyd_mon5;
1931 + PHY_LE32 phyd_mon6;
1932 + PHY_LE32 phyd_mon7;
1933 + //0xc0
1934 + PHY_LE32 phya_rx_mon0;
1935 + PHY_LE32 phya_rx_mon1;
1936 + PHY_LE32 phya_rx_mon2;
1937 + PHY_LE32 phya_rx_mon3;
1938 + //0xd0
1939 + PHY_LE32 phya_rx_mon4;
1940 + PHY_LE32 phya_rx_mon5;
1941 + PHY_LE32 phyd_cppat2;
1942 + PHY_LE32 eq_eye3;
1943 + //0xe0
1944 + PHY_LE32 kband_out;
1945 + PHY_LE32 kband_out1;
1946 +};
1947 +
1948 +//U3D_PHYD_MIX0
1949 +#define RG_SSUSB_P_P3_TX_NG (0x1<<31) //31:31
1950 +#define RG_SSUSB_TSEQ_EN (0x1<<30) //30:30
1951 +#define RG_SSUSB_TSEQ_POLEN (0x1<<29) //29:29
1952 +#define RG_SSUSB_TSEQ_POL (0x1<<28) //28:28
1953 +#define RG_SSUSB_P_P3_PCLK_NG (0x1<<27) //27:27
1954 +#define RG_SSUSB_TSEQ_TH (0x7<<24) //26:24
1955 +#define RG_SSUSB_PRBS_BERTH (0xff<<16) //23:16
1956 +#define RG_SSUSB_DISABLE_PHY_U2_ON (0x1<<15) //15:15
1957 +#define RG_SSUSB_DISABLE_PHY_U2_OFF (0x1<<14) //14:14
1958 +#define RG_SSUSB_PRBS_EN (0x1<<13) //13:13
1959 +#define RG_SSUSB_BPSLOCK (0x1<<12) //12:12
1960 +#define RG_SSUSB_RTCOMCNT (0xf<<8) //11:8
1961 +#define RG_SSUSB_COMCNT (0xf<<4) //7:4
1962 +#define RG_SSUSB_PRBSEL_CALIB (0xf<<0) //3:0
1963 +
1964 +//U3D_PHYD_MIX1
1965 +#define RG_SSUSB_SLEEP_EN (0x1<<31) //31:31
1966 +#define RG_SSUSB_PRBSEL_PCS (0x7<<28) //30:28
1967 +#define RG_SSUSB_TXLFPS_PRD (0xf<<24) //27:24
1968 +#define RG_SSUSB_P_RX_P0S_CK (0x1<<23) //23:23
1969 +#define RG_SSUSB_P_TX_P0S_CK (0x1<<22) //22:22
1970 +#define RG_SSUSB_PDNCTL (0x3f<<16) //21:16
1971 +#define RG_SSUSB_TX_DRV_EN (0x1<<15) //15:15
1972 +#define RG_SSUSB_TX_DRV_SEL (0x1<<14) //14:14
1973 +#define RG_SSUSB_TX_DRV_DLY (0x3f<<8) //13:8
1974 +#define RG_SSUSB_BERT_EN (0x1<<7) //7:7
1975 +#define RG_SSUSB_SCP_TH (0x7<<4) //6:4
1976 +#define RG_SSUSB_SCP_EN (0x1<<3) //3:3
1977 +#define RG_SSUSB_RXANSIDEC_TEST (0x7<<0) //2:0
1978 +
1979 +//U3D_PHYD_LFPS0
1980 +#define RG_SSUSB_LFPS_PWD (0x1<<30) //30:30
1981 +#define RG_SSUSB_FORCE_LFPS_PWD (0x1<<29) //29:29
1982 +#define RG_SSUSB_RXLFPS_OVF (0x1f<<24) //28:24
1983 +#define RG_SSUSB_P3_ENTRY_SEL (0x1<<23) //23:23
1984 +#define RG_SSUSB_P3_ENTRY (0x1<<22) //22:22
1985 +#define RG_SSUSB_RXLFPS_CDRSEL (0x3<<20) //21:20
1986 +#define RG_SSUSB_RXLFPS_CDRTH (0xf<<16) //19:16
1987 +#define RG_SSUSB_LOCK5G_BLOCK (0x1<<15) //15:15
1988 +#define RG_SSUSB_TFIFO_EXT_D_SEL (0x1<<14) //14:14
1989 +#define RG_SSUSB_TFIFO_NO_EXTEND (0x1<<13) //13:13
1990 +#define RG_SSUSB_RXLFPS_LOB (0x1f<<8) //12:8
1991 +#define RG_SSUSB_TXLFPS_EN (0x1<<7) //7:7
1992 +#define RG_SSUSB_TXLFPS_SEL (0x1<<6) //6:6
1993 +#define RG_SSUSB_RXLFPS_CDRLOCK (0x1<<5) //5:5
1994 +#define RG_SSUSB_RXLFPS_UPB (0x1f<<0) //4:0
1995 +
1996 +//U3D_PHYD_LFPS1
1997 +#define RG_SSUSB_RX_IMP_BIAS (0xf<<28) //31:28
1998 +#define RG_SSUSB_TX_IMP_BIAS (0xf<<24) //27:24
1999 +#define RG_SSUSB_FWAKE_TH (0x3f<<16) //21:16
2000 +#define RG_SSUSB_RXLFPS_UDF (0x1f<<8) //12:8
2001 +#define RG_SSUSB_RXLFPS_P0IDLETH (0xff<<0) //7:0
2002 +
2003 +//U3D_PHYD_IMPCAL0
2004 +#define RG_SSUSB_FORCE_TX_IMPSEL (0x1<<31) //31:31
2005 +#define RG_SSUSB_TX_IMPCAL_EN (0x1<<30) //30:30
2006 +#define RG_SSUSB_FORCE_TX_IMPCAL_EN (0x1<<29) //29:29
2007 +#define RG_SSUSB_TX_IMPSEL (0x1f<<24) //28:24
2008 +#define RG_SSUSB_TX_IMPCAL_CALCYC (0x3f<<16) //21:16
2009 +#define RG_SSUSB_TX_IMPCAL_STBCYC (0x1f<<10) //14:10
2010 +#define RG_SSUSB_TX_IMPCAL_CYCCNT (0x3ff<<0) //9:0
2011 +
2012 +//U3D_PHYD_IMPCAL1
2013 +#define RG_SSUSB_FORCE_RX_IMPSEL (0x1<<31) //31:31
2014 +#define RG_SSUSB_RX_IMPCAL_EN (0x1<<30) //30:30
2015 +#define RG_SSUSB_FORCE_RX_IMPCAL_EN (0x1<<29) //29:29
2016 +#define RG_SSUSB_RX_IMPSEL (0x1f<<24) //28:24
2017 +#define RG_SSUSB_RX_IMPCAL_CALCYC (0x3f<<16) //21:16
2018 +#define RG_SSUSB_RX_IMPCAL_STBCYC (0x1f<<10) //14:10
2019 +#define RG_SSUSB_RX_IMPCAL_CYCCNT (0x3ff<<0) //9:0
2020 +
2021 +//U3D_PHYD_TXPLL0
2022 +#define RG_SSUSB_TXPLL_DDSEN_CYC (0x1f<<27) //31:27
2023 +#define RG_SSUSB_TXPLL_ON (0x1<<26) //26:26
2024 +#define RG_SSUSB_FORCE_TXPLLON (0x1<<25) //25:25
2025 +#define RG_SSUSB_TXPLL_STBCYC (0x1ff<<16) //24:16
2026 +#define RG_SSUSB_TXPLL_NCPOCHG_CYC (0xf<<12) //15:12
2027 +#define RG_SSUSB_TXPLL_NCPOEN_CYC (0x3<<10) //11:10
2028 +#define RG_SSUSB_TXPLL_DDSRSTB_CYC (0x7<<0) //2:0
2029 +
2030 +//U3D_PHYD_TXPLL1
2031 +#define RG_SSUSB_PLL_NCPO_EN (0x1<<31) //31:31
2032 +#define RG_SSUSB_PLL_FIFO_START_MAN (0x1<<30) //30:30
2033 +#define RG_SSUSB_PLL_NCPO_CHG (0x1<<28) //28:28
2034 +#define RG_SSUSB_PLL_DDS_RSTB (0x1<<27) //27:27
2035 +#define RG_SSUSB_PLL_DDS_PWDB (0x1<<26) //26:26
2036 +#define RG_SSUSB_PLL_DDSEN (0x1<<25) //25:25
2037 +#define RG_SSUSB_PLL_AUTOK_VCO (0x1<<24) //24:24
2038 +#define RG_SSUSB_PLL_PWD (0x1<<23) //23:23
2039 +#define RG_SSUSB_RX_AFE_PWD (0x1<<22) //22:22
2040 +#define RG_SSUSB_PLL_TCADJ (0x3f<<16) //21:16
2041 +#define RG_SSUSB_FORCE_CDR_TCADJ (0x1<<15) //15:15
2042 +#define RG_SSUSB_FORCE_CDR_AUTOK_VCO (0x1<<14) //14:14
2043 +#define RG_SSUSB_FORCE_CDR_PWD (0x1<<13) //13:13
2044 +#define RG_SSUSB_FORCE_PLL_NCPO_EN (0x1<<12) //12:12
2045 +#define RG_SSUSB_FORCE_PLL_FIFO_START_MAN (0x1<<11) //11:11
2046 +#define RG_SSUSB_FORCE_PLL_NCPO_CHG (0x1<<9) //9:9
2047 +#define RG_SSUSB_FORCE_PLL_DDS_RSTB (0x1<<8) //8:8
2048 +#define RG_SSUSB_FORCE_PLL_DDS_PWDB (0x1<<7) //7:7
2049 +#define RG_SSUSB_FORCE_PLL_DDSEN (0x1<<6) //6:6
2050 +#define RG_SSUSB_FORCE_PLL_TCADJ (0x1<<5) //5:5
2051 +#define RG_SSUSB_FORCE_PLL_AUTOK_VCO (0x1<<4) //4:4
2052 +#define RG_SSUSB_FORCE_PLL_PWD (0x1<<3) //3:3
2053 +#define RG_SSUSB_FLT_1_DISPERR_B (0x1<<2) //2:2
2054 +
2055 +//U3D_PHYD_TXPLL2
2056 +#define RG_SSUSB_TX_LFPS_EN (0x1<<31) //31:31
2057 +#define RG_SSUSB_FORCE_TX_LFPS_EN (0x1<<30) //30:30
2058 +#define RG_SSUSB_TX_LFPS (0x1<<29) //29:29
2059 +#define RG_SSUSB_FORCE_TX_LFPS (0x1<<28) //28:28
2060 +#define RG_SSUSB_RXPLL_STB (0x1<<27) //27:27
2061 +#define RG_SSUSB_TXPLL_STB (0x1<<26) //26:26
2062 +#define RG_SSUSB_FORCE_RXPLL_STB (0x1<<25) //25:25
2063 +#define RG_SSUSB_FORCE_TXPLL_STB (0x1<<24) //24:24
2064 +#define RG_SSUSB_RXPLL_REFCKSEL (0x1<<16) //16:16
2065 +#define RG_SSUSB_RXPLL_STBMODE (0x1<<11) //11:11
2066 +#define RG_SSUSB_RXPLL_ON (0x1<<10) //10:10
2067 +#define RG_SSUSB_FORCE_RXPLLON (0x1<<9) //9:9
2068 +#define RG_SSUSB_FORCE_RX_AFE_PWD (0x1<<8) //8:8
2069 +#define RG_SSUSB_CDR_AUTOK_VCO (0x1<<7) //7:7
2070 +#define RG_SSUSB_CDR_PWD (0x1<<6) //6:6
2071 +#define RG_SSUSB_CDR_TCADJ (0x3f<<0) //5:0
2072 +
2073 +//U3D_PHYD_FL0
2074 +#define RG_SSUSB_RX_FL_TARGET (0xffff<<16) //31:16
2075 +#define RG_SSUSB_RX_FL_CYCLECNT (0xffff<<0) //15:0
2076 +
2077 +//U3D_PHYD_MIX2
2078 +#define RG_SSUSB_RX_EQ_RST (0x1<<31) //31:31
2079 +#define RG_SSUSB_RX_EQ_RST_SEL (0x1<<30) //30:30
2080 +#define RG_SSUSB_RXVAL_RST (0x1<<29) //29:29
2081 +#define RG_SSUSB_RXVAL_CNT (0x1f<<24) //28:24
2082 +#define RG_SSUSB_CDROS_EN (0x1<<18) //18:18
2083 +#define RG_SSUSB_CDR_LCKOP (0x3<<16) //17:16
2084 +#define RG_SSUSB_RX_FL_LOCKTH (0xf<<8) //11:8
2085 +#define RG_SSUSB_RX_FL_OFFSET (0xff<<0) //7:0
2086 +
2087 +//U3D_PHYD_RX0
2088 +#define RG_SSUSB_T2RLB_BERTH (0xff<<24) //31:24
2089 +#define RG_SSUSB_T2RLB_PAT (0xff<<16) //23:16
2090 +#define RG_SSUSB_T2RLB_EN (0x1<<15) //15:15
2091 +#define RG_SSUSB_T2RLB_BPSCRAMB (0x1<<14) //14:14
2092 +#define RG_SSUSB_T2RLB_SERIAL (0x1<<13) //13:13
2093 +#define RG_SSUSB_T2RLB_MODE (0x3<<11) //12:11
2094 +#define RG_SSUSB_RX_SAOSC_EN (0x1<<10) //10:10
2095 +#define RG_SSUSB_RX_SAOSC_EN_SEL (0x1<<9) //9:9
2096 +#define RG_SSUSB_RX_DFE_OPTION (0x1<<8) //8:8
2097 +#define RG_SSUSB_RX_DFE_EN (0x1<<7) //7:7
2098 +#define RG_SSUSB_RX_DFE_EN_SEL (0x1<<6) //6:6
2099 +#define RG_SSUSB_RX_EQ_EN (0x1<<5) //5:5
2100 +#define RG_SSUSB_RX_EQ_EN_SEL (0x1<<4) //4:4
2101 +#define RG_SSUSB_RX_SAOSC_RST (0x1<<3) //3:3
2102 +#define RG_SSUSB_RX_SAOSC_RST_SEL (0x1<<2) //2:2
2103 +#define RG_SSUSB_RX_DFE_RST (0x1<<1) //1:1
2104 +#define RG_SSUSB_RX_DFE_RST_SEL (0x1<<0) //0:0
2105 +
2106 +//U3D_PHYD_T2RLB
2107 +#define RG_SSUSB_EQTRAIN_CH_MODE (0x1<<28) //28:28
2108 +#define RG_SSUSB_PRB_OUT_CPPAT (0x1<<27) //27:27
2109 +#define RG_SSUSB_BPANSIENC (0x1<<26) //26:26
2110 +#define RG_SSUSB_VALID_EN (0x1<<25) //25:25
2111 +#define RG_SSUSB_EBUF_SRST (0x1<<24) //24:24
2112 +#define RG_SSUSB_K_EMP (0xf<<20) //23:20
2113 +#define RG_SSUSB_K_FUL (0xf<<16) //19:16
2114 +#define RG_SSUSB_T2RLB_BDATRST (0xf<<12) //15:12
2115 +#define RG_SSUSB_P_T2RLB_SKP_EN (0x1<<10) //10:10
2116 +#define RG_SSUSB_T2RLB_PATMODE (0x3<<8) //9:8
2117 +#define RG_SSUSB_T2RLB_TSEQCNT (0xff<<0) //7:0
2118 +
2119 +//U3D_PHYD_CPPAT
2120 +#define RG_SSUSB_CPPAT_PROGRAM_EN (0x1<<24) //24:24
2121 +#define RG_SSUSB_CPPAT_TOZ (0x3<<21) //22:21
2122 +#define RG_SSUSB_CPPAT_PRBS_EN (0x1<<20) //20:20
2123 +#define RG_SSUSB_CPPAT_OUT_TMP2 (0xf<<16) //19:16
2124 +#define RG_SSUSB_CPPAT_OUT_TMP1 (0xff<<8) //15:8
2125 +#define RG_SSUSB_CPPAT_OUT_TMP0 (0xff<<0) //7:0
2126 +
2127 +//U3D_PHYD_MIX3
2128 +#define RG_SSUSB_CDR_TCADJ_MINUS (0x1<<31) //31:31
2129 +#define RG_SSUSB_P_CDROS_EN (0x1<<30) //30:30
2130 +#define RG_SSUSB_P_P2_TX_DRV_DIS (0x1<<28) //28:28
2131 +#define RG_SSUSB_CDR_TCADJ_OFFSET (0x7<<24) //26:24
2132 +#define RG_SSUSB_PLL_TCADJ_MINUS (0x1<<23) //23:23
2133 +#define RG_SSUSB_FORCE_PLL_BIAS_LPF_EN (0x1<<20) //20:20
2134 +#define RG_SSUSB_PLL_BIAS_LPF_EN (0x1<<19) //19:19
2135 +#define RG_SSUSB_PLL_TCADJ_OFFSET (0x7<<16) //18:16
2136 +#define RG_SSUSB_FORCE_PLL_SSCEN (0x1<<15) //15:15
2137 +#define RG_SSUSB_PLL_SSCEN (0x1<<14) //14:14
2138 +#define RG_SSUSB_FORCE_CDR_PI_PWD (0x1<<13) //13:13
2139 +#define RG_SSUSB_CDR_PI_PWD (0x1<<12) //12:12
2140 +#define RG_SSUSB_CDR_PI_MODE (0x1<<11) //11:11
2141 +#define RG_SSUSB_TXPLL_SSCEN_CYC (0x3ff<<0) //9:0
2142 +
2143 +//U3D_PHYD_EBUFCTL
2144 +#define RG_SSUSB_EBUFCTL (0xffffffff<<0) //31:0
2145 +
2146 +//U3D_PHYD_PIPE0
2147 +#define RG_SSUSB_RXTERMINATION (0x1<<30) //30:30
2148 +#define RG_SSUSB_RXEQTRAINING (0x1<<29) //29:29
2149 +#define RG_SSUSB_RXPOLARITY (0x1<<28) //28:28
2150 +#define RG_SSUSB_TXDEEMPH (0x3<<26) //27:26
2151 +#define RG_SSUSB_POWERDOWN (0x3<<24) //25:24
2152 +#define RG_SSUSB_TXONESZEROS (0x1<<23) //23:23
2153 +#define RG_SSUSB_TXELECIDLE (0x1<<22) //22:22
2154 +#define RG_SSUSB_TXDETECTRX (0x1<<21) //21:21
2155 +#define RG_SSUSB_PIPE_SEL (0x1<<20) //20:20
2156 +#define RG_SSUSB_TXDATAK (0xf<<16) //19:16
2157 +#define RG_SSUSB_CDR_STABLE_SEL (0x1<<15) //15:15
2158 +#define RG_SSUSB_CDR_STABLE (0x1<<14) //14:14
2159 +#define RG_SSUSB_CDR_RSTB_SEL (0x1<<13) //13:13
2160 +#define RG_SSUSB_CDR_RSTB (0x1<<12) //12:12
2161 +#define RG_SSUSB_P_ERROR_SEL (0x3<<4) //5:4
2162 +#define RG_SSUSB_TXMARGIN (0x7<<1) //3:1
2163 +#define RG_SSUSB_TXCOMPLIANCE (0x1<<0) //0:0
2164 +
2165 +//U3D_PHYD_PIPE1
2166 +#define RG_SSUSB_TXDATA (0xffffffff<<0) //31:0
2167 +
2168 +//U3D_PHYD_MIX4
2169 +#define RG_SSUSB_CDROS_CNT (0x3f<<24) //29:24
2170 +#define RG_SSUSB_T2RLB_BER_EN (0x1<<16) //16:16
2171 +#define RG_SSUSB_T2RLB_BER_RATE (0xffff<<0) //15:0
2172 +
2173 +//U3D_PHYD_CKGEN0
2174 +#define RG_SSUSB_RFIFO_IMPLAT (0x1<<27) //27:27
2175 +#define RG_SSUSB_TFIFO_PSEL (0x7<<24) //26:24
2176 +#define RG_SSUSB_CKGEN_PSEL (0x3<<8) //9:8
2177 +#define RG_SSUSB_RXCK_INV (0x1<<0) //0:0
2178 +
2179 +//U3D_PHYD_MIX5
2180 +#define RG_SSUSB_PRB_SEL (0xffff<<16) //31:16
2181 +#define RG_SSUSB_RXPLL_STBCYC (0x7ff<<0) //10:0
2182 +
2183 +//U3D_PHYD_RESERVED
2184 +#define RG_SSUSB_PHYD_RESERVE (0xffffffff<<0) //31:0
2185 +//#define RG_SSUSB_RX_SIGDET_SEL (0x1<<11)
2186 +//#define RG_SSUSB_RX_SIGDET_EN (0x1<<12)
2187 +//#define RG_SSUSB_RX_PI_CAL_MANUAL_SEL (0x1<<9)
2188 +//#define RG_SSUSB_RX_PI_CAL_MANUAL_EN (0x1<<10)
2189 +
2190 +//U3D_PHYD_CDR0
2191 +#define RG_SSUSB_CDR_BIC_LTR (0xf<<28) //31:28
2192 +#define RG_SSUSB_CDR_BIC_LTD0 (0xf<<24) //27:24
2193 +#define RG_SSUSB_CDR_BC_LTD1 (0x1f<<16) //20:16
2194 +#define RG_SSUSB_CDR_BC_LTR (0x1f<<8) //12:8
2195 +#define RG_SSUSB_CDR_BC_LTD0 (0x1f<<0) //4:0
2196 +
2197 +//U3D_PHYD_CDR1
2198 +#define RG_SSUSB_CDR_BIR_LTD1 (0x1f<<24) //28:24
2199 +#define RG_SSUSB_CDR_BIR_LTR (0x1f<<16) //20:16
2200 +#define RG_SSUSB_CDR_BIR_LTD0 (0x1f<<8) //12:8
2201 +#define RG_SSUSB_CDR_BW_SEL (0x3<<6) //7:6
2202 +#define RG_SSUSB_CDR_BIC_LTD1 (0xf<<0) //3:0
2203 +
2204 +//U3D_PHYD_PLL_0
2205 +#define RG_SSUSB_FORCE_CDR_BAND_5G (0x1<<28) //28:28
2206 +#define RG_SSUSB_FORCE_CDR_BAND_2P5G (0x1<<27) //27:27
2207 +#define RG_SSUSB_FORCE_PLL_BAND_5G (0x1<<26) //26:26
2208 +#define RG_SSUSB_FORCE_PLL_BAND_2P5G (0x1<<25) //25:25
2209 +#define RG_SSUSB_P_EQ_T_SEL (0x3ff<<15) //24:15
2210 +#define RG_SSUSB_PLL_ISO_EN_CYC (0x3ff<<5) //14:5
2211 +#define RG_SSUSB_PLLBAND_RECAL (0x1<<4) //4:4
2212 +#define RG_SSUSB_PLL_DDS_ISO_EN (0x1<<3) //3:3
2213 +#define RG_SSUSB_FORCE_PLL_DDS_ISO_EN (0x1<<2) //2:2
2214 +#define RG_SSUSB_PLL_DDS_PWR_ON (0x1<<1) //1:1
2215 +#define RG_SSUSB_FORCE_PLL_DDS_PWR_ON (0x1<<0) //0:0
2216 +
2217 +//U3D_PHYD_PLL_1
2218 +#define RG_SSUSB_CDR_BAND_5G (0xff<<24) //31:24
2219 +#define RG_SSUSB_CDR_BAND_2P5G (0xff<<16) //23:16
2220 +#define RG_SSUSB_PLL_BAND_5G (0xff<<8) //15:8
2221 +#define RG_SSUSB_PLL_BAND_2P5G (0xff<<0) //7:0
2222 +
2223 +//U3D_PHYD_BCN_DET_1
2224 +#define RG_SSUSB_P_BCN_OBS_PRD (0xffff<<16) //31:16
2225 +#define RG_SSUSB_U_BCN_OBS_PRD (0xffff<<0) //15:0
2226 +
2227 +//U3D_PHYD_BCN_DET_2
2228 +#define RG_SSUSB_P_BCN_OBS_SEL (0xfff<<16) //27:16
2229 +#define RG_SSUSB_BCN_DET_DIS (0x1<<12) //12:12
2230 +#define RG_SSUSB_U_BCN_OBS_SEL (0xfff<<0) //11:0
2231 +
2232 +//U3D_EQ0
2233 +#define RG_SSUSB_EQ_DLHL_LFI (0x7f<<24) //30:24
2234 +#define RG_SSUSB_EQ_DHHL_LFI (0x7f<<16) //22:16
2235 +#define RG_SSUSB_EQ_DD0HOS_LFI (0x7f<<8) //14:8
2236 +#define RG_SSUSB_EQ_DD0LOS_LFI (0x7f<<0) //6:0
2237 +
2238 +//U3D_EQ1
2239 +#define RG_SSUSB_EQ_DD1HOS_LFI (0x7f<<24) //30:24
2240 +#define RG_SSUSB_EQ_DD1LOS_LFI (0x7f<<16) //22:16
2241 +#define RG_SSUSB_EQ_DE0OS_LFI (0x7f<<8) //14:8
2242 +#define RG_SSUSB_EQ_DE1OS_LFI (0x7f<<0) //6:0
2243 +
2244 +//U3D_EQ2
2245 +#define RG_SSUSB_EQ_DLHLOS_LFI (0x7f<<24) //30:24
2246 +#define RG_SSUSB_EQ_DHHLOS_LFI (0x7f<<16) //22:16
2247 +#define RG_SSUSB_EQ_STOPTIME (0x1<<14) //14:14
2248 +#define RG_SSUSB_EQ_DHHL_LF_SEL (0x7<<11) //13:11
2249 +#define RG_SSUSB_EQ_DSAOS_LF_SEL (0x7<<8) //10:8
2250 +#define RG_SSUSB_EQ_STARTTIME (0x3<<6) //7:6
2251 +#define RG_SSUSB_EQ_DLEQ_LF_SEL (0x7<<3) //5:3
2252 +#define RG_SSUSB_EQ_DLHL_LF_SEL (0x7<<0) //2:0
2253 +
2254 +//U3D_EQ3
2255 +#define RG_SSUSB_EQ_DLEQ_LFI_GEN2 (0xf<<28) //31:28
2256 +#define RG_SSUSB_EQ_DLEQ_LFI_GEN1 (0xf<<24) //27:24
2257 +#define RG_SSUSB_EQ_DEYE0OS_LFI (0x7f<<16) //22:16
2258 +#define RG_SSUSB_EQ_DEYE1OS_LFI (0x7f<<8) //14:8
2259 +#define RG_SSUSB_EQ_TRI_DET_EN (0x1<<7) //7:7
2260 +#define RG_SSUSB_EQ_TRI_DET_TH (0x7f<<0) //6:0
2261 +
2262 +//U3D_EQ_EYE0
2263 +#define RG_SSUSB_EQ_EYE_XOFFSET (0x7f<<25) //31:25
2264 +#define RG_SSUSB_EQ_EYE_MON_EN (0x1<<24) //24:24
2265 +#define RG_SSUSB_EQ_EYE0_Y (0x7f<<16) //22:16
2266 +#define RG_SSUSB_EQ_EYE1_Y (0x7f<<8) //14:8
2267 +#define RG_SSUSB_EQ_PILPO_ROUT (0x1<<7) //7:7
2268 +#define RG_SSUSB_EQ_PI_KPGAIN (0x7<<4) //6:4
2269 +#define RG_SSUSB_EQ_EYE_CNT_EN (0x1<<3) //3:3
2270 +
2271 +//U3D_EQ_EYE1
2272 +#define RG_SSUSB_EQ_SIGDET (0x7f<<24) //30:24
2273 +#define RG_SSUSB_EQ_EYE_MASK (0x3ff<<7) //16:7
2274 +
2275 +//U3D_EQ_EYE2
2276 +#define RG_SSUSB_EQ_RX500M_CK_SEL (0x1<<31) //31:31
2277 +#define RG_SSUSB_EQ_SD_CNT1 (0x3f<<24) //29:24
2278 +#define RG_SSUSB_EQ_ISIFLAG_SEL (0x3<<22) //23:22
2279 +#define RG_SSUSB_EQ_SD_CNT0 (0x3f<<16) //21:16
2280 +
2281 +//U3D_EQ_DFE0
2282 +#define RG_SSUSB_EQ_LEQMAX (0xf<<28) //31:28
2283 +#define RG_SSUSB_EQ_DFEX_EN (0x1<<27) //27:27
2284 +#define RG_SSUSB_EQ_DFEX_LF_SEL (0x7<<24) //26:24
2285 +#define RG_SSUSB_EQ_CHK_EYE_H (0x1<<23) //23:23
2286 +#define RG_SSUSB_EQ_PIEYE_INI (0x7f<<16) //22:16
2287 +#define RG_SSUSB_EQ_PI90_INI (0x7f<<8) //14:8
2288 +#define RG_SSUSB_EQ_PI0_INI (0x7f<<0) //6:0
2289 +
2290 +//U3D_EQ_DFE1
2291 +#define RG_SSUSB_EQ_REV (0xffff<<16) //31:16
2292 +#define RG_SSUSB_EQ_DFEYEN_DUR (0x7<<12) //14:12
2293 +#define RG_SSUSB_EQ_DFEXEN_DUR (0x7<<8) //10:8
2294 +#define RG_SSUSB_EQ_DFEX_RST (0x1<<7) //7:7
2295 +#define RG_SSUSB_EQ_GATED_RXD_B (0x1<<6) //6:6
2296 +#define RG_SSUSB_EQ_PI90CK_SEL (0x3<<4) //5:4
2297 +#define RG_SSUSB_EQ_DFEX_DIS (0x1<<2) //2:2
2298 +#define RG_SSUSB_EQ_DFEYEN_STOP_DIS (0x1<<1) //1:1
2299 +#define RG_SSUSB_EQ_DFEXEN_SEL (0x1<<0) //0:0
2300 +
2301 +//U3D_EQ_DFE2
2302 +#define RG_SSUSB_EQ_MON_SEL (0x1f<<24) //28:24
2303 +#define RG_SSUSB_EQ_LEQOSC_DLYCNT (0x7<<16) //18:16
2304 +#define RG_SSUSB_EQ_DLEQOS_LFI (0x1f<<8) //12:8
2305 +#define RG_SSUSB_EQ_LEQ_STOP_TO (0x3<<0) //1:0
2306 +
2307 +//U3D_EQ_DFE3
2308 +#define RG_SSUSB_EQ_RESERVED (0xffffffff<<0) //31:0
2309 +
2310 +//U3D_PHYD_MON0
2311 +#define RGS_SSUSB_BERT_BERC (0xffff<<16) //31:16
2312 +#define RGS_SSUSB_LFPS (0xf<<12) //15:12
2313 +#define RGS_SSUSB_TRAINDEC (0x7<<8) //10:8
2314 +#define RGS_SSUSB_SCP_PAT (0xff<<0) //7:0
2315 +
2316 +//U3D_PHYD_MON1
2317 +#define RGS_SSUSB_RX_FL_OUT (0xffff<<0) //15:0
2318 +
2319 +//U3D_PHYD_MON2
2320 +#define RGS_SSUSB_T2RLB_ERRCNT (0xffff<<16) //31:16
2321 +#define RGS_SSUSB_RETRACK (0xf<<12) //15:12
2322 +#define RGS_SSUSB_RXPLL_LOCK (0x1<<10) //10:10
2323 +#define RGS_SSUSB_CDR_VCOCAL_CPLT_D (0x1<<9) //9:9
2324 +#define RGS_SSUSB_PLL_VCOCAL_CPLT_D (0x1<<8) //8:8
2325 +#define RGS_SSUSB_PDNCTL (0xff<<0) //7:0
2326 +
2327 +//U3D_PHYD_MON3
2328 +#define RGS_SSUSB_TSEQ_ERRCNT (0xffff<<16) //31:16
2329 +#define RGS_SSUSB_PRBS_ERRCNT (0xffff<<0) //15:0
2330 +
2331 +//U3D_PHYD_MON4
2332 +#define RGS_SSUSB_RX_LSLOCK_CNT (0xf<<24) //27:24
2333 +#define RGS_SSUSB_SCP_DETCNT (0xff<<16) //23:16
2334 +#define RGS_SSUSB_TSEQ_DETCNT (0xffff<<0) //15:0
2335 +
2336 +//U3D_PHYD_MON5
2337 +#define RGS_SSUSB_EBUFMSG (0xffff<<16) //31:16
2338 +#define RGS_SSUSB_BERT_LOCK (0x1<<15) //15:15
2339 +#define RGS_SSUSB_SCP_DET (0x1<<14) //14:14
2340 +#define RGS_SSUSB_TSEQ_DET (0x1<<13) //13:13
2341 +#define RGS_SSUSB_EBUF_UDF (0x1<<12) //12:12
2342 +#define RGS_SSUSB_EBUF_OVF (0x1<<11) //11:11
2343 +#define RGS_SSUSB_PRBS_PASSTH (0x1<<10) //10:10
2344 +#define RGS_SSUSB_PRBS_PASS (0x1<<9) //9:9
2345 +#define RGS_SSUSB_PRBS_LOCK (0x1<<8) //8:8
2346 +#define RGS_SSUSB_T2RLB_ERR (0x1<<6) //6:6
2347 +#define RGS_SSUSB_T2RLB_PASSTH (0x1<<5) //5:5
2348 +#define RGS_SSUSB_T2RLB_PASS (0x1<<4) //4:4
2349 +#define RGS_SSUSB_T2RLB_LOCK (0x1<<3) //3:3
2350 +#define RGS_SSUSB_RX_IMPCAL_DONE (0x1<<2) //2:2
2351 +#define RGS_SSUSB_TX_IMPCAL_DONE (0x1<<1) //1:1
2352 +#define RGS_SSUSB_RXDETECTED (0x1<<0) //0:0
2353 +
2354 +//U3D_PHYD_MON6
2355 +#define RGS_SSUSB_SIGCAL_DONE (0x1<<30) //30:30
2356 +#define RGS_SSUSB_SIGCAL_CAL_OUT (0x1<<29) //29:29
2357 +#define RGS_SSUSB_SIGCAL_OFFSET (0x1f<<24) //28:24
2358 +#define RGS_SSUSB_RX_IMP_SEL (0x1f<<16) //20:16
2359 +#define RGS_SSUSB_TX_IMP_SEL (0x1f<<8) //12:8
2360 +#define RGS_SSUSB_TFIFO_MSG (0xf<<4) //7:4
2361 +#define RGS_SSUSB_RFIFO_MSG (0xf<<0) //3:0
2362 +
2363 +//U3D_PHYD_MON7
2364 +#define RGS_SSUSB_FT_OUT (0xff<<8) //15:8
2365 +#define RGS_SSUSB_PRB_OUT (0xff<<0) //7:0
2366 +
2367 +//U3D_PHYA_RX_MON0
2368 +#define RGS_SSUSB_EQ_DCLEQ (0xf<<24) //27:24
2369 +#define RGS_SSUSB_EQ_DCD0H (0x7f<<16) //22:16
2370 +#define RGS_SSUSB_EQ_DCD0L (0x7f<<8) //14:8
2371 +#define RGS_SSUSB_EQ_DCD1H (0x7f<<0) //6:0
2372 +
2373 +//U3D_PHYA_RX_MON1
2374 +#define RGS_SSUSB_EQ_DCD1L (0x7f<<24) //30:24
2375 +#define RGS_SSUSB_EQ_DCE0 (0x7f<<16) //22:16
2376 +#define RGS_SSUSB_EQ_DCE1 (0x7f<<8) //14:8
2377 +#define RGS_SSUSB_EQ_DCHHL (0x7f<<0) //6:0
2378 +
2379 +//U3D_PHYA_RX_MON2
2380 +#define RGS_SSUSB_EQ_LEQ_STOP (0x1<<31) //31:31
2381 +#define RGS_SSUSB_EQ_DCLHL (0x7f<<24) //30:24
2382 +#define RGS_SSUSB_EQ_STATUS (0xff<<16) //23:16
2383 +#define RGS_SSUSB_EQ_DCEYE0 (0x7f<<8) //14:8
2384 +#define RGS_SSUSB_EQ_DCEYE1 (0x7f<<0) //6:0
2385 +
2386 +//U3D_PHYA_RX_MON3
2387 +#define RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_0 (0xfffff<<0) //19:0
2388 +
2389 +//U3D_PHYA_RX_MON4
2390 +#define RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_1 (0xfffff<<0) //19:0
2391 +
2392 +//U3D_PHYA_RX_MON5
2393 +#define RGS_SSUSB_EQ_DCLEQOS (0x1f<<8) //12:8
2394 +#define RGS_SSUSB_EQ_EYE_CNT_RDY (0x1<<7) //7:7
2395 +#define RGS_SSUSB_EQ_PILPO (0x7f<<0) //6:0
2396 +
2397 +//U3D_PHYD_CPPAT2
2398 +#define RG_SSUSB_CPPAT_OUT_H_TMP2 (0xf<<16) //19:16
2399 +#define RG_SSUSB_CPPAT_OUT_H_TMP1 (0xff<<8) //15:8
2400 +#define RG_SSUSB_CPPAT_OUT_H_TMP0 (0xff<<0) //7:0
2401 +
2402 +//U3D_EQ_EYE3
2403 +#define RG_SSUSB_EQ_LEQ_SHIFT (0x7<<24) //26:24
2404 +#define RG_SSUSB_EQ_EYE_CNT (0xfffff<<0) //19:0
2405 +
2406 +//U3D_KBAND_OUT
2407 +#define RGS_SSUSB_CDR_BAND_5G (0xff<<24) //31:24
2408 +#define RGS_SSUSB_CDR_BAND_2P5G (0xff<<16) //23:16
2409 +#define RGS_SSUSB_PLL_BAND_5G (0xff<<8) //15:8
2410 +#define RGS_SSUSB_PLL_BAND_2P5G (0xff<<0) //7:0
2411 +
2412 +//U3D_KBAND_OUT1
2413 +#define RGS_SSUSB_CDR_VCOCAL_FAIL (0x1<<24) //24:24
2414 +#define RGS_SSUSB_CDR_VCOCAL_STATE (0xff<<16) //23:16
2415 +#define RGS_SSUSB_PLL_VCOCAL_FAIL (0x1<<8) //8:8
2416 +#define RGS_SSUSB_PLL_VCOCAL_STATE (0xff<<0) //7:0
2417 +
2418 +
2419 +/* OFFSET */
2420 +
2421 +//U3D_PHYD_MIX0
2422 +#define RG_SSUSB_P_P3_TX_NG_OFST (31)
2423 +#define RG_SSUSB_TSEQ_EN_OFST (30)
2424 +#define RG_SSUSB_TSEQ_POLEN_OFST (29)
2425 +#define RG_SSUSB_TSEQ_POL_OFST (28)
2426 +#define RG_SSUSB_P_P3_PCLK_NG_OFST (27)
2427 +#define RG_SSUSB_TSEQ_TH_OFST (24)
2428 +#define RG_SSUSB_PRBS_BERTH_OFST (16)
2429 +#define RG_SSUSB_DISABLE_PHY_U2_ON_OFST (15)
2430 +#define RG_SSUSB_DISABLE_PHY_U2_OFF_OFST (14)
2431 +#define RG_SSUSB_PRBS_EN_OFST (13)
2432 +#define RG_SSUSB_BPSLOCK_OFST (12)
2433 +#define RG_SSUSB_RTCOMCNT_OFST (8)
2434 +#define RG_SSUSB_COMCNT_OFST (4)
2435 +#define RG_SSUSB_PRBSEL_CALIB_OFST (0)
2436 +
2437 +//U3D_PHYD_MIX1
2438 +#define RG_SSUSB_SLEEP_EN_OFST (31)
2439 +#define RG_SSUSB_PRBSEL_PCS_OFST (28)
2440 +#define RG_SSUSB_TXLFPS_PRD_OFST (24)
2441 +#define RG_SSUSB_P_RX_P0S_CK_OFST (23)
2442 +#define RG_SSUSB_P_TX_P0S_CK_OFST (22)
2443 +#define RG_SSUSB_PDNCTL_OFST (16)
2444 +#define RG_SSUSB_TX_DRV_EN_OFST (15)
2445 +#define RG_SSUSB_TX_DRV_SEL_OFST (14)
2446 +#define RG_SSUSB_TX_DRV_DLY_OFST (8)
2447 +#define RG_SSUSB_BERT_EN_OFST (7)
2448 +#define RG_SSUSB_SCP_TH_OFST (4)
2449 +#define RG_SSUSB_SCP_EN_OFST (3)
2450 +#define RG_SSUSB_RXANSIDEC_TEST_OFST (0)
2451 +
2452 +//U3D_PHYD_LFPS0
2453 +#define RG_SSUSB_LFPS_PWD_OFST (30)
2454 +#define RG_SSUSB_FORCE_LFPS_PWD_OFST (29)
2455 +#define RG_SSUSB_RXLFPS_OVF_OFST (24)
2456 +#define RG_SSUSB_P3_ENTRY_SEL_OFST (23)
2457 +#define RG_SSUSB_P3_ENTRY_OFST (22)
2458 +#define RG_SSUSB_RXLFPS_CDRSEL_OFST (20)
2459 +#define RG_SSUSB_RXLFPS_CDRTH_OFST (16)
2460 +#define RG_SSUSB_LOCK5G_BLOCK_OFST (15)
2461 +#define RG_SSUSB_TFIFO_EXT_D_SEL_OFST (14)
2462 +#define RG_SSUSB_TFIFO_NO_EXTEND_OFST (13)
2463 +#define RG_SSUSB_RXLFPS_LOB_OFST (8)
2464 +#define RG_SSUSB_TXLFPS_EN_OFST (7)
2465 +#define RG_SSUSB_TXLFPS_SEL_OFST (6)
2466 +#define RG_SSUSB_RXLFPS_CDRLOCK_OFST (5)
2467 +#define RG_SSUSB_RXLFPS_UPB_OFST (0)
2468 +
2469 +//U3D_PHYD_LFPS1
2470 +#define RG_SSUSB_RX_IMP_BIAS_OFST (28)
2471 +#define RG_SSUSB_TX_IMP_BIAS_OFST (24)
2472 +#define RG_SSUSB_FWAKE_TH_OFST (16)
2473 +#define RG_SSUSB_RXLFPS_UDF_OFST (8)
2474 +#define RG_SSUSB_RXLFPS_P0IDLETH_OFST (0)
2475 +
2476 +//U3D_PHYD_IMPCAL0
2477 +#define RG_SSUSB_FORCE_TX_IMPSEL_OFST (31)
2478 +#define RG_SSUSB_TX_IMPCAL_EN_OFST (30)
2479 +#define RG_SSUSB_FORCE_TX_IMPCAL_EN_OFST (29)
2480 +#define RG_SSUSB_TX_IMPSEL_OFST (24)
2481 +#define RG_SSUSB_TX_IMPCAL_CALCYC_OFST (16)
2482 +#define RG_SSUSB_TX_IMPCAL_STBCYC_OFST (10)
2483 +#define RG_SSUSB_TX_IMPCAL_CYCCNT_OFST (0)
2484 +
2485 +//U3D_PHYD_IMPCAL1
2486 +#define RG_SSUSB_FORCE_RX_IMPSEL_OFST (31)
2487 +#define RG_SSUSB_RX_IMPCAL_EN_OFST (30)
2488 +#define RG_SSUSB_FORCE_RX_IMPCAL_EN_OFST (29)
2489 +#define RG_SSUSB_RX_IMPSEL_OFST (24)
2490 +#define RG_SSUSB_RX_IMPCAL_CALCYC_OFST (16)
2491 +#define RG_SSUSB_RX_IMPCAL_STBCYC_OFST (10)
2492 +#define RG_SSUSB_RX_IMPCAL_CYCCNT_OFST (0)
2493 +
2494 +//U3D_PHYD_TXPLL0
2495 +#define RG_SSUSB_TXPLL_DDSEN_CYC_OFST (27)
2496 +#define RG_SSUSB_TXPLL_ON_OFST (26)
2497 +#define RG_SSUSB_FORCE_TXPLLON_OFST (25)
2498 +#define RG_SSUSB_TXPLL_STBCYC_OFST (16)
2499 +#define RG_SSUSB_TXPLL_NCPOCHG_CYC_OFST (12)
2500 +#define RG_SSUSB_TXPLL_NCPOEN_CYC_OFST (10)
2501 +#define RG_SSUSB_TXPLL_DDSRSTB_CYC_OFST (0)
2502 +
2503 +//U3D_PHYD_TXPLL1
2504 +#define RG_SSUSB_PLL_NCPO_EN_OFST (31)
2505 +#define RG_SSUSB_PLL_FIFO_START_MAN_OFST (30)
2506 +#define RG_SSUSB_PLL_NCPO_CHG_OFST (28)
2507 +#define RG_SSUSB_PLL_DDS_RSTB_OFST (27)
2508 +#define RG_SSUSB_PLL_DDS_PWDB_OFST (26)
2509 +#define RG_SSUSB_PLL_DDSEN_OFST (25)
2510 +#define RG_SSUSB_PLL_AUTOK_VCO_OFST (24)
2511 +#define RG_SSUSB_PLL_PWD_OFST (23)
2512 +#define RG_SSUSB_RX_AFE_PWD_OFST (22)
2513 +#define RG_SSUSB_PLL_TCADJ_OFST (16)
2514 +#define RG_SSUSB_FORCE_CDR_TCADJ_OFST (15)
2515 +#define RG_SSUSB_FORCE_CDR_AUTOK_VCO_OFST (14)
2516 +#define RG_SSUSB_FORCE_CDR_PWD_OFST (13)
2517 +#define RG_SSUSB_FORCE_PLL_NCPO_EN_OFST (12)
2518 +#define RG_SSUSB_FORCE_PLL_FIFO_START_MAN_OFST (11)
2519 +#define RG_SSUSB_FORCE_PLL_NCPO_CHG_OFST (9)
2520 +#define RG_SSUSB_FORCE_PLL_DDS_RSTB_OFST (8)
2521 +#define RG_SSUSB_FORCE_PLL_DDS_PWDB_OFST (7)
2522 +#define RG_SSUSB_FORCE_PLL_DDSEN_OFST (6)
2523 +#define RG_SSUSB_FORCE_PLL_TCADJ_OFST (5)
2524 +#define RG_SSUSB_FORCE_PLL_AUTOK_VCO_OFST (4)
2525 +#define RG_SSUSB_FORCE_PLL_PWD_OFST (3)
2526 +#define RG_SSUSB_FLT_1_DISPERR_B_OFST (2)
2527 +
2528 +//U3D_PHYD_TXPLL2
2529 +#define RG_SSUSB_TX_LFPS_EN_OFST (31)
2530 +#define RG_SSUSB_FORCE_TX_LFPS_EN_OFST (30)
2531 +#define RG_SSUSB_TX_LFPS_OFST (29)
2532 +#define RG_SSUSB_FORCE_TX_LFPS_OFST (28)
2533 +#define RG_SSUSB_RXPLL_STB_OFST (27)
2534 +#define RG_SSUSB_TXPLL_STB_OFST (26)
2535 +#define RG_SSUSB_FORCE_RXPLL_STB_OFST (25)
2536 +#define RG_SSUSB_FORCE_TXPLL_STB_OFST (24)
2537 +#define RG_SSUSB_RXPLL_REFCKSEL_OFST (16)
2538 +#define RG_SSUSB_RXPLL_STBMODE_OFST (11)
2539 +#define RG_SSUSB_RXPLL_ON_OFST (10)
2540 +#define RG_SSUSB_FORCE_RXPLLON_OFST (9)
2541 +#define RG_SSUSB_FORCE_RX_AFE_PWD_OFST (8)
2542 +#define RG_SSUSB_CDR_AUTOK_VCO_OFST (7)
2543 +#define RG_SSUSB_CDR_PWD_OFST (6)
2544 +#define RG_SSUSB_CDR_TCADJ_OFST (0)
2545 +
2546 +//U3D_PHYD_FL0
2547 +#define RG_SSUSB_RX_FL_TARGET_OFST (16)
2548 +#define RG_SSUSB_RX_FL_CYCLECNT_OFST (0)
2549 +
2550 +//U3D_PHYD_MIX2
2551 +#define RG_SSUSB_RX_EQ_RST_OFST (31)
2552 +#define RG_SSUSB_RX_EQ_RST_SEL_OFST (30)
2553 +#define RG_SSUSB_RXVAL_RST_OFST (29)
2554 +#define RG_SSUSB_RXVAL_CNT_OFST (24)
2555 +#define RG_SSUSB_CDROS_EN_OFST (18)
2556 +#define RG_SSUSB_CDR_LCKOP_OFST (16)
2557 +#define RG_SSUSB_RX_FL_LOCKTH_OFST (8)
2558 +#define RG_SSUSB_RX_FL_OFFSET_OFST (0)
2559 +
2560 +//U3D_PHYD_RX0
2561 +#define RG_SSUSB_T2RLB_BERTH_OFST (24)
2562 +#define RG_SSUSB_T2RLB_PAT_OFST (16)
2563 +#define RG_SSUSB_T2RLB_EN_OFST (15)
2564 +#define RG_SSUSB_T2RLB_BPSCRAMB_OFST (14)
2565 +#define RG_SSUSB_T2RLB_SERIAL_OFST (13)
2566 +#define RG_SSUSB_T2RLB_MODE_OFST (11)
2567 +#define RG_SSUSB_RX_SAOSC_EN_OFST (10)
2568 +#define RG_SSUSB_RX_SAOSC_EN_SEL_OFST (9)
2569 +#define RG_SSUSB_RX_DFE_OPTION_OFST (8)
2570 +#define RG_SSUSB_RX_DFE_EN_OFST (7)
2571 +#define RG_SSUSB_RX_DFE_EN_SEL_OFST (6)
2572 +#define RG_SSUSB_RX_EQ_EN_OFST (5)
2573 +#define RG_SSUSB_RX_EQ_EN_SEL_OFST (4)
2574 +#define RG_SSUSB_RX_SAOSC_RST_OFST (3)
2575 +#define RG_SSUSB_RX_SAOSC_RST_SEL_OFST (2)
2576 +#define RG_SSUSB_RX_DFE_RST_OFST (1)
2577 +#define RG_SSUSB_RX_DFE_RST_SEL_OFST (0)
2578 +
2579 +//U3D_PHYD_T2RLB
2580 +#define RG_SSUSB_EQTRAIN_CH_MODE_OFST (28)
2581 +#define RG_SSUSB_PRB_OUT_CPPAT_OFST (27)
2582 +#define RG_SSUSB_BPANSIENC_OFST (26)
2583 +#define RG_SSUSB_VALID_EN_OFST (25)
2584 +#define RG_SSUSB_EBUF_SRST_OFST (24)
2585 +#define RG_SSUSB_K_EMP_OFST (20)
2586 +#define RG_SSUSB_K_FUL_OFST (16)
2587 +#define RG_SSUSB_T2RLB_BDATRST_OFST (12)
2588 +#define RG_SSUSB_P_T2RLB_SKP_EN_OFST (10)
2589 +#define RG_SSUSB_T2RLB_PATMODE_OFST (8)
2590 +#define RG_SSUSB_T2RLB_TSEQCNT_OFST (0)
2591 +
2592 +//U3D_PHYD_CPPAT
2593 +#define RG_SSUSB_CPPAT_PROGRAM_EN_OFST (24)
2594 +#define RG_SSUSB_CPPAT_TOZ_OFST (21)
2595 +#define RG_SSUSB_CPPAT_PRBS_EN_OFST (20)
2596 +#define RG_SSUSB_CPPAT_OUT_TMP2_OFST (16)
2597 +#define RG_SSUSB_CPPAT_OUT_TMP1_OFST (8)
2598 +#define RG_SSUSB_CPPAT_OUT_TMP0_OFST (0)
2599 +
2600 +//U3D_PHYD_MIX3
2601 +#define RG_SSUSB_CDR_TCADJ_MINUS_OFST (31)
2602 +#define RG_SSUSB_P_CDROS_EN_OFST (30)
2603 +#define RG_SSUSB_P_P2_TX_DRV_DIS_OFST (28)
2604 +#define RG_SSUSB_CDR_TCADJ_OFFSET_OFST (24)
2605 +#define RG_SSUSB_PLL_TCADJ_MINUS_OFST (23)
2606 +#define RG_SSUSB_FORCE_PLL_BIAS_LPF_EN_OFST (20)
2607 +#define RG_SSUSB_PLL_BIAS_LPF_EN_OFST (19)
2608 +#define RG_SSUSB_PLL_TCADJ_OFFSET_OFST (16)
2609 +#define RG_SSUSB_FORCE_PLL_SSCEN_OFST (15)
2610 +#define RG_SSUSB_PLL_SSCEN_OFST (14)
2611 +#define RG_SSUSB_FORCE_CDR_PI_PWD_OFST (13)
2612 +#define RG_SSUSB_CDR_PI_PWD_OFST (12)
2613 +#define RG_SSUSB_CDR_PI_MODE_OFST (11)
2614 +#define RG_SSUSB_TXPLL_SSCEN_CYC_OFST (0)
2615 +
2616 +//U3D_PHYD_EBUFCTL
2617 +#define RG_SSUSB_EBUFCTL_OFST (0)
2618 +
2619 +//U3D_PHYD_PIPE0
2620 +#define RG_SSUSB_RXTERMINATION_OFST (30)
2621 +#define RG_SSUSB_RXEQTRAINING_OFST (29)
2622 +#define RG_SSUSB_RXPOLARITY_OFST (28)
2623 +#define RG_SSUSB_TXDEEMPH_OFST (26)
2624 +#define RG_SSUSB_POWERDOWN_OFST (24)
2625 +#define RG_SSUSB_TXONESZEROS_OFST (23)
2626 +#define RG_SSUSB_TXELECIDLE_OFST (22)
2627 +#define RG_SSUSB_TXDETECTRX_OFST (21)
2628 +#define RG_SSUSB_PIPE_SEL_OFST (20)
2629 +#define RG_SSUSB_TXDATAK_OFST (16)
2630 +#define RG_SSUSB_CDR_STABLE_SEL_OFST (15)
2631 +#define RG_SSUSB_CDR_STABLE_OFST (14)
2632 +#define RG_SSUSB_CDR_RSTB_SEL_OFST (13)
2633 +#define RG_SSUSB_CDR_RSTB_OFST (12)
2634 +#define RG_SSUSB_P_ERROR_SEL_OFST (4)
2635 +#define RG_SSUSB_TXMARGIN_OFST (1)
2636 +#define RG_SSUSB_TXCOMPLIANCE_OFST (0)
2637 +
2638 +//U3D_PHYD_PIPE1
2639 +#define RG_SSUSB_TXDATA_OFST (0)
2640 +
2641 +//U3D_PHYD_MIX4
2642 +#define RG_SSUSB_CDROS_CNT_OFST (24)
2643 +#define RG_SSUSB_T2RLB_BER_EN_OFST (16)
2644 +#define RG_SSUSB_T2RLB_BER_RATE_OFST (0)
2645 +
2646 +//U3D_PHYD_CKGEN0
2647 +#define RG_SSUSB_RFIFO_IMPLAT_OFST (27)
2648 +#define RG_SSUSB_TFIFO_PSEL_OFST (24)
2649 +#define RG_SSUSB_CKGEN_PSEL_OFST (8)
2650 +#define RG_SSUSB_RXCK_INV_OFST (0)
2651 +
2652 +//U3D_PHYD_MIX5
2653 +#define RG_SSUSB_PRB_SEL_OFST (16)
2654 +#define RG_SSUSB_RXPLL_STBCYC_OFST (0)
2655 +
2656 +//U3D_PHYD_RESERVED
2657 +#define RG_SSUSB_PHYD_RESERVE_OFST (0)
2658 +//#define RG_SSUSB_RX_SIGDET_SEL_OFST (11)
2659 +//#define RG_SSUSB_RX_SIGDET_EN_OFST (12)
2660 +//#define RG_SSUSB_RX_PI_CAL_MANUAL_SEL_OFST (9)
2661 +//#define RG_SSUSB_RX_PI_CAL_MANUAL_EN_OFST (10)
2662 +
2663 +//U3D_PHYD_CDR0
2664 +#define RG_SSUSB_CDR_BIC_LTR_OFST (28)
2665 +#define RG_SSUSB_CDR_BIC_LTD0_OFST (24)
2666 +#define RG_SSUSB_CDR_BC_LTD1_OFST (16)
2667 +#define RG_SSUSB_CDR_BC_LTR_OFST (8)
2668 +#define RG_SSUSB_CDR_BC_LTD0_OFST (0)
2669 +
2670 +//U3D_PHYD_CDR1
2671 +#define RG_SSUSB_CDR_BIR_LTD1_OFST (24)
2672 +#define RG_SSUSB_CDR_BIR_LTR_OFST (16)
2673 +#define RG_SSUSB_CDR_BIR_LTD0_OFST (8)
2674 +#define RG_SSUSB_CDR_BW_SEL_OFST (6)
2675 +#define RG_SSUSB_CDR_BIC_LTD1_OFST (0)
2676 +
2677 +//U3D_PHYD_PLL_0
2678 +#define RG_SSUSB_FORCE_CDR_BAND_5G_OFST (28)
2679 +#define RG_SSUSB_FORCE_CDR_BAND_2P5G_OFST (27)
2680 +#define RG_SSUSB_FORCE_PLL_BAND_5G_OFST (26)
2681 +#define RG_SSUSB_FORCE_PLL_BAND_2P5G_OFST (25)
2682 +#define RG_SSUSB_P_EQ_T_SEL_OFST (15)
2683 +#define RG_SSUSB_PLL_ISO_EN_CYC_OFST (5)
2684 +#define RG_SSUSB_PLLBAND_RECAL_OFST (4)
2685 +#define RG_SSUSB_PLL_DDS_ISO_EN_OFST (3)
2686 +#define RG_SSUSB_FORCE_PLL_DDS_ISO_EN_OFST (2)
2687 +#define RG_SSUSB_PLL_DDS_PWR_ON_OFST (1)
2688 +#define RG_SSUSB_FORCE_PLL_DDS_PWR_ON_OFST (0)
2689 +
2690 +//U3D_PHYD_PLL_1
2691 +#define RG_SSUSB_CDR_BAND_5G_OFST (24)
2692 +#define RG_SSUSB_CDR_BAND_2P5G_OFST (16)
2693 +#define RG_SSUSB_PLL_BAND_5G_OFST (8)
2694 +#define RG_SSUSB_PLL_BAND_2P5G_OFST (0)
2695 +
2696 +//U3D_PHYD_BCN_DET_1
2697 +#define RG_SSUSB_P_BCN_OBS_PRD_OFST (16)
2698 +#define RG_SSUSB_U_BCN_OBS_PRD_OFST (0)
2699 +
2700 +//U3D_PHYD_BCN_DET_2
2701 +#define RG_SSUSB_P_BCN_OBS_SEL_OFST (16)
2702 +#define RG_SSUSB_BCN_DET_DIS_OFST (12)
2703 +#define RG_SSUSB_U_BCN_OBS_SEL_OFST (0)
2704 +
2705 +//U3D_EQ0
2706 +#define RG_SSUSB_EQ_DLHL_LFI_OFST (24)
2707 +#define RG_SSUSB_EQ_DHHL_LFI_OFST (16)
2708 +#define RG_SSUSB_EQ_DD0HOS_LFI_OFST (8)
2709 +#define RG_SSUSB_EQ_DD0LOS_LFI_OFST (0)
2710 +
2711 +//U3D_EQ1
2712 +#define RG_SSUSB_EQ_DD1HOS_LFI_OFST (24)
2713 +#define RG_SSUSB_EQ_DD1LOS_LFI_OFST (16)
2714 +#define RG_SSUSB_EQ_DE0OS_LFI_OFST (8)
2715 +#define RG_SSUSB_EQ_DE1OS_LFI_OFST (0)
2716 +
2717 +//U3D_EQ2
2718 +#define RG_SSUSB_EQ_DLHLOS_LFI_OFST (24)
2719 +#define RG_SSUSB_EQ_DHHLOS_LFI_OFST (16)
2720 +#define RG_SSUSB_EQ_STOPTIME_OFST (14)
2721 +#define RG_SSUSB_EQ_DHHL_LF_SEL_OFST (11)
2722 +#define RG_SSUSB_EQ_DSAOS_LF_SEL_OFST (8)
2723 +#define RG_SSUSB_EQ_STARTTIME_OFST (6)
2724 +#define RG_SSUSB_EQ_DLEQ_LF_SEL_OFST (3)
2725 +#define RG_SSUSB_EQ_DLHL_LF_SEL_OFST (0)
2726 +
2727 +//U3D_EQ3
2728 +#define RG_SSUSB_EQ_DLEQ_LFI_GEN2_OFST (28)
2729 +#define RG_SSUSB_EQ_DLEQ_LFI_GEN1_OFST (24)
2730 +#define RG_SSUSB_EQ_DEYE0OS_LFI_OFST (16)
2731 +#define RG_SSUSB_EQ_DEYE1OS_LFI_OFST (8)
2732 +#define RG_SSUSB_EQ_TRI_DET_EN_OFST (7)
2733 +#define RG_SSUSB_EQ_TRI_DET_TH_OFST (0)
2734 +
2735 +//U3D_EQ_EYE0
2736 +#define RG_SSUSB_EQ_EYE_XOFFSET_OFST (25)
2737 +#define RG_SSUSB_EQ_EYE_MON_EN_OFST (24)
2738 +#define RG_SSUSB_EQ_EYE0_Y_OFST (16)
2739 +#define RG_SSUSB_EQ_EYE1_Y_OFST (8)
2740 +#define RG_SSUSB_EQ_PILPO_ROUT_OFST (7)
2741 +#define RG_SSUSB_EQ_PI_KPGAIN_OFST (4)
2742 +#define RG_SSUSB_EQ_EYE_CNT_EN_OFST (3)
2743 +
2744 +//U3D_EQ_EYE1
2745 +#define RG_SSUSB_EQ_SIGDET_OFST (24)
2746 +#define RG_SSUSB_EQ_EYE_MASK_OFST (7)
2747 +
2748 +//U3D_EQ_EYE2
2749 +#define RG_SSUSB_EQ_RX500M_CK_SEL_OFST (31)
2750 +#define RG_SSUSB_EQ_SD_CNT1_OFST (24)
2751 +#define RG_SSUSB_EQ_ISIFLAG_SEL_OFST (22)
2752 +#define RG_SSUSB_EQ_SD_CNT0_OFST (16)
2753 +
2754 +//U3D_EQ_DFE0
2755 +#define RG_SSUSB_EQ_LEQMAX_OFST (28)
2756 +#define RG_SSUSB_EQ_DFEX_EN_OFST (27)
2757 +#define RG_SSUSB_EQ_DFEX_LF_SEL_OFST (24)
2758 +#define RG_SSUSB_EQ_CHK_EYE_H_OFST (23)
2759 +#define RG_SSUSB_EQ_PIEYE_INI_OFST (16)
2760 +#define RG_SSUSB_EQ_PI90_INI_OFST (8)
2761 +#define RG_SSUSB_EQ_PI0_INI_OFST (0)
2762 +
2763 +//U3D_EQ_DFE1
2764 +#define RG_SSUSB_EQ_REV_OFST (16)
2765 +#define RG_SSUSB_EQ_DFEYEN_DUR_OFST (12)
2766 +#define RG_SSUSB_EQ_DFEXEN_DUR_OFST (8)
2767 +#define RG_SSUSB_EQ_DFEX_RST_OFST (7)
2768 +#define RG_SSUSB_EQ_GATED_RXD_B_OFST (6)
2769 +#define RG_SSUSB_EQ_PI90CK_SEL_OFST (4)
2770 +#define RG_SSUSB_EQ_DFEX_DIS_OFST (2)
2771 +#define RG_SSUSB_EQ_DFEYEN_STOP_DIS_OFST (1)
2772 +#define RG_SSUSB_EQ_DFEXEN_SEL_OFST (0)
2773 +
2774 +//U3D_EQ_DFE2
2775 +#define RG_SSUSB_EQ_MON_SEL_OFST (24)
2776 +#define RG_SSUSB_EQ_LEQOSC_DLYCNT_OFST (16)
2777 +#define RG_SSUSB_EQ_DLEQOS_LFI_OFST (8)
2778 +#define RG_SSUSB_EQ_LEQ_STOP_TO_OFST (0)
2779 +
2780 +//U3D_EQ_DFE3
2781 +#define RG_SSUSB_EQ_RESERVED_OFST (0)
2782 +
2783 +//U3D_PHYD_MON0
2784 +#define RGS_SSUSB_BERT_BERC_OFST (16)
2785 +#define RGS_SSUSB_LFPS_OFST (12)
2786 +#define RGS_SSUSB_TRAINDEC_OFST (8)
2787 +#define RGS_SSUSB_SCP_PAT_OFST (0)
2788 +
2789 +//U3D_PHYD_MON1
2790 +#define RGS_SSUSB_RX_FL_OUT_OFST (0)
2791 +
2792 +//U3D_PHYD_MON2
2793 +#define RGS_SSUSB_T2RLB_ERRCNT_OFST (16)
2794 +#define RGS_SSUSB_RETRACK_OFST (12)
2795 +#define RGS_SSUSB_RXPLL_LOCK_OFST (10)
2796 +#define RGS_SSUSB_CDR_VCOCAL_CPLT_D_OFST (9)
2797 +#define RGS_SSUSB_PLL_VCOCAL_CPLT_D_OFST (8)
2798 +#define RGS_SSUSB_PDNCTL_OFST (0)
2799 +
2800 +//U3D_PHYD_MON3
2801 +#define RGS_SSUSB_TSEQ_ERRCNT_OFST (16)
2802 +#define RGS_SSUSB_PRBS_ERRCNT_OFST (0)
2803 +
2804 +//U3D_PHYD_MON4
2805 +#define RGS_SSUSB_RX_LSLOCK_CNT_OFST (24)
2806 +#define RGS_SSUSB_SCP_DETCNT_OFST (16)
2807 +#define RGS_SSUSB_TSEQ_DETCNT_OFST (0)
2808 +
2809 +//U3D_PHYD_MON5
2810 +#define RGS_SSUSB_EBUFMSG_OFST (16)
2811 +#define RGS_SSUSB_BERT_LOCK_OFST (15)
2812 +#define RGS_SSUSB_SCP_DET_OFST (14)
2813 +#define RGS_SSUSB_TSEQ_DET_OFST (13)
2814 +#define RGS_SSUSB_EBUF_UDF_OFST (12)
2815 +#define RGS_SSUSB_EBUF_OVF_OFST (11)
2816 +#define RGS_SSUSB_PRBS_PASSTH_OFST (10)
2817 +#define RGS_SSUSB_PRBS_PASS_OFST (9)
2818 +#define RGS_SSUSB_PRBS_LOCK_OFST (8)
2819 +#define RGS_SSUSB_T2RLB_ERR_OFST (6)
2820 +#define RGS_SSUSB_T2RLB_PASSTH_OFST (5)
2821 +#define RGS_SSUSB_T2RLB_PASS_OFST (4)
2822 +#define RGS_SSUSB_T2RLB_LOCK_OFST (3)
2823 +#define RGS_SSUSB_RX_IMPCAL_DONE_OFST (2)
2824 +#define RGS_SSUSB_TX_IMPCAL_DONE_OFST (1)
2825 +#define RGS_SSUSB_RXDETECTED_OFST (0)
2826 +
2827 +//U3D_PHYD_MON6
2828 +#define RGS_SSUSB_SIGCAL_DONE_OFST (30)
2829 +#define RGS_SSUSB_SIGCAL_CAL_OUT_OFST (29)
2830 +#define RGS_SSUSB_SIGCAL_OFFSET_OFST (24)
2831 +#define RGS_SSUSB_RX_IMP_SEL_OFST (16)
2832 +#define RGS_SSUSB_TX_IMP_SEL_OFST (8)
2833 +#define RGS_SSUSB_TFIFO_MSG_OFST (4)
2834 +#define RGS_SSUSB_RFIFO_MSG_OFST (0)
2835 +
2836 +//U3D_PHYD_MON7
2837 +#define RGS_SSUSB_FT_OUT_OFST (8)
2838 +#define RGS_SSUSB_PRB_OUT_OFST (0)
2839 +
2840 +//U3D_PHYA_RX_MON0
2841 +#define RGS_SSUSB_EQ_DCLEQ_OFST (24)
2842 +#define RGS_SSUSB_EQ_DCD0H_OFST (16)
2843 +#define RGS_SSUSB_EQ_DCD0L_OFST (8)
2844 +#define RGS_SSUSB_EQ_DCD1H_OFST (0)
2845 +
2846 +//U3D_PHYA_RX_MON1
2847 +#define RGS_SSUSB_EQ_DCD1L_OFST (24)
2848 +#define RGS_SSUSB_EQ_DCE0_OFST (16)
2849 +#define RGS_SSUSB_EQ_DCE1_OFST (8)
2850 +#define RGS_SSUSB_EQ_DCHHL_OFST (0)
2851 +
2852 +//U3D_PHYA_RX_MON2
2853 +#define RGS_SSUSB_EQ_LEQ_STOP_OFST (31)
2854 +#define RGS_SSUSB_EQ_DCLHL_OFST (24)
2855 +#define RGS_SSUSB_EQ_STATUS_OFST (16)
2856 +#define RGS_SSUSB_EQ_DCEYE0_OFST (8)
2857 +#define RGS_SSUSB_EQ_DCEYE1_OFST (0)
2858 +
2859 +//U3D_PHYA_RX_MON3
2860 +#define RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_0_OFST (0)
2861 +
2862 +//U3D_PHYA_RX_MON4
2863 +#define RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_1_OFST (0)
2864 +
2865 +//U3D_PHYA_RX_MON5
2866 +#define RGS_SSUSB_EQ_DCLEQOS_OFST (8)
2867 +#define RGS_SSUSB_EQ_EYE_CNT_RDY_OFST (7)
2868 +#define RGS_SSUSB_EQ_PILPO_OFST (0)
2869 +
2870 +//U3D_PHYD_CPPAT2
2871 +#define RG_SSUSB_CPPAT_OUT_H_TMP2_OFST (16)
2872 +#define RG_SSUSB_CPPAT_OUT_H_TMP1_OFST (8)
2873 +#define RG_SSUSB_CPPAT_OUT_H_TMP0_OFST (0)
2874 +
2875 +//U3D_EQ_EYE3
2876 +#define RG_SSUSB_EQ_LEQ_SHIFT_OFST (24)
2877 +#define RG_SSUSB_EQ_EYE_CNT_OFST (0)
2878 +
2879 +//U3D_KBAND_OUT
2880 +#define RGS_SSUSB_CDR_BAND_5G_OFST (24)
2881 +#define RGS_SSUSB_CDR_BAND_2P5G_OFST (16)
2882 +#define RGS_SSUSB_PLL_BAND_5G_OFST (8)
2883 +#define RGS_SSUSB_PLL_BAND_2P5G_OFST (0)
2884 +
2885 +//U3D_KBAND_OUT1
2886 +#define RGS_SSUSB_CDR_VCOCAL_FAIL_OFST (24)
2887 +#define RGS_SSUSB_CDR_VCOCAL_STATE_OFST (16)
2888 +#define RGS_SSUSB_PLL_VCOCAL_FAIL_OFST (8)
2889 +#define RGS_SSUSB_PLL_VCOCAL_STATE_OFST (0)
2890 +
2891 +
2892 +///////////////////////////////////////////////////////////////////////////////
2893 +
2894 +struct u3phyd_bank2_reg {
2895 + //0x0
2896 + PHY_LE32 b2_phyd_top1;
2897 + PHY_LE32 b2_phyd_top2;
2898 + PHY_LE32 b2_phyd_top3;
2899 + PHY_LE32 b2_phyd_top4;
2900 + //0x10
2901 + PHY_LE32 b2_phyd_top5;
2902 + PHY_LE32 b2_phyd_top6;
2903 + PHY_LE32 b2_phyd_top7;
2904 + PHY_LE32 b2_phyd_p_sigdet1;
2905 + //0x20
2906 + PHY_LE32 b2_phyd_p_sigdet2;
2907 + PHY_LE32 b2_phyd_p_sigdet_cal1;
2908 + PHY_LE32 b2_phyd_rxdet1;
2909 + PHY_LE32 b2_phyd_rxdet2;
2910 + //0x30
2911 + PHY_LE32 b2_phyd_misc0;
2912 + PHY_LE32 b2_phyd_misc2;
2913 + PHY_LE32 b2_phyd_misc3;
2914 + PHY_LE32 reserve0;
2915 + //0x40
2916 + PHY_LE32 b2_rosc_0;
2917 + PHY_LE32 b2_rosc_1;
2918 + PHY_LE32 b2_rosc_2;
2919 + PHY_LE32 b2_rosc_3;
2920 + //0x50
2921 + PHY_LE32 b2_rosc_4;
2922 + PHY_LE32 b2_rosc_5;
2923 + PHY_LE32 b2_rosc_6;
2924 + PHY_LE32 b2_rosc_7;
2925 + //0x60
2926 + PHY_LE32 b2_rosc_8;
2927 + PHY_LE32 b2_rosc_9;
2928 + PHY_LE32 b2_rosc_a;
2929 + PHY_LE32 reserve1;
2930 + //0x70~0xd0
2931 + PHY_LE32 reserve2[28];
2932 + //0xe0
2933 + PHY_LE32 phyd_version;
2934 + PHY_LE32 phyd_model;
2935 +};
2936 +
2937 +//U3D_B2_PHYD_TOP1
2938 +#define RG_SSUSB_PCIE2_K_EMP (0xf<<28) //31:28
2939 +#define RG_SSUSB_PCIE2_K_FUL (0xf<<24) //27:24
2940 +#define RG_SSUSB_TX_EIDLE_LP_EN (0x1<<17) //17:17
2941 +#define RG_SSUSB_FORCE_TX_EIDLE_LP_EN (0x1<<16) //16:16
2942 +#define RG_SSUSB_SIGDET_EN (0x1<<15) //15:15
2943 +#define RG_SSUSB_FORCE_SIGDET_EN (0x1<<14) //14:14
2944 +#define RG_SSUSB_CLKRX_EN (0x1<<13) //13:13
2945 +#define RG_SSUSB_FORCE_CLKRX_EN (0x1<<12) //12:12
2946 +#define RG_SSUSB_CLKTX_EN (0x1<<11) //11:11
2947 +#define RG_SSUSB_FORCE_CLKTX_EN (0x1<<10) //10:10
2948 +#define RG_SSUSB_CLK_REQ_N_I (0x1<<9) //9:9
2949 +#define RG_SSUSB_FORCE_CLK_REQ_N_I (0x1<<8) //8:8
2950 +#define RG_SSUSB_RATE (0x1<<6) //6:6
2951 +#define RG_SSUSB_FORCE_RATE (0x1<<5) //5:5
2952 +#define RG_SSUSB_PCIE_MODE_SEL (0x1<<4) //4:4
2953 +#define RG_SSUSB_FORCE_PCIE_MODE_SEL (0x1<<3) //3:3
2954 +#define RG_SSUSB_PHY_MODE (0x3<<1) //2:1
2955 +#define RG_SSUSB_FORCE_PHY_MODE (0x1<<0) //0:0
2956 +
2957 +//U3D_B2_PHYD_TOP2
2958 +#define RG_SSUSB_FORCE_IDRV_6DB (0x1<<30) //30:30
2959 +#define RG_SSUSB_IDRV_6DB (0x3f<<24) //29:24
2960 +#define RG_SSUSB_FORCE_IDEM_3P5DB (0x1<<22) //22:22
2961 +#define RG_SSUSB_IDEM_3P5DB (0x3f<<16) //21:16
2962 +#define RG_SSUSB_FORCE_IDRV_3P5DB (0x1<<14) //14:14
2963 +#define RG_SSUSB_IDRV_3P5DB (0x3f<<8) //13:8
2964 +#define RG_SSUSB_FORCE_IDRV_0DB (0x1<<6) //6:6
2965 +#define RG_SSUSB_IDRV_0DB (0x3f<<0) //5:0
2966 +
2967 +//U3D_B2_PHYD_TOP3
2968 +#define RG_SSUSB_TX_BIASI (0x7<<25) //27:25
2969 +#define RG_SSUSB_FORCE_TX_BIASI_EN (0x1<<24) //24:24
2970 +#define RG_SSUSB_TX_BIASI_EN (0x1<<16) //16:16
2971 +#define RG_SSUSB_FORCE_TX_BIASI (0x1<<13) //13:13
2972 +#define RG_SSUSB_FORCE_IDEM_6DB (0x1<<8) //8:8
2973 +#define RG_SSUSB_IDEM_6DB (0x3f<<0) //5:0
2974 +
2975 +//U3D_B2_PHYD_TOP4
2976 +#define RG_SSUSB_G1_CDR_BIC_LTR (0xf<<28) //31:28
2977 +#define RG_SSUSB_G1_CDR_BIC_LTD0 (0xf<<24) //27:24
2978 +#define RG_SSUSB_G1_CDR_BC_LTD1 (0x1f<<16) //20:16
2979 +#define RG_SSUSB_G1_CDR_BC_LTR (0x1f<<8) //12:8
2980 +#define RG_SSUSB_G1_CDR_BC_LTD0 (0x1f<<0) //4:0
2981 +
2982 +//U3D_B2_PHYD_TOP5
2983 +#define RG_SSUSB_G1_CDR_BIR_LTD1 (0x1f<<24) //28:24
2984 +#define RG_SSUSB_G1_CDR_BIR_LTR (0x1f<<16) //20:16
2985 +#define RG_SSUSB_G1_CDR_BIR_LTD0 (0x1f<<8) //12:8
2986 +#define RG_SSUSB_G1_CDR_BIC_LTD1 (0xf<<0) //3:0
2987 +
2988 +//U3D_B2_PHYD_TOP6
2989 +#define RG_SSUSB_G2_CDR_BIC_LTR (0xf<<28) //31:28
2990 +#define RG_SSUSB_G2_CDR_BIC_LTD0 (0xf<<24) //27:24
2991 +#define RG_SSUSB_G2_CDR_BC_LTD1 (0x1f<<16) //20:16
2992 +#define RG_SSUSB_G2_CDR_BC_LTR (0x1f<<8) //12:8
2993 +#define RG_SSUSB_G2_CDR_BC_LTD0 (0x1f<<0) //4:0
2994 +
2995 +//U3D_B2_PHYD_TOP7
2996 +#define RG_SSUSB_G2_CDR_BIR_LTD1 (0x1f<<24) //28:24
2997 +#define RG_SSUSB_G2_CDR_BIR_LTR (0x1f<<16) //20:16
2998 +#define RG_SSUSB_G2_CDR_BIR_LTD0 (0x1f<<8) //12:8
2999 +#define RG_SSUSB_G2_CDR_BIC_LTD1 (0xf<<0) //3:0
3000 +
3001 +//U3D_B2_PHYD_P_SIGDET1
3002 +#define RG_SSUSB_P_SIGDET_FLT_DIS (0x1<<31) //31:31
3003 +#define RG_SSUSB_P_SIGDET_FLT_G2_DEAST_SEL (0x7f<<24) //30:24
3004 +#define RG_SSUSB_P_SIGDET_FLT_G1_DEAST_SEL (0x7f<<16) //22:16
3005 +#define RG_SSUSB_P_SIGDET_FLT_P2_AST_SEL (0x7f<<8) //14:8
3006 +#define RG_SSUSB_P_SIGDET_FLT_PX_AST_SEL (0x7f<<0) //6:0
3007 +
3008 +//U3D_B2_PHYD_P_SIGDET2
3009 +#define RG_SSUSB_P_SIGDET_RX_VAL_S (0x1<<29) //29:29
3010 +#define RG_SSUSB_P_SIGDET_L0S_DEAS_SEL (0x1<<28) //28:28
3011 +#define RG_SSUSB_P_SIGDET_L0_EXIT_S (0x1<<27) //27:27
3012 +#define RG_SSUSB_P_SIGDET_L0S_EXIT_T_S (0x3<<25) //26:25
3013 +#define RG_SSUSB_P_SIGDET_L0S_EXIT_S (0x1<<24) //24:24
3014 +#define RG_SSUSB_P_SIGDET_L0S_ENTRY_S (0x1<<16) //16:16
3015 +#define RG_SSUSB_P_SIGDET_PRB_SEL (0x1<<10) //10:10
3016 +#define RG_SSUSB_P_SIGDET_BK_SIG_T (0x3<<8) //9:8
3017 +#define RG_SSUSB_P_SIGDET_P2_RXLFPS (0x1<<6) //6:6
3018 +#define RG_SSUSB_P_SIGDET_NON_BK_AD (0x1<<5) //5:5
3019 +#define RG_SSUSB_P_SIGDET_BK_B_RXEQ (0x1<<4) //4:4
3020 +#define RG_SSUSB_P_SIGDET_G2_KO_SEL (0x3<<2) //3:2
3021 +#define RG_SSUSB_P_SIGDET_G1_KO_SEL (0x3<<0) //1:0
3022 +
3023 +//U3D_B2_PHYD_P_SIGDET_CAL1
3024 +#define RG_SSUSB_P_SIGDET_CAL_OFFSET (0x1f<<24) //28:24
3025 +#define RG_SSUSB_P_FORCE_SIGDET_CAL_OFFSET (0x1<<16) //16:16
3026 +#define RG_SSUSB_P_SIGDET_CAL_EN (0x1<<8) //8:8
3027 +#define RG_SSUSB_P_FORCE_SIGDET_CAL_EN (0x1<<3) //3:3
3028 +#define RG_SSUSB_P_SIGDET_FLT_EN (0x1<<2) //2:2
3029 +#define RG_SSUSB_P_SIGDET_SAMPLE_PRD (0x1<<1) //1:1
3030 +#define RG_SSUSB_P_SIGDET_REK (0x1<<0) //0:0
3031 +
3032 +//U3D_B2_PHYD_RXDET1
3033 +#define RG_SSUSB_RXDET_PRB_SEL (0x1<<31) //31:31
3034 +#define RG_SSUSB_FORCE_CMDET (0x1<<30) //30:30
3035 +#define RG_SSUSB_RXDET_EN (0x1<<29) //29:29
3036 +#define RG_SSUSB_FORCE_RXDET_EN (0x1<<28) //28:28
3037 +#define RG_SSUSB_RXDET_K_TWICE (0x1<<27) //27:27
3038 +#define RG_SSUSB_RXDET_STB3_SET (0x1ff<<18) //26:18
3039 +#define RG_SSUSB_RXDET_STB2_SET (0x1ff<<9) //17:9
3040 +#define RG_SSUSB_RXDET_STB1_SET (0x1ff<<0) //8:0
3041 +
3042 +//U3D_B2_PHYD_RXDET2
3043 +#define RG_SSUSB_PHYD_TRAINDEC_FORCE_CGEN (0x1<<31) //31:31
3044 +#define RG_SSUSB_PHYD_BERTLB_FORCE_CGEN (0x1<<30) //30:30
3045 +#define RG_SSUSB_PHYD_T2RLB_FORCE_CGEN (0x1<<29) //29:29
3046 +#define RG_SSUSB_PDN_T_SEL (0x3<<18) //19:18
3047 +#define RG_SSUSB_RXDET_STB3_SET_P3 (0x1ff<<9) //17:9
3048 +#define RG_SSUSB_RXDET_STB2_SET_P3 (0x1ff<<0) //8:0
3049 +
3050 +//U3D_B2_PHYD_MISC0
3051 +#define RG_SSUSB_FORCE_PLL_DDS_HF_EN (0x1<<22) //22:22
3052 +#define RG_SSUSB_PLL_DDS_HF_EN_MAN (0x1<<21) //21:21
3053 +#define RG_SSUSB_RXLFPS_ENTXDRV (0x1<<20) //20:20
3054 +#define RG_SSUSB_RX_FL_UNLOCKTH (0xf<<16) //19:16
3055 +#define RG_SSUSB_LFPS_PSEL (0x1<<15) //15:15
3056 +#define RG_SSUSB_RX_SIGDET_EN (0x1<<14) //14:14
3057 +#define RG_SSUSB_RX_SIGDET_EN_SEL (0x1<<13) //13:13
3058 +#define RG_SSUSB_RX_PI_CAL_EN (0x1<<12) //12:12
3059 +#define RG_SSUSB_RX_PI_CAL_EN_SEL (0x1<<11) //11:11
3060 +#define RG_SSUSB_P3_CLS_CK_SEL (0x1<<10) //10:10
3061 +#define RG_SSUSB_T2RLB_PSEL (0x3<<8) //9:8
3062 +#define RG_SSUSB_PPCTL_PSEL (0x7<<5) //7:5
3063 +#define RG_SSUSB_PHYD_TX_DATA_INV (0x1<<4) //4:4
3064 +#define RG_SSUSB_BERTLB_PSEL (0x3<<2) //3:2
3065 +#define RG_SSUSB_RETRACK_DIS (0x1<<1) //1:1
3066 +#define RG_SSUSB_PPERRCNT_CLR (0x1<<0) //0:0
3067 +
3068 +//U3D_B2_PHYD_MISC2
3069 +#define RG_SSUSB_FRC_PLL_DDS_PREDIV2 (0x1<<31) //31:31
3070 +#define RG_SSUSB_FRC_PLL_DDS_IADJ (0xf<<27) //30:27
3071 +#define RG_SSUSB_P_SIGDET_125FILTER (0x1<<26) //26:26
3072 +#define RG_SSUSB_P_SIGDET_RST_FILTER (0x1<<25) //25:25
3073 +#define RG_SSUSB_P_SIGDET_EID_USE_RAW (0x1<<24) //24:24
3074 +#define RG_SSUSB_P_SIGDET_LTD_USE_RAW (0x1<<23) //23:23
3075 +#define RG_SSUSB_EIDLE_BF_RXDET (0x1<<22) //22:22
3076 +#define RG_SSUSB_EIDLE_LP_STBCYC (0x1ff<<13) //21:13
3077 +#define RG_SSUSB_TX_EIDLE_LP_POSTDLY (0x3f<<7) //12:7
3078 +#define RG_SSUSB_TX_EIDLE_LP_PREDLY (0x3f<<1) //6:1
3079 +#define RG_SSUSB_TX_EIDLE_LP_EN_ADV (0x1<<0) //0:0
3080 +
3081 +//U3D_B2_PHYD_MISC3
3082 +#define RGS_SSUSB_DDS_CALIB_C_STATE (0x7<<16) //18:16
3083 +#define RGS_SSUSB_PPERRCNT (0xffff<<0) //15:0
3084 +
3085 +//U3D_B2_ROSC_0
3086 +#define RG_SSUSB_RING_OSC_CNTEND (0x1ff<<23) //31:23
3087 +#define RG_SSUSB_XTAL_OSC_CNTEND (0x7f<<16) //22:16
3088 +#define RG_SSUSB_RING_OSC_EN (0x1<<3) //3:3
3089 +#define RG_SSUSB_RING_OSC_FORCE_EN (0x1<<2) //2:2
3090 +#define RG_SSUSB_FRC_RING_BYPASS_DET (0x1<<1) //1:1
3091 +#define RG_SSUSB_RING_BYPASS_DET (0x1<<0) //0:0
3092 +
3093 +//U3D_B2_ROSC_1
3094 +#define RG_SSUSB_RING_OSC_FRC_P3 (0x1<<20) //20:20
3095 +#define RG_SSUSB_RING_OSC_P3 (0x1<<19) //19:19
3096 +#define RG_SSUSB_RING_OSC_FRC_RECAL (0x3<<17) //18:17
3097 +#define RG_SSUSB_RING_OSC_RECAL (0x1<<16) //16:16
3098 +#define RG_SSUSB_RING_OSC_SEL (0xff<<8) //15:8
3099 +#define RG_SSUSB_RING_OSC_FRC_SEL (0x1<<0) //0:0
3100 +
3101 +//U3D_B2_ROSC_2
3102 +#define RG_SSUSB_RING_DET_STRCYC2 (0xffff<<16) //31:16
3103 +#define RG_SSUSB_RING_DET_STRCYC1 (0xffff<<0) //15:0
3104 +
3105 +//U3D_B2_ROSC_3
3106 +#define RG_SSUSB_RING_DET_DETWIN1 (0xffff<<16) //31:16
3107 +#define RG_SSUSB_RING_DET_STRCYC3 (0xffff<<0) //15:0
3108 +
3109 +//U3D_B2_ROSC_4
3110 +#define RG_SSUSB_RING_DET_DETWIN3 (0xffff<<16) //31:16
3111 +#define RG_SSUSB_RING_DET_DETWIN2 (0xffff<<0) //15:0
3112 +
3113 +//U3D_B2_ROSC_5
3114 +#define RG_SSUSB_RING_DET_LBOND1 (0xffff<<16) //31:16
3115 +#define RG_SSUSB_RING_DET_UBOND1 (0xffff<<0) //15:0
3116 +
3117 +//U3D_B2_ROSC_6
3118 +#define RG_SSUSB_RING_DET_LBOND2 (0xffff<<16) //31:16
3119 +#define RG_SSUSB_RING_DET_UBOND2 (0xffff<<0) //15:0
3120 +
3121 +//U3D_B2_ROSC_7
3122 +#define RG_SSUSB_RING_DET_LBOND3 (0xffff<<16) //31:16
3123 +#define RG_SSUSB_RING_DET_UBOND3 (0xffff<<0) //15:0
3124 +
3125 +//U3D_B2_ROSC_8
3126 +#define RG_SSUSB_RING_RESERVE (0xffff<<16) //31:16
3127 +#define RG_SSUSB_ROSC_PROB_SEL (0xf<<2) //5:2
3128 +#define RG_SSUSB_RING_FREQMETER_EN (0x1<<1) //1:1
3129 +#define RG_SSUSB_RING_DET_BPS_UBOND (0x1<<0) //0:0
3130 +
3131 +//U3D_B2_ROSC_9
3132 +#define RGS_FM_RING_CNT (0xffff<<16) //31:16
3133 +#define RGS_SSUSB_RING_OSC_STATE (0x3<<10) //11:10
3134 +#define RGS_SSUSB_RING_OSC_STABLE (0x1<<9) //9:9
3135 +#define RGS_SSUSB_RING_OSC_CAL_FAIL (0x1<<8) //8:8
3136 +#define RGS_SSUSB_RING_OSC_CAL (0xff<<0) //7:0
3137 +
3138 +//U3D_B2_ROSC_A
3139 +#define RGS_SSUSB_ROSC_PROB_OUT (0xff<<0) //7:0
3140 +
3141 +//U3D_PHYD_VERSION
3142 +#define RGS_SSUSB_PHYD_VERSION (0xffffffff<<0) //31:0
3143 +
3144 +//U3D_PHYD_MODEL
3145 +#define RGS_SSUSB_PHYD_MODEL (0xffffffff<<0) //31:0
3146 +
3147 +
3148 +/* OFFSET */
3149 +
3150 +//U3D_B2_PHYD_TOP1
3151 +#define RG_SSUSB_PCIE2_K_EMP_OFST (28)
3152 +#define RG_SSUSB_PCIE2_K_FUL_OFST (24)
3153 +#define RG_SSUSB_TX_EIDLE_LP_EN_OFST (17)
3154 +#define RG_SSUSB_FORCE_TX_EIDLE_LP_EN_OFST (16)
3155 +#define RG_SSUSB_SIGDET_EN_OFST (15)
3156 +#define RG_SSUSB_FORCE_SIGDET_EN_OFST (14)
3157 +#define RG_SSUSB_CLKRX_EN_OFST (13)
3158 +#define RG_SSUSB_FORCE_CLKRX_EN_OFST (12)
3159 +#define RG_SSUSB_CLKTX_EN_OFST (11)
3160 +#define RG_SSUSB_FORCE_CLKTX_EN_OFST (10)
3161 +#define RG_SSUSB_CLK_REQ_N_I_OFST (9)
3162 +#define RG_SSUSB_FORCE_CLK_REQ_N_I_OFST (8)
3163 +#define RG_SSUSB_RATE_OFST (6)
3164 +#define RG_SSUSB_FORCE_RATE_OFST (5)
3165 +#define RG_SSUSB_PCIE_MODE_SEL_OFST (4)
3166 +#define RG_SSUSB_FORCE_PCIE_MODE_SEL_OFST (3)
3167 +#define RG_SSUSB_PHY_MODE_OFST (1)
3168 +#define RG_SSUSB_FORCE_PHY_MODE_OFST (0)
3169 +
3170 +//U3D_B2_PHYD_TOP2
3171 +#define RG_SSUSB_FORCE_IDRV_6DB_OFST (30)
3172 +#define RG_SSUSB_IDRV_6DB_OFST (24)
3173 +#define RG_SSUSB_FORCE_IDEM_3P5DB_OFST (22)
3174 +#define RG_SSUSB_IDEM_3P5DB_OFST (16)
3175 +#define RG_SSUSB_FORCE_IDRV_3P5DB_OFST (14)
3176 +#define RG_SSUSB_IDRV_3P5DB_OFST (8)
3177 +#define RG_SSUSB_FORCE_IDRV_0DB_OFST (6)
3178 +#define RG_SSUSB_IDRV_0DB_OFST (0)
3179 +
3180 +//U3D_B2_PHYD_TOP3
3181 +#define RG_SSUSB_TX_BIASI_OFST (25)
3182 +#define RG_SSUSB_FORCE_TX_BIASI_EN_OFST (24)
3183 +#define RG_SSUSB_TX_BIASI_EN_OFST (16)
3184 +#define RG_SSUSB_FORCE_TX_BIASI_OFST (13)
3185 +#define RG_SSUSB_FORCE_IDEM_6DB_OFST (8)
3186 +#define RG_SSUSB_IDEM_6DB_OFST (0)
3187 +
3188 +//U3D_B2_PHYD_TOP4
3189 +#define RG_SSUSB_G1_CDR_BIC_LTR_OFST (28)
3190 +#define RG_SSUSB_G1_CDR_BIC_LTD0_OFST (24)
3191 +#define RG_SSUSB_G1_CDR_BC_LTD1_OFST (16)
3192 +#define RG_SSUSB_G1_CDR_BC_LTR_OFST (8)
3193 +#define RG_SSUSB_G1_CDR_BC_LTD0_OFST (0)
3194 +
3195 +//U3D_B2_PHYD_TOP5
3196 +#define RG_SSUSB_G1_CDR_BIR_LTD1_OFST (24)
3197 +#define RG_SSUSB_G1_CDR_BIR_LTR_OFST (16)
3198 +#define RG_SSUSB_G1_CDR_BIR_LTD0_OFST (8)
3199 +#define RG_SSUSB_G1_CDR_BIC_LTD1_OFST (0)
3200 +
3201 +//U3D_B2_PHYD_TOP6
3202 +#define RG_SSUSB_G2_CDR_BIC_LTR_OFST (28)
3203 +#define RG_SSUSB_G2_CDR_BIC_LTD0_OFST (24)
3204 +#define RG_SSUSB_G2_CDR_BC_LTD1_OFST (16)
3205 +#define RG_SSUSB_G2_CDR_BC_LTR_OFST (8)
3206 +#define RG_SSUSB_G2_CDR_BC_LTD0_OFST (0)
3207 +
3208 +//U3D_B2_PHYD_TOP7
3209 +#define RG_SSUSB_G2_CDR_BIR_LTD1_OFST (24)
3210 +#define RG_SSUSB_G2_CDR_BIR_LTR_OFST (16)
3211 +#define RG_SSUSB_G2_CDR_BIR_LTD0_OFST (8)
3212 +#define RG_SSUSB_G2_CDR_BIC_LTD1_OFST (0)
3213 +
3214 +//U3D_B2_PHYD_P_SIGDET1
3215 +#define RG_SSUSB_P_SIGDET_FLT_DIS_OFST (31)
3216 +#define RG_SSUSB_P_SIGDET_FLT_G2_DEAST_SEL_OFST (24)
3217 +#define RG_SSUSB_P_SIGDET_FLT_G1_DEAST_SEL_OFST (16)
3218 +#define RG_SSUSB_P_SIGDET_FLT_P2_AST_SEL_OFST (8)
3219 +#define RG_SSUSB_P_SIGDET_FLT_PX_AST_SEL_OFST (0)
3220 +
3221 +//U3D_B2_PHYD_P_SIGDET2
3222 +#define RG_SSUSB_P_SIGDET_RX_VAL_S_OFST (29)
3223 +#define RG_SSUSB_P_SIGDET_L0S_DEAS_SEL_OFST (28)
3224 +#define RG_SSUSB_P_SIGDET_L0_EXIT_S_OFST (27)
3225 +#define RG_SSUSB_P_SIGDET_L0S_EXIT_T_S_OFST (25)
3226 +#define RG_SSUSB_P_SIGDET_L0S_EXIT_S_OFST (24)
3227 +#define RG_SSUSB_P_SIGDET_L0S_ENTRY_S_OFST (16)
3228 +#define RG_SSUSB_P_SIGDET_PRB_SEL_OFST (10)
3229 +#define RG_SSUSB_P_SIGDET_BK_SIG_T_OFST (8)
3230 +#define RG_SSUSB_P_SIGDET_P2_RXLFPS_OFST (6)
3231 +#define RG_SSUSB_P_SIGDET_NON_BK_AD_OFST (5)
3232 +#define RG_SSUSB_P_SIGDET_BK_B_RXEQ_OFST (4)
3233 +#define RG_SSUSB_P_SIGDET_G2_KO_SEL_OFST (2)
3234 +#define RG_SSUSB_P_SIGDET_G1_KO_SEL_OFST (0)
3235 +
3236 +//U3D_B2_PHYD_P_SIGDET_CAL1
3237 +#define RG_SSUSB_P_SIGDET_CAL_OFFSET_OFST (24)
3238 +#define RG_SSUSB_P_FORCE_SIGDET_CAL_OFFSET_OFST (16)
3239 +#define RG_SSUSB_P_SIGDET_CAL_EN_OFST (8)
3240 +#define RG_SSUSB_P_FORCE_SIGDET_CAL_EN_OFST (3)
3241 +#define RG_SSUSB_P_SIGDET_FLT_EN_OFST (2)
3242 +#define RG_SSUSB_P_SIGDET_SAMPLE_PRD_OFST (1)
3243 +#define RG_SSUSB_P_SIGDET_REK_OFST (0)
3244 +
3245 +//U3D_B2_PHYD_RXDET1
3246 +#define RG_SSUSB_RXDET_PRB_SEL_OFST (31)
3247 +#define RG_SSUSB_FORCE_CMDET_OFST (30)
3248 +#define RG_SSUSB_RXDET_EN_OFST (29)
3249 +#define RG_SSUSB_FORCE_RXDET_EN_OFST (28)
3250 +#define RG_SSUSB_RXDET_K_TWICE_OFST (27)
3251 +#define RG_SSUSB_RXDET_STB3_SET_OFST (18)
3252 +#define RG_SSUSB_RXDET_STB2_SET_OFST (9)
3253 +#define RG_SSUSB_RXDET_STB1_SET_OFST (0)
3254 +
3255 +//U3D_B2_PHYD_RXDET2
3256 +#define RG_SSUSB_PHYD_TRAINDEC_FORCE_CGEN_OFST (31)
3257 +#define RG_SSUSB_PHYD_BERTLB_FORCE_CGEN_OFST (30)
3258 +#define RG_SSUSB_PHYD_T2RLB_FORCE_CGEN_OFST (29)
3259 +#define RG_SSUSB_PDN_T_SEL_OFST (18)
3260 +#define RG_SSUSB_RXDET_STB3_SET_P3_OFST (9)
3261 +#define RG_SSUSB_RXDET_STB2_SET_P3_OFST (0)
3262 +
3263 +//U3D_B2_PHYD_MISC0
3264 +#define RG_SSUSB_FORCE_PLL_DDS_HF_EN_OFST (22)
3265 +#define RG_SSUSB_PLL_DDS_HF_EN_MAN_OFST (21)
3266 +#define RG_SSUSB_RXLFPS_ENTXDRV_OFST (20)
3267 +#define RG_SSUSB_RX_FL_UNLOCKTH_OFST (16)
3268 +#define RG_SSUSB_LFPS_PSEL_OFST (15)
3269 +#define RG_SSUSB_RX_SIGDET_EN_OFST (14)
3270 +#define RG_SSUSB_RX_SIGDET_EN_SEL_OFST (13)
3271 +#define RG_SSUSB_RX_PI_CAL_EN_OFST (12)
3272 +#define RG_SSUSB_RX_PI_CAL_EN_SEL_OFST (11)
3273 +#define RG_SSUSB_P3_CLS_CK_SEL_OFST (10)
3274 +#define RG_SSUSB_T2RLB_PSEL_OFST (8)
3275 +#define RG_SSUSB_PPCTL_PSEL_OFST (5)
3276 +#define RG_SSUSB_PHYD_TX_DATA_INV_OFST (4)
3277 +#define RG_SSUSB_BERTLB_PSEL_OFST (2)
3278 +#define RG_SSUSB_RETRACK_DIS_OFST (1)
3279 +#define RG_SSUSB_PPERRCNT_CLR_OFST (0)
3280 +
3281 +//U3D_B2_PHYD_MISC2
3282 +#define RG_SSUSB_FRC_PLL_DDS_PREDIV2_OFST (31)
3283 +#define RG_SSUSB_FRC_PLL_DDS_IADJ_OFST (27)
3284 +#define RG_SSUSB_P_SIGDET_125FILTER_OFST (26)
3285 +#define RG_SSUSB_P_SIGDET_RST_FILTER_OFST (25)
3286 +#define RG_SSUSB_P_SIGDET_EID_USE_RAW_OFST (24)
3287 +#define RG_SSUSB_P_SIGDET_LTD_USE_RAW_OFST (23)
3288 +#define RG_SSUSB_EIDLE_BF_RXDET_OFST (22)
3289 +#define RG_SSUSB_EIDLE_LP_STBCYC_OFST (13)
3290 +#define RG_SSUSB_TX_EIDLE_LP_POSTDLY_OFST (7)
3291 +#define RG_SSUSB_TX_EIDLE_LP_PREDLY_OFST (1)
3292 +#define RG_SSUSB_TX_EIDLE_LP_EN_ADV_OFST (0)
3293 +
3294 +//U3D_B2_PHYD_MISC3
3295 +#define RGS_SSUSB_DDS_CALIB_C_STATE_OFST (16)
3296 +#define RGS_SSUSB_PPERRCNT_OFST (0)
3297 +
3298 +//U3D_B2_ROSC_0
3299 +#define RG_SSUSB_RING_OSC_CNTEND_OFST (23)
3300 +#define RG_SSUSB_XTAL_OSC_CNTEND_OFST (16)
3301 +#define RG_SSUSB_RING_OSC_EN_OFST (3)
3302 +#define RG_SSUSB_RING_OSC_FORCE_EN_OFST (2)
3303 +#define RG_SSUSB_FRC_RING_BYPASS_DET_OFST (1)
3304 +#define RG_SSUSB_RING_BYPASS_DET_OFST (0)
3305 +
3306 +//U3D_B2_ROSC_1
3307 +#define RG_SSUSB_RING_OSC_FRC_P3_OFST (20)
3308 +#define RG_SSUSB_RING_OSC_P3_OFST (19)
3309 +#define RG_SSUSB_RING_OSC_FRC_RECAL_OFST (17)
3310 +#define RG_SSUSB_RING_OSC_RECAL_OFST (16)
3311 +#define RG_SSUSB_RING_OSC_SEL_OFST (8)
3312 +#define RG_SSUSB_RING_OSC_FRC_SEL_OFST (0)
3313 +
3314 +//U3D_B2_ROSC_2
3315 +#define RG_SSUSB_RING_DET_STRCYC2_OFST (16)
3316 +#define RG_SSUSB_RING_DET_STRCYC1_OFST (0)
3317 +
3318 +//U3D_B2_ROSC_3
3319 +#define RG_SSUSB_RING_DET_DETWIN1_OFST (16)
3320 +#define RG_SSUSB_RING_DET_STRCYC3_OFST (0)
3321 +
3322 +//U3D_B2_ROSC_4
3323 +#define RG_SSUSB_RING_DET_DETWIN3_OFST (16)
3324 +#define RG_SSUSB_RING_DET_DETWIN2_OFST (0)
3325 +
3326 +//U3D_B2_ROSC_5
3327 +#define RG_SSUSB_RING_DET_LBOND1_OFST (16)
3328 +#define RG_SSUSB_RING_DET_UBOND1_OFST (0)
3329 +
3330 +//U3D_B2_ROSC_6
3331 +#define RG_SSUSB_RING_DET_LBOND2_OFST (16)
3332 +#define RG_SSUSB_RING_DET_UBOND2_OFST (0)
3333 +
3334 +//U3D_B2_ROSC_7
3335 +#define RG_SSUSB_RING_DET_LBOND3_OFST (16)
3336 +#define RG_SSUSB_RING_DET_UBOND3_OFST (0)
3337 +
3338 +//U3D_B2_ROSC_8
3339 +#define RG_SSUSB_RING_RESERVE_OFST (16)
3340 +#define RG_SSUSB_ROSC_PROB_SEL_OFST (2)
3341 +#define RG_SSUSB_RING_FREQMETER_EN_OFST (1)
3342 +#define RG_SSUSB_RING_DET_BPS_UBOND_OFST (0)
3343 +
3344 +//U3D_B2_ROSC_9
3345 +#define RGS_FM_RING_CNT_OFST (16)
3346 +#define RGS_SSUSB_RING_OSC_STATE_OFST (10)
3347 +#define RGS_SSUSB_RING_OSC_STABLE_OFST (9)
3348 +#define RGS_SSUSB_RING_OSC_CAL_FAIL_OFST (8)
3349 +#define RGS_SSUSB_RING_OSC_CAL_OFST (0)
3350 +
3351 +//U3D_B2_ROSC_A
3352 +#define RGS_SSUSB_ROSC_PROB_OUT_OFST (0)
3353 +
3354 +//U3D_PHYD_VERSION
3355 +#define RGS_SSUSB_PHYD_VERSION_OFST (0)
3356 +
3357 +//U3D_PHYD_MODEL
3358 +#define RGS_SSUSB_PHYD_MODEL_OFST (0)
3359 +
3360 +
3361 +///////////////////////////////////////////////////////////////////////////////
3362 +
3363 +struct sifslv_chip_reg {
3364 + PHY_LE32 xtalbias;
3365 + PHY_LE32 syspll1;
3366 + PHY_LE32 gpio_ctla;
3367 + PHY_LE32 gpio_ctlb;
3368 + PHY_LE32 gpio_ctlc;
3369 +};
3370 +
3371 +//U3D_GPIO_CTLA
3372 +#define RG_C60802_GPIO_CTLA (0xffffffff<<0) //31:0
3373 +
3374 +//U3D_GPIO_CTLB
3375 +#define RG_C60802_GPIO_CTLB (0xffffffff<<0) //31:0
3376 +
3377 +//U3D_GPIO_CTLC
3378 +#define RG_C60802_GPIO_CTLC (0xffffffff<<0) //31:0
3379 +
3380 +/* OFFSET */
3381 +
3382 +//U3D_GPIO_CTLA
3383 +#define RG_C60802_GPIO_CTLA_OFST (0)
3384 +
3385 +//U3D_GPIO_CTLB
3386 +#define RG_C60802_GPIO_CTLB_OFST (0)
3387 +
3388 +//U3D_GPIO_CTLC
3389 +#define RG_C60802_GPIO_CTLC_OFST (0)
3390 +
3391 +///////////////////////////////////////////////////////////////////////////////
3392 +
3393 +struct sifslv_fm_feg {
3394 + //0x0
3395 + PHY_LE32 fmcr0;
3396 + PHY_LE32 fmcr1;
3397 + PHY_LE32 fmcr2;
3398 + PHY_LE32 fmmonr0;
3399 + //0x10
3400 + PHY_LE32 fmmonr1;
3401 +};
3402 +
3403 +//U3D_FMCR0
3404 +#define RG_LOCKTH (0xf<<28) //31:28
3405 +#define RG_MONCLK_SEL (0x3<<26) //27:26
3406 +#define RG_FM_MODE (0x1<<25) //25:25
3407 +#define RG_FREQDET_EN (0x1<<24) //24:24
3408 +#define RG_CYCLECNT (0xffffff<<0) //23:0
3409 +
3410 +//U3D_FMCR1
3411 +#define RG_TARGET (0xffffffff<<0) //31:0
3412 +
3413 +//U3D_FMCR2
3414 +#define RG_OFFSET (0xffffffff<<0) //31:0
3415 +
3416 +//U3D_FMMONR0
3417 +#define USB_FM_OUT (0xffffffff<<0) //31:0
3418 +
3419 +//U3D_FMMONR1
3420 +#define RG_MONCLK_SEL_3 (0x1<<9) //9:9
3421 +#define RG_FRCK_EN (0x1<<8) //8:8
3422 +#define USBPLL_LOCK (0x1<<1) //1:1
3423 +#define USB_FM_VLD (0x1<<0) //0:0
3424 +
3425 +
3426 +/* OFFSET */
3427 +
3428 +//U3D_FMCR0
3429 +#define RG_LOCKTH_OFST (28)
3430 +#define RG_MONCLK_SEL_OFST (26)
3431 +#define RG_FM_MODE_OFST (25)
3432 +#define RG_FREQDET_EN_OFST (24)
3433 +#define RG_CYCLECNT_OFST (0)
3434 +
3435 +//U3D_FMCR1
3436 +#define RG_TARGET_OFST (0)
3437 +
3438 +//U3D_FMCR2
3439 +#define RG_OFFSET_OFST (0)
3440 +
3441 +//U3D_FMMONR0
3442 +#define USB_FM_OUT_OFST (0)
3443 +
3444 +//U3D_FMMONR1
3445 +#define RG_MONCLK_SEL_3_OFST (9)
3446 +#define RG_FRCK_EN_OFST (8)
3447 +#define USBPLL_LOCK_OFST (1)
3448 +#define USB_FM_VLD_OFST (0)
3449 +
3450 +
3451 +///////////////////////////////////////////////////////////////////////////////
3452 +
3453 +PHY_INT32 phy_init(struct u3phy_info *info);
3454 +PHY_INT32 phy_change_pipe_phase(struct u3phy_info *info, PHY_INT32 phy_drv, PHY_INT32 pipe_phase);
3455 +PHY_INT32 eyescan_init(struct u3phy_info *info);
3456 +PHY_INT32 phy_eyescan(struct u3phy_info *info, PHY_INT32 x_t1, PHY_INT32 y_t1, PHY_INT32 x_br, PHY_INT32 y_br, PHY_INT32 delta_x, PHY_INT32 delta_y
3457 + , PHY_INT32 eye_cnt, PHY_INT32 num_cnt, PHY_INT32 PI_cal_en, PHY_INT32 num_ignore_cnt);
3458 +PHY_INT32 u2_save_cur_en(struct u3phy_info *info);
3459 +PHY_INT32 u2_save_cur_re(struct u3phy_info *info);
3460 +PHY_INT32 u2_slew_rate_calibration(struct u3phy_info *info);
3461 +
3462 +#endif
3463 +#endif
3464 --- /dev/null
3465 +++ b/drivers/usb/host/mtk-phy-ahb.c
3466 @@ -0,0 +1,58 @@
3467 +#include "mtk-phy.h"
3468 +#ifdef CONFIG_U3D_HAL_SUPPORT
3469 +#include "mu3d_hal_osal.h"
3470 +#endif
3471 +
3472 +#ifdef CONFIG_U3_PHY_AHB_SUPPORT
3473 +#include <linux/gfp.h>
3474 +#include <linux/kernel.h>
3475 +#include <linux/slab.h>
3476 +
3477 +#ifndef CONFIG_U3D_HAL_SUPPORT
3478 +#define os_writel(addr,data) {\
3479 + (*((volatile PHY_UINT32*)(addr)) = data);\
3480 + }
3481 +#define os_readl(addr) *((volatile PHY_UINT32*)(addr))
3482 +#define os_writelmsk(addr, data, msk) \
3483 + { os_writel(addr, ((os_readl(addr) & ~(msk)) | ((data) & (msk)))); \
3484 + }
3485 +#define os_setmsk(addr, msk) \
3486 + { os_writel(addr, os_readl(addr) | msk); \
3487 + }
3488 +#define os_clrmsk(addr, msk) \
3489 + { os_writel(addr, os_readl(addr) &~ msk); \
3490 + }
3491 +/*msk the data first, then umsk with the umsk.*/
3492 +#define os_writelmskumsk(addr, data, msk, umsk) \
3493 +{\
3494 + os_writel(addr, ((os_readl(addr) & ~(msk)) | ((data) & (msk))) & (umsk));\
3495 +}
3496 +
3497 +#endif
3498 +
3499 +PHY_INT32 U3PhyWriteReg32(PHY_UINT32 addr, PHY_UINT32 data)
3500 +{
3501 + os_writel(addr, data);
3502 +
3503 + return 0;
3504 +}
3505 +
3506 +PHY_INT32 U3PhyReadReg32(PHY_UINT32 addr)
3507 +{
3508 + return os_readl(addr);
3509 +}
3510 +
3511 +PHY_INT32 U3PhyWriteReg8(PHY_UINT32 addr, PHY_UINT8 data)
3512 +{
3513 + os_writelmsk(addr&0xfffffffc, data<<((addr%4)*8), 0xff<<((addr%4)*8));
3514 +
3515 + return 0;
3516 +}
3517 +
3518 +PHY_INT8 U3PhyReadReg8(PHY_UINT32 addr)
3519 +{
3520 + return ((os_readl(addr)>>((addr%4)*8))&0xff);
3521 +}
3522 +
3523 +#endif
3524 +
3525 --- /dev/null
3526 +++ b/drivers/usb/host/mtk-phy.c
3527 @@ -0,0 +1,102 @@
3528 +#include <linux/gfp.h>
3529 +#include <linux/kernel.h>
3530 +#include <linux/slab.h>
3531 +#define U3_PHY_LIB
3532 +#include "mtk-phy.h"
3533 +#ifdef CONFIG_PROJECT_7621
3534 +#include "mtk-phy-7621.h"
3535 +#endif
3536 +#ifdef CONFIG_PROJECT_PHY
3537 +static struct u3phy_operator project_operators = {
3538 + .init = phy_init,
3539 + .change_pipe_phase = phy_change_pipe_phase,
3540 + .eyescan_init = eyescan_init,
3541 + .eyescan = phy_eyescan,
3542 + .u2_slew_rate_calibration = u2_slew_rate_calibration,
3543 +};
3544 +#endif
3545 +
3546 +
3547 +PHY_INT32 u3phy_init(){
3548 +#ifndef CONFIG_PROJECT_PHY
3549 + PHY_INT32 u3phy_version;
3550 +#endif
3551 +
3552 + if(u3phy != NULL){
3553 + return PHY_TRUE;
3554 + }
3555 +
3556 + u3phy = kmalloc(sizeof(struct u3phy_info), GFP_NOIO);
3557 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
3558 + u3phy_p1 = kmalloc(sizeof(struct u3phy_info), GFP_NOIO);
3559 +#endif
3560 +#ifdef CONFIG_U3_PHY_GPIO_SUPPORT
3561 + u3phy->phyd_version_addr = 0x2000e4;
3562 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
3563 + u3phy_p1->phyd_version_addr = 0x2000e4;
3564 +#endif
3565 +#else
3566 + u3phy->phyd_version_addr = U3_PHYD_B2_BASE + 0xe4;
3567 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
3568 + u3phy_p1->phyd_version_addr = U3_PHYD_B2_BASE_P1 + 0xe4;
3569 +#endif
3570 +#endif
3571 +
3572 +#ifdef CONFIG_PROJECT_PHY
3573 +
3574 + u3phy->u2phy_regs = (struct u2phy_reg *)U2_PHY_BASE;
3575 + u3phy->u3phyd_regs = (struct u3phyd_reg *)U3_PHYD_BASE;
3576 + u3phy->u3phyd_bank2_regs = (struct u3phyd_bank2_reg *)U3_PHYD_B2_BASE;
3577 + u3phy->u3phya_regs = (struct u3phya_reg *)U3_PHYA_BASE;
3578 + u3phy->u3phya_da_regs = (struct u3phya_da_reg *)U3_PHYA_DA_BASE;
3579 + u3phy->sifslv_chip_regs = (struct sifslv_chip_reg *)SIFSLV_CHIP_BASE;
3580 + u3phy->sifslv_fm_regs = (struct sifslv_fm_feg *)SIFSLV_FM_FEG_BASE;
3581 + u3phy_ops = &project_operators;
3582 +
3583 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
3584 + u3phy_p1->u2phy_regs = (struct u2phy_reg *)U2_PHY_BASE_P1;
3585 + u3phy_p1->u3phyd_regs = (struct u3phyd_reg *)U3_PHYD_BASE_P1;
3586 + u3phy_p1->u3phyd_bank2_regs = (struct u3phyd_bank2_reg *)U3_PHYD_B2_BASE_P1;
3587 + u3phy_p1->u3phya_regs = (struct u3phya_reg *)U3_PHYA_BASE_P1;
3588 + u3phy_p1->u3phya_da_regs = (struct u3phya_da_reg *)U3_PHYA_DA_BASE_P1;
3589 + u3phy_p1->sifslv_chip_regs = (struct sifslv_chip_reg *)SIFSLV_CHIP_BASE;
3590 + u3phy_p1->sifslv_fm_regs = (struct sifslv_fm_feg *)SIFSLV_FM_FEG_BASE;
3591 +#endif
3592 +#endif
3593 +
3594 + return PHY_TRUE;
3595 +}
3596 +
3597 +PHY_INT32 U3PhyWriteField8(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask, PHY_INT32 value){
3598 + PHY_INT8 cur_value;
3599 + PHY_INT8 new_value;
3600 +
3601 + cur_value = U3PhyReadReg8(addr);
3602 + new_value = (cur_value & (~mask)) | (value << offset);
3603 + //udelay(i2cdelayus);
3604 + U3PhyWriteReg8(addr, new_value);
3605 + return PHY_TRUE;
3606 +}
3607 +
3608 +PHY_INT32 U3PhyWriteField32(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask, PHY_INT32 value){
3609 + PHY_INT32 cur_value;
3610 + PHY_INT32 new_value;
3611 +
3612 + cur_value = U3PhyReadReg32(addr);
3613 + new_value = (cur_value & (~mask)) | ((value << offset) & mask);
3614 + U3PhyWriteReg32(addr, new_value);
3615 + //DRV_MDELAY(100);
3616 +
3617 + return PHY_TRUE;
3618 +}
3619 +
3620 +PHY_INT32 U3PhyReadField8(PHY_INT32 addr,PHY_INT32 offset,PHY_INT32 mask){
3621 +
3622 + return ((U3PhyReadReg8(addr) & mask) >> offset);
3623 +}
3624 +
3625 +PHY_INT32 U3PhyReadField32(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask){
3626 +
3627 + return ((U3PhyReadReg32(addr) & mask) >> offset);
3628 +}
3629 +
3630 --- /dev/null
3631 +++ b/drivers/usb/host/mtk-phy.h
3632 @@ -0,0 +1,179 @@
3633 +#ifndef __MTK_PHY_NEW_H
3634 +#define __MTK_PHY_NEW_H
3635 +
3636 +//#define CONFIG_U3D_HAL_SUPPORT
3637 +
3638 +/* include system library */
3639 +#include <linux/gfp.h>
3640 +#include <linux/kernel.h>
3641 +#include <linux/slab.h>
3642 +#include <linux/delay.h>
3643 +
3644 +/* Choose PHY R/W implementation */
3645 +//#define CONFIG_U3_PHY_GPIO_SUPPORT //SW I2C implemented by GPIO
3646 +#define CONFIG_U3_PHY_AHB_SUPPORT //AHB, only on SoC
3647 +
3648 +/* Choose PHY version */
3649 +//Select your project by defining one of the followings
3650 +#define CONFIG_PROJECT_7621 //7621
3651 +#define CONFIG_PROJECT_PHY
3652 +
3653 +/* BASE ADDRESS DEFINE, should define this on ASIC */
3654 +#define PHY_BASE 0xBE1D0000
3655 +#define SIFSLV_FM_FEG_BASE (PHY_BASE+0x100)
3656 +#define SIFSLV_CHIP_BASE (PHY_BASE+0x700)
3657 +#define U2_PHY_BASE (PHY_BASE+0x800)
3658 +#define U3_PHYD_BASE (PHY_BASE+0x900)
3659 +#define U3_PHYD_B2_BASE (PHY_BASE+0xa00)
3660 +#define U3_PHYA_BASE (PHY_BASE+0xb00)
3661 +#define U3_PHYA_DA_BASE (PHY_BASE+0xc00)
3662 +
3663 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
3664 +#define SIFSLV_FM_FEG_BASE_P1 (PHY_BASE+0x100)
3665 +#define SIFSLV_CHIP_BASE_P1 (PHY_BASE+0x700)
3666 +#define U2_PHY_BASE_P1 (PHY_BASE+0x1000)
3667 +#define U3_PHYD_BASE_P1 (PHY_BASE+0x1100)
3668 +#define U3_PHYD_B2_BASE_P1 (PHY_BASE+0x1200)
3669 +#define U3_PHYA_BASE_P1 (PHY_BASE+0x1300)
3670 +#define U3_PHYA_DA_BASE_P1 (PHY_BASE+0x1400)
3671 +#endif
3672 +
3673 +/*
3674 +
3675 +0x00000100 MODULE ssusb_sifslv_fmreg ssusb_sifslv_fmreg
3676 +0x00000700 MODULE ssusb_sifslv_ippc ssusb_sifslv_ippc
3677 +0x00000800 MODULE ssusb_sifslv_u2phy_com ssusb_sifslv_u2_phy_com_T28
3678 +0x00000900 MODULE ssusb_sifslv_u3phyd ssusb_sifslv_u3phyd_T28
3679 +0x00000a00 MODULE ssusb_sifslv_u3phyd_bank2 ssusb_sifslv_u3phyd_bank2_T28
3680 +0x00000b00 MODULE ssusb_sifslv_u3phya ssusb_sifslv_u3phya_T28
3681 +0x00000c00 MODULE ssusb_sifslv_u3phya_da ssusb_sifslv_u3phya_da_T28
3682 +*/
3683 +
3684 +
3685 +/* TYPE DEFINE */
3686 +typedef unsigned int PHY_UINT32;
3687 +typedef int PHY_INT32;
3688 +typedef unsigned short PHY_UINT16;
3689 +typedef short PHY_INT16;
3690 +typedef unsigned char PHY_UINT8;
3691 +typedef char PHY_INT8;
3692 +
3693 +typedef PHY_UINT32 __bitwise PHY_LE32;
3694 +
3695 +/* CONSTANT DEFINE */
3696 +#define PHY_FALSE 0
3697 +#define PHY_TRUE 1
3698 +
3699 +/* MACRO DEFINE */
3700 +#define DRV_WriteReg32(addr,data) ((*(volatile PHY_UINT32 *)(addr)) = (unsigned long)(data))
3701 +#define DRV_Reg32(addr) (*(volatile PHY_UINT32 *)(addr))
3702 +
3703 +#define DRV_MDELAY mdelay
3704 +#define DRV_MSLEEP msleep
3705 +#define DRV_UDELAY udelay
3706 +#define DRV_USLEEP usleep
3707 +
3708 +/* PHY FUNCTION DEFINE, implemented in platform files, ex. ahb, gpio */
3709 +PHY_INT32 U3PhyWriteReg32(PHY_UINT32 addr, PHY_UINT32 data);
3710 +PHY_INT32 U3PhyReadReg32(PHY_UINT32 addr);
3711 +PHY_INT32 U3PhyWriteReg8(PHY_UINT32 addr, PHY_UINT8 data);
3712 +PHY_INT8 U3PhyReadReg8(PHY_UINT32 addr);
3713 +
3714 +/* PHY GENERAL USAGE FUNC, implemented in mtk-phy.c */
3715 +PHY_INT32 U3PhyWriteField8(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask, PHY_INT32 value);
3716 +PHY_INT32 U3PhyWriteField32(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask, PHY_INT32 value);
3717 +PHY_INT32 U3PhyReadField8(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask);
3718 +PHY_INT32 U3PhyReadField32(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask);
3719 +
3720 +struct u3phy_info {
3721 + PHY_INT32 phy_version;
3722 + PHY_INT32 phyd_version_addr;
3723 +
3724 +#ifdef CONFIG_PROJECT_PHY
3725 + struct u2phy_reg *u2phy_regs;
3726 + struct u3phya_reg *u3phya_regs;
3727 + struct u3phya_da_reg *u3phya_da_regs;
3728 + struct u3phyd_reg *u3phyd_regs;
3729 + struct u3phyd_bank2_reg *u3phyd_bank2_regs;
3730 + struct sifslv_chip_reg *sifslv_chip_regs;
3731 + struct sifslv_fm_feg *sifslv_fm_regs;
3732 +#endif
3733 +};
3734 +
3735 +struct u3phy_operator {
3736 + PHY_INT32 (*init) (struct u3phy_info *info);
3737 + PHY_INT32 (*change_pipe_phase) (struct u3phy_info *info, PHY_INT32 phy_drv, PHY_INT32 pipe_phase);
3738 + PHY_INT32 (*eyescan_init) (struct u3phy_info *info);
3739 + PHY_INT32 (*eyescan) (struct u3phy_info *info, PHY_INT32 x_t1, PHY_INT32 y_t1, PHY_INT32 x_br, PHY_INT32 y_br, PHY_INT32 delta_x, PHY_INT32 delta_y, PHY_INT32 eye_cnt, PHY_INT32 num_cnt, PHY_INT32 PI_cal_en, PHY_INT32 num_ignore_cnt);
3740 + PHY_INT32 (*u2_save_current_entry) (struct u3phy_info *info);
3741 + PHY_INT32 (*u2_save_current_recovery) (struct u3phy_info *info);
3742 + PHY_INT32 (*u2_slew_rate_calibration) (struct u3phy_info *info);
3743 +};
3744 +
3745 +#ifdef U3_PHY_LIB
3746 +#define AUTOEXT
3747 +#else
3748 +#define AUTOEXT extern
3749 +#endif
3750 +
3751 +AUTOEXT struct u3phy_info *u3phy;
3752 +AUTOEXT struct u3phy_info *u3phy_p1;
3753 +AUTOEXT struct u3phy_operator *u3phy_ops;
3754 +
3755 +/*********eye scan required*********/
3756 +
3757 +#define LO_BYTE(x) ((PHY_UINT8)((x) & 0xFF))
3758 +#define HI_BYTE(x) ((PHY_UINT8)(((x) & 0xFF00) >> 8))
3759 +
3760 +typedef enum
3761 +{
3762 + SCAN_UP,
3763 + SCAN_DN
3764 +} enumScanDir;
3765 +
3766 +struct strucScanRegion
3767 +{
3768 + PHY_INT8 bX_tl;
3769 + PHY_INT8 bY_tl;
3770 + PHY_INT8 bX_br;
3771 + PHY_INT8 bY_br;
3772 + PHY_INT8 bDeltaX;
3773 + PHY_INT8 bDeltaY;
3774 +};
3775 +
3776 +struct strucTestCycle
3777 +{
3778 + PHY_UINT16 wEyeCnt;
3779 + PHY_INT8 bNumOfEyeCnt;
3780 + PHY_INT8 bPICalEn;
3781 + PHY_INT8 bNumOfIgnoreCnt;
3782 +};
3783 +
3784 +#define ERRCNT_MAX 128
3785 +#define CYCLE_COUNT_MAX 15
3786 +
3787 +/// the map resolution is 128 x 128 pts
3788 +#define MAX_X 127
3789 +#define MAX_Y 127
3790 +#define MIN_X 0
3791 +#define MIN_Y 0
3792 +
3793 +PHY_INT32 u3phy_init(void);
3794 +
3795 +AUTOEXT struct strucScanRegion _rEye1;
3796 +AUTOEXT struct strucScanRegion _rEye2;
3797 +AUTOEXT struct strucTestCycle _rTestCycle;
3798 +AUTOEXT PHY_UINT8 _bXcurr;
3799 +AUTOEXT PHY_UINT8 _bYcurr;
3800 +AUTOEXT enumScanDir _eScanDir;
3801 +AUTOEXT PHY_INT8 _fgXChged;
3802 +AUTOEXT PHY_INT8 _bPIResult;
3803 +/* use local variable instead to save memory use */
3804 +#if 0
3805 +AUTOEXT PHY_UINT32 pwErrCnt0[CYCLE_COUNT_MAX][ERRCNT_MAX][ERRCNT_MAX];
3806 +AUTOEXT PHY_UINT32 pwErrCnt1[CYCLE_COUNT_MAX][ERRCNT_MAX][ERRCNT_MAX];
3807 +#endif
3808 +
3809 +/***********************************/
3810 +#endif
3811 +
3812 --- a/drivers/usb/host/pci-quirks.h
3813 +++ b/drivers/usb/host/pci-quirks.h
3814 @@ -1,7 +1,7 @@
3815 #ifndef __LINUX_USB_PCI_QUIRKS_H
3816 #define __LINUX_USB_PCI_QUIRKS_H
3817
3818 -#ifdef CONFIG_PCI
3819 +#if defined (CONFIG_PCI) && !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
3820 void uhci_reset_hc(struct pci_dev *pdev, unsigned long base);
3821 int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base);
3822 #endif /* CONFIG_PCI */
3823 --- a/drivers/usb/host/xhci-dbg.c
3824 +++ b/drivers/usb/host/xhci-dbg.c
3825 @@ -21,6 +21,9 @@
3826 */
3827
3828 #include "xhci.h"
3829 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
3830 +#include "xhci-mtk.h"
3831 +#endif
3832
3833 #define XHCI_INIT_VALUE 0x0
3834
3835 --- a/drivers/usb/host/xhci-mem.c
3836 +++ b/drivers/usb/host/xhci-mem.c
3837 @@ -67,6 +67,9 @@ static struct xhci_segment *xhci_segment
3838
3839 static void xhci_segment_free(struct xhci_hcd *xhci, struct xhci_segment *seg)
3840 {
3841 + if (!seg)
3842 + return;
3843 +
3844 if (seg->trbs) {
3845 dma_pool_free(xhci->segment_pool, seg->trbs, seg->dma);
3846 seg->trbs = NULL;
3847 @@ -1471,9 +1474,17 @@ int xhci_endpoint_init(struct xhci_hcd *
3848 max_burst = (usb_endpoint_maxp(&ep->desc)
3849 & 0x1800) >> 11;
3850 }
3851 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
3852 + if ((max_packet % 4 == 2) && (max_packet % 16 != 14) && (max_burst == 0) && usb_endpoint_dir_in(&ep->desc))
3853 + max_packet += 2;
3854 +#endif
3855 break;
3856 case USB_SPEED_FULL:
3857 case USB_SPEED_LOW:
3858 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
3859 + if ((max_packet % 4 == 2) && (max_packet % 16 != 14) && (max_burst == 0) && usb_endpoint_dir_in(&ep->desc))
3860 + max_packet += 2;
3861 +#endif
3862 break;
3863 default:
3864 BUG();
3865 --- /dev/null
3866 +++ b/drivers/usb/host/xhci-mtk-power.c
3867 @@ -0,0 +1,115 @@
3868 +#include "xhci-mtk.h"
3869 +#include "xhci-mtk-power.h"
3870 +#include "xhci.h"
3871 +#include <linux/kernel.h> /* printk() */
3872 +#include <linux/slab.h>
3873 +#include <linux/delay.h>
3874 +
3875 +static int g_num_u3_port;
3876 +static int g_num_u2_port;
3877 +
3878 +
3879 +void enableXhciAllPortPower(struct xhci_hcd *xhci){
3880 + int i;
3881 + u32 port_id, temp;
3882 + u32 __iomem *addr;
3883 +
3884 + g_num_u3_port = SSUSB_U3_PORT_NUM(readl(SSUSB_IP_CAP));
3885 + g_num_u2_port = SSUSB_U2_PORT_NUM(readl(SSUSB_IP_CAP));
3886 +
3887 + for(i=1; i<=g_num_u3_port; i++){
3888 + port_id=i;
3889 + addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(port_id-1 & 0xff);
3890 + temp = readl(addr);
3891 + temp = xhci_port_state_to_neutral(temp);
3892 + temp |= PORT_POWER;
3893 + writel(temp, addr);
3894 + }
3895 + for(i=1; i<=g_num_u2_port; i++){
3896 + port_id=i+g_num_u3_port;
3897 + addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(port_id-1 & 0xff);
3898 + temp = readl(addr);
3899 + temp = xhci_port_state_to_neutral(temp);
3900 + temp |= PORT_POWER;
3901 + writel(temp, addr);
3902 + }
3903 +}
3904 +
3905 +void enableAllClockPower(){
3906 +
3907 + int i;
3908 + u32 temp;
3909 +
3910 + g_num_u3_port = SSUSB_U3_PORT_NUM(readl(SSUSB_IP_CAP));
3911 + g_num_u2_port = SSUSB_U2_PORT_NUM(readl(SSUSB_IP_CAP));
3912 +
3913 + //2. Enable xHC
3914 + writel(readl(SSUSB_IP_PW_CTRL) | (SSUSB_IP_SW_RST), SSUSB_IP_PW_CTRL);
3915 + writel(readl(SSUSB_IP_PW_CTRL) & (~SSUSB_IP_SW_RST), SSUSB_IP_PW_CTRL);
3916 + writel(readl(SSUSB_IP_PW_CTRL_1) & (~SSUSB_IP_PDN), SSUSB_IP_PW_CTRL_1);
3917 +
3918 + //1. Enable target ports
3919 + for(i=0; i<g_num_u3_port; i++){
3920 + temp = readl(SSUSB_U3_CTRL(i));
3921 + temp = temp & (~SSUSB_U3_PORT_PDN) & (~SSUSB_U3_PORT_DIS);
3922 + writel(temp, SSUSB_U3_CTRL(i));
3923 + }
3924 + for(i=0; i<g_num_u2_port; i++){
3925 + temp = readl(SSUSB_U2_CTRL(i));
3926 + temp = temp & (~SSUSB_U2_PORT_PDN) & (~SSUSB_U2_PORT_DIS);
3927 + writel(temp, SSUSB_U2_CTRL(i));
3928 + }
3929 + msleep(100);
3930 +}
3931 +
3932 +
3933 +//(X)disable clock/power of a port
3934 +//(X)if all ports are disabled, disable IP ctrl power
3935 +//disable all ports and IP clock/power, this is just mention HW that the power/clock of port
3936 +//and IP could be disable if suspended.
3937 +//If doesn't not disable all ports at first, the IP clock/power will never be disabled
3938 +//(some U2 and U3 ports are binded to the same connection, that is, they will never enter suspend at the same time
3939 +//port_index: port number
3940 +//port_rev: 0x2 - USB2.0, 0x3 - USB3.0 (SuperSpeed)
3941 +void disablePortClockPower(void){
3942 + int i;
3943 + u32 temp;
3944 +
3945 + g_num_u3_port = SSUSB_U3_PORT_NUM(readl(SSUSB_IP_CAP));
3946 + g_num_u2_port = SSUSB_U2_PORT_NUM(readl(SSUSB_IP_CAP));
3947 +
3948 + for(i=0; i<g_num_u3_port; i++){
3949 + temp = readl(SSUSB_U3_CTRL(i));
3950 + temp = temp | (SSUSB_U3_PORT_PDN);
3951 + writel(temp, SSUSB_U3_CTRL(i));
3952 + }
3953 + for(i=0; i<g_num_u2_port; i++){
3954 + temp = readl(SSUSB_U2_CTRL(i));
3955 + temp = temp | (SSUSB_U2_PORT_PDN);
3956 + writel(temp, SSUSB_U2_CTRL(i));
3957 + }
3958 + writel(readl(SSUSB_IP_PW_CTRL_1) | (SSUSB_IP_PDN), SSUSB_IP_PW_CTRL_1);
3959 +}
3960 +
3961 +//if IP ctrl power is disabled, enable it
3962 +//enable clock/power of a port
3963 +//port_index: port number
3964 +//port_rev: 0x2 - USB2.0, 0x3 - USB3.0 (SuperSpeed)
3965 +void enablePortClockPower(int port_index, int port_rev){
3966 + int i;
3967 + u32 temp;
3968 +
3969 + writel(readl(SSUSB_IP_PW_CTRL_1) & (~SSUSB_IP_PDN), SSUSB_IP_PW_CTRL_1);
3970 +
3971 + if(port_rev == 0x3){
3972 + temp = readl(SSUSB_U3_CTRL(port_index));
3973 + temp = temp & (~SSUSB_U3_PORT_PDN);
3974 + writel(temp, SSUSB_U3_CTRL(port_index));
3975 + }
3976 + else if(port_rev == 0x2){
3977 + temp = readl(SSUSB_U2_CTRL(port_index));
3978 + temp = temp & (~SSUSB_U2_PORT_PDN);
3979 + writel(temp, SSUSB_U2_CTRL(port_index));
3980 + }
3981 +}
3982 +
3983 --- /dev/null
3984 +++ b/drivers/usb/host/xhci-mtk-power.h
3985 @@ -0,0 +1,13 @@
3986 +#ifndef _XHCI_MTK_POWER_H
3987 +#define _XHCI_MTK_POWER_H
3988 +
3989 +#include <linux/usb.h>
3990 +#include "xhci.h"
3991 +#include "xhci-mtk.h"
3992 +
3993 +void enableXhciAllPortPower(struct xhci_hcd *xhci);
3994 +void enableAllClockPower(void);
3995 +void disablePortClockPower(void);
3996 +void enablePortClockPower(int port_index, int port_rev);
3997 +
3998 +#endif
3999 --- /dev/null
4000 +++ b/drivers/usb/host/xhci-mtk-scheduler.c
4001 @@ -0,0 +1,608 @@
4002 +#include "xhci-mtk-scheduler.h"
4003 +#include <linux/kernel.h> /* printk() */
4004 +
4005 +static struct sch_ep **ss_out_eps[MAX_EP_NUM];
4006 +static struct sch_ep **ss_in_eps[MAX_EP_NUM];
4007 +static struct sch_ep **hs_eps[MAX_EP_NUM]; //including tt isoc
4008 +static struct sch_ep **tt_intr_eps[MAX_EP_NUM];
4009 +
4010 +
4011 +int mtk_xhci_scheduler_init(void){
4012 + int i;
4013 +
4014 + for(i=0; i<MAX_EP_NUM; i++){
4015 + ss_out_eps[i] = NULL;
4016 + }
4017 + for(i=0; i<MAX_EP_NUM; i++){
4018 + ss_in_eps[i] = NULL;
4019 + }
4020 + for(i=0; i<MAX_EP_NUM; i++){
4021 + hs_eps[i] = NULL;
4022 + }
4023 + for(i=0; i<MAX_EP_NUM; i++){
4024 + tt_intr_eps[i] = NULL;
4025 + }
4026 + return 0;
4027 +}
4028 +
4029 +int add_sch_ep(int dev_speed, int is_in, int isTT, int ep_type, int maxp, int interval, int burst
4030 + , int mult, int offset, int repeat, int pkts, int cs_count, int burst_mode
4031 + , int bw_cost, mtk_u32 *ep, struct sch_ep *tmp_ep){
4032 +
4033 + struct sch_ep **ep_array;
4034 + int i;
4035 +
4036 + if(is_in && dev_speed == USB_SPEED_SUPER ){
4037 + ep_array = (struct sch_ep **)ss_in_eps;
4038 + }
4039 + else if(dev_speed == USB_SPEED_SUPER){
4040 + ep_array = (struct sch_ep **)ss_out_eps;
4041 + }
4042 + else if(dev_speed == USB_SPEED_HIGH || (isTT && ep_type == USB_EP_ISOC)){
4043 + ep_array = (struct sch_ep **)hs_eps;
4044 + }
4045 + else{
4046 + ep_array = (struct sch_ep **)tt_intr_eps;
4047 + }
4048 + for(i=0; i<MAX_EP_NUM; i++){
4049 + if(ep_array[i] == NULL){
4050 + tmp_ep->dev_speed = dev_speed;
4051 + tmp_ep->isTT = isTT;
4052 + tmp_ep->is_in = is_in;
4053 + tmp_ep->ep_type = ep_type;
4054 + tmp_ep->maxp = maxp;
4055 + tmp_ep->interval = interval;
4056 + tmp_ep->burst = burst;
4057 + tmp_ep->mult = mult;
4058 + tmp_ep->offset = offset;
4059 + tmp_ep->repeat = repeat;
4060 + tmp_ep->pkts = pkts;
4061 + tmp_ep->cs_count = cs_count;
4062 + tmp_ep->burst_mode = burst_mode;
4063 + tmp_ep->bw_cost = bw_cost;
4064 + tmp_ep->ep = ep;
4065 + ep_array[i] = tmp_ep;
4066 + return SCH_SUCCESS;
4067 + }
4068 + }
4069 + return SCH_FAIL;
4070 +}
4071 +
4072 +int count_ss_bw(int is_in, int ep_type, int maxp, int interval, int burst, int mult, int offset, int repeat
4073 + , int td_size){
4074 + int i, j, k;
4075 + int bw_required[3];
4076 + int final_bw_required;
4077 + int bw_required_per_repeat;
4078 + int tmp_bw_required;
4079 + struct sch_ep *cur_sch_ep;
4080 + struct sch_ep **ep_array;
4081 + int cur_offset;
4082 + int cur_ep_offset;
4083 + int tmp_offset;
4084 + int tmp_interval;
4085 + int ep_offset;
4086 + int ep_interval;
4087 + int ep_repeat;
4088 + int ep_mult;
4089 +
4090 + if(is_in){
4091 + ep_array = (struct sch_ep **)ss_in_eps;
4092 + }
4093 + else{
4094 + ep_array = (struct sch_ep **)ss_out_eps;
4095 + }
4096 +
4097 + bw_required[0] = 0;
4098 + bw_required[1] = 0;
4099 + bw_required[2] = 0;
4100 +
4101 + if(repeat == 0){
4102 + final_bw_required = 0;
4103 + for(i=0; i<MAX_EP_NUM; i++){
4104 + cur_sch_ep = ep_array[i];
4105 + if(cur_sch_ep == NULL){
4106 + continue;
4107 + }
4108 + ep_interval = cur_sch_ep->interval;
4109 + ep_offset = cur_sch_ep->offset;
4110 + if(cur_sch_ep->repeat == 0){
4111 + if(ep_interval >= interval){
4112 + tmp_offset = ep_offset + ep_interval - offset;
4113 + tmp_interval = interval;
4114 + }
4115 + else{
4116 + tmp_offset = offset + interval - ep_offset;
4117 + tmp_interval = ep_interval;
4118 + }
4119 + if(tmp_offset % tmp_interval == 0){
4120 + final_bw_required += cur_sch_ep->bw_cost;
4121 + }
4122 + }
4123 + else{
4124 + ep_repeat = cur_sch_ep->repeat;
4125 + ep_mult = cur_sch_ep->mult;
4126 + for(k=0; k<=ep_mult; k++){
4127 + cur_ep_offset = ep_offset+(k*ep_mult);
4128 + if(ep_interval >= interval){
4129 + tmp_offset = cur_ep_offset + ep_interval - offset;
4130 + tmp_interval = interval;
4131 + }
4132 + else{
4133 + tmp_offset = offset + interval - cur_ep_offset;
4134 + tmp_interval = ep_interval;
4135 + }
4136 + if(tmp_offset % tmp_interval == 0){
4137 + final_bw_required += cur_sch_ep->bw_cost;
4138 + break;
4139 + }
4140 + }
4141 + }
4142 + }
4143 + final_bw_required += td_size;
4144 + }
4145 + else{
4146 + bw_required_per_repeat = maxp * (burst+1);
4147 + for(j=0; j<=mult; j++){
4148 + tmp_bw_required = 0;
4149 + cur_offset = offset+(j*repeat);
4150 + for(i=0; i<MAX_EP_NUM; i++){
4151 + cur_sch_ep = ep_array[i];
4152 + if(cur_sch_ep == NULL){
4153 + continue;
4154 + }
4155 + ep_interval = cur_sch_ep->interval;
4156 + ep_offset = cur_sch_ep->offset;
4157 + if(cur_sch_ep->repeat == 0){
4158 + if(ep_interval >= interval){
4159 + tmp_offset = ep_offset + ep_interval - cur_offset;
4160 + tmp_interval = interval;
4161 + }
4162 + else{
4163 + tmp_offset = cur_offset + interval - ep_offset;
4164 + tmp_interval = ep_interval;
4165 + }
4166 + if(tmp_offset % tmp_interval == 0){
4167 + tmp_bw_required += cur_sch_ep->bw_cost;
4168 + }
4169 + }
4170 + else{
4171 + ep_repeat = cur_sch_ep->repeat;
4172 + ep_mult = cur_sch_ep->mult;
4173 + for(k=0; k<=ep_mult; k++){
4174 + cur_ep_offset = ep_offset+(k*ep_repeat);
4175 + if(ep_interval >= interval){
4176 + tmp_offset = cur_ep_offset + ep_interval - cur_offset;
4177 + tmp_interval = interval;
4178 + }
4179 + else{
4180 + tmp_offset = cur_offset + interval - cur_ep_offset;
4181 + tmp_interval = ep_interval;
4182 + }
4183 + if(tmp_offset % tmp_interval == 0){
4184 + tmp_bw_required += cur_sch_ep->bw_cost;
4185 + break;
4186 + }
4187 + }
4188 + }
4189 + }
4190 + bw_required[j] = tmp_bw_required;
4191 + }
4192 + final_bw_required = SS_BW_BOUND;
4193 + for(j=0; j<=mult; j++){
4194 + if(bw_required[j] < final_bw_required){
4195 + final_bw_required = bw_required[j];
4196 + }
4197 + }
4198 + final_bw_required += bw_required_per_repeat;
4199 + }
4200 + return final_bw_required;
4201 +}
4202 +
4203 +int count_hs_bw(int ep_type, int maxp, int interval, int offset, int td_size){
4204 + int i;
4205 + int bw_required;
4206 + struct sch_ep *cur_sch_ep;
4207 + int tmp_offset;
4208 + int tmp_interval;
4209 + int ep_offset;
4210 + int ep_interval;
4211 + int cur_tt_isoc_interval; //for isoc tt check
4212 +
4213 + bw_required = 0;
4214 + for(i=0; i<MAX_EP_NUM; i++){
4215 +
4216 + cur_sch_ep = (struct sch_ep *)hs_eps[i];
4217 + if(cur_sch_ep == NULL){
4218 + continue;
4219 + }
4220 + ep_offset = cur_sch_ep->offset;
4221 + ep_interval = cur_sch_ep->interval;
4222 +
4223 + if(cur_sch_ep->isTT && cur_sch_ep->ep_type == USB_EP_ISOC){
4224 + cur_tt_isoc_interval = ep_interval<<3;
4225 + if(ep_interval >= interval){
4226 + tmp_offset = ep_offset + cur_tt_isoc_interval - offset;
4227 + tmp_interval = interval;
4228 + }
4229 + else{
4230 + tmp_offset = offset + interval - ep_offset;
4231 + tmp_interval = cur_tt_isoc_interval;
4232 + }
4233 + if(cur_sch_ep->is_in){
4234 + if((tmp_offset%tmp_interval >=2) && (tmp_offset%tmp_interval <= cur_sch_ep->cs_count)){
4235 + bw_required += 188;
4236 + }
4237 + }
4238 + else{
4239 + if(tmp_offset%tmp_interval <= cur_sch_ep->cs_count){
4240 + bw_required += 188;
4241 + }
4242 + }
4243 + }
4244 + else{
4245 + if(ep_interval >= interval){
4246 + tmp_offset = ep_offset + ep_interval - offset;
4247 + tmp_interval = interval;
4248 + }
4249 + else{
4250 + tmp_offset = offset + interval - ep_offset;
4251 + tmp_interval = ep_interval;
4252 + }
4253 + if(tmp_offset%tmp_interval == 0){
4254 + bw_required += cur_sch_ep->bw_cost;
4255 + }
4256 + }
4257 + }
4258 + bw_required += td_size;
4259 + return bw_required;
4260 +}
4261 +
4262 +int count_tt_isoc_bw(int is_in, int maxp, int interval, int offset, int td_size){
4263 + char is_cs;
4264 + int mframe_idx, frame_idx, s_frame, s_mframe, cur_mframe;
4265 + int bw_required, max_bw;
4266 + int ss_cs_count;
4267 + int cs_mframe;
4268 + int max_frame;
4269 + int i,j;
4270 + struct sch_ep *cur_sch_ep;
4271 + int ep_offset;
4272 + int ep_interval;
4273 + int ep_cs_count;
4274 + int tt_isoc_interval; //for isoc tt check
4275 + int cur_tt_isoc_interval; //for isoc tt check
4276 + int tmp_offset;
4277 + int tmp_interval;
4278 +
4279 + is_cs = 0;
4280 +
4281 + tt_isoc_interval = interval<<3; //frame to mframe
4282 + if(is_in){
4283 + is_cs = 1;
4284 + }
4285 + s_frame = offset/8;
4286 + s_mframe = offset%8;
4287 + ss_cs_count = (maxp + (188 - 1))/188;
4288 + if(is_cs){
4289 + cs_mframe = offset%8 + 2 + ss_cs_count;
4290 + if (cs_mframe <= 6)
4291 + ss_cs_count += 2;
4292 + else if (cs_mframe == 7)
4293 + ss_cs_count++;
4294 + else if (cs_mframe > 8)
4295 + return -1;
4296 + }
4297 + max_bw = 0;
4298 + if(is_in){
4299 + i=2;
4300 + }
4301 + for(cur_mframe = offset+i; i<ss_cs_count; cur_mframe++, i++){
4302 + bw_required = 0;
4303 + for(j=0; j<MAX_EP_NUM; j++){
4304 + cur_sch_ep = (struct sch_ep *)hs_eps[j];
4305 + if(cur_sch_ep == NULL){
4306 + continue;
4307 + }
4308 + ep_offset = cur_sch_ep->offset;
4309 + ep_interval = cur_sch_ep->interval;
4310 + if(cur_sch_ep->isTT && cur_sch_ep->ep_type == USB_EP_ISOC){
4311 + //isoc tt
4312 + //check if mframe offset overlap
4313 + //if overlap, add 188 to the bw
4314 + cur_tt_isoc_interval = ep_interval<<3;
4315 + if(cur_tt_isoc_interval >= tt_isoc_interval){
4316 + tmp_offset = (ep_offset+cur_tt_isoc_interval) - cur_mframe;
4317 + tmp_interval = tt_isoc_interval;
4318 + }
4319 + else{
4320 + tmp_offset = (cur_mframe+tt_isoc_interval) - ep_offset;
4321 + tmp_interval = cur_tt_isoc_interval;
4322 + }
4323 + if(cur_sch_ep->is_in){
4324 + if((tmp_offset%tmp_interval >=2) && (tmp_offset%tmp_interval <= cur_sch_ep->cs_count)){
4325 + bw_required += 188;
4326 + }
4327 + }
4328 + else{
4329 + if(tmp_offset%tmp_interval <= cur_sch_ep->cs_count){
4330 + bw_required += 188;
4331 + }
4332 + }
4333 +
4334 + }
4335 + else if(cur_sch_ep->ep_type == USB_EP_INT || cur_sch_ep->ep_type == USB_EP_ISOC){
4336 + //check if mframe
4337 + if(ep_interval >= tt_isoc_interval){
4338 + tmp_offset = (ep_offset+ep_interval) - cur_mframe;
4339 + tmp_interval = tt_isoc_interval;
4340 + }
4341 + else{
4342 + tmp_offset = (cur_mframe+tt_isoc_interval) - ep_offset;
4343 + tmp_interval = ep_interval;
4344 + }
4345 + if(tmp_offset%tmp_interval == 0){
4346 + bw_required += cur_sch_ep->bw_cost;
4347 + }
4348 + }
4349 + }
4350 + bw_required += 188;
4351 + if(bw_required > max_bw){
4352 + max_bw = bw_required;
4353 + }
4354 + }
4355 + return max_bw;
4356 +}
4357 +
4358 +int count_tt_intr_bw(int interval, int frame_offset){
4359 + //check all eps in tt_intr_eps
4360 + int ret;
4361 + int i,j;
4362 + int ep_offset;
4363 + int ep_interval;
4364 + int tmp_offset;
4365 + int tmp_interval;
4366 + ret = SCH_SUCCESS;
4367 + struct sch_ep *cur_sch_ep;
4368 +
4369 + for(i=0; i<MAX_EP_NUM; i++){
4370 + cur_sch_ep = (struct sch_ep *)tt_intr_eps[i];
4371 + if(cur_sch_ep == NULL){
4372 + continue;
4373 + }
4374 + ep_offset = cur_sch_ep->offset;
4375 + ep_interval = cur_sch_ep->interval;
4376 + if(ep_interval >= interval){
4377 + tmp_offset = ep_offset + ep_interval - frame_offset;
4378 + tmp_interval = interval;
4379 + }
4380 + else{
4381 + tmp_offset = frame_offset + interval - ep_offset;
4382 + tmp_interval = ep_interval;
4383 + }
4384 +
4385 + if(tmp_offset%tmp_interval==0){
4386 + return SCH_FAIL;
4387 + }
4388 + }
4389 + return SCH_SUCCESS;
4390 +}
4391 +
4392 +struct sch_ep * mtk_xhci_scheduler_remove_ep(int dev_speed, int is_in, int isTT, int ep_type, mtk_u32 *ep){
4393 + int i;
4394 + struct sch_ep **ep_array;
4395 + struct sch_ep *cur_ep;
4396 +
4397 + if (is_in && dev_speed == USB_SPEED_SUPER) {
4398 + ep_array = (struct sch_ep **)ss_in_eps;
4399 + }
4400 + else if (dev_speed == USB_SPEED_SUPER) {
4401 + ep_array = (struct sch_ep **)ss_out_eps;
4402 + }
4403 + else if (dev_speed == USB_SPEED_HIGH || (isTT && ep_type == USB_EP_ISOC)) {
4404 + ep_array = (struct sch_ep **)hs_eps;
4405 + }
4406 + else {
4407 + ep_array = (struct sch_ep **)tt_intr_eps;
4408 + }
4409 + for (i = 0; i < MAX_EP_NUM; i++) {
4410 + cur_ep = (struct sch_ep *)ep_array[i];
4411 + if(cur_ep != NULL && cur_ep->ep == ep){
4412 + ep_array[i] = NULL;
4413 + return cur_ep;
4414 + }
4415 + }
4416 + return NULL;
4417 +}
4418 +
4419 +int mtk_xhci_scheduler_add_ep(int dev_speed, int is_in, int isTT, int ep_type, int maxp, int interval, int burst
4420 + , int mult, mtk_u32 *ep, mtk_u32 *ep_ctx, struct sch_ep *sch_ep){
4421 + mtk_u32 bPkts = 0;
4422 + mtk_u32 bCsCount = 0;
4423 + mtk_u32 bBm = 1;
4424 + mtk_u32 bOffset = 0;
4425 + mtk_u32 bRepeat = 0;
4426 + int ret;
4427 + struct mtk_xhci_ep_ctx *temp_ep_ctx;
4428 + int td_size;
4429 + int mframe_idx, frame_idx;
4430 + int bw_cost;
4431 + int cur_bw, best_bw, best_bw_idx,repeat, max_repeat, best_bw_repeat;
4432 + int cur_offset, cs_mframe;
4433 + int break_out;
4434 + int frame_interval;
4435 +
4436 + printk(KERN_ERR "add_ep parameters, dev_speed %d, is_in %d, isTT %d, ep_type %d, maxp %d, interval %d, burst %d, mult %d, ep 0x%x, ep_ctx 0x%x, sch_ep 0x%x\n", dev_speed, is_in, isTT, ep_type, maxp
4437 + , interval, burst, mult, ep, ep_ctx, sch_ep);
4438 + if(isTT && ep_type == USB_EP_INT && ((dev_speed == USB_SPEED_LOW) || (dev_speed == USB_SPEED_FULL))){
4439 + frame_interval = interval >> 3;
4440 + for(frame_idx=0; frame_idx<frame_interval; frame_idx++){
4441 + printk(KERN_ERR "check tt_intr_bw interval %d, frame_idx %d\n", frame_interval, frame_idx);
4442 + if(count_tt_intr_bw(frame_interval, frame_idx) == SCH_SUCCESS){
4443 + printk(KERN_ERR "check OK............\n");
4444 + bOffset = frame_idx<<3;
4445 + bPkts = 1;
4446 + bCsCount = 3;
4447 + bw_cost = maxp;
4448 + bRepeat = 0;
4449 + if(add_sch_ep(dev_speed, is_in, isTT, ep_type, maxp, frame_interval, burst, mult
4450 + , bOffset, bRepeat, bPkts, bCsCount, bBm, maxp, ep, sch_ep) == SCH_FAIL){
4451 + return SCH_FAIL;
4452 + }
4453 + ret = SCH_SUCCESS;
4454 + break;
4455 + }
4456 + }
4457 + }
4458 + else if(isTT && ep_type == USB_EP_ISOC){
4459 + best_bw = HS_BW_BOUND;
4460 + best_bw_idx = -1;
4461 + cur_bw = 0;
4462 + td_size = maxp;
4463 + break_out = 0;
4464 + frame_interval = interval>>3;
4465 + for(frame_idx=0; frame_idx<frame_interval && !break_out; frame_idx++){
4466 + for(mframe_idx=0; mframe_idx<8; mframe_idx++){
4467 + cur_offset = (frame_idx*8) + mframe_idx;
4468 + cur_bw = count_tt_isoc_bw(is_in, maxp, frame_interval, cur_offset, td_size);
4469 + if(cur_bw > 0 && cur_bw < best_bw){
4470 + best_bw_idx = cur_offset;
4471 + best_bw = cur_bw;
4472 + if(cur_bw == td_size || cur_bw < (HS_BW_BOUND>>1)){
4473 + break_out = 1;
4474 + break;
4475 + }
4476 + }
4477 + }
4478 + }
4479 + if(best_bw_idx == -1){
4480 + return SCH_FAIL;
4481 + }
4482 + else{
4483 + bOffset = best_bw_idx;
4484 + bPkts = 1;
4485 + bCsCount = (maxp + (188 - 1)) / 188;
4486 + if(is_in){
4487 + cs_mframe = bOffset%8 + 2 + bCsCount;
4488 + if (cs_mframe <= 6)
4489 + bCsCount += 2;
4490 + else if (cs_mframe == 7)
4491 + bCsCount++;
4492 + }
4493 + bw_cost = 188;
4494 + bRepeat = 0;
4495 + if(add_sch_ep( dev_speed, is_in, isTT, ep_type, maxp, interval, burst, mult
4496 + , bOffset, bRepeat, bPkts, bCsCount, bBm, bw_cost, ep, sch_ep) == SCH_FAIL){
4497 + return SCH_FAIL;
4498 + }
4499 + ret = SCH_SUCCESS;
4500 + }
4501 + }
4502 + else if((dev_speed == USB_SPEED_FULL || dev_speed == USB_SPEED_LOW) && ep_type == USB_EP_INT){
4503 + bPkts = 1;
4504 + ret = SCH_SUCCESS;
4505 + }
4506 + else if(dev_speed == USB_SPEED_FULL && ep_type == USB_EP_ISOC){
4507 + bPkts = 1;
4508 + ret = SCH_SUCCESS;
4509 + }
4510 + else if(dev_speed == USB_SPEED_HIGH && (ep_type == USB_EP_INT || ep_type == USB_EP_ISOC)){
4511 + best_bw = HS_BW_BOUND;
4512 + best_bw_idx = -1;
4513 + cur_bw = 0;
4514 + td_size = maxp*(burst+1);
4515 + for(cur_offset = 0; cur_offset<interval; cur_offset++){
4516 + cur_bw = count_hs_bw(ep_type, maxp, interval, cur_offset, td_size);
4517 + if(cur_bw > 0 && cur_bw < best_bw){
4518 + best_bw_idx = cur_offset;
4519 + best_bw = cur_bw;
4520 + if(cur_bw == td_size || cur_bw < (HS_BW_BOUND>>1)){
4521 + break;
4522 + }
4523 + }
4524 + }
4525 + if(best_bw_idx == -1){
4526 + return SCH_FAIL;
4527 + }
4528 + else{
4529 + bOffset = best_bw_idx;
4530 + bPkts = burst + 1;
4531 + bCsCount = 0;
4532 + bw_cost = td_size;
4533 + bRepeat = 0;
4534 + if(add_sch_ep(dev_speed, is_in, isTT, ep_type, maxp, interval, burst, mult
4535 + , bOffset, bRepeat, bPkts, bCsCount, bBm, bw_cost, ep, sch_ep) == SCH_FAIL){
4536 + return SCH_FAIL;
4537 + }
4538 + ret = SCH_SUCCESS;
4539 + }
4540 + }
4541 + else if(dev_speed == USB_SPEED_SUPER && (ep_type == USB_EP_INT || ep_type == USB_EP_ISOC)){
4542 + best_bw = SS_BW_BOUND;
4543 + best_bw_idx = -1;
4544 + cur_bw = 0;
4545 + td_size = maxp * (mult+1) * (burst+1);
4546 + if(mult == 0){
4547 + max_repeat = 0;
4548 + }
4549 + else{
4550 + max_repeat = (interval-1)/(mult+1);
4551 + }
4552 + break_out = 0;
4553 + for(frame_idx = 0; (frame_idx < interval) && !break_out; frame_idx++){
4554 + for(repeat = max_repeat; repeat >= 0; repeat--){
4555 + cur_bw = count_ss_bw(is_in, ep_type, maxp, interval, burst, mult, frame_idx
4556 + , repeat, td_size);
4557 + printk(KERN_ERR "count_ss_bw, frame_idx %d, repeat %d, td_size %d, result bw %d\n"
4558 + , frame_idx, repeat, td_size, cur_bw);
4559 + if(cur_bw > 0 && cur_bw < best_bw){
4560 + best_bw_idx = frame_idx;
4561 + best_bw_repeat = repeat;
4562 + best_bw = cur_bw;
4563 + if(cur_bw <= td_size || cur_bw < (HS_BW_BOUND>>1)){
4564 + break_out = 1;
4565 + break;
4566 + }
4567 + }
4568 + }
4569 + }
4570 + printk(KERN_ERR "final best idx %d, best repeat %d\n", best_bw_idx, best_bw_repeat);
4571 + if(best_bw_idx == -1){
4572 + return SCH_FAIL;
4573 + }
4574 + else{
4575 + bOffset = best_bw_idx;
4576 + bCsCount = 0;
4577 + bRepeat = best_bw_repeat;
4578 + if(bRepeat == 0){
4579 + bw_cost = (burst+1)*(mult+1)*maxp;
4580 + bPkts = (burst+1)*(mult+1);
4581 + }
4582 + else{
4583 + bw_cost = (burst+1)*maxp;
4584 + bPkts = (burst+1);
4585 + }
4586 + if(add_sch_ep(dev_speed, is_in, isTT, ep_type, maxp, interval, burst, mult
4587 + , bOffset, bRepeat, bPkts, bCsCount, bBm, bw_cost, ep, sch_ep) == SCH_FAIL){
4588 + return SCH_FAIL;
4589 + }
4590 + ret = SCH_SUCCESS;
4591 + }
4592 + }
4593 + else{
4594 + bPkts = 1;
4595 + ret = SCH_SUCCESS;
4596 + }
4597 + if(ret == SCH_SUCCESS){
4598 + temp_ep_ctx = (struct mtk_xhci_ep_ctx *)ep_ctx;
4599 + temp_ep_ctx->reserved[0] |= (BPKTS(bPkts) | BCSCOUNT(bCsCount) | BBM(bBm));
4600 + temp_ep_ctx->reserved[1] |= (BOFFSET(bOffset) | BREPEAT(bRepeat));
4601 +
4602 + printk(KERN_DEBUG "[DBG] BPKTS: %x, BCSCOUNT: %x, BBM: %x\n", bPkts, bCsCount, bBm);
4603 + printk(KERN_DEBUG "[DBG] BOFFSET: %x, BREPEAT: %x\n", bOffset, bRepeat);
4604 + return SCH_SUCCESS;
4605 + }
4606 + else{
4607 + return SCH_FAIL;
4608 + }
4609 +}
4610 --- /dev/null
4611 +++ b/drivers/usb/host/xhci-mtk-scheduler.h
4612 @@ -0,0 +1,77 @@
4613 +#ifndef _XHCI_MTK_SCHEDULER_H
4614 +#define _XHCI_MTK_SCHEDULER_H
4615 +
4616 +#define MTK_SCH_NEW 1
4617 +
4618 +#define SCH_SUCCESS 1
4619 +#define SCH_FAIL 0
4620 +
4621 +#define MAX_EP_NUM 64
4622 +#define SS_BW_BOUND 51000
4623 +#define HS_BW_BOUND 6144
4624 +
4625 +#define USB_EP_CONTROL 0
4626 +#define USB_EP_ISOC 1
4627 +#define USB_EP_BULK 2
4628 +#define USB_EP_INT 3
4629 +
4630 +#define USB_SPEED_LOW 1
4631 +#define USB_SPEED_FULL 2
4632 +#define USB_SPEED_HIGH 3
4633 +#define USB_SPEED_SUPER 5
4634 +
4635 +/* mtk scheduler bitmasks */
4636 +#define BPKTS(p) ((p) & 0x3f)
4637 +#define BCSCOUNT(p) (((p) & 0x7) << 8)
4638 +#define BBM(p) ((p) << 11)
4639 +#define BOFFSET(p) ((p) & 0x3fff)
4640 +#define BREPEAT(p) (((p) & 0x7fff) << 16)
4641 +
4642 +
4643 +#if 1
4644 +typedef unsigned int mtk_u32;
4645 +typedef unsigned long long mtk_u64;
4646 +#endif
4647 +
4648 +#define NULL ((void *)0)
4649 +
4650 +struct mtk_xhci_ep_ctx {
4651 + mtk_u32 ep_info;
4652 + mtk_u32 ep_info2;
4653 + mtk_u64 deq;
4654 + mtk_u32 tx_info;
4655 + /* offset 0x14 - 0x1f reserved for HC internal use */
4656 + mtk_u32 reserved[3];
4657 +};
4658 +
4659 +
4660 +struct sch_ep
4661 +{
4662 + //device info
4663 + int dev_speed;
4664 + int isTT;
4665 + //ep info
4666 + int is_in;
4667 + int ep_type;
4668 + int maxp;
4669 + int interval;
4670 + int burst;
4671 + int mult;
4672 + //scheduling info
4673 + int offset;
4674 + int repeat;
4675 + int pkts;
4676 + int cs_count;
4677 + int burst_mode;
4678 + //other
4679 + int bw_cost; //bandwidth cost in each repeat; including overhead
4680 + mtk_u32 *ep; //address of usb_endpoint pointer
4681 +};
4682 +
4683 +int mtk_xhci_scheduler_init(void);
4684 +int mtk_xhci_scheduler_add_ep(int dev_speed, int is_in, int isTT, int ep_type, int maxp, int interval, int burst
4685 + , int mult, mtk_u32 *ep, mtk_u32 *ep_ctx, struct sch_ep *sch_ep);
4686 +struct sch_ep * mtk_xhci_scheduler_remove_ep(int dev_speed, int is_in, int isTT, int ep_type, mtk_u32 *ep);
4687 +
4688 +
4689 +#endif
4690 --- /dev/null
4691 +++ b/drivers/usb/host/xhci-mtk.c
4692 @@ -0,0 +1,265 @@
4693 +#include "xhci-mtk.h"
4694 +#include "xhci-mtk-power.h"
4695 +#include "xhci.h"
4696 +#include "mtk-phy.h"
4697 +#ifdef CONFIG_C60802_SUPPORT
4698 +#include "mtk-phy-c60802.h"
4699 +#endif
4700 +#include "xhci-mtk-scheduler.h"
4701 +#include <linux/kernel.h> /* printk() */
4702 +#include <linux/slab.h>
4703 +#include <linux/delay.h>
4704 +#include <asm/uaccess.h>
4705 +#include <linux/dma-mapping.h>
4706 +#include <linux/platform_device.h>
4707 +
4708 +void setInitialReg(void )
4709 +{
4710 + __u32 __iomem *addr;
4711 + u32 temp;
4712 +
4713 + /* set SSUSB DMA burst size to 128B */
4714 + addr = SSUSB_U3_XHCI_BASE + SSUSB_HDMA_CFG;
4715 + temp = SSUSB_HDMA_CFG_MT7621_VALUE;
4716 + writel(temp, addr);
4717 +
4718 + /* extend U3 LTSSM Polling.LFPS timeout value */
4719 + addr = SSUSB_U3_XHCI_BASE + U3_LTSSM_TIMING_PARAMETER3;
4720 + temp = U3_LTSSM_TIMING_PARAMETER3_VALUE;
4721 + writel(temp, addr);
4722 +
4723 + /* EOF */
4724 + addr = SSUSB_U3_XHCI_BASE + SYNC_HS_EOF;
4725 + temp = SYNC_HS_EOF_VALUE;
4726 + writel(temp, addr);
4727 +
4728 +#if defined (CONFIG_PERIODIC_ENP)
4729 + /* HSCH_CFG1: SCH2_FIFO_DEPTH */
4730 + addr = SSUSB_U3_XHCI_BASE + HSCH_CFG1;
4731 + temp = readl(addr);
4732 + temp &= ~(0x3 << SCH2_FIFO_DEPTH_OFFSET);
4733 + writel(temp, addr);
4734 +#endif
4735 +
4736 + /* Doorbell handling */
4737 + addr = SIFSLV_IPPC + SSUSB_IP_SPAR0;
4738 + temp = 0x1;
4739 + writel(temp, addr);
4740 +
4741 + /* Set SW PLL Stable mode to 1 for U2 LPM device remote wakeup */
4742 + /* Port 0 */
4743 + addr = U2_PHY_BASE + U2_PHYD_CR1;
4744 + temp = readl(addr);
4745 + temp &= ~(0x3 << 18);
4746 + temp |= (1 << 18);
4747 + writel(temp, addr);
4748 +
4749 + /* Port 1 */
4750 + addr = U2_PHY_BASE_P1 + U2_PHYD_CR1;
4751 + temp = readl(addr);
4752 + temp &= ~(0x3 << 18);
4753 + temp |= (1 << 18);
4754 + writel(temp, addr);
4755 +}
4756 +
4757 +
4758 +void setLatchSel(void){
4759 + __u32 __iomem *latch_sel_addr;
4760 + u32 latch_sel_value;
4761 + latch_sel_addr = U3_PIPE_LATCH_SEL_ADD;
4762 + latch_sel_value = ((U3_PIPE_LATCH_TX)<<2) | (U3_PIPE_LATCH_RX);
4763 + writel(latch_sel_value, latch_sel_addr);
4764 +}
4765 +
4766 +void reinitIP(void){
4767 + __u32 __iomem *ip_reset_addr;
4768 + u32 ip_reset_value;
4769 +
4770 + enableAllClockPower();
4771 + mtk_xhci_scheduler_init();
4772 +}
4773 +
4774 +void dbg_prb_out(void){
4775 + mtk_probe_init(0x0f0f0f0f);
4776 + mtk_probe_out(0xffffffff);
4777 + mtk_probe_out(0x01010101);
4778 + mtk_probe_out(0x02020202);
4779 + mtk_probe_out(0x04040404);
4780 + mtk_probe_out(0x08080808);
4781 + mtk_probe_out(0x10101010);
4782 + mtk_probe_out(0x20202020);
4783 + mtk_probe_out(0x40404040);
4784 + mtk_probe_out(0x80808080);
4785 + mtk_probe_out(0x55555555);
4786 + mtk_probe_out(0xaaaaaaaa);
4787 +}
4788 +
4789 +
4790 +
4791 +///////////////////////////////////////////////////////////////////////////////
4792 +
4793 +#define RET_SUCCESS 0
4794 +#define RET_FAIL 1
4795 +
4796 +static int dbg_u3w(int argc, char**argv)
4797 +{
4798 + int u4TimingValue;
4799 + char u1TimingValue;
4800 + int u4TimingAddress;
4801 +
4802 + if (argc<3)
4803 + {
4804 + printk(KERN_ERR "Arg: address value\n");
4805 + return RET_FAIL;
4806 + }
4807 + u3phy_init();
4808 +
4809 + u4TimingAddress = (int)simple_strtol(argv[1], &argv[1], 16);
4810 + u4TimingValue = (int)simple_strtol(argv[2], &argv[2], 16);
4811 + u1TimingValue = u4TimingValue & 0xff;
4812 + /* access MMIO directly */
4813 + writel(u1TimingValue, u4TimingAddress);
4814 + printk(KERN_ERR "Write done\n");
4815 + return RET_SUCCESS;
4816 +
4817 +}
4818 +
4819 +static int dbg_u3r(int argc, char**argv)
4820 +{
4821 + char u1ReadTimingValue;
4822 + int u4TimingAddress;
4823 + if (argc<2)
4824 + {
4825 + printk(KERN_ERR "Arg: address\n");
4826 + return 0;
4827 + }
4828 + u3phy_init();
4829 + mdelay(500);
4830 + u4TimingAddress = (int)simple_strtol(argv[1], &argv[1], 16);
4831 + /* access MMIO directly */
4832 + u1ReadTimingValue = readl(u4TimingAddress);
4833 + printk(KERN_ERR "Value = 0x%x\n", u1ReadTimingValue);
4834 + return 0;
4835 +}
4836 +
4837 +static int dbg_u3init(int argc, char**argv)
4838 +{
4839 + int ret;
4840 + ret = u3phy_init();
4841 + printk(KERN_ERR "phy registers and operations initial done\n");
4842 + if(u3phy_ops->u2_slew_rate_calibration){
4843 + u3phy_ops->u2_slew_rate_calibration(u3phy);
4844 + }
4845 + else{
4846 + printk(KERN_ERR "WARN: PHY doesn't implement u2 slew rate calibration function\n");
4847 + }
4848 + if(u3phy_ops->init(u3phy) == PHY_TRUE)
4849 + return RET_SUCCESS;
4850 + return RET_FAIL;
4851 +}
4852 +
4853 +void dbg_setU1U2(int argc, char**argv){
4854 + struct xhci_hcd *xhci;
4855 + int u1_value;
4856 + int u2_value;
4857 + u32 port_id, temp;
4858 + u32 __iomem *addr;
4859 +
4860 + if (argc<3)
4861 + {
4862 + printk(KERN_ERR "Arg: u1value u2value\n");
4863 + return RET_FAIL;
4864 + }
4865 +
4866 + u1_value = (int)simple_strtol(argv[1], &argv[1], 10);
4867 + u2_value = (int)simple_strtol(argv[2], &argv[2], 10);
4868 + addr = (SSUSB_U3_XHCI_BASE + 0x424);
4869 + temp = readl(addr);
4870 + temp = temp & (~(0x0000ffff));
4871 + temp = temp | u1_value | (u2_value<<8);
4872 + writel(temp, addr);
4873 +}
4874 +///////////////////////////////////////////////////////////////////////////////
4875 +
4876 +int call_function(char *buf)
4877 +{
4878 + int i;
4879 + int argc;
4880 + char *argv[80];
4881 +
4882 + argc = 0;
4883 + do
4884 + {
4885 + argv[argc] = strsep(&buf, " ");
4886 + printk(KERN_DEBUG "[%d] %s\r\n", argc, argv[argc]);
4887 + argc++;
4888 + } while (buf);
4889 + if (!strcmp("dbg.r", argv[0]))
4890 + dbg_prb_out();
4891 + else if (!strcmp("dbg.u3w", argv[0]))
4892 + dbg_u3w(argc, argv);
4893 + else if (!strcmp("dbg.u3r", argv[0]))
4894 + dbg_u3r(argc, argv);
4895 + else if (!strcmp("dbg.u3i", argv[0]))
4896 + dbg_u3init(argc, argv);
4897 + else if (!strcmp("pw.u1u2", argv[0]))
4898 + dbg_setU1U2(argc, argv);
4899 + return 0;
4900 +}
4901 +
4902 +long xhci_mtk_test_unlock_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
4903 +{
4904 + char w_buf[200];
4905 + char r_buf[200] = "this is a test";
4906 + int len = 200;
4907 +
4908 + switch (cmd) {
4909 + case IOCTL_READ:
4910 + copy_to_user((char *) arg, r_buf, len);
4911 + printk(KERN_DEBUG "IOCTL_READ: %s\r\n", r_buf);
4912 + break;
4913 + case IOCTL_WRITE:
4914 + copy_from_user(w_buf, (char *) arg, len);
4915 + printk(KERN_DEBUG "IOCTL_WRITE: %s\r\n", w_buf);
4916 +
4917 + //invoke function
4918 + return call_function(w_buf);
4919 + break;
4920 + default:
4921 + return -ENOTTY;
4922 + }
4923 +
4924 + return len;
4925 +}
4926 +
4927 +int xhci_mtk_test_open(struct inode *inode, struct file *file)
4928 +{
4929 +
4930 + printk(KERN_DEBUG "xhci_mtk_test open: successful\n");
4931 + return 0;
4932 +}
4933 +
4934 +int xhci_mtk_test_release(struct inode *inode, struct file *file)
4935 +{
4936 +
4937 + printk(KERN_DEBUG "xhci_mtk_test release: successful\n");
4938 + return 0;
4939 +}
4940 +
4941 +ssize_t xhci_mtk_test_read(struct file *file, char *buf, size_t count, loff_t *ptr)
4942 +{
4943 +
4944 + printk(KERN_DEBUG "xhci_mtk_test read: returning zero bytes\n");
4945 + return 0;
4946 +}
4947 +
4948 +ssize_t xhci_mtk_test_write(struct file *file, const char *buf, size_t count, loff_t * ppos)
4949 +{
4950 +
4951 + printk(KERN_DEBUG "xhci_mtk_test write: accepting zero bytes\n");
4952 + return 0;
4953 +}
4954 +
4955 +
4956 +
4957 +
4958 --- /dev/null
4959 +++ b/drivers/usb/host/xhci-mtk.h
4960 @@ -0,0 +1,120 @@
4961 +#ifndef _XHCI_MTK_H
4962 +#define _XHCI_MTK_H
4963 +
4964 +#include <linux/usb.h>
4965 +#include "xhci.h"
4966 +
4967 +#define SSUSB_U3_XHCI_BASE 0xBE1C0000
4968 +#define SSUSB_U3_MAC_BASE 0xBE1C2400
4969 +#define SSUSB_U3_SYS_BASE 0xBE1C2600
4970 +#define SSUSB_U2_SYS_BASE 0xBE1C3400
4971 +#define SSUB_SIF_SLV_TOP 0xBE1D0000
4972 +#define SIFSLV_IPPC (SSUB_SIF_SLV_TOP + 0x700)
4973 +
4974 +#define U3_PIPE_LATCH_SEL_ADD SSUSB_U3_MAC_BASE + 0x130
4975 +#define U3_PIPE_LATCH_TX 0
4976 +#define U3_PIPE_LATCH_RX 0
4977 +
4978 +#define U3_UX_EXIT_LFPS_TIMING_PAR 0xa0
4979 +#define U3_REF_CK_PAR 0xb0
4980 +#define U3_RX_UX_EXIT_LFPS_REF_OFFSET 8
4981 +#define U3_RX_UX_EXIT_LFPS_REF 3
4982 +#define U3_REF_CK_VAL 10
4983 +
4984 +#define U3_TIMING_PULSE_CTRL 0xb4
4985 +#define CNT_1US_VALUE 63 //62.5MHz:63, 70MHz:70, 80MHz:80, 100MHz:100, 125MHz:125
4986 +
4987 +#define USB20_TIMING_PARAMETER 0x40
4988 +#define TIME_VALUE_1US 63 //62.5MHz:63, 80MHz:80, 100MHz:100, 125MHz:125
4989 +
4990 +#define LINK_PM_TIMER 0x8
4991 +#define PM_LC_TIMEOUT_VALUE 3
4992 +
4993 +#define XHCI_IMOD 0x624
4994 +#define XHCI_IMOD_MT7621_VALUE 0x10
4995 +
4996 +#define SSUSB_HDMA_CFG 0x950
4997 +#define SSUSB_HDMA_CFG_MT7621_VALUE 0x10E0E0C
4998 +
4999 +#define U3_LTSSM_TIMING_PARAMETER3 0x2514
5000 +#define U3_LTSSM_TIMING_PARAMETER3_VALUE 0x3E8012C
5001 +
5002 +#define U2_PHYD_CR1 0x64
5003 +
5004 +#define SSUSB_IP_SPAR0 0xC8
5005 +
5006 +#define SYNC_HS_EOF 0x938
5007 +#define SYNC_HS_EOF_VALUE 0x201F3
5008 +
5009 +#define HSCH_CFG1 0x960
5010 +#define SCH2_FIFO_DEPTH_OFFSET 16
5011 +
5012 +
5013 +#define SSUSB_IP_PW_CTRL (SIFSLV_IPPC+0x0)
5014 +#define SSUSB_IP_SW_RST (1<<0)
5015 +#define SSUSB_IP_PW_CTRL_1 (SIFSLV_IPPC+0x4)
5016 +#define SSUSB_IP_PDN (1<<0)
5017 +#define SSUSB_U3_CTRL(p) (SIFSLV_IPPC+0x30+(p*0x08))
5018 +#define SSUSB_U3_PORT_DIS (1<<0)
5019 +#define SSUSB_U3_PORT_PDN (1<<1)
5020 +#define SSUSB_U3_PORT_HOST_SEL (1<<2)
5021 +#define SSUSB_U3_PORT_CKBG_EN (1<<3)
5022 +#define SSUSB_U3_PORT_MAC_RST (1<<4)
5023 +#define SSUSB_U3_PORT_PHYD_RST (1<<5)
5024 +#define SSUSB_U2_CTRL(p) (SIFSLV_IPPC+(0x50)+(p*0x08))
5025 +#define SSUSB_U2_PORT_DIS (1<<0)
5026 +#define SSUSB_U2_PORT_PDN (1<<1)
5027 +#define SSUSB_U2_PORT_HOST_SEL (1<<2)
5028 +#define SSUSB_U2_PORT_CKBG_EN (1<<3)
5029 +#define SSUSB_U2_PORT_MAC_RST (1<<4)
5030 +#define SSUSB_U2_PORT_PHYD_RST (1<<5)
5031 +#define SSUSB_IP_CAP (SIFSLV_IPPC+0x024)
5032 +
5033 +#define SSUSB_U3_PORT_NUM(p) (p & 0xff)
5034 +#define SSUSB_U2_PORT_NUM(p) ((p>>8) & 0xff)
5035 +
5036 +
5037 +#define XHCI_MTK_TEST_MAJOR 234
5038 +#define DEVICE_NAME "xhci_mtk_test"
5039 +
5040 +#define CLI_MAGIC 'CLI'
5041 +#define IOCTL_READ _IOR(CLI_MAGIC, 0, int)
5042 +#define IOCTL_WRITE _IOW(CLI_MAGIC, 1, int)
5043 +
5044 +void reinitIP(void);
5045 +void setInitialReg(void);
5046 +void dbg_prb_out(void);
5047 +int call_function(char *buf);
5048 +
5049 +long xhci_mtk_test_unlock_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
5050 +int xhci_mtk_test_open(struct inode *inode, struct file *file);
5051 +int xhci_mtk_test_release(struct inode *inode, struct file *file);
5052 +ssize_t xhci_mtk_test_read(struct file *file, char *buf, size_t count, loff_t *ptr);
5053 +ssize_t xhci_mtk_test_write(struct file *file, const char *buf, size_t count, loff_t * ppos);
5054 +
5055 +/*
5056 + mediatek probe out
5057 +*/
5058 +/************************************************************************************/
5059 +
5060 +#define SW_PRB_OUT_ADDR (SIFSLV_IPPC+0xc0)
5061 +#define PRB_MODULE_SEL_ADDR (SIFSLV_IPPC+0xbc)
5062 +
5063 +static inline void mtk_probe_init(const u32 byte){
5064 + __u32 __iomem *ptr = (__u32 __iomem *) PRB_MODULE_SEL_ADDR;
5065 + writel(byte, ptr);
5066 +}
5067 +
5068 +static inline void mtk_probe_out(const u32 value){
5069 + __u32 __iomem *ptr = (__u32 __iomem *) SW_PRB_OUT_ADDR;
5070 + writel(value, ptr);
5071 +}
5072 +
5073 +static inline u32 mtk_probe_value(void){
5074 + __u32 __iomem *ptr = (__u32 __iomem *) SW_PRB_OUT_ADDR;
5075 +
5076 + return readl(ptr);
5077 +}
5078 +
5079 +
5080 +#endif
5081 --- a/drivers/usb/host/xhci-plat.c
5082 +++ b/drivers/usb/host/xhci-plat.c
5083 @@ -43,6 +43,13 @@ static void xhci_plat_quirks(struct devi
5084 * dev struct in order to setup MSI
5085 */
5086 xhci->quirks |= XHCI_PLAT;
5087 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5088 + /* MTK host controller gives a spurious successful event after a
5089 + * short transfer. Ignore it.
5090 + */
5091 + xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
5092 + xhci->quirks |= XHCI_LPM_SUPPORT;
5093 +#endif
5094 }
5095
5096 /* called during probe() after chip reset completes */
5097 @@ -89,7 +96,11 @@ static int xhci_plat_probe(struct platfo
5098
5099 driver = &xhci_plat_hc_driver;
5100
5101 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5102 + irq = XHC_IRQ;
5103 +#else
5104 irq = platform_get_irq(pdev, 0);
5105 +#endif
5106 if (irq < 0)
5107 return -ENODEV;
5108
5109 --- a/drivers/usb/host/xhci-ring.c
5110 +++ b/drivers/usb/host/xhci-ring.c
5111 @@ -254,16 +254,20 @@ static void inc_enq(struct xhci_hcd *xhc
5112 static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
5113 unsigned int num_trbs)
5114 {
5115 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5116 int num_trbs_in_deq_seg;
5117 +#endif
5118
5119 if (ring->num_trbs_free < num_trbs)
5120 return 0;
5121
5122 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5123 if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) {
5124 num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs;
5125 if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg)
5126 return 0;
5127 }
5128 +#endif
5129
5130 return 1;
5131 }
5132 @@ -2869,6 +2873,7 @@ static int prepare_ring(struct xhci_hcd
5133 next = ring->enqueue;
5134
5135 while (last_trb(xhci, ring, ring->enq_seg, next)) {
5136 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5137 /* If we're not dealing with 0.95 hardware or isoc rings
5138 * on AMD 0.96 host, clear the chain bit.
5139 */
5140 @@ -2878,6 +2883,9 @@ static int prepare_ring(struct xhci_hcd
5141 next->link.control &= cpu_to_le32(~TRB_CHAIN);
5142 else
5143 next->link.control |= cpu_to_le32(TRB_CHAIN);
5144 +#else
5145 + next->link.control &= cpu_to_le32(~TRB_CHAIN);
5146 +#endif
5147
5148 wmb();
5149 next->link.control ^= cpu_to_le32(TRB_CYCLE);
5150 @@ -3008,6 +3016,9 @@ static void giveback_first_trb(struct xh
5151 start_trb->field[3] |= cpu_to_le32(start_cycle);
5152 else
5153 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
5154 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5155 + wmb();
5156 +#endif
5157 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
5158 }
5159
5160 @@ -3063,6 +3074,29 @@ static u32 xhci_td_remainder(unsigned in
5161 return (remainder >> 10) << 17;
5162 }
5163
5164 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5165 +static u32 mtk_xhci_td_remainder(unsigned int td_transfer_size, unsigned int td_running_total, unsigned int maxp, unsigned trb_buffer_length)
5166 +{
5167 + u32 max = 31;
5168 + int remainder, td_packet_count, packet_transferred;
5169 +
5170 + //0 for the last TRB
5171 + //FIXME: need to workaround if there is ZLP in this TD
5172 + if (td_running_total + trb_buffer_length == td_transfer_size)
5173 + return 0;
5174 +
5175 + //FIXME: need to take care of high-bandwidth (MAX_ESIT)
5176 + packet_transferred = (td_running_total /*+ trb_buffer_length*/) / maxp;
5177 + td_packet_count = DIV_ROUND_UP(td_transfer_size, maxp);
5178 + remainder = td_packet_count - packet_transferred;
5179 +
5180 + if (remainder > max)
5181 + return max << 17;
5182 + else
5183 + return remainder << 17;
5184 +}
5185 +#endif
5186 +
5187 /*
5188 * For xHCI 1.0 host controllers, TD size is the number of max packet sized
5189 * packets remaining in the TD (*not* including this TRB).
5190 @@ -3220,6 +3254,7 @@ static int queue_bulk_sg_tx(struct xhci_
5191 }
5192
5193 /* Set the TRB length, TD size, and interrupter fields. */
5194 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5195 if (xhci->hci_version < 0x100) {
5196 remainder = xhci_td_remainder(
5197 urb->transfer_buffer_length -
5198 @@ -3229,6 +3264,12 @@ static int queue_bulk_sg_tx(struct xhci_
5199 trb_buff_len, total_packet_count, urb,
5200 num_trbs - 1);
5201 }
5202 +#else
5203 + if (num_trbs > 1)
5204 + remainder = mtk_xhci_td_remainder(urb->transfer_buffer_length,
5205 + running_total, urb->ep->desc.wMaxPacketSize, trb_buff_len);
5206 +#endif
5207 +
5208 length_field = TRB_LEN(trb_buff_len) |
5209 remainder |
5210 TRB_INTR_TARGET(0);
5211 @@ -3293,6 +3334,9 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
5212 int running_total, trb_buff_len, ret;
5213 unsigned int total_packet_count;
5214 u64 addr;
5215 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5216 + int max_packet;
5217 +#endif
5218
5219 if (urb->num_sgs)
5220 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
5221 @@ -3317,6 +3361,25 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
5222 num_trbs++;
5223 running_total += TRB_MAX_BUFF_SIZE;
5224 }
5225 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5226 + switch(urb->dev->speed){
5227 + case USB_SPEED_SUPER:
5228 + max_packet = urb->ep->desc.wMaxPacketSize;
5229 + break;
5230 + case USB_SPEED_HIGH:
5231 + case USB_SPEED_FULL:
5232 + case USB_SPEED_LOW:
5233 + case USB_SPEED_WIRELESS:
5234 + case USB_SPEED_UNKNOWN:
5235 + default:
5236 + max_packet = urb->ep->desc.wMaxPacketSize & 0x7ff;
5237 + break;
5238 + }
5239 + if((urb->transfer_flags & URB_ZERO_PACKET)
5240 + && ((urb->transfer_buffer_length % max_packet) == 0)){
5241 + num_trbs++;
5242 + }
5243 +#endif
5244
5245 ret = prepare_transfer(xhci, xhci->devs[slot_id],
5246 ep_index, urb->stream_id,
5247 @@ -3393,6 +3456,7 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
5248 field |= TRB_ISP;
5249
5250 /* Set the TRB length, TD size, and interrupter fields. */
5251 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5252 if (xhci->hci_version < 0x100) {
5253 remainder = xhci_td_remainder(
5254 urb->transfer_buffer_length -
5255 @@ -3402,6 +3466,10 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
5256 trb_buff_len, total_packet_count, urb,
5257 num_trbs - 1);
5258 }
5259 +#else
5260 + remainder = mtk_xhci_td_remainder(urb->transfer_buffer_length, running_total, max_packet, trb_buff_len);
5261 +#endif
5262 +
5263 length_field = TRB_LEN(trb_buff_len) |
5264 remainder |
5265 TRB_INTR_TARGET(0);
5266 @@ -3491,7 +3559,11 @@ int xhci_queue_ctrl_tx(struct xhci_hcd *
5267 field |= 0x1;
5268
5269 /* xHCI 1.0/1.1 6.4.1.2.1: Transfer Type field */
5270 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5271 + if (1) {
5272 +#else
5273 if (xhci->hci_version >= 0x100) {
5274 +#endif
5275 if (urb->transfer_buffer_length > 0) {
5276 if (setup->bRequestType & USB_DIR_IN)
5277 field |= TRB_TX_TYPE(TRB_DATA_IN);
5278 @@ -3515,7 +3587,12 @@ int xhci_queue_ctrl_tx(struct xhci_hcd *
5279 field = TRB_TYPE(TRB_DATA);
5280
5281 length_field = TRB_LEN(urb->transfer_buffer_length) |
5282 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5283 xhci_td_remainder(urb->transfer_buffer_length) |
5284 +#else
5285 + //CC: MTK style, no scatter-gather for control transfer
5286 + 0 |
5287 +#endif
5288 TRB_INTR_TARGET(0);
5289 if (urb->transfer_buffer_length > 0) {
5290 if (setup->bRequestType & USB_DIR_IN)
5291 @@ -3731,6 +3808,9 @@ static int xhci_queue_isoc_tx(struct xhc
5292 bool more_trbs_coming;
5293 struct xhci_virt_ep *xep;
5294
5295 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5296 + int max_packet;
5297 +#endif
5298 xep = &xhci->devs[slot_id]->eps[ep_index];
5299 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
5300
5301 @@ -3744,6 +3824,21 @@ static int xhci_queue_isoc_tx(struct xhc
5302 start_trb = &ep_ring->enqueue->generic;
5303 start_cycle = ep_ring->cycle_state;
5304
5305 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5306 + switch(urb->dev->speed){
5307 + case USB_SPEED_SUPER:
5308 + max_packet = urb->ep->desc.wMaxPacketSize;
5309 + break;
5310 + case USB_SPEED_HIGH:
5311 + case USB_SPEED_FULL:
5312 + case USB_SPEED_LOW:
5313 + case USB_SPEED_WIRELESS:
5314 + case USB_SPEED_UNKNOWN:
5315 + max_packet = urb->ep->desc.wMaxPacketSize & 0x7ff;
5316 + break;
5317 + }
5318 +#endif
5319 +
5320 urb_priv = urb->hcpriv;
5321 /* Queue the first TRB, even if it's zero-length */
5322 for (i = 0; i < num_tds; i++) {
5323 @@ -3828,9 +3923,13 @@ static int xhci_queue_isoc_tx(struct xhc
5324 } else {
5325 td->last_trb = ep_ring->enqueue;
5326 field |= TRB_IOC;
5327 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5328 + if (!(xhci->quirks & XHCI_AVOID_BEI)) {
5329 +#else
5330 if (xhci->hci_version == 0x100 &&
5331 !(xhci->quirks &
5332 XHCI_AVOID_BEI)) {
5333 +#endif
5334 /* Set BEI bit except for the last td */
5335 if (i < num_tds - 1)
5336 field |= TRB_BEI;
5337 @@ -3845,6 +3944,7 @@ static int xhci_queue_isoc_tx(struct xhc
5338 trb_buff_len = td_remain_len;
5339
5340 /* Set the TRB length, TD size, & interrupter fields. */
5341 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5342 if (xhci->hci_version < 0x100) {
5343 remainder = xhci_td_remainder(
5344 td_len - running_total);
5345 @@ -3854,6 +3954,10 @@ static int xhci_queue_isoc_tx(struct xhc
5346 total_packet_count, urb,
5347 (trbs_per_td - j - 1));
5348 }
5349 +#else
5350 + remainder = mtk_xhci_td_remainder(urb->transfer_buffer_length, running_total, max_packet, trb_buff_len);
5351 +#endif
5352 +
5353 length_field = TRB_LEN(trb_buff_len) |
5354 remainder |
5355 TRB_INTR_TARGET(0);
5356 --- a/drivers/usb/host/xhci.c
5357 +++ b/drivers/usb/host/xhci.c
5358 @@ -32,6 +32,16 @@
5359 #include "xhci.h"
5360 #include "xhci-trace.h"
5361
5362 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5363 +#include <asm/uaccess.h>
5364 +#include <linux/dma-mapping.h>
5365 +#include <linux/platform_device.h>
5366 +#include "mtk-phy.h"
5367 +#include "xhci-mtk-scheduler.h"
5368 +#include "xhci-mtk-power.h"
5369 +#include "xhci-mtk.h"
5370 +#endif
5371 +
5372 #define DRIVER_AUTHOR "Sarah Sharp"
5373 #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
5374
5375 @@ -46,6 +56,18 @@ static unsigned int quirks;
5376 module_param(quirks, uint, S_IRUGO);
5377 MODULE_PARM_DESC(quirks, "Bit flags for quirks to be enabled as default");
5378
5379 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5380 +long xhci_mtk_test_unlock_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
5381 +static struct file_operations xhci_mtk_test_fops = {
5382 + .owner = THIS_MODULE,
5383 + .read = xhci_mtk_test_read,
5384 + .write = xhci_mtk_test_write,
5385 + .unlocked_ioctl = xhci_mtk_test_unlock_ioctl,
5386 + .open = xhci_mtk_test_open,
5387 + .release = xhci_mtk_test_release,
5388 +};
5389 +#endif
5390 +
5391 /* TODO: copied from ehci-hcd.c - can this be refactored? */
5392 /*
5393 * xhci_handshake - spin reading hc until handshake completes or fails
5394 @@ -208,7 +230,7 @@ int xhci_reset(struct xhci_hcd *xhci)
5395 return ret;
5396 }
5397
5398 -#ifdef CONFIG_PCI
5399 +#if defined (CONFIG_PCI) && !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5400 static int xhci_free_msi(struct xhci_hcd *xhci)
5401 {
5402 int i;
5403 @@ -458,6 +480,11 @@ static void compliance_mode_recovery(uns
5404 "Attempting compliance mode recovery");
5405 hcd = xhci->shared_hcd;
5406
5407 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5408 + temp |= (1 << 31);
5409 + writel(temp, xhci->usb3_ports[i]);
5410 +#endif
5411 +
5412 if (hcd->state == HC_STATE_SUSPENDED)
5413 usb_hcd_resume_root_hub(hcd);
5414
5415 @@ -505,6 +532,9 @@ static bool xhci_compliance_mode_recover
5416 {
5417 const char *dmi_product_name, *dmi_sys_vendor;
5418
5419 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5420 + return true;
5421 +#endif
5422 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
5423 dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
5424 if (!dmi_product_name || !dmi_sys_vendor)
5425 @@ -550,6 +580,10 @@ int xhci_init(struct usb_hcd *hcd)
5426 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
5427 "xHCI doesn't need link TRB QUIRK");
5428 }
5429 +
5430 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5431 + mtk_xhci_scheduler_init();
5432 +#endif
5433 retval = xhci_mem_init(xhci, GFP_KERNEL);
5434 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Finished xhci_init");
5435
5436 @@ -634,7 +668,11 @@ int xhci_run(struct usb_hcd *hcd)
5437 "// Set the interrupt modulation register");
5438 temp = readl(&xhci->ir_set->irq_control);
5439 temp &= ~ER_IRQ_INTERVAL_MASK;
5440 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5441 + temp |= (u32) 16;
5442 +#else
5443 temp |= (u32) 160;
5444 +#endif
5445 writel(temp, &xhci->ir_set->irq_control);
5446
5447 /* Set the HCD state before we enable the irqs */
5448 @@ -659,6 +697,9 @@ int xhci_run(struct usb_hcd *hcd)
5449 xhci_queue_vendor_command(xhci, command, 0, 0, 0,
5450 TRB_TYPE(TRB_NEC_GET_FW));
5451 }
5452 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5453 + enableXhciAllPortPower(xhci);
5454 +#endif
5455 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
5456 "Finished xhci_run for USB2 roothub");
5457 return 0;
5458 @@ -1649,6 +1690,14 @@ int xhci_drop_endpoint(struct usb_hcd *h
5459 u32 drop_flag;
5460 u32 new_add_flags, new_drop_flags;
5461 int ret;
5462 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5463 +#if MTK_SCH_NEW
5464 + struct xhci_slot_ctx *slot_ctx;
5465 + struct sch_ep *sch_ep = NULL;
5466 + int isTT;
5467 + int ep_type;
5468 +#endif
5469 +#endif
5470
5471 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
5472 if (ret <= 0)
5473 @@ -1698,6 +1747,40 @@ int xhci_drop_endpoint(struct usb_hcd *h
5474
5475 xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
5476
5477 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5478 +#if MTK_SCH_NEW
5479 + slot_ctx = xhci_get_slot_ctx(xhci, xhci->devs[udev->slot_id]->out_ctx);
5480 + if ((slot_ctx->tt_info & 0xff) > 0) {
5481 + isTT = 1;
5482 + }
5483 + else {
5484 + isTT = 0;
5485 + }
5486 + if (usb_endpoint_xfer_int(&ep->desc)) {
5487 + ep_type = USB_EP_INT;
5488 + }
5489 + else if (usb_endpoint_xfer_isoc(&ep->desc)) {
5490 + ep_type = USB_EP_ISOC;
5491 + }
5492 + else if (usb_endpoint_xfer_bulk(&ep->desc)) {
5493 + ep_type = USB_EP_BULK;
5494 + }
5495 + else
5496 + ep_type = USB_EP_CONTROL;
5497 +
5498 + sch_ep = mtk_xhci_scheduler_remove_ep(udev->speed, usb_endpoint_dir_in(&ep->desc)
5499 + , isTT, ep_type, (mtk_u32 *)ep);
5500 + if (sch_ep != NULL) {
5501 + kfree(sch_ep);
5502 + }
5503 + else {
5504 + xhci_dbg(xhci, "[MTK]Doesn't find ep_sch instance when removing endpoint\n");
5505 + }
5506 +#else
5507 + mtk_xhci_scheduler_remove_ep(xhci, udev, ep);
5508 +#endif
5509 +#endif
5510 +
5511 xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
5512 (unsigned int) ep->desc.bEndpointAddress,
5513 udev->slot_id,
5514 @@ -1730,6 +1813,19 @@ int xhci_add_endpoint(struct usb_hcd *hc
5515 u32 new_add_flags, new_drop_flags;
5516 struct xhci_virt_device *virt_dev;
5517 int ret = 0;
5518 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5519 + struct xhci_ep_ctx *in_ep_ctx;
5520 +#if MTK_SCH_NEW
5521 + struct xhci_slot_ctx *slot_ctx;
5522 + struct sch_ep *sch_ep;
5523 + int isTT;
5524 + int ep_type;
5525 + int maxp = 0;
5526 + int burst = 0;
5527 + int mult = 0;
5528 + int interval;
5529 +#endif
5530 +#endif
5531
5532 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
5533 if (ret <= 0) {
5534 @@ -1793,6 +1889,56 @@ int xhci_add_endpoint(struct usb_hcd *hc
5535 return -ENOMEM;
5536 }
5537
5538 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5539 + in_ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
5540 +#if MTK_SCH_NEW
5541 + slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
5542 + if ((slot_ctx->tt_info & 0xff) > 0) {
5543 + isTT = 1;
5544 + }
5545 + else {
5546 + isTT = 0;
5547 + }
5548 + if (usb_endpoint_xfer_int(&ep->desc)) {
5549 + ep_type = USB_EP_INT;
5550 + }
5551 + else if (usb_endpoint_xfer_isoc(&ep->desc)) {
5552 + ep_type = USB_EP_ISOC;
5553 + }
5554 + else if (usb_endpoint_xfer_bulk(&ep->desc)) {
5555 + ep_type = USB_EP_BULK;
5556 + }
5557 + else
5558 + ep_type = USB_EP_CONTROL;
5559 +
5560 + if (udev->speed == USB_SPEED_FULL || udev->speed == USB_SPEED_HIGH
5561 + || udev->speed == USB_SPEED_LOW) {
5562 + maxp = ep->desc.wMaxPacketSize & 0x7FF;
5563 + burst = ep->desc.wMaxPacketSize >> 11;
5564 + mult = 0;
5565 + }
5566 + else if (udev->speed == USB_SPEED_SUPER) {
5567 + maxp = ep->desc.wMaxPacketSize & 0x7FF;
5568 + burst = ep->ss_ep_comp.bMaxBurst;
5569 + mult = ep->ss_ep_comp.bmAttributes & 0x3;
5570 + }
5571 + interval = (1 << ((in_ep_ctx->ep_info >> 16) & 0xff));
5572 + sch_ep = kmalloc(sizeof(struct sch_ep), GFP_KERNEL);
5573 + if (mtk_xhci_scheduler_add_ep(udev->speed, usb_endpoint_dir_in(&ep->desc),
5574 + isTT, ep_type, maxp, interval, burst, mult, (mtk_u32 *)ep
5575 + , (mtk_u32 *)in_ep_ctx, sch_ep) != SCH_SUCCESS) {
5576 + xhci_err(xhci, "[MTK] not enough bandwidth\n");
5577 +
5578 + return -ENOSPC;
5579 + }
5580 +#else
5581 + if (mtk_xhci_scheduler_add_ep(xhci, udev, ep, in_ep_ctx) != SCH_SUCCESS) {
5582 + xhci_err(xhci, "[MTK] not enough bandwidth\n");
5583 +
5584 + return -ENOSPC;
5585 + }
5586 +#endif
5587 +#endif
5588 ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
5589 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
5590
5591 @@ -4456,8 +4602,14 @@ static u16 xhci_call_host_update_timeout
5592 u16 *timeout)
5593 {
5594 if (state == USB3_LPM_U1)
5595 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5596 + if (xhci->quirks & XHCI_INTEL_HOST)
5597 +#endif
5598 return xhci_calculate_u1_timeout(xhci, udev, desc);
5599 else if (state == USB3_LPM_U2)
5600 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5601 + if (xhci->quirks & XHCI_INTEL_HOST)
5602 +#endif
5603 return xhci_calculate_u2_timeout(xhci, udev, desc);
5604
5605 return USB3_LPM_DISABLED;
5606 @@ -4849,7 +5001,9 @@ int xhci_gen_setup(struct usb_hcd *hcd,
5607 hcd->self.no_sg_constraint = 1;
5608
5609 /* XHCI controllers don't stop the ep queue on short packets :| */
5610 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5611 hcd->self.no_stop_on_short = 1;
5612 +#endif
5613
5614 if (usb_hcd_is_primary_hcd(hcd)) {
5615 xhci = hcd_to_xhci(hcd);
5616 @@ -4910,6 +5064,10 @@ int xhci_gen_setup(struct usb_hcd *hcd,
5617 return retval;
5618 xhci_dbg(xhci, "Reset complete\n");
5619
5620 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5621 + setInitialReg();
5622 +#endif
5623 +
5624 /* Set dma_mask and coherent_dma_mask to 64-bits,
5625 * if xHC supports 64-bit addressing */
5626 if (HCC_64BIT_ADDR(xhci->hcc_params) &&
5627 @@ -5015,8 +5173,57 @@ MODULE_DESCRIPTION(DRIVER_DESC);
5628 MODULE_AUTHOR(DRIVER_AUTHOR);
5629 MODULE_LICENSE("GPL");
5630
5631 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5632 +static struct resource xhci_resouce[] = {
5633 + {
5634 + .name = "xhci-hcd",
5635 + .start = XHC_IO_START,
5636 + .end = XHC_IO_START + XHC_IO_LENGTH -1,
5637 + .flags = IORESOURCE_MEM,
5638 + }
5639 +};
5640 +
5641 +static struct platform_device xhci_platform_dev = {
5642 + .name = "xhci-hcd",
5643 + .id = -1,
5644 + .dev = {
5645 + .coherent_dma_mask = 0xffffffff,
5646 + },
5647 + .resource = xhci_resouce,
5648 +};
5649 +#endif
5650 +
5651 static int __init xhci_hcd_init(void)
5652 {
5653 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5654 + struct platform_device *pPlatformDev;
5655 +
5656 + register_chrdev(XHCI_MTK_TEST_MAJOR, DEVICE_NAME, &xhci_mtk_test_fops);
5657 +
5658 + u3phy_init();
5659 + if (u3phy_ops->u2_slew_rate_calibration) {
5660 + u3phy_ops->u2_slew_rate_calibration(u3phy);
5661 + u3phy_ops->u2_slew_rate_calibration(u3phy_p1);
5662 + }
5663 + else{
5664 + printk(KERN_ERR "WARN: PHY doesn't implement u2 slew rate calibration function\n");
5665 + }
5666 + u3phy_ops->init(u3phy);
5667 + reinitIP();
5668 +
5669 + pPlatformDev = &xhci_platform_dev;
5670 + memset(pPlatformDev, 0, sizeof(struct platform_device));
5671 + pPlatformDev->name = "xhci-hcd";
5672 + pPlatformDev->id = -1;
5673 + pPlatformDev->dev.coherent_dma_mask = 0xffffffff;
5674 + pPlatformDev->dev.dma_mask = &pPlatformDev->dev.coherent_dma_mask;
5675 + pPlatformDev->resource = xhci_resouce;
5676 + pPlatformDev->num_resources = ARRAY_SIZE(xhci_resouce);
5677 +
5678 +// platform_device_register(&xhci_platform_dev);
5679 +
5680 +#endif
5681 +
5682 /*
5683 * Check the compiler generated sizes of structures that must be laid
5684 * out in specific ways for hardware access.
5685 --- a/drivers/usb/host/xhci.h
5686 +++ b/drivers/usb/host/xhci.h
5687 @@ -33,6 +33,21 @@
5688 #include "xhci-ext-caps.h"
5689 #include "pci-quirks.h"
5690
5691 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5692 +#define XHC_IRQ (22 + 7)
5693 +#define XHC_IO_START 0x1E1C0000
5694 +#define XHC_IO_LENGTH 0x10000
5695 +/* mtk scheduler bitmasks */
5696 +#define BPKTS(p) ((p) & 0x3f)
5697 +#define BCSCOUNT(p) (((p) & 0x7) << 8)
5698 +#define BBM(p) ((p) << 11)
5699 +#define BOFFSET(p) ((p) & 0x3fff)
5700 +#define BREPEAT(p) (((p) & 0x7fff) << 16)
5701 +#endif
5702 +
5703 +
5704 +
5705 +
5706 /* xHCI PCI Configuration Registers */
5707 #define XHCI_SBRN_OFFSET (0x60)
5708
5709 @@ -1597,8 +1612,12 @@ struct xhci_hcd {
5710 /* Compliance Mode Recovery Data */
5711 struct timer_list comp_mode_recovery_timer;
5712 u32 port_status_u0;
5713 +#ifdef CONFIG_USB_MT7621_XHCI_PLATFORM
5714 +#define COMP_MODE_RCVRY_MSECS 5000
5715 +#else
5716 /* Compliance Mode Timer Triggered every 2 seconds */
5717 #define COMP_MODE_RCVRY_MSECS 2000
5718 +#endif
5719 };
5720
5721 /* Platform specific overrides to generic XHCI hc_driver ops */
5722 @@ -1763,6 +1782,26 @@ void xhci_urb_free_priv(struct urb_priv
5723 void xhci_free_command(struct xhci_hcd *xhci,
5724 struct xhci_command *command);
5725
5726 +#if defined (CONFIG_PCI) && !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5727 +/* xHCI PCI glue */
5728 +int xhci_register_pci(void);
5729 +void xhci_unregister_pci(void);
5730 +#else
5731 +static inline int xhci_register_pci(void) { return 0; }
5732 +static inline void xhci_unregister_pci(void) {}
5733 +#endif
5734 +
5735 +#if defined(CONFIG_USB_XHCI_PLATFORM) \
5736 + || defined(CONFIG_USB_XHCI_PLATFORM_MODULE)
5737 +int xhci_register_plat(void);
5738 +void xhci_unregister_plat(void);
5739 +#else
5740 +static inline int xhci_register_plat(void)
5741 +{ return 0; }
5742 +static inline void xhci_unregister_plat(void)
5743 +{ }
5744 +#endif
5745 +
5746 /* xHCI host controller glue */
5747 typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *);
5748 int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, int usec);
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