target/linux/ramips/patches-4.4/0004-MIPS-ralink-add-MT7621-pcie-driver.patch

   1 From fec11d4e8dc5cc79bcd7c8fd55038ac21ac39965 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Sun, 16 Mar 2014 05:22:39 +0000
   4 Subject: [PATCH 04/53] MIPS: ralink: add MT7621 pcie driver
   5
   6 Signed-off-by: John Crispin <blogic@openwrt.org>
   7 ---
   8  arch/mips/pci/Makefile     |    1 +
   9  arch/mips/pci/pci-mt7621.c |  813 ++++++++++++++++++++++++++++++++++++++++++++
  10  2 files changed, 814 insertions(+)
  11  create mode 100644 arch/mips/pci/pci-mt7621.c
  12
  13 --- a/arch/mips/pci/Makefile
  14 +++ b/arch/mips/pci/Makefile
  15 @@ -43,6 +43,7 @@ obj-$(CONFIG_SIBYTE_BCM1x80)  += pci-bcm1
  16  obj-$(CONFIG_SNI_RM)           += fixup-sni.o ops-sni.o
  17  obj-$(CONFIG_LANTIQ)           += fixup-lantiq.o
  18  obj-$(CONFIG_PCI_LANTIQ)       += pci-lantiq.o ops-lantiq.o
  19 +obj-$(CONFIG_SOC_MT7621)       += pci-mt7621.o
  20  obj-$(CONFIG_SOC_RT288X)       += pci-rt2880.o
  21  obj-$(CONFIG_SOC_RT3883)       += pci-rt3883.o
  22  obj-$(CONFIG_TANBAC_TB0219)    += fixup-tb0219.o
  23 --- /dev/null
  24 +++ b/arch/mips/pci/pci-mt7621.c
  25 @@ -0,0 +1,832 @@
  26 +/**************************************************************************
  27 + *
  28 + *  BRIEF MODULE DESCRIPTION
  29 + *     PCI init for Ralink RT2880 solution
  30 + *
  31 + *  Copyright 2007 Ralink Inc. (bruce_chang@ralinktech.com.tw)
  32 + *
  33 + *  This program is free software; you can redistribute  it and/or modify it
  34 + *  under  the terms of  the GNU General  Public License as published by the
  35 + *  Free Software Foundation;  either version 2 of the  License, or (at your
  36 + *  option) any later version.
  37 + *
  38 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  39 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  40 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  41 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  42 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  43 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  44 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  45 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  46 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  47 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  48 + *
  49 + *  You should have received a copy of the  GNU General Public License along
  50 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
  51 + *  675 Mass Ave, Cambridge, MA 02139, USA.
  52 + *
  53 + *
  54 + **************************************************************************
  55 + * May 2007 Bruce Chang
  56 + * Initial Release
  57 + *
  58 + * May 2009 Bruce Chang
  59 + * support RT2880/RT3883 PCIe
  60 + *
  61 + * May 2011 Bruce Chang
  62 + * support RT6855/MT7620 PCIe
  63 + *
  64 + **************************************************************************
  65 + */
  66 +
  67 +#include <linux/types.h>
  68 +#include <linux/pci.h>
  69 +#include <linux/kernel.h>
  70 +#include <linux/slab.h>
  71 +#include <linux/version.h>
  72 +#include <asm/pci.h>
  73 +#include <asm/io.h>
  74 +#include <asm/mips-cm.h>
  75 +#include <linux/init.h>
  76 +#include <linux/module.h>
  77 +#include <linux/delay.h>
  78 +#include <linux/of.h>
  79 +#include <linux/of_pci.h>
  80 +#include <linux/platform_device.h>
  81 +
  82 +#include <ralink_regs.h>
  83 +
  84 +extern void pcie_phy_init(void);
  85 +extern void chk_phy_pll(void);
  86 +
  87 +/*
  88 + * These functions and structures provide the BIOS scan and mapping of the PCI
  89 + * devices.
  90 + */
  91 +
  92 +#define CONFIG_PCIE_PORT0
  93 +#define CONFIG_PCIE_PORT1
  94 +#define CONFIG_PCIE_PORT2
  95 +#define RALINK_PCIE0_CLK_EN             (1<<24)
  96 +#define RALINK_PCIE1_CLK_EN             (1<<25)
  97 +#define RALINK_PCIE2_CLK_EN             (1<<26)
  98 +
  99 +#define RALINK_PCI_CONFIG_ADDR                         0x20
 100 +#define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG     0x24
 101 +#define SURFBOARDINT_PCIE0       11      /* PCIE0 */
 102 +#define RALINK_INT_PCIE0         SURFBOARDINT_PCIE0
 103 +#define RALINK_INT_PCIE1         SURFBOARDINT_PCIE1
 104 +#define RALINK_INT_PCIE2         SURFBOARDINT_PCIE2
 105 +#define SURFBOARDINT_PCIE1       31     /* PCIE1 */
 106 +#define SURFBOARDINT_PCIE2       32     /* PCIE2 */
 107 +#define RALINK_PCI_MEMBASE              *(volatile u32 *)(RALINK_PCI_BASE + 0x0028)
 108 +#define RALINK_PCI_IOBASE               *(volatile u32 *)(RALINK_PCI_BASE + 0x002C)
 109 +#define RALINK_PCIE0_RST                (1<<24)
 110 +#define RALINK_PCIE1_RST                (1<<25)
 111 +#define RALINK_PCIE2_RST                (1<<26)
 112 +#define RALINK_SYSCTL_BASE              0xBE000000
 113 +
 114 +#define RALINK_PCI_PCICFG_ADDR          *(volatile u32 *)(RALINK_PCI_BASE + 0x0000)
 115 +#define RALINK_PCI_PCIMSK_ADDR          *(volatile u32 *)(RALINK_PCI_BASE + 0x000C)
 116 +#define RALINK_PCI_BASE                 0xBE140000
 117 +
 118 +#define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000)
 119 +#define RT6855_PCIE0_OFFSET     0x2000
 120 +#define RT6855_PCIE1_OFFSET     0x3000
 121 +#define RT6855_PCIE2_OFFSET     0x4000
 122 +
 123 +#define RALINK_PCI0_BAR0SETUP_ADDR      *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0010)
 124 +#define RALINK_PCI0_IMBASEBAR0_ADDR     *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0018)
 125 +#define RALINK_PCI0_ID                  *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0030)
 126 +#define RALINK_PCI0_CLASS               *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0034)
 127 +#define RALINK_PCI0_SUBID               *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0038)
 128 +#define RALINK_PCI0_STATUS              *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0050)
 129 +#define RALINK_PCI0_DERR                *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0060)
 130 +#define RALINK_PCI0_ECRC                *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0064)
 131 +
 132 +#define RALINK_PCI1_BAR0SETUP_ADDR      *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0010)
 133 +#define RALINK_PCI1_IMBASEBAR0_ADDR     *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0018)
 134 +#define RALINK_PCI1_ID                  *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0030)
 135 +#define RALINK_PCI1_CLASS               *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0034)
 136 +#define RALINK_PCI1_SUBID               *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0038)
 137 +#define RALINK_PCI1_STATUS              *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0050)
 138 +#define RALINK_PCI1_DERR                *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0060)
 139 +#define RALINK_PCI1_ECRC                *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0064)
 140 +
 141 +#define RALINK_PCI2_BAR0SETUP_ADDR      *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0010)
 142 +#define RALINK_PCI2_IMBASEBAR0_ADDR     *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0018)
 143 +#define RALINK_PCI2_ID                  *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0030)
 144 +#define RALINK_PCI2_CLASS               *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0034)
 145 +#define RALINK_PCI2_SUBID               *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0038)
 146 +#define RALINK_PCI2_STATUS              *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0050)
 147 +#define RALINK_PCI2_DERR                *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0060)
 148 +#define RALINK_PCI2_ECRC                *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0064)
 149 +
 150 +#define RALINK_PCIEPHY_P0P1_CTL_OFFSET  (RALINK_PCI_BASE + 0x9000)
 151 +#define RALINK_PCIEPHY_P2_CTL_OFFSET    (RALINK_PCI_BASE + 0xA000)
 152 +
 153 +
 154 +#define MV_WRITE(ofs, data)  \
 155 +        *(volatile u32 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le32(data)
 156 +#define MV_READ(ofs, data)   \
 157 +               *(data) = le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
 158 +#define MV_READ_DATA(ofs)    \
 159 +                       le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
 160 +
 161 +#define MV_WRITE_16(ofs, data)  \
 162 +        *(volatile u16 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le16(data)
 163 +#define MV_READ_16(ofs, data)   \
 164 +               *(data) = le16_to_cpu(*(volatile u16 *)(RALINK_PCI_BASE+(ofs)))
 165 +
 166 +#define MV_WRITE_8(ofs, data)  \
 167 +        *(volatile u8 *)(RALINK_PCI_BASE+(ofs)) = data
 168 +#define MV_READ_8(ofs, data)   \
 169 +               *(data) = *(volatile u8 *)(RALINK_PCI_BASE+(ofs))
 170 +
 171 +
 172 +
 173 +#define RALINK_PCI_MM_MAP_BASE 0x60000000
 174 +#define RALINK_PCI_IO_MAP_BASE 0x1e160000
 175 +
 176 +#define RALINK_SYSTEM_CONTROL_BASE     0xbe000000
 177 +#define GPIO_PERST
 178 +#define ASSERT_SYSRST_PCIE(val)                do {    \
 179 +                                               if (*(unsigned int *)(0xbe00000c) == 0x00030101)        \
 180 +                                                       RALINK_RSTCTRL |= val;  \
 181 +                                               else    \
 182 +                                                       RALINK_RSTCTRL &= ~val; \
 183 +                                       } while(0)
 184 +#define DEASSERT_SYSRST_PCIE(val)      do {    \
 185 +                                               if (*(unsigned int *)(0xbe00000c) == 0x00030101)        \
 186 +                                                       RALINK_RSTCTRL &= ~val; \
 187 +                                               else    \
 188 +                                                       RALINK_RSTCTRL |= val;  \
 189 +                                       } while(0)
 190 +#define RALINK_SYSCFG1                 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x14)
 191 +#define RALINK_CLKCFG1                 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x30)
 192 +#define RALINK_RSTCTRL                 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x34)
 193 +#define RALINK_GPIOMODE                        *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x60)
 194 +#define RALINK_PCIE_CLK_GEN            *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x7c)
 195 +#define RALINK_PCIE_CLK_GEN1           *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x80)
 196 +#define PPLL_CFG1                      *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x9c)
 197 +#define PPLL_DRV                       *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0xa0)
 198 +//RALINK_SYSCFG1 bit
 199 +#define RALINK_PCI_HOST_MODE_EN                (1<<7)
 200 +#define RALINK_PCIE_RC_MODE_EN         (1<<8)
 201 +//RALINK_RSTCTRL bit
 202 +#define RALINK_PCIE_RST                        (1<<23)
 203 +#define RALINK_PCI_RST                 (1<<24)
 204 +//RALINK_CLKCFG1 bit
 205 +#define RALINK_PCI_CLK_EN              (1<<19)
 206 +#define RALINK_PCIE_CLK_EN             (1<<21)
 207 +//RALINK_GPIOMODE bit
 208 +#define PCI_SLOTx2                     (1<<11)
 209 +#define PCI_SLOTx1                     (2<<11)
 210 +//MTK PCIE PLL bit
 211 +#define PDRV_SW_SET                    (1<<31)
 212 +#define LC_CKDRVPD_                    (1<<19)
 213 +
 214 +#define MEMORY_BASE 0x0
 215 +static int pcie_link_status = 0;
 216 +
 217 +#define PCI_ACCESS_READ_1  0
 218 +#define PCI_ACCESS_READ_2  1
 219 +#define PCI_ACCESS_READ_4  2
 220 +#define PCI_ACCESS_WRITE_1 3
 221 +#define PCI_ACCESS_WRITE_2 4
 222 +#define PCI_ACCESS_WRITE_4 5
 223 +
 224 +static int config_access(unsigned char access_type, struct pci_bus *bus,
 225 +                       unsigned int devfn, unsigned int where, u32 * data)
 226 +{
 227 +       unsigned int slot = PCI_SLOT(devfn);
 228 +       u8 func = PCI_FUNC(devfn);
 229 +       uint32_t address_reg, data_reg;
 230 +       unsigned int address;
 231 +
 232 +       address_reg = RALINK_PCI_CONFIG_ADDR;
 233 +       data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
 234 +
 235 +       address = (((where&0xF00)>>8)<<24) |(bus->number << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000;
 236 +       MV_WRITE(address_reg, address);
 237 +
 238 +       switch(access_type) {
 239 +       case PCI_ACCESS_WRITE_1:
 240 +               MV_WRITE_8(data_reg+(where&0x3), *data);
 241 +               break;
 242 +       case PCI_ACCESS_WRITE_2:
 243 +               MV_WRITE_16(data_reg+(where&0x3), *data);
 244 +               break;
 245 +       case PCI_ACCESS_WRITE_4:
 246 +               MV_WRITE(data_reg, *data);
 247 +               break;
 248 +       case PCI_ACCESS_READ_1:
 249 +               MV_READ_8( data_reg+(where&0x3), data);
 250 +               break;
 251 +       case PCI_ACCESS_READ_2:
 252 +               MV_READ_16(data_reg+(where&0x3), data);
 253 +               break;
 254 +       case PCI_ACCESS_READ_4:
 255 +               MV_READ(data_reg, data);
 256 +               break;
 257 +       default:
 258 +               printk("no specify access type\n");
 259 +               break;
 260 +       }
 261 +       return 0;
 262 +}
 263 +
 264 +static int
 265 +read_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 * val)
 266 +{
 267 +       return config_access(PCI_ACCESS_READ_1, bus, devfn, (unsigned int)where, (u32 *)val);
 268 +}
 269 +
 270 +static int
 271 +read_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 * val)
 272 +{
 273 +       return config_access(PCI_ACCESS_READ_2, bus, devfn, (unsigned int)where, (u32 *)val);
 274 +}
 275 +
 276 +static int
 277 +read_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 * val)
 278 +{
 279 +       return config_access(PCI_ACCESS_READ_4, bus, devfn, (unsigned int)where, (u32 *)val);
 280 +}
 281 +
 282 +static int
 283 +write_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 val)
 284 +{
 285 +       if (config_access(PCI_ACCESS_WRITE_1, bus, devfn, (unsigned int)where, (u32 *)&val))
 286 +               return -1;
 287 +
 288 +       return PCIBIOS_SUCCESSFUL;
 289 +}
 290 +
 291 +static int
 292 +write_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 val)
 293 +{
 294 +       if (config_access(PCI_ACCESS_WRITE_2, bus, devfn, where, (u32 *)&val))
 295 +               return -1;
 296 +
 297 +       return PCIBIOS_SUCCESSFUL;
 298 +}
 299 +
 300 +static int
 301 +write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 val)
 302 +{
 303 +       if (config_access(PCI_ACCESS_WRITE_4, bus, devfn, where, &val))
 304 +               return -1;
 305 +
 306 +       return PCIBIOS_SUCCESSFUL;
 307 +}
 308 +
 309 +
 310 +static int
 311 +pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val)
 312 +{
 313 +       switch (size) {
 314 +       case 1:
 315 +               return read_config_byte(bus, devfn, where, (u8 *) val);
 316 +       case 2:
 317 +               return read_config_word(bus, devfn, where, (u16 *) val);
 318 +       default:
 319 +               return read_config_dword(bus, devfn, where, val);
 320 +       }
 321 +}
 322 +
 323 +static int
 324 +pci_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
 325 +{
 326 +       switch (size) {
 327 +       case 1:
 328 +               return write_config_byte(bus, devfn, where, (u8) val);
 329 +       case 2:
 330 +               return write_config_word(bus, devfn, where, (u16) val);
 331 +       default:
 332 +               return write_config_dword(bus, devfn, where, val);
 333 +       }
 334 +}
 335 +
 336 +struct pci_ops mt7621_pci_ops= {
 337 +       .read           =  pci_config_read,
 338 +       .write          = pci_config_write,
 339 +};
 340 +
 341 +static struct resource mt7621_res_pci_mem1 = {
 342 +       .name           = "PCI MEM1",
 343 +       .start          = RALINK_PCI_MM_MAP_BASE,
 344 +       .end            = (u32)((RALINK_PCI_MM_MAP_BASE + (unsigned char *)0x0fffffff)),
 345 +       .flags          = IORESOURCE_MEM,
 346 +};
 347 +static struct resource mt7621_res_pci_io1 = {
 348 +       .name           = "PCI I/O1",
 349 +       .start          = RALINK_PCI_IO_MAP_BASE,
 350 +       .end            = (u32)((RALINK_PCI_IO_MAP_BASE + (unsigned char *)0x0ffff)),
 351 +       .flags          = IORESOURCE_IO,
 352 +};
 353 +
 354 +static struct pci_controller mt7621_controller = {
 355 +       .pci_ops        = &mt7621_pci_ops,
 356 +       .mem_resource   = &mt7621_res_pci_mem1,
 357 +       .io_resource    = &mt7621_res_pci_io1,
 358 +       .mem_offset     = 0x00000000UL,
 359 +       .io_offset      = 0x00000000UL,
 360 +       .io_map_base    = 0xa0000000,
 361 +};
 362 +
 363 +static void
 364 +read_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned long reg, unsigned long *val)
 365 +{
 366 +       unsigned int address_reg, data_reg, address;
 367 +
 368 +       address_reg = RALINK_PCI_CONFIG_ADDR;
 369 +        data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
 370 +       address = (((reg & 0xF00)>>8)<<24) | (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 0x80000000 ;
 371 +        MV_WRITE(address_reg, address);
 372 +        MV_READ(data_reg, val);
 373 +       return;
 374 +}
 375 +
 376 +static void
 377 +write_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned long reg, unsigned long val)
 378 +{
 379 +       unsigned int address_reg, data_reg, address;
 380 +
 381 +       address_reg = RALINK_PCI_CONFIG_ADDR;
 382 +       data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
 383 +       address = (((reg & 0xF00)>>8)<<24) | (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 0x80000000 ;
 384 +       MV_WRITE(address_reg, address);
 385 +       MV_WRITE(data_reg, val);
 386 +       return;
 387 +}
 388 +
 389 +
 390 +int __init
 391 +pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 392 +{
 393 +       u16 cmd;
 394 +       u32 val;
 395 +       int irq = 0;
 396 +
 397 +       if ((dev->bus->number == 0) && (slot == 0)) {
 398 +               write_config(0, 0, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
 399 +               read_config(0, 0, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
 400 +               printk("BAR0 at slot 0 = %x\n", val);
 401 +               printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
 402 +       } else if((dev->bus->number == 0) && (slot == 0x1)) {
 403 +               write_config(0, 1, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
 404 +               read_config(0, 1, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
 405 +               printk("BAR0 at slot 1 = %x\n", val);
 406 +               printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
 407 +       } else if((dev->bus->number == 0) && (slot == 0x2)) {
 408 +               write_config(0, 2, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
 409 +               read_config(0, 2, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
 410 +               printk("BAR0 at slot 2 = %x\n", val);
 411 +               printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
 412 +       } else if ((dev->bus->number == 1) && (slot == 0x0)) {
 413 +               switch (pcie_link_status) {
 414 +               case 2:
 415 +               case 6:
 416 +                       irq = RALINK_INT_PCIE1;
 417 +                       break;
 418 +               case 4:
 419 +                       irq = RALINK_INT_PCIE2;
 420 +                       break;
 421 +               default:
 422 +                       irq = RALINK_INT_PCIE0;
 423 +               }
 424 +               printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
 425 +       } else if ((dev->bus->number == 2) && (slot == 0x0)) {
 426 +               switch (pcie_link_status) {
 427 +               case 5:
 428 +               case 6:
 429 +                       irq = RALINK_INT_PCIE2;
 430 +                       break;
 431 +               default:
 432 +                       irq = RALINK_INT_PCIE1;
 433 +               }
 434 +               printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
 435 +       } else if ((dev->bus->number == 2) && (slot == 0x1)) {
 436 +               switch (pcie_link_status) {
 437 +               case 5:
 438 +               case 6:
 439 +                       irq = RALINK_INT_PCIE2;
 440 +                       break;
 441 +               default:
 442 +                       irq = RALINK_INT_PCIE1;
 443 +               }
 444 +               printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
 445 +       } else if ((dev->bus->number ==3) && (slot == 0x0)) {
 446 +               irq = RALINK_INT_PCIE2;
 447 +               printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
 448 +       } else if ((dev->bus->number ==3) && (slot == 0x1)) {
 449 +               irq = RALINK_INT_PCIE2;
 450 +               printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
 451 +       } else if ((dev->bus->number ==3) && (slot == 0x2)) {
 452 +               irq = RALINK_INT_PCIE2;
 453 +               printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
 454 +       } else {
 455 +               printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
 456 +               return 0;
 457 +       }
 458 +
 459 +       pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14);  //configure cache line size 0x14
 460 +       pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xFF);  //configure latency timer 0x10
 461 +       pci_read_config_word(dev, PCI_COMMAND, &cmd);
 462 +       cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
 463 +       pci_write_config_word(dev, PCI_COMMAND, cmd);
 464 +       pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
 465 +       return irq;
 466 +}
 467 +
 468 +void
 469 +set_pcie_phy(u32 *addr, int start_b, int bits, int val)
 470 +{
 471 +//     printk("0x%p:", addr);
 472 +//     printk(" %x", *addr);
 473 +       *(unsigned int *)(addr) &= ~(((1<<bits) - 1)<<start_b);
 474 +       *(unsigned int *)(addr) |= val << start_b;
 475 +//     printk(" -> %x\n", *addr);
 476 +}
 477 +
 478 +void
 479 +bypass_pipe_rst(void)
 480 +{
 481 +#if defined (CONFIG_PCIE_PORT0)
 482 +       /* PCIe Port 0 */
 483 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c), 12, 1, 0x01);     // rg_pe1_pipe_rst_b
 484 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c),  4, 1, 0x01);     // rg_pe1_pipe_cmd_frc[4]
 485 +#endif
 486 +#if defined (CONFIG_PCIE_PORT1)
 487 +       /* PCIe Port 1 */
 488 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c), 12, 1, 0x01);     // rg_pe1_pipe_rst_b
 489 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c),  4, 1, 0x01);     // rg_pe1_pipe_cmd_frc[4]
 490 +#endif
 491 +#if defined (CONFIG_PCIE_PORT2)
 492 +       /* PCIe Port 2 */
 493 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c), 12, 1, 0x01);       // rg_pe1_pipe_rst_b
 494 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c),  4, 1, 0x01);       // rg_pe1_pipe_cmd_frc[4]
 495 +#endif
 496 +}
 497 +
 498 +void
 499 +set_phy_for_ssc(void)
 500 +{
 501 +       unsigned long reg = (*(volatile u32 *)(RALINK_SYSCTL_BASE + 0x10));
 502 +
 503 +       reg = (reg >> 6) & 0x7;
 504 +#if defined (CONFIG_PCIE_PORT0) || defined (CONFIG_PCIE_PORT1)
 505 +       /* Set PCIe Port0 & Port1 PHY to disable SSC */
 506 +       /* Debug Xtal Type */
 507 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400),  8, 1, 0x01);     // rg_pe1_frc_h_xtal_type
 508 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400),  9, 2, 0x00);     // rg_pe1_h_xtal_type
 509 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000),  4, 1, 0x01);     // rg_pe1_frc_phy_en               //Force Port 0 enable control
 510 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100),  4, 1, 0x01);     // rg_pe1_frc_phy_en               //Force Port 1 enable control
 511 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000),  5, 1, 0x00);     // rg_pe1_phy_en                   //Port 0 disable
 512 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100),  5, 1, 0x00);     // rg_pe1_phy_en                   //Port 1 disable
 513 +       if(reg <= 5 && reg >= 3) {      // 40MHz Xtal
 514 +               set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),  6, 2, 0x01);     // RG_PE1_H_PLL_PREDIV             //Pre-divider ratio (for host mode)
 515 +               printk("***** Xtal 40MHz *****\n");
 516 +       } else {                        // 25MHz | 20MHz Xtal
 517 +               set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),  6, 2, 0x00);     // RG_PE1_H_PLL_PREDIV             //Pre-divider ratio (for host mode)
 518 +               if (reg >= 6) {
 519 +                       printk("***** Xtal 25MHz *****\n");
 520 +                       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4bc),  4, 2, 0x01);     // RG_PE1_H_PLL_FBKSEL             //Feedback clock select
 521 +                       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x49c),  0,31, 0x18000000);       // RG_PE1_H_LCDDS_PCW_NCPO         //DDS NCPO PCW (for host mode)
 522 +                       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a4),  0,16, 0x18d);    // RG_PE1_H_LCDDS_SSC_PRD          //DDS SSC dither period control
 523 +                       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8),  0,12, 0x4a);     // RG_PE1_H_LCDDS_SSC_DELTA        //DDS SSC dither amplitude control
 524 +                       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8), 16,12, 0x4a);     // RG_PE1_H_LCDDS_SSC_DELTA1       //DDS SSC dither amplitude control for initial
 525 +               } else {
 526 +                       printk("***** Xtal 20MHz *****\n");
 527 +               }
 528 +       }
 529 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a0),  5, 1, 0x01);     // RG_PE1_LCDDS_CLK_PH_INV         //DDS clock inversion
 530 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 22, 2, 0x02);     // RG_PE1_H_PLL_BC
 531 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 18, 4, 0x06);     // RG_PE1_H_PLL_BP
 532 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 12, 4, 0x02);     // RG_PE1_H_PLL_IR
 533 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),  8, 4, 0x01);     // RG_PE1_H_PLL_IC
 534 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4ac), 16, 3, 0x00);     // RG_PE1_H_PLL_BR
 535 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),  1, 3, 0x02);     // RG_PE1_PLL_DIVEN
 536 +       if(reg <= 5 && reg >= 3) {      // 40MHz Xtal
 537 +               set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414),  6, 2, 0x01);     // rg_pe1_mstckdiv              //value of da_pe1_mstckdiv when force mode enable
 538 +               set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414),  5, 1, 0x01);     // rg_pe1_frc_mstckdiv          //force mode enable of da_pe1_mstckdiv
 539 +       }
 540 +       /* Enable PHY and disable force mode */
 541 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000),  5, 1, 0x01);     // rg_pe1_phy_en                   //Port 0 enable
 542 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100),  5, 1, 0x01);     // rg_pe1_phy_en                   //Port 1 enable
 543 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000),  4, 1, 0x00);     // rg_pe1_frc_phy_en               //Force Port 0 disable control
 544 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100),  4, 1, 0x00);     // rg_pe1_frc_phy_en               //Force Port 1 disable control
 545 +#endif
 546 +#if defined (CONFIG_PCIE_PORT2)
 547 +       /* Set PCIe Port2 PHY to disable SSC */
 548 +       /* Debug Xtal Type */
 549 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400),  8, 1, 0x01);       // rg_pe1_frc_h_xtal_type
 550 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400),  9, 2, 0x00);       // rg_pe1_h_xtal_type
 551 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000),  4, 1, 0x01);       // rg_pe1_frc_phy_en               //Force Port 0 enable control
 552 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000),  5, 1, 0x00);       // rg_pe1_phy_en                   //Port 0 disable
 553 +       if(reg <= 5 && reg >= 3) {      // 40MHz Xtal
 554 +               set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490),  6, 2, 0x01);       // RG_PE1_H_PLL_PREDIV             //Pre-divider ratio (for host mode)
 555 +       } else {                        // 25MHz | 20MHz Xtal
 556 +               set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490),  6, 2, 0x00);       // RG_PE1_H_PLL_PREDIV             //Pre-divider ratio (for host mode)
 557 +               if (reg >= 6) {         // 25MHz Xtal
 558 +                       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4bc),  4, 2, 0x01);       // RG_PE1_H_PLL_FBKSEL             //Feedback clock select
 559 +                       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x49c),  0,31, 0x18000000); // RG_PE1_H_LCDDS_PCW_NCPO         //DDS NCPO PCW (for host mode)
 560 +                       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a4),  0,16, 0x18d);      // RG_PE1_H_LCDDS_SSC_PRD          //DDS SSC dither period control
 561 +                       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8),  0,12, 0x4a);       // RG_PE1_H_LCDDS_SSC_DELTA        //DDS SSC dither amplitude control
 562 +                       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8), 16,12, 0x4a);       // RG_PE1_H_LCDDS_SSC_DELTA1       //DDS SSC dither amplitude control for initial
 563 +               }
 564 +       }
 565 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a0),  5, 1, 0x01);       // RG_PE1_LCDDS_CLK_PH_INV         //DDS clock inversion
 566 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 22, 2, 0x02);       // RG_PE1_H_PLL_BC
 567 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 18, 4, 0x06);       // RG_PE1_H_PLL_BP
 568 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 12, 4, 0x02);       // RG_PE1_H_PLL_IR
 569 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490),  8, 4, 0x01);       // RG_PE1_H_PLL_IC
 570 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4ac), 16, 3, 0x00);       // RG_PE1_H_PLL_BR
 571 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490),  1, 3, 0x02);       // RG_PE1_PLL_DIVEN
 572 +       if(reg <= 5 && reg >= 3) {      // 40MHz Xtal
 573 +               set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414),  6, 2, 0x01);       // rg_pe1_mstckdiv              //value of da_pe1_mstckdiv when force mode enable
 574 +               set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414),  5, 1, 0x01);       // rg_pe1_frc_mstckdiv          //force mode enable of da_pe1_mstckdiv
 575 +       }
 576 +       /* Enable PHY and disable force mode */
 577 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000),  5, 1, 0x01);       // rg_pe1_phy_en                   //Port 0 enable
 578 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000),  4, 1, 0x00);       // rg_pe1_frc_phy_en               //Force Port 0 disable control
 579 +#endif
 580 +}
 581 +
 582 +void setup_cm_memory_region(struct resource *mem_resource)
 583 +{
 584 +       resource_size_t mask;
 585 +       if (mips_cm_numiocu()) {
 586 +               /* FIXME: hardware doesn't accept mask values with 1s after
 587 +                  0s (e.g. 0xffef), so it would be great to warn if that's
 588 +                  about to happen */
 589 +               mask = ~(mem_resource->end - mem_resource->start);
 590 +
 591 +               write_gcr_reg1_base(mem_resource->start);
 592 +               write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0);
 593 +               printk("PCI coherence region base: 0x%08lx, mask/settings: 0x%08lx\n",
 594 +                      read_gcr_reg1_base(),
 595 +                      read_gcr_reg1_mask());
 596 +       }
 597 +}
 598 +
 599 +static int mt7621_pci_probe(struct platform_device *pdev)
 600 +{
 601 +       unsigned long val = 0;
 602 +
 603 +       iomem_resource.start = 0;
 604 +       iomem_resource.end= ~0;
 605 +       ioport_resource.start= 0;
 606 +       ioport_resource.end = ~0;
 607 +
 608 +#if defined (CONFIG_PCIE_PORT0)
 609 +       val = RALINK_PCIE0_RST;
 610 +#endif
 611 +#if defined (CONFIG_PCIE_PORT1)
 612 +       val |= RALINK_PCIE1_RST;
 613 +#endif
 614 +#if defined (CONFIG_PCIE_PORT2)
 615 +       val |= RALINK_PCIE2_RST;
 616 +#endif
 617 +       ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST | RALINK_PCIE1_RST | RALINK_PCIE2_RST);
 618 +       printk("pull PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
 619 +#if defined GPIO_PERST /* add GPIO control instead of PERST_N */ /*chhung*/
 620 +       *(unsigned int *)(0xbe000060) &= ~(0x3<<10 | 0x3<<3);
 621 +       *(unsigned int *)(0xbe000060) |= 0x1<<10 | 0x1<<3;
 622 +       mdelay(100);
 623 +       *(unsigned int *)(0xbe000600) |= 0x1<<19 | 0x1<<8 | 0x1<<7; // use GPIO19/GPIO8/GPIO7 (PERST_N/UART_RXD3/UART_TXD3)
 624 +       mdelay(100);
 625 +       *(unsigned int *)(0xbe000620) &= ~(0x1<<19 | 0x1<<8 | 0x1<<7);          // clear DATA
 626 +
 627 +       mdelay(100);
 628 +#else
 629 +       *(unsigned int *)(0xbe000060) &= ~0x00000c00;
 630 +#endif
 631 +#if defined (CONFIG_PCIE_PORT0)
 632 +       val = RALINK_PCIE0_RST;
 633 +#endif
 634 +#if defined (CONFIG_PCIE_PORT1)
 635 +       val |= RALINK_PCIE1_RST;
 636 +#endif
 637 +#if defined (CONFIG_PCIE_PORT2)
 638 +       val |= RALINK_PCIE2_RST;
 639 +#endif
 640 +       DEASSERT_SYSRST_PCIE(val);
 641 +       printk("release PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
 642 +
 643 +       if ((*(unsigned int *)(0xbe00000c)&0xFFFF) == 0x0101) // MT7621 E2
 644 +               bypass_pipe_rst();
 645 +       set_phy_for_ssc();
 646 +       printk("release PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
 647 +
 648 +#if defined (CONFIG_PCIE_PORT0)
 649 +       read_config(0, 0, 0, 0x70c, &val);
 650 +       printk("Port 0 N_FTS = %x\n", (unsigned int)val);
 651 +#endif
 652 +#if defined (CONFIG_PCIE_PORT1)
 653 +       read_config(0, 1, 0, 0x70c, &val);
 654 +       printk("Port 1 N_FTS = %x\n", (unsigned int)val);
 655 +#endif
 656 +#if defined (CONFIG_PCIE_PORT2)
 657 +       read_config(0, 2, 0, 0x70c, &val);
 658 +       printk("Port 2 N_FTS = %x\n", (unsigned int)val);
 659 +#endif
 660 +
 661 +       RALINK_RSTCTRL = (RALINK_RSTCTRL | RALINK_PCIE_RST);
 662 +       RALINK_SYSCFG1 &= ~(0x30);
 663 +       RALINK_SYSCFG1 |= (2<<4);
 664 +       RALINK_PCIE_CLK_GEN &= 0x7fffffff;
 665 +       RALINK_PCIE_CLK_GEN1 &= 0x80ffffff;
 666 +       RALINK_PCIE_CLK_GEN1 |= 0xa << 24;
 667 +       RALINK_PCIE_CLK_GEN |= 0x80000000;
 668 +       mdelay(50);
 669 +       RALINK_RSTCTRL = (RALINK_RSTCTRL & ~RALINK_PCIE_RST);
 670 +
 671 +
 672 +#if defined GPIO_PERST /* add GPIO control instead of PERST_N */  /*chhung*/
 673 +       *(unsigned int *)(0xbe000620) |= 0x1<<19 | 0x1<<8 | 0x1<<7;             // set DATA
 674 +       mdelay(100);
 675 +#else
 676 +       RALINK_PCI_PCICFG_ADDR &= ~(1<<1); //de-assert PERST
 677 +#endif
 678 +       mdelay(500);
 679 +
 680 +
 681 +       mdelay(500);
 682 +#if defined (CONFIG_PCIE_PORT0)
 683 +       if(( RALINK_PCI0_STATUS & 0x1) == 0)
 684 +       {
 685 +               printk("PCIE0 no card, disable it(RST&CLK)\n");
 686 +               ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST);
 687 +               RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE0_CLK_EN);
 688 +               pcie_link_status &= ~(1<<0);
 689 +       } else {
 690 +               pcie_link_status |= 1<<0;
 691 +               RALINK_PCI_PCIMSK_ADDR |= (1<<20); // enable pcie1 interrupt
 692 +       }
 693 +#endif
 694 +#if defined (CONFIG_PCIE_PORT1)
 695 +       if(( RALINK_PCI1_STATUS & 0x1) == 0)
 696 +       {
 697 +               printk("PCIE1 no card, disable it(RST&CLK)\n");
 698 +               ASSERT_SYSRST_PCIE(RALINK_PCIE1_RST);
 699 +               RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE1_CLK_EN);
 700 +               pcie_link_status &= ~(1<<1);
 701 +       } else {
 702 +               pcie_link_status |= 1<<1;
 703 +               RALINK_PCI_PCIMSK_ADDR |= (1<<21); // enable pcie1 interrupt
 704 +       }
 705 +#endif
 706 +#if defined (CONFIG_PCIE_PORT2)
 707 +       if (( RALINK_PCI2_STATUS & 0x1) == 0) {
 708 +               printk("PCIE2 no card, disable it(RST&CLK)\n");
 709 +               ASSERT_SYSRST_PCIE(RALINK_PCIE2_RST);
 710 +               RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE2_CLK_EN);
 711 +               pcie_link_status &= ~(1<<2);
 712 +       } else {
 713 +               pcie_link_status |= 1<<2;
 714 +               RALINK_PCI_PCIMSK_ADDR |= (1<<22); // enable pcie2 interrupt
 715 +       }
 716 +#endif
 717 +       if (pcie_link_status == 0)
 718 +               return 0;
 719 +
 720 +/*
 721 +pcie(2/1/0) link status        pcie2_num       pcie1_num       pcie0_num
 722 +3'b000                 x               x               x
 723 +3'b001                 x               x               0
 724 +3'b010                 x               0               x
 725 +3'b011                 x               1               0
 726 +3'b100                 0               x               x
 727 +3'b101                 1               x               0
 728 +3'b110                 1               0               x
 729 +3'b111                 2               1               0
 730 +*/
 731 +       switch(pcie_link_status) {
 732 +       case 2:
 733 +               RALINK_PCI_PCICFG_ADDR &= ~0x00ff0000;
 734 +               RALINK_PCI_PCICFG_ADDR |= 0x1 << 16;    //port0
 735 +               RALINK_PCI_PCICFG_ADDR |= 0x0 << 20;    //port1
 736 +               break;
 737 +       case 4:
 738 +               RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000;
 739 +               RALINK_PCI_PCICFG_ADDR |= 0x1 << 16;    //port0
 740 +               RALINK_PCI_PCICFG_ADDR |= 0x2 << 20;    //port1
 741 +               RALINK_PCI_PCICFG_ADDR |= 0x0 << 24;    //port2
 742 +               break;
 743 +       case 5:
 744 +               RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000;
 745 +               RALINK_PCI_PCICFG_ADDR |= 0x0 << 16;    //port0
 746 +               RALINK_PCI_PCICFG_ADDR |= 0x2 << 20;    //port1
 747 +               RALINK_PCI_PCICFG_ADDR |= 0x1 << 24;    //port2
 748 +               break;
 749 +       case 6:
 750 +               RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000;
 751 +               RALINK_PCI_PCICFG_ADDR |= 0x2 << 16;    //port0
 752 +               RALINK_PCI_PCICFG_ADDR |= 0x0 << 20;    //port1
 753 +               RALINK_PCI_PCICFG_ADDR |= 0x1 << 24;    //port2
 754 +               break;
 755 +       }
 756 +       printk(" -> %x\n", RALINK_PCI_PCICFG_ADDR);
 757 +       //printk(" RALINK_PCI_ARBCTL = %x\n", RALINK_PCI_ARBCTL);
 758 +
 759 +/*
 760 +       ioport_resource.start = mt7621_res_pci_io1.start;
 761 +       ioport_resource.end = mt7621_res_pci_io1.end;
 762 +*/
 763 +
 764 +       RALINK_PCI_MEMBASE = 0xffffffff; //RALINK_PCI_MM_MAP_BASE;
 765 +       RALINK_PCI_IOBASE = RALINK_PCI_IO_MAP_BASE;
 766 +
 767 +#if defined (CONFIG_PCIE_PORT0)
 768 +       //PCIe0
 769 +       if((pcie_link_status & 0x1) != 0) {
 770 +               RALINK_PCI0_BAR0SETUP_ADDR = 0x7FFF0001;        //open 7FFF:2G; ENABLE
 771 +               RALINK_PCI0_IMBASEBAR0_ADDR = MEMORY_BASE;
 772 +               RALINK_PCI0_CLASS = 0x06040001;
 773 +               printk("PCIE0 enabled\n");
 774 +       }
 775 +#endif
 776 +#if defined (CONFIG_PCIE_PORT1)
 777 +       //PCIe1
 778 +       if ((pcie_link_status & 0x2) != 0) {
 779 +               RALINK_PCI1_BAR0SETUP_ADDR = 0x7FFF0001;        //open 7FFF:2G; ENABLE
 780 +               RALINK_PCI1_IMBASEBAR0_ADDR = MEMORY_BASE;
 781 +               RALINK_PCI1_CLASS = 0x06040001;
 782 +               printk("PCIE1 enabled\n");
 783 +       }
 784 +#endif
 785 +#if defined (CONFIG_PCIE_PORT2)
 786 +       //PCIe2
 787 +       if ((pcie_link_status & 0x4) != 0) {
 788 +               RALINK_PCI2_BAR0SETUP_ADDR = 0x7FFF0001;        //open 7FFF:2G; ENABLE
 789 +               RALINK_PCI2_IMBASEBAR0_ADDR = MEMORY_BASE;
 790 +               RALINK_PCI2_CLASS = 0x06040001;
 791 +               printk("PCIE2 enabled\n");
 792 +       }
 793 +#endif
 794 +
 795 +
 796 +       switch(pcie_link_status) {
 797 +       case 7:
 798 +               read_config(0, 2, 0, 0x4, &val);
 799 +               write_config(0, 2, 0, 0x4, val|0x4);
 800 +               // write_config(0, 1, 0, 0x4, val|0x7);
 801 +               read_config(0, 2, 0, 0x70c, &val);
 802 +               val &= ~(0xff)<<8;
 803 +               val |= 0x50<<8;
 804 +               write_config(0, 2, 0, 0x70c, val);
 805 +       case 3:
 806 +       case 5:
 807 +       case 6:
 808 +               read_config(0, 1, 0, 0x4, &val);
 809 +               write_config(0, 1, 0, 0x4, val|0x4);
 810 +               // write_config(0, 1, 0, 0x4, val|0x7);
 811 +               read_config(0, 1, 0, 0x70c, &val);
 812 +               val &= ~(0xff)<<8;
 813 +               val |= 0x50<<8;
 814 +               write_config(0, 1, 0, 0x70c, val);
 815 +       default:
 816 +               read_config(0, 0, 0, 0x4, &val);
 817 +               write_config(0, 0, 0, 0x4, val|0x4); //bus master enable
 818 +               // write_config(0, 0, 0, 0x4, val|0x7); //bus master enable
 819 +               read_config(0, 0, 0, 0x70c, &val);
 820 +               val &= ~(0xff)<<8;
 821 +               val |= 0x50<<8;
 822 +               write_config(0, 0, 0, 0x70c, val);
 823 +       }
 824 +
 825 +       pci_load_of_ranges(&mt7621_controller, pdev->dev.of_node);
 826 +       setup_cm_memory_region(mt7621_controller.mem_resource);
 827 +       register_pci_controller(&mt7621_controller);
 828 +       return 0;
 829 +
 830 +}
 831 +
 832 +int pcibios_plat_dev_init(struct pci_dev *dev)
 833 +{
 834 +       return 0;
 835 +}
 836 +
 837 +static const struct of_device_id mt7621_pci_ids[] = {
 838 +       { .compatible = "mediatek,mt7621-pci" },
 839 +       {},
 840 +};
 841 +MODULE_DEVICE_TABLE(of, mt7621_pci_ids);
 842 +
 843 +static struct platform_driver mt7621_pci_driver = {
 844 +       .probe = mt7621_pci_probe,
 845 +       .driver = {
 846 +               .name = "mt7621-pci",
 847 +               .owner = THIS_MODULE,
 848 +               .of_match_table = of_match_ptr(mt7621_pci_ids),
 849 +       },
 850 +};
 851 +
 852 +static int __init mt7621_pci_init(void)
 853 +{
 854 +       return platform_driver_register(&mt7621_pci_driver);
 855 +}
 856 +
 857 +arch_initcall(mt7621_pci_init);