target/linux/ramips/patches-4.4/0504-net-next-mediatek-add-switch-driver-for-mt7621.patch

   1 From 9fc19d5f7354709298dcb15b3a4c7cd9a18acebf Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Mon, 14 Dec 2015 21:24:46 +0100
   4 Subject: [PATCH 504/513] net-next: mediatek: add switch driver for mt7621
   5
   6 This driver is very basic and only provides basic init and irq support.
   7 Switchdev support for this device will follow.
   8
   9 Signed-off-by: John Crispin <blogic@openwrt.org>
  10 ---
  11  drivers/net/ethernet/mediatek/gsw_mt7621.c |  284 ++++++++++++++++++++++++++++
  12  1 file changed, 284 insertions(+)
  13  create mode 100644 drivers/net/ethernet/mediatek/gsw_mt7621.c
  14
  15 --- /dev/null
  16 +++ b/drivers/net/ethernet/mediatek/gsw_mt7621.c
  17 @@ -0,0 +1,287 @@
  18 +/*   This program is free software; you can redistribute it and/or modify
  19 + *   it under the terms of the GNU General Public License as published by
  20 + *   the Free Software Foundation; version 2 of the License
  21 + *
  22 + *   This program is distributed in the hope that it will be useful,
  23 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  24 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  25 + *   GNU General Public License for more details.
  26 + *
  27 + *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
  28 + *   Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
  29 + *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
  30 + */
  31 +
  32 +#include <linux/module.h>
  33 +#include <linux/kernel.h>
  34 +#include <linux/types.h>
  35 +#include <linux/platform_device.h>
  36 +#include <linux/of_device.h>
  37 +#include <linux/of_irq.h>
  38 +
  39 +#include <ralink_regs.h>
  40 +
  41 +#include "mtk_eth_soc.h"
  42 +#include "gsw_mt7620.h"
  43 +
  44 +void mtk_switch_w32(struct mt7620_gsw *gsw, u32 val, unsigned reg)
  45 +{
  46 +       iowrite32(val, gsw->base + reg);
  47 +}
  48 +
  49 +u32 mtk_switch_r32(struct mt7620_gsw *gsw, unsigned reg)
  50 +{
  51 +       return ioread32(gsw->base + reg);
  52 +}
  53 +
  54 +static irqreturn_t gsw_interrupt_mt7621(int irq, void *_priv)
  55 +{
  56 +       struct fe_priv *priv = (struct fe_priv *)_priv;
  57 +       struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;
  58 +       u32 reg, i;
  59 +
  60 +       reg = mt7530_mdio_r32(gsw, 0x700c);
  61 +
  62 +       for (i = 0; i < 5; i++)
  63 +               if (reg & BIT(i)) {
  64 +                       unsigned int link;
  65 +
  66 +                       link = mt7530_mdio_r32(gsw,
  67 +                                              0x3008 + (i * 0x100)) & 0x1;
  68 +
  69 +                       if (link != priv->link[i]) {
  70 +                               priv->link[i] = link;
  71 +                               if (link)
  72 +                                       netdev_info(priv->netdev,
  73 +                                                   "port %d link up\n", i);
  74 +                               else
  75 +                                       netdev_info(priv->netdev,
  76 +                                                   "port %d link down\n", i);
  77 +                       }
  78 +               }
  79 +
  80 +       mt7530_mdio_w32(gsw, 0x700c, 0x1f);
  81 +
  82 +       return IRQ_HANDLED;
  83 +}
  84 +
  85 +static void mt7621_hw_init(struct mt7620_gsw *gsw, struct device_node *np)
  86 +{
  87 +       u32 i;
  88 +       u32 val;
  89 +
  90 +       /* wardware reset the switch */
  91 +       fe_reset(RST_CTRL_MCM);
  92 +       mdelay(10);
  93 +
  94 +       /* reduce RGMII2 PAD driving strength */
  95 +       rt_sysc_m32(3 << 4, 0, SYSC_PAD_RGMII2_MDIO);
  96 +
  97 +       /* gpio mux - RGMII1=Normal mode */
  98 +       rt_sysc_m32(BIT(14), 0, SYSC_GPIO_MODE);
  99 +
 100 +       /* set GMAC1 RGMII mode */
 101 +       rt_sysc_m32(3 << 12, 0, SYSC_REG_CFG1);
 102 +
 103 +       /* enable MDIO to control MT7530 */
 104 +       rt_sysc_m32(3 << 12, 0, SYSC_GPIO_MODE);
 105 +
 106 +       /* turn off all PHYs */
 107 +       for (i = 0; i <= 4; i++) {
 108 +               val = _mt7620_mii_read(gsw, i, 0x0);
 109 +               val |= BIT(11);
 110 +               _mt7620_mii_write(gsw, i, 0x0, val);
 111 +       }
 112 +
 113 +       /* reset the switch */
 114 +       mt7530_mdio_w32(gsw, 0x7000, 0x3);
 115 +       usleep_range(10, 20);
 116 +
 117 +       if ((rt_sysc_r32(SYSC_REG_CHIP_REV_ID) & 0xFFFF) == 0x0101) {
 118 +               /* (GE1, Force 1000M/FD, FC ON, MAX_RX_LENGTH 2k) */
 119 +               mtk_switch_w32(gsw, 0x2305e30b, GSW_REG_MAC_P0_MCR);
 120 +               mt7530_mdio_w32(gsw, 0x3600, 0x5e30b);
 121 +       } else {
 122 +               /* (GE1, Force 1000M/FD, FC ON, MAX_RX_LENGTH 2k) */
 123 +               mtk_switch_w32(gsw, 0x2305e33b, GSW_REG_MAC_P0_MCR);
 124 +               mt7530_mdio_w32(gsw, 0x3600, 0x5e33b);
 125 +       }
 126 +
 127 +       /* (GE2, Link down) */
 128 +       mtk_switch_w32(gsw, 0x8000, GSW_REG_MAC_P1_MCR);
 129 +
 130 +       /* Set switch max RX frame length to 2k */
 131 +       mt7530_mdio_w32(gsw, GSW_REG_GMACCR, 0x3F0B);
 132 +
 133 +       /* Enable Port 6, P5 as GMAC5, P5 disable */
 134 +       val = mt7530_mdio_r32(gsw, 0x7804);
 135 +       val &= ~BIT(8);
 136 +       val |= BIT(6) | BIT(13) | BIT(16);
 137 +       mt7530_mdio_w32(gsw, 0x7804, val);
 138 +
 139 +       val = rt_sysc_r32(0x10);
 140 +       val = (val >> 6) & 0x7;
 141 +       if (val >= 6) {
 142 +               /* 25Mhz Xtal - do nothing */
 143 +       } else if (val >= 3) {
 144 +               /* 40Mhz */
 145 +
 146 +               /* disable MT7530 core clock */
 147 +               _mt7620_mii_write(gsw, 0, 13, 0x1f);
 148 +               _mt7620_mii_write(gsw, 0, 14, 0x410);
 149 +               _mt7620_mii_write(gsw, 0, 13, 0x401f);
 150 +               _mt7620_mii_write(gsw, 0, 14, 0x0);
 151 +
 152 +               /* disable MT7530 PLL */
 153 +               _mt7620_mii_write(gsw, 0, 13, 0x1f);
 154 +               _mt7620_mii_write(gsw, 0, 14, 0x40d);
 155 +               _mt7620_mii_write(gsw, 0, 13, 0x401f);
 156 +               _mt7620_mii_write(gsw, 0, 14, 0x2020);
 157 +
 158 +               /* for MT7530 core clock = 500Mhz */
 159 +               _mt7620_mii_write(gsw, 0, 13, 0x1f);
 160 +               _mt7620_mii_write(gsw, 0, 14, 0x40e);
 161 +               _mt7620_mii_write(gsw, 0, 13, 0x401f);
 162 +               _mt7620_mii_write(gsw, 0, 14, 0x119);
 163 +
 164 +               /* enable MT7530 PLL */
 165 +               _mt7620_mii_write(gsw, 0, 13, 0x1f);
 166 +               _mt7620_mii_write(gsw, 0, 14, 0x40d);
 167 +               _mt7620_mii_write(gsw, 0, 13, 0x401f);
 168 +               _mt7620_mii_write(gsw, 0, 14, 0x2820);
 169 +
 170 +               usleep_range(20, 40);
 171 +
 172 +               /* enable MT7530 core clock */
 173 +               _mt7620_mii_write(gsw, 0, 13, 0x1f);
 174 +               _mt7620_mii_write(gsw, 0, 14, 0x410);
 175 +               _mt7620_mii_write(gsw, 0, 13, 0x401f);
 176 +       } else {
 177 +               /* 20Mhz Xtal - TODO */
 178 +       }
 179 +
 180 +       /* RGMII */
 181 +       _mt7620_mii_write(gsw, 0, 14, 0x1);
 182 +
 183 +       /* set MT7530 central align */
 184 +       val = mt7530_mdio_r32(gsw, 0x7830);
 185 +       val &= ~BIT(0);
 186 +       val |= BIT(1);
 187 +       mt7530_mdio_w32(gsw, 0x7830, val);
 188 +       val = mt7530_mdio_r32(gsw, 0x7a40);
 189 +       val &= ~BIT(30);
 190 +       mt7530_mdio_w32(gsw, 0x7a40, val);
 191 +       mt7530_mdio_w32(gsw, 0x7a78, 0x855);
 192 +
 193 +       /* delay setting for 10/1000M */
 194 +       mt7530_mdio_w32(gsw, 0x7b00, 0x102);
 195 +       mt7530_mdio_w32(gsw, 0x7b04, 0x14);
 196 +
 197 +       /* lower Tx Driving*/
 198 +       mt7530_mdio_w32(gsw, 0x7a54, 0x44);
 199 +       mt7530_mdio_w32(gsw, 0x7a5c, 0x44);
 200 +       mt7530_mdio_w32(gsw, 0x7a64, 0x44);
 201 +       mt7530_mdio_w32(gsw, 0x7a6c, 0x44);
 202 +       mt7530_mdio_w32(gsw, 0x7a74, 0x44);
 203 +       mt7530_mdio_w32(gsw, 0x7a7c, 0x44);
 204 +
 205 +       /* turn on all PHYs */
 206 +       for (i = 0; i <= 4; i++) {
 207 +               val = _mt7620_mii_read(gsw, i, 0);
 208 +               val &= ~BIT(11);
 209 +               _mt7620_mii_write(gsw, i, 0, val);
 210 +       }
 211 +
 212 +       /* enable irq */
 213 +       val = mt7530_mdio_r32(gsw, 0x7808);
 214 +       val |= 3 << 16;
 215 +       mt7530_mdio_w32(gsw, 0x7808, val);
 216 +}
 217 +
 218 +static const struct of_device_id mediatek_gsw_match[] = {
 219 +       { .compatible = "mediatek,mt7621-gsw" },
 220 +       {},
 221 +};
 222 +MODULE_DEVICE_TABLE(of, mediatek_gsw_match);
 223 +
 224 +int mtk_gsw_init(struct fe_priv *priv)
 225 +{
 226 +       struct device_node *np = priv->switch_np;
 227 +       struct platform_device *pdev = of_find_device_by_node(np);
 228 +       struct mt7620_gsw *gsw;
 229 +
 230 +       if (!pdev)
 231 +               return -ENODEV;
 232 +
 233 +       if (!of_device_is_compatible(np, mediatek_gsw_match->compatible))
 234 +               return -EINVAL;
 235 +
 236 +       gsw = platform_get_drvdata(pdev);
 237 +       priv->soc->swpriv = gsw;
 238 +
 239 +       mt7621_hw_init(gsw, np);
 240 +
 241 +       if (gsw->irq) {
 242 +               request_irq(gsw->irq, gsw_interrupt_mt7621, 0,
 243 +                           "gsw", priv);
 244 +               mt7530_mdio_w32(gsw, 0x7008, 0x1f);
 245 +       }
 246 +
 247 +       return 0;
 248 +}
 249 +
 250 +static int mt7621_gsw_probe(struct platform_device *pdev)
 251 +{
 252 +       struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 253 +       const char *port4 = NULL;
 254 +       struct mt7620_gsw *gsw;
 255 +       struct device_node *np;
 256 +
 257 +       gsw = devm_kzalloc(&pdev->dev, sizeof(struct mt7620_gsw), GFP_KERNEL);
 258 +       if (!gsw)
 259 +               return -ENOMEM;
 260 +
 261 +       gsw->base = devm_ioremap_resource(&pdev->dev, res);
 262 +       if (!gsw->base)
 263 +               return -EADDRNOTAVAIL;
 264 +
 265 +       gsw->dev = &pdev->dev;
 266 +
 267 +       of_property_read_string(np, "mediatek,port4", &port4);
 268 +       if (port4 && !strcmp(port4, "ephy"))
 269 +               gsw->port4 = PORT4_EPHY;
 270 +       else if (port4 && !strcmp(port4, "gmac"))
 271 +               gsw->port4 = PORT4_EXT;
 272 +       else
 273 +               gsw->port4 = PORT4_EPHY;
 274 +
 275 +       gsw->irq = platform_get_irq(pdev, 0);
 276 +
 277 +       platform_set_drvdata(pdev, gsw);
 278 +
 279 +       return 0;
 280 +}
 281 +
 282 +static int mt7621_gsw_remove(struct platform_device *pdev)
 283 +{
 284 +       platform_set_drvdata(pdev, NULL);
 285 +
 286 +       return 0;
 287 +}
 288 +
 289 +static struct platform_driver gsw_driver = {
 290 +       .probe = mt7621_gsw_probe,
 291 +       .remove = mt7621_gsw_remove,
 292 +       .driver = {
 293 +               .name = "mt7621-gsw",
 294 +               .owner = THIS_MODULE,
 295 +               .of_match_table = mediatek_gsw_match,
 296 +       },
 297 +};
 298 +
 299 +module_platform_driver(gsw_driver);
 300 +
 301 +MODULE_LICENSE("GPL");
 302 +MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
 303 +MODULE_DESCRIPTION("GBit switch driver for Mediatek MT7621 SoC");
 304 +MODULE_VERSION(MTK_FE_DRV_VERSION);