target/linux/realtek/dts-5.10/rtl8382_panasonic_m24eg-pn28240k.dts

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2
   3 #include "rtl838x.dtsi"
   4 #include "rtl83xx_panasonic_mxxeg-pn28xx0k.dtsi"
   5
   6 #include <dt-bindings/interrupt-controller/irq.h>
   7
   8 / {
   9         compatible = "panasonic,m24eg-pn28240k", "realtek,rtl8382-soc";
  10         model = "Panasonic Switch-M24eG PN28240K";
  11
  12         aliases {
  13                 led-boot = &led_status_eco_green;
  14                 led-failsafe = &led_status_eco_amber;
  15                 led-running = &led_status_eco_green;
  16                 led-upgrade = &led_status_eco_green;
  17         };
  18
  19         /*
  20          * sfp0/1 are "combo" port with each TP port (23/24), and they are
  21          * connected to the RTL8218FB. Currently, there is no support for
  22          * the chip and only TP ports work by the RTL8218D support.
  23          */
  24         sfp0: sfp-p23 {
  25                 compatible = "sff,sfp";
  26                 i2c-bus = <&i2c0>;
  27                 tx-fault-gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
  28                 tx-disable-gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>;
  29                 mod-def0-gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
  30                 los-gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>;
  31         };
  32
  33         sfp1: sfp-p24 {
  34                 compatible = "sff,sfp";
  35                 i2c-bus = <&i2c1>;
  36                 tx-fault-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
  37                 tx-disable-gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
  38                 mod-def0-gpio = <&gpio1 6 GPIO_ACTIVE_LOW>;
  39                 los-gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
  40         };
  41 };
  42
  43 &leds {
  44         led_status_eco_amber: led-5 {
  45                 label = "amber:status_eco";
  46                 gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
  47                 color = <LED_COLOR_ID_AMBER>;
  48                 function = LED_FUNCTION_STATUS;
  49                 function-enumerator = <1>;
  50         };
  51
  52         led_status_eco_green: led-6 {
  53                 label = "green:status_eco";
  54                 gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
  55                 color = <LED_COLOR_ID_GREEN>;
  56                 function = LED_FUNCTION_STATUS;
  57                 function-enumerator = <2>;
  58         };
  59 };
  60
  61 &i2c_gpio_0 {
  62         scl-gpios = <&gpio0 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
  63         sda-gpios = <&gpio0 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
  64 };
  65
  66 &i2c_gpio_1 {
  67         scl-gpios = <&gpio0 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
  68         sda-gpios = <&gpio0 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
  69 };
  70
  71 &gpio2 {
  72         interrupt-controller;
  73         #interrupt-cells = <2>;
  74         interrupt-parent = <&gpio0>;
  75         interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
  76
  77         /*
  78          * GPIO12 (IO1_4): RTL8218B + RTL8218FB
  79          *
  80          * This GPIO pin should be specified as "reset-gpio" in mdio node,
  81          * but the current configuration of RTL8218B phy in the phy driver
  82          * seems to be incomplete and RTL8218FB phy won't be configured on
  83          * RTL8218D support. So, ethernet ports on these phys will be broken
  84          * after hard-resetting.
  85          * (RTL8218FB phy will be detected as RTL8218D by the phy driver)
  86          * At the moment, configure this GPIO pin as gpio-hog to avoid breaking
  87          * by resetting.
  88          */
  89         ext_switch_reset {
  90                 gpio-hog;
  91                 gpios = <12 GPIO_ACTIVE_HIGH>;
  92                 output-high;
  93                 line-name = "ext-switch-reset";
  94         };
  95 };
  96
  97 &i2c_switch {
  98         i2c0: i2c@0 {
  99                 #address-cells = <1>;
 100                 #size-cells = <0>;
 101                 reg = <0>;
 102         };
 103
 104         i2c1: i2c@1 {
 105                 #address-cells = <1>;
 106                 #size-cells = <0>;
 107                 reg = <1>;
 108         };
 109 };
 110
 111 &ethernet0 {
 112         mdio-bus {
 113                 compatible = "realtek,rtl838x-mdio";
 114                 #address-cells = <1>;
 115                 #size-cells = <0>;
 116
 117                 EXTERNAL_PHY(0)
 118                 EXTERNAL_PHY(1)
 119                 EXTERNAL_PHY(2)
 120                 EXTERNAL_PHY(3)
 121                 EXTERNAL_PHY(4)
 122                 EXTERNAL_PHY(5)
 123                 EXTERNAL_PHY(6)
 124                 EXTERNAL_PHY(7)
 125
 126                 INTERNAL_PHY(8)
 127                 INTERNAL_PHY(9)
 128                 INTERNAL_PHY(10)
 129                 INTERNAL_PHY(11)
 130                 INTERNAL_PHY(12)
 131                 INTERNAL_PHY(13)
 132                 INTERNAL_PHY(14)
 133                 INTERNAL_PHY(15)
 134
 135                 /* RTL8218FB */
 136                 EXTERNAL_PHY(16)
 137                 EXTERNAL_PHY(17)
 138                 EXTERNAL_PHY(18)
 139                 EXTERNAL_PHY(19)
 140                 EXTERNAL_PHY(20)
 141                 EXTERNAL_PHY(21)
 142                 EXTERNAL_PHY(22)
 143                 EXTERNAL_PHY(23)
 144         };
 145 };
 146
 147 &switch0 {
 148         ports {
 149                 #address-cells = <1>;
 150                 #size-cells = <0>;
 151
 152                 SWITCH_PORT(0, 1, qsgmii)
 153                 SWITCH_PORT(1, 2, qsgmii)
 154                 SWITCH_PORT(2, 3, qsgmii)
 155                 SWITCH_PORT(3, 4, qsgmii)
 156                 SWITCH_PORT(4, 5, qsgmii)
 157                 SWITCH_PORT(5, 6, qsgmii)
 158                 SWITCH_PORT(6, 7, qsgmii)
 159                 SWITCH_PORT(7, 8, qsgmii)
 160
 161                 SWITCH_PORT(8, 9, internal)
 162                 SWITCH_PORT(9, 10, internal)
 163                 SWITCH_PORT(10, 11, internal)
 164                 SWITCH_PORT(11, 12, internal)
 165                 SWITCH_PORT(12, 13, internal)
 166                 SWITCH_PORT(13, 14, internal)
 167                 SWITCH_PORT(14, 15, internal)
 168                 SWITCH_PORT(15, 16, internal)
 169
 170                 SWITCH_PORT(16, 17, qsgmii)
 171                 SWITCH_PORT(17, 18, qsgmii)
 172                 SWITCH_PORT(18, 19, qsgmii)
 173                 SWITCH_PORT(19, 20, qsgmii)
 174                 SWITCH_PORT(20, 21, qsgmii)
 175                 SWITCH_PORT(21, 22, qsgmii)
 176                 SWITCH_PORT(22, 23, qsgmii)
 177                 SWITCH_PORT(23, 24, qsgmii)
 178
 179                 port@28 {
 180                         ethernet = <&ethernet0>;
 181                         reg = <28>;
 182                         phy-mode = "internal";
 183
 184                         fixed-link {
 185                                 speed = <1000>;
 186                                 full-duplex;
 187                         };
 188                 };
 189         };
 190 };