8dd4cfdc928ce677e1fdc8ed4aaeec0e5e2e1068
[openwrt/openwrt.git] / target / linux / realtek / dts-5.10 / rtl931x.dtsi
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
3 #include <dt-bindings/interrupt-controller/mips-gic.h>
4
5 / {
6 #address-cells = <1>;
7 #size-cells = <1>;
8
9 compatible = "realtek,rtl838x-soc";
10
11 cpus {
12 #address-cells = <1>;
13 #size-cells = <0>;
14 frequency = <1000000000>;
15
16 cpu@0 {
17 compatible = "mti,interaptive";
18 reg = <0>;
19 };
20
21 cpu@1 {
22 compatible = "mti,interaptive";
23 reg = <1>;
24 };
25 };
26
27 memory@0 {
28 device_type = "memory";
29 reg = <0x0 0x10000000>;
30 };
31
32 chosen {
33 bootargs = "console=ttyS0,38400";
34 };
35
36 lx_clk: lx_clk {
37 compatible = "fixed-clock";
38 #clock-cells = <0>;
39 clock-frequency = <200000000>;
40 };
41
42 cpuclock: cpuclock@0 {
43 #clock-cells = <0>;
44 compatible = "fixed-clock";
45
46 /* FIXME: there should be way to detect this */
47 clock-frequency = <1000000000>;
48 };
49
50 cpuintc: cpuintc {
51 compatible = "mti,cpu-interrupt-controller";
52 #address-cells = <0>;
53 #interrupt-cells = <1>;
54 interrupt-controller;
55 };
56
57 gic: interrupt-controller@1ddc0000 {
58 compatible = "mti,gic";
59 reg = <0x1ddc0000 0x20000>;
60
61 interrupt-controller;
62 #interrupt-cells = <3>;
63
64 /*
65 * Declare the interrupt-parent even though the mti,gic
66 * binding doesn't require it, such that the kernel can
67 * figure out that cpu_intc is the root interrupt
68 * controller & should be probed first.
69 */
70 interrupt-parent = <&cpuintc>;
71
72 timer {
73 compatible = "mti,gic-timer";
74 interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
75 clocks = <&cpuclock>;
76 };
77 };
78
79 soc: soc {
80 compatible = "simple-bus";
81 #address-cells = <1>;
82 #size-cells = <1>;
83 ranges = <0x0 0x18000000 0x10000>;
84
85 spi0: spi@1200 {
86 status = "okay";
87
88 compatible = "realtek,rtl8380-spi";
89 reg = <0x1200 0x100>;
90
91 #address-cells = <1>;
92 #size-cells = <0>;
93 };
94
95 watchdog0: watchdog@3260 {
96 compatible = "realtek,rtl9310-wdt";
97 reg = <0x3260 0xc>;
98
99 realtek,reset-mode = "soc";
100
101 clocks = <&lx_clk>;
102 timeout-sec = <30>;
103
104 interrupt-parent = <&gic>;
105 interrupt-names = "phase1", "phase2";
106 interrupts = <GIC_SHARED 8 IRQ_TYPE_LEVEL_HIGH>, <GIC_SHARED 9 IRQ_TYPE_LEVEL_HIGH>;
107 };
108
109 gpio0: gpio-controller@3300 {
110 compatible = "realtek,rtl9310-gpio", "realtek,otto-gpio";
111 reg = <0x3300 0x1c>;
112
113 gpio-controller;
114 #gpio-cells = <2>;
115 ngpios = <32>;
116
117 interrupt-controller;
118 #interrupt-cells = <3>;
119 interrupt-parent = <&gic>;
120 interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
121 };
122
123 uart0: uart@2000 {
124 compatible = "ns16550a";
125 reg = <0x2000 0x100>;
126
127 clock-frequency = <200000000>;
128
129 interrupt-parent = <&gic>;
130 #interrupt-cells = <3>;
131 interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
132
133 reg-io-width = <1>;
134 reg-shift = <2>;
135 fifo-size = <1>;
136 no-loopback-test;
137 };
138
139 uart1: uart@2100 {
140 compatible = "ns16550a";
141 reg = <0x2100 0x100>;
142
143 clock-frequency = <200000000>;
144
145 interrupt-parent = <&gic>;
146 #interrupt-cells = <3>;
147 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
148
149 reg-io-width = <1>;
150 reg-shift = <2>;
151 fifo-size = <1>;
152 no-loopback-test;
153
154 status = "disabled";
155 };
156 };
157
158
159 ethernet0: ethernet@1b00a300 {
160 status = "okay";
161 compatible = "realtek,rtl838x-eth";
162 reg = <0x1b00a300 0x100>;
163 interrupt-parent = <&gic>;
164 #interrupt-cells = <3>;
165 interrupts = <GIC_SHARED 16 IRQ_TYPE_LEVEL_HIGH>;
166 phy-mode = "internal";
167 fixed-link {
168 speed = <1000>;
169 full-duplex;
170 };
171 };
172
173 switch0: switch@1b000000 {
174 compatible = "realtek,rtl83xx-switch";
175 status = "okay";
176
177 interrupt-parent = <&gic>;
178 #interrupt-cells = <3>;
179 interrupts = <GIC_SHARED 15 IRQ_TYPE_LEVEL_HIGH>;
180 };
181 };