realtek: refresh and update config-5.10
[openwrt/openwrt.git] / target / linux / realtek / dts / rtl838x.dtsi
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
3 /dts-v1/;
4
5 #define STRINGIZE(s) #s
6 #define LAN_LABEL(p, s) STRINGIZE(p ## s)
7 #define SWITCH_PORT_LABEL(n) LAN_LABEL(lan, n)
8
9 #define INTERNAL_PHY(n) \
10 phy##n: ethernet-phy@##n { \
11 reg = <##n>; \
12 compatible = "ethernet-phy-ieee802.3-c22"; \
13 phy-is-integrated; \
14 };
15
16 #define EXTERNAL_PHY(n) \
17 phy##n: ethernet-phy@##n { \
18 reg = <##n>; \
19 compatible = "ethernet-phy-ieee802.3-c22"; \
20 };
21
22 #define EXTERNAL_SFP_PHY(n) \
23 phy##n: ethernet-phy@##n { \
24 compatible = "ethernet-phy-ieee802.3-c22"; \
25 sfp; \
26 media = "fibre"; \
27 reg = <##n>; \
28 };
29
30 #define SWITCH_PORT(n, s, m) \
31 port@##n { \
32 reg = <##n>; \
33 label = SWITCH_PORT_LABEL(s) ; \
34 phy-handle = <&phy##n>; \
35 phy-mode = #m ; \
36 };
37
38 #define SWITCH_SFP_PORT(n, s, m) \
39 port@##n { \
40 reg = <##n>; \
41 label = SWITCH_PORT_LABEL(s) ; \
42 phy-handle = <&phy##n>; \
43 phy-mode = #m ; \
44 fixed-link { \
45 speed = <1000>; \
46 full-duplex; \
47 }; \
48 };
49
50 / {
51 #address-cells = <1>;
52 #size-cells = <1>;
53
54 compatible = "realtek,rtl838x-soc";
55
56 cpus {
57 #address-cells = <1>;
58 #size-cells = <0>;
59 frequency = <500000000>;
60
61 cpu@0 {
62 compatible = "mips,mips4KEc";
63 reg = <0>;
64 };
65 };
66
67 chosen {
68 bootargs = "console=ttyS0,38400";
69 };
70
71 cpuintc: cpuintc {
72 #address-cells = <0>;
73 #interrupt-cells = <1>;
74 interrupt-controller;
75 compatible = "mti,cpu-interrupt-controller";
76 };
77
78 intc: rtlintc {
79 #address-cells = <0>;
80 #interrupt-cells = <1>;
81 interrupt-controller;
82 compatible = "realtek,rt8380-intc";
83 reg = <0xb8003000 0x20>;
84 };
85
86 spi0: spi@b8001200 {
87 status = "okay";
88
89 compatible = "realtek,rtl838x-nor";
90 reg = <0xb8001200 0x100>;
91
92 #address-cells = <1>;
93 #size-cells = <0>;
94 };
95
96 uart0: uart@b8002000 {
97 status = "okay";
98
99 compatible = "ns16550a";
100 reg = <0xb8002000 0x100>;
101
102 clock-frequency = <200000000>;
103
104 interrupt-parent = <&intc>;
105 interrupts = <31>;
106
107 reg-io-width = <1>;
108 reg-shift = <2>;
109 fifo-size = <1>;
110 no-loopback-test;
111 };
112
113 uart1: uart@b8002100 {
114 pinctrl-names = "default";
115 pinctrl-0 = <&enable_uart1>;
116
117 status = "okay";
118
119 compatible = "ns16550a";
120 reg = <0xb8002100 0x100>;
121
122 clock-frequency = <200000000>;
123
124 interrupt-parent = <&intc>;
125 interrupts = <30>;
126
127 reg-io-width = <1>;
128 reg-shift = <2>;
129 fifo-size = <1>;
130 no-loopback-test;
131 };
132
133 gpio0: gpio-controller@b8003500 {
134 compatible = "realtek,rtl838x-gpio";
135 reg = <0xb8003500 0x20>;
136 gpio-controller;
137 #gpio-cells = <2>;
138 interrupt-parent = <&intc>;
139 interrupts = <23>;
140 };
141
142 gpio1: rtl8231-gpio {
143 status = "disabled";
144 compatible = "realtek,rtl8231-gpio";
145 #gpio-cells = <2>;
146 indirect-access-bus-id = <0>;
147 gpio-controller;
148 };
149
150 pinmux: pinmux@bb001000 {
151 compatible = "pinctrl-single";
152 reg = <0xbb001000 0x4>;
153
154 pinctrl-single,bit-per-mux;
155 pinctrl-single,register-width = <32>;
156 pinctrl-single,function-mask = <0x1>;
157 #pinctrl-cells = <2>;
158
159 enable_uart1: pinmux_enable_uart1 {
160 pinctrl-single,bits = <0x0 0x10 0x10>;
161 };
162 };
163
164 ethernet0: ethernet@bb00a300 {
165 status = "okay";
166
167 compatible = "realtek,rtl838x-eth";
168 reg = <0xbb00a300 0x100>;
169 interrupt-parent = <&intc>;
170 interrupts = <24>;
171 #interrupt-cells = <1>;
172 phy-mode = "internal";
173
174 fixed-link {
175 speed = <1000>;
176 full-duplex;
177 };
178 };
179
180 switch0: switch@bb000000 {
181 status = "okay";
182
183 interrupt-parent = <&intc>;
184 interrupts = <20>;
185
186 compatible = "realtek,rtl83xx-switch";
187 };
188 };