target/linux/realtek/files-5.10/arch/mips/rtl838x/prom.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * prom.c
   4  * Early intialization code for the Realtek RTL838X SoC
   5  *
   6  * based on the original BSP by
   7  * Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com)
   8  * Copyright (C) 2020 B. Koblitz
   9  *
  10  */
  11
  12 #include <linux/init.h>
  13 #include <linux/kernel.h>
  14 #include <linux/string.h>
  15 #include <linux/of_fdt.h>
  16 #include <linux/libfdt.h>
  17 #include <asm/bootinfo.h>
  18 #include <asm/addrspace.h>
  19 #include <asm/page.h>
  20 #include <asm/cpu.h>
  21 #include <asm/smp-ops.h>
  22 #include <asm/mips-cps.h>
  23
  24 #include <mach-rtl83xx.h>
  25
  26 extern char arcs_cmdline[];
  27 extern const char __appended_dtb;
  28
  29 struct rtl83xx_soc_info soc_info;
  30 const void *fdt;
  31
  32 #ifdef CONFIG_MIPS_MT_SMP
  33 extern const struct plat_smp_ops vsmp_smp_ops;
  34 static struct plat_smp_ops rtl_smp_ops;
  35
  36 static void rtl_init_secondary(void)
  37 {
  38 #ifndef CONFIG_CEVT_R4K
  39 /*
  40  * These devices are low on resources. There might be the chance that CEVT_R4K
  41  * is not enabled in kernel build. Nevertheless the timer and interrupt 7 might
  42  * be active by default after startup of secondary VPE. With no registered
  43  * handler that leads to continuous unhandeled interrupts. In this case disable
  44  * counting (DC) in the core and confirm a pending interrupt.
  45  */
  46         write_c0_cause(read_c0_cause() | CAUSEF_DC);
  47         write_c0_compare(0);
  48 #endif /* CONFIG_CEVT_R4K */
  49 /*
  50  * Enable all CPU interrupts, as everything is managed by the external
  51  * controller. TODO: Standard vsmp_init_secondary() has special treatment for
  52  * Malta if external GIC is available. Maybe we need this too.
  53  */
  54         if (mips_gic_present())
  55                 pr_warn("%s: GIC present. Maybe interrupt enabling required.\n", __func__);
  56         else
  57                 set_c0_status(ST0_IM);
  58 }
  59 #endif /* CONFIG_MIPS_MT_SMP */
  60
  61 const char *get_system_type(void)
  62 {
  63         return soc_info.name;
  64 }
  65
  66 void __init prom_free_prom_memory(void)
  67 {
  68
  69 }
  70
  71 void __init device_tree_init(void)
  72 {
  73         if (!fdt_check_header(&__appended_dtb)) {
  74                 fdt = &__appended_dtb;
  75                 pr_info("Using appended Device Tree.\n");
  76         }
  77         initial_boot_params = (void *)fdt;
  78         unflatten_and_copy_device_tree();
  79 }
  80
  81 static void __init prom_init_cmdline(void)
  82 {
  83         int argc = fw_arg0;
  84         char **argv = (char **) KSEG1ADDR(fw_arg1);
  85         int i;
  86
  87         arcs_cmdline[0] = '\0';
  88
  89         for (i = 0; i < argc; i++) {
  90                 char *p = (char *) KSEG1ADDR(argv[i]);
  91
  92                 if (CPHYSADDR(p) && *p) {
  93                         strlcat(arcs_cmdline, p, sizeof(arcs_cmdline));
  94                         strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline));
  95                 }
  96         }
  97         pr_info("Kernel command line: %s\n", arcs_cmdline);
  98 }
  99
 100 void __init identify_rtl9302(void)
 101 {
 102         switch (sw_r32(RTL93XX_MODEL_NAME_INFO) & 0xfffffff0) {
 103         case 0x93020810:
 104                 soc_info.name = "RTL9302A 12x2.5G";
 105                 break;
 106         case 0x93021010:
 107                 soc_info.name = "RTL9302B 8x2.5G";
 108                 break;
 109         case 0x93021810:
 110                 soc_info.name = "RTL9302C 16x2.5G";
 111                 break;
 112         case 0x93022010:
 113                 soc_info.name = "RTL9302D 24x2.5G";
 114                 break;
 115         case 0x93020800:
 116                 soc_info.name = "RTL9302A";
 117                 break;
 118         case 0x93021000:
 119                 soc_info.name = "RTL9302B";
 120                 break;
 121         case 0x93021800:
 122                 soc_info.name = "RTL9302C";
 123                 break;
 124         case 0x93022000:
 125                 soc_info.name = "RTL9302D";
 126                 break;
 127         case 0x93023001:
 128                 soc_info.name = "RTL9302F";
 129                 break;
 130         default:
 131                 soc_info.name = "RTL9302";
 132         }
 133 }
 134
 135 void __init prom_init(void)
 136 {
 137         uint32_t model;
 138
 139         /* uart0 */
 140         setup_8250_early_printk_port(0xb8002000, 2, 0);
 141
 142         model = sw_r32(RTL838X_MODEL_NAME_INFO);
 143         pr_info("RTL838X model is %x\n", model);
 144         model = model >> 16 & 0xFFFF;
 145
 146         if ((model != 0x8328) && (model != 0x8330) && (model != 0x8332)
 147             && (model != 0x8380) && (model != 0x8382)) {
 148                 model = sw_r32(RTL839X_MODEL_NAME_INFO);
 149                 pr_info("RTL839X model is %x\n", model);
 150                 model = model >> 16 & 0xFFFF;
 151         }
 152
 153         if ((model & 0x8390) != 0x8380 && (model & 0x8390) != 0x8390) {
 154                 model = sw_r32(RTL93XX_MODEL_NAME_INFO);
 155                 pr_info("RTL93XX model is %x\n", model);
 156                 model = model >> 16 & 0xFFFF;
 157         }
 158
 159         soc_info.id = model;
 160
 161         switch (model) {
 162         case 0x8328:
 163                 soc_info.name = "RTL8328";
 164                 soc_info.family = RTL8328_FAMILY_ID;
 165                 break;
 166         case 0x8332:
 167                 soc_info.name = "RTL8332";
 168                 soc_info.family = RTL8380_FAMILY_ID;
 169                 break;
 170         case 0x8380:
 171                 soc_info.name = "RTL8380";
 172                 soc_info.family = RTL8380_FAMILY_ID;
 173                 break;
 174         case 0x8382:
 175                 soc_info.name = "RTL8382";
 176                 soc_info.family = RTL8380_FAMILY_ID;
 177                 break;
 178         case 0x8390:
 179                 soc_info.name = "RTL8390";
 180                 soc_info.family = RTL8390_FAMILY_ID;
 181                 break;
 182         case 0x8391:
 183                 soc_info.name = "RTL8391";
 184                 soc_info.family = RTL8390_FAMILY_ID;
 185                 break;
 186         case 0x8392:
 187                 soc_info.name = "RTL8392";
 188                 soc_info.family = RTL8390_FAMILY_ID;
 189                 break;
 190         case 0x8393:
 191                 soc_info.name = "RTL8393";
 192                 soc_info.family = RTL8390_FAMILY_ID;
 193                 break;
 194         case 0x9301:
 195                 soc_info.name = "RTL9301";
 196                 soc_info.family = RTL9300_FAMILY_ID;
 197                 break;
 198         case 0x9302:
 199                 identify_rtl9302();
 200                 soc_info.family = RTL9300_FAMILY_ID;
 201                 break;
 202         case 0x9303:
 203                 soc_info.name = "RTL9303";
 204                 soc_info.family = RTL9300_FAMILY_ID;
 205                 break;
 206         case 0x9313:
 207                 soc_info.name = "RTL9313";
 208                 soc_info.family = RTL9310_FAMILY_ID;
 209                 break;
 210         default:
 211                 soc_info.name = "DEFAULT";
 212                 soc_info.family = 0;
 213         }
 214
 215         pr_info("SoC Type: %s\n", get_system_type());
 216
 217         prom_init_cmdline();
 218
 219         mips_cpc_probe();
 220
 221         if (!register_cps_smp_ops())
 222                 return;
 223
 224 #ifdef CONFIG_MIPS_MT_SMP
 225         if (cpu_has_mipsmt) {
 226                 rtl_smp_ops = vsmp_smp_ops;
 227                 rtl_smp_ops.init_secondary = rtl_init_secondary;
 228                 register_smp_ops(&rtl_smp_ops);
 229                 return;
 230         }
 231 #endif
 232
 233         register_up_smp_ops();
 234 }