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[openwrt/openwrt.git] / target / linux / realtek / files-5.10 / drivers / net / dsa / rtl83xx / dsa.c
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <net/dsa.h>
4 #include <linux/if_bridge.h>
5
6 #include <asm/mach-rtl838x/mach-rtl83xx.h>
7 #include "rtl83xx.h"
8
9
10 extern struct rtl83xx_soc_info soc_info;
11
12
13 static void rtl83xx_init_stats(struct rtl838x_switch_priv *priv)
14 {
15 mutex_lock(&priv->reg_mutex);
16
17 /* Enable statistics module: all counters plus debug.
18 * On RTL839x all counters are enabled by default
19 */
20 if (priv->family_id == RTL8380_FAMILY_ID)
21 sw_w32_mask(0, 3, RTL838X_STAT_CTRL);
22
23 /* Reset statistics counters */
24 sw_w32_mask(0, 1, priv->r->stat_rst);
25
26 mutex_unlock(&priv->reg_mutex);
27 }
28
29 static void rtl83xx_enable_phy_polling(struct rtl838x_switch_priv *priv)
30 {
31 int i;
32 u64 v = 0;
33
34 msleep(1000);
35 /* Enable all ports with a PHY, including the SFP-ports */
36 for (i = 0; i < priv->cpu_port; i++) {
37 if (priv->ports[i].phy)
38 v |= BIT_ULL(i);
39 }
40
41 pr_info("%s: %16llx\n", __func__, v);
42 priv->r->set_port_reg_le(v, priv->r->smi_poll_ctrl);
43
44 /* PHY update complete, there is no global PHY polling enable bit on the 9300 */
45 if (priv->family_id == RTL8390_FAMILY_ID)
46 sw_w32_mask(0, BIT(7), RTL839X_SMI_GLB_CTRL);
47 else if(priv->family_id == RTL9300_FAMILY_ID)
48 sw_w32_mask(0, 0x8000, RTL838X_SMI_GLB_CTRL);
49 }
50
51 const struct rtl83xx_mib_desc rtl83xx_mib[] = {
52 MIB_DESC(2, 0xf8, "ifInOctets"),
53 MIB_DESC(2, 0xf0, "ifOutOctets"),
54 MIB_DESC(1, 0xec, "dot1dTpPortInDiscards"),
55 MIB_DESC(1, 0xe8, "ifInUcastPkts"),
56 MIB_DESC(1, 0xe4, "ifInMulticastPkts"),
57 MIB_DESC(1, 0xe0, "ifInBroadcastPkts"),
58 MIB_DESC(1, 0xdc, "ifOutUcastPkts"),
59 MIB_DESC(1, 0xd8, "ifOutMulticastPkts"),
60 MIB_DESC(1, 0xd4, "ifOutBroadcastPkts"),
61 MIB_DESC(1, 0xd0, "ifOutDiscards"),
62 MIB_DESC(1, 0xcc, ".3SingleCollisionFrames"),
63 MIB_DESC(1, 0xc8, ".3MultipleCollisionFrames"),
64 MIB_DESC(1, 0xc4, ".3DeferredTransmissions"),
65 MIB_DESC(1, 0xc0, ".3LateCollisions"),
66 MIB_DESC(1, 0xbc, ".3ExcessiveCollisions"),
67 MIB_DESC(1, 0xb8, ".3SymbolErrors"),
68 MIB_DESC(1, 0xb4, ".3ControlInUnknownOpcodes"),
69 MIB_DESC(1, 0xb0, ".3InPauseFrames"),
70 MIB_DESC(1, 0xac, ".3OutPauseFrames"),
71 MIB_DESC(1, 0xa8, "DropEvents"),
72 MIB_DESC(1, 0xa4, "tx_BroadcastPkts"),
73 MIB_DESC(1, 0xa0, "tx_MulticastPkts"),
74 MIB_DESC(1, 0x9c, "CRCAlignErrors"),
75 MIB_DESC(1, 0x98, "tx_UndersizePkts"),
76 MIB_DESC(1, 0x94, "rx_UndersizePkts"),
77 MIB_DESC(1, 0x90, "rx_UndersizedropPkts"),
78 MIB_DESC(1, 0x8c, "tx_OversizePkts"),
79 MIB_DESC(1, 0x88, "rx_OversizePkts"),
80 MIB_DESC(1, 0x84, "Fragments"),
81 MIB_DESC(1, 0x80, "Jabbers"),
82 MIB_DESC(1, 0x7c, "Collisions"),
83 MIB_DESC(1, 0x78, "tx_Pkts64Octets"),
84 MIB_DESC(1, 0x74, "rx_Pkts64Octets"),
85 MIB_DESC(1, 0x70, "tx_Pkts65to127Octets"),
86 MIB_DESC(1, 0x6c, "rx_Pkts65to127Octets"),
87 MIB_DESC(1, 0x68, "tx_Pkts128to255Octets"),
88 MIB_DESC(1, 0x64, "rx_Pkts128to255Octets"),
89 MIB_DESC(1, 0x60, "tx_Pkts256to511Octets"),
90 MIB_DESC(1, 0x5c, "rx_Pkts256to511Octets"),
91 MIB_DESC(1, 0x58, "tx_Pkts512to1023Octets"),
92 MIB_DESC(1, 0x54, "rx_Pkts512to1023Octets"),
93 MIB_DESC(1, 0x50, "tx_Pkts1024to1518Octets"),
94 MIB_DESC(1, 0x4c, "rx_StatsPkts1024to1518Octets"),
95 MIB_DESC(1, 0x48, "tx_Pkts1519toMaxOctets"),
96 MIB_DESC(1, 0x44, "rx_Pkts1519toMaxOctets"),
97 MIB_DESC(1, 0x40, "rxMacDiscards")
98 };
99
100
101 /* DSA callbacks */
102
103
104 static enum dsa_tag_protocol rtl83xx_get_tag_protocol(struct dsa_switch *ds,
105 int port,
106 enum dsa_tag_protocol mprot)
107 {
108 /* The switch does not tag the frames, instead internally the header
109 * structure for each packet is tagged accordingly.
110 */
111 return DSA_TAG_PROTO_TRAILER;
112 }
113
114 /*
115 * Initialize all VLANS
116 */
117 static void rtl83xx_vlan_setup(struct rtl838x_switch_priv *priv)
118 {
119 struct rtl838x_vlan_info info;
120 int i;
121
122 pr_info("In %s\n", __func__);
123
124 priv->r->vlan_profile_setup(0);
125 priv->r->vlan_profile_setup(1);
126 pr_info("UNKNOWN_MC_PMASK: %016llx\n", priv->r->read_mcast_pmask(UNKNOWN_MC_PMASK));
127 priv->r->vlan_profile_dump(0);
128
129 info.fid = 0; // Default Forwarding ID / MSTI
130 info.hash_uc_fid = false; // Do not build the L2 lookup hash with FID, but VID
131 info.hash_mc_fid = false; // Do the same for Multicast packets
132 info.profile_id = 0; // Use default Vlan Profile 0
133 info.tagged_ports = 0; // Initially no port members
134 if (priv->family_id == RTL9310_FAMILY_ID) {
135 info.if_id = 0;
136 info.multicast_grp_mask = 0;
137 info.l2_tunnel_list_id = -1;
138 }
139
140 // Initialize all vlans 0-4095
141 for (i = 0; i < MAX_VLANS; i ++)
142 priv->r->vlan_set_tagged(i, &info);
143
144 // reset PVIDs; defaults to 1 on reset
145 for (i = 0; i <= priv->ds->num_ports; i++) {
146 priv->r->vlan_port_pvid_set(i, PBVLAN_TYPE_INNER, 0);
147 priv->r->vlan_port_pvid_set(i, PBVLAN_TYPE_OUTER, 0);
148 priv->r->vlan_port_pvidmode_set(i, PBVLAN_TYPE_INNER, PBVLAN_MODE_UNTAG_AND_PRITAG);
149 priv->r->vlan_port_pvidmode_set(i, PBVLAN_TYPE_OUTER, PBVLAN_MODE_UNTAG_AND_PRITAG);
150 }
151
152 // Set forwarding action based on inner VLAN tag
153 for (i = 0; i < priv->cpu_port; i++)
154 priv->r->vlan_fwd_on_inner(i, true);
155 }
156
157 static void rtl83xx_setup_bpdu_traps(struct rtl838x_switch_priv *priv)
158 {
159 int i;
160
161 for (i = 0; i < priv->cpu_port; i++)
162 priv->r->set_receive_management_action(i, BPDU, COPY2CPU);
163 }
164
165 static int rtl83xx_setup(struct dsa_switch *ds)
166 {
167 int i;
168 struct rtl838x_switch_priv *priv = ds->priv;
169 u64 port_bitmap = BIT_ULL(priv->cpu_port);
170
171 pr_debug("%s called\n", __func__);
172
173 /* Disable MAC polling the PHY so that we can start configuration */
174 priv->r->set_port_reg_le(0ULL, priv->r->smi_poll_ctrl);
175
176 for (i = 0; i < ds->num_ports; i++)
177 priv->ports[i].enable = false;
178 priv->ports[priv->cpu_port].enable = true;
179
180 /* Isolate ports from each other: traffic only CPU <-> port */
181 /* Setting bit j in register RTL838X_PORT_ISO_CTRL(i) allows
182 * traffic from source port i to destination port j
183 */
184 for (i = 0; i < priv->cpu_port; i++) {
185 if (priv->ports[i].phy) {
186 priv->r->set_port_reg_be(BIT_ULL(priv->cpu_port) | BIT_ULL(i),
187 priv->r->port_iso_ctrl(i));
188 port_bitmap |= BIT_ULL(i);
189 }
190 }
191 priv->r->set_port_reg_be(port_bitmap, priv->r->port_iso_ctrl(priv->cpu_port));
192
193 if (priv->family_id == RTL8380_FAMILY_ID)
194 rtl838x_print_matrix();
195 else
196 rtl839x_print_matrix();
197
198 rtl83xx_init_stats(priv);
199
200 rtl83xx_vlan_setup(priv);
201
202 rtl83xx_setup_bpdu_traps(priv);
203
204 ds->configure_vlan_while_not_filtering = true;
205
206 priv->r->l2_learning_setup();
207
208 /* Enable MAC Polling PHY again */
209 rtl83xx_enable_phy_polling(priv);
210 pr_debug("Please wait until PHY is settled\n");
211 msleep(1000);
212 priv->r->pie_init(priv);
213
214 return 0;
215 }
216
217 static int rtl93xx_setup(struct dsa_switch *ds)
218 {
219 int i;
220 struct rtl838x_switch_priv *priv = ds->priv;
221 u32 port_bitmap = BIT(priv->cpu_port);
222
223 pr_info("%s called\n", __func__);
224
225 /* Disable MAC polling the PHY so that we can start configuration */
226 if (priv->family_id == RTL9300_FAMILY_ID)
227 sw_w32(0, RTL930X_SMI_POLL_CTRL);
228
229 if (priv->family_id == RTL9310_FAMILY_ID) {
230 sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL);
231 sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL + 4);
232 }
233
234 // Disable all ports except CPU port
235 for (i = 0; i < ds->num_ports; i++)
236 priv->ports[i].enable = false;
237 priv->ports[priv->cpu_port].enable = true;
238
239 for (i = 0; i < priv->cpu_port; i++) {
240 if (priv->ports[i].phy) {
241 priv->r->traffic_set(i, BIT_ULL(priv->cpu_port) | BIT_ULL(i));
242 port_bitmap |= BIT_ULL(i);
243 }
244 }
245 priv->r->traffic_set(priv->cpu_port, port_bitmap);
246
247 rtl930x_print_matrix();
248
249 // TODO: Initialize statistics
250
251 rtl83xx_vlan_setup(priv);
252
253 ds->configure_vlan_while_not_filtering = true;
254
255 priv->r->l2_learning_setup();
256
257 rtl83xx_enable_phy_polling(priv);
258
259 priv->r->pie_init(priv);
260
261 priv->r->led_init(priv);
262
263 return 0;
264 }
265
266 static int rtl93xx_get_sds(struct phy_device *phydev)
267 {
268 struct device *dev = &phydev->mdio.dev;
269 struct device_node *dn;
270 u32 sds_num;
271
272 if (!dev)
273 return -1;
274 if (dev->of_node) {
275 dn = dev->of_node;
276 if (of_property_read_u32(dn, "sds", &sds_num))
277 sds_num = -1;
278 } else {
279 dev_err(dev, "No DT node.\n");
280 return -1;
281 }
282
283 return sds_num;
284 }
285
286 static void rtl83xx_phylink_validate(struct dsa_switch *ds, int port,
287 unsigned long *supported,
288 struct phylink_link_state *state)
289 {
290 struct rtl838x_switch_priv *priv = ds->priv;
291 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
292
293 pr_debug("In %s port %d, state is %d", __func__, port, state->interface);
294
295 if (!phy_interface_mode_is_rgmii(state->interface) &&
296 state->interface != PHY_INTERFACE_MODE_NA &&
297 state->interface != PHY_INTERFACE_MODE_1000BASEX &&
298 state->interface != PHY_INTERFACE_MODE_MII &&
299 state->interface != PHY_INTERFACE_MODE_REVMII &&
300 state->interface != PHY_INTERFACE_MODE_GMII &&
301 state->interface != PHY_INTERFACE_MODE_QSGMII &&
302 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
303 state->interface != PHY_INTERFACE_MODE_SGMII) {
304 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
305 dev_err(ds->dev,
306 "Unsupported interface: %d for port %d\n",
307 state->interface, port);
308 return;
309 }
310
311 /* Allow all the expected bits */
312 phylink_set(mask, Autoneg);
313 phylink_set_port_modes(mask);
314 phylink_set(mask, Pause);
315 phylink_set(mask, Asym_Pause);
316
317 /* With the exclusion of MII and Reverse MII, we support Gigabit,
318 * including Half duplex
319 */
320 if (state->interface != PHY_INTERFACE_MODE_MII &&
321 state->interface != PHY_INTERFACE_MODE_REVMII) {
322 phylink_set(mask, 1000baseT_Full);
323 phylink_set(mask, 1000baseT_Half);
324 }
325
326 /* On both the 8380 and 8382, ports 24-27 are SFP ports */
327 if (port >= 24 && port <= 27 && priv->family_id == RTL8380_FAMILY_ID)
328 phylink_set(mask, 1000baseX_Full);
329
330 /* On the RTL839x family of SoCs, ports 48 to 51 are SFP ports */
331 if (port >= 48 && port <= 51 && priv->family_id == RTL8390_FAMILY_ID)
332 phylink_set(mask, 1000baseX_Full);
333
334 phylink_set(mask, 10baseT_Half);
335 phylink_set(mask, 10baseT_Full);
336 phylink_set(mask, 100baseT_Half);
337 phylink_set(mask, 100baseT_Full);
338
339 bitmap_and(supported, supported, mask,
340 __ETHTOOL_LINK_MODE_MASK_NBITS);
341 bitmap_and(state->advertising, state->advertising, mask,
342 __ETHTOOL_LINK_MODE_MASK_NBITS);
343 }
344
345 static void rtl93xx_phylink_validate(struct dsa_switch *ds, int port,
346 unsigned long *supported,
347 struct phylink_link_state *state)
348 {
349 struct rtl838x_switch_priv *priv = ds->priv;
350 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
351
352 pr_debug("In %s port %d, state is %d (%s)", __func__, port, state->interface,
353 phy_modes(state->interface));
354
355 if (!phy_interface_mode_is_rgmii(state->interface) &&
356 state->interface != PHY_INTERFACE_MODE_NA &&
357 state->interface != PHY_INTERFACE_MODE_1000BASEX &&
358 state->interface != PHY_INTERFACE_MODE_MII &&
359 state->interface != PHY_INTERFACE_MODE_REVMII &&
360 state->interface != PHY_INTERFACE_MODE_GMII &&
361 state->interface != PHY_INTERFACE_MODE_QSGMII &&
362 state->interface != PHY_INTERFACE_MODE_XGMII &&
363 state->interface != PHY_INTERFACE_MODE_HSGMII &&
364 state->interface != PHY_INTERFACE_MODE_10GBASER &&
365 state->interface != PHY_INTERFACE_MODE_10GKR &&
366 state->interface != PHY_INTERFACE_MODE_USXGMII &&
367 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
368 state->interface != PHY_INTERFACE_MODE_SGMII) {
369 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
370 dev_err(ds->dev,
371 "Unsupported interface: %d for port %d\n",
372 state->interface, port);
373 return;
374 }
375
376 /* Allow all the expected bits */
377 phylink_set(mask, Autoneg);
378 phylink_set_port_modes(mask);
379 phylink_set(mask, Pause);
380 phylink_set(mask, Asym_Pause);
381
382 /* With the exclusion of MII and Reverse MII, we support Gigabit,
383 * including Half duplex
384 */
385 if (state->interface != PHY_INTERFACE_MODE_MII &&
386 state->interface != PHY_INTERFACE_MODE_REVMII) {
387 phylink_set(mask, 1000baseT_Full);
388 phylink_set(mask, 1000baseT_Half);
389 }
390
391 // Internal phys of the RTL93xx family provide 10G
392 if (priv->ports[port].phy_is_integrated
393 && state->interface == PHY_INTERFACE_MODE_1000BASEX) {
394 phylink_set(mask, 1000baseX_Full);
395 } else if (priv->ports[port].phy_is_integrated) {
396 phylink_set(mask, 1000baseX_Full);
397 phylink_set(mask, 10000baseKR_Full);
398 phylink_set(mask, 10000baseSR_Full);
399 phylink_set(mask, 10000baseCR_Full);
400 }
401 if (state->interface == PHY_INTERFACE_MODE_INTERNAL) {
402 phylink_set(mask, 1000baseX_Full);
403 phylink_set(mask, 1000baseT_Full);
404 phylink_set(mask, 10000baseKR_Full);
405 phylink_set(mask, 10000baseT_Full);
406 phylink_set(mask, 10000baseSR_Full);
407 phylink_set(mask, 10000baseCR_Full);
408 }
409
410 if (state->interface == PHY_INTERFACE_MODE_USXGMII)
411 phylink_set(mask, 10000baseT_Full);
412
413 phylink_set(mask, 10baseT_Half);
414 phylink_set(mask, 10baseT_Full);
415 phylink_set(mask, 100baseT_Half);
416 phylink_set(mask, 100baseT_Full);
417
418 bitmap_and(supported, supported, mask,
419 __ETHTOOL_LINK_MODE_MASK_NBITS);
420 bitmap_and(state->advertising, state->advertising, mask,
421 __ETHTOOL_LINK_MODE_MASK_NBITS);
422 pr_debug("%s leaving supported: %*pb", __func__, __ETHTOOL_LINK_MODE_MASK_NBITS, supported);
423 }
424
425 static int rtl83xx_phylink_mac_link_state(struct dsa_switch *ds, int port,
426 struct phylink_link_state *state)
427 {
428 struct rtl838x_switch_priv *priv = ds->priv;
429 u64 speed;
430 u64 link;
431
432 if (port < 0 || port > priv->cpu_port)
433 return -EINVAL;
434
435 state->link = 0;
436 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
437 if (link & BIT_ULL(port))
438 state->link = 1;
439 pr_debug("%s: link state port %d: %llx\n", __func__, port, link & BIT_ULL(port));
440
441 state->duplex = 0;
442 if (priv->r->get_port_reg_le(priv->r->mac_link_dup_sts) & BIT_ULL(port))
443 state->duplex = 1;
444
445 speed = priv->r->get_port_reg_le(priv->r->mac_link_spd_sts(port));
446 speed >>= (port % 16) << 1;
447 switch (speed & 0x3) {
448 case 0:
449 state->speed = SPEED_10;
450 break;
451 case 1:
452 state->speed = SPEED_100;
453 break;
454 case 2:
455 state->speed = SPEED_1000;
456 break;
457 case 3:
458 if (priv->family_id == RTL9300_FAMILY_ID
459 && (port == 24 || port == 26)) /* Internal serdes */
460 state->speed = SPEED_2500;
461 else
462 state->speed = SPEED_100; /* Is in fact 500Mbit */
463 }
464
465 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
466 if (priv->r->get_port_reg_le(priv->r->mac_rx_pause_sts) & BIT_ULL(port))
467 state->pause |= MLO_PAUSE_RX;
468 if (priv->r->get_port_reg_le(priv->r->mac_tx_pause_sts) & BIT_ULL(port))
469 state->pause |= MLO_PAUSE_TX;
470 return 1;
471 }
472
473 static int rtl93xx_phylink_mac_link_state(struct dsa_switch *ds, int port,
474 struct phylink_link_state *state)
475 {
476 struct rtl838x_switch_priv *priv = ds->priv;
477 u64 speed;
478 u64 link;
479 u64 media;
480
481 if (port < 0 || port > priv->cpu_port)
482 return -EINVAL;
483
484 /*
485 * On the RTL9300 for at least the RTL8226B PHY, the MAC-side link
486 * state needs to be read twice in order to read a correct result.
487 * This would not be necessary for ports connected e.g. to RTL8218D
488 * PHYs.
489 */
490 state->link = 0;
491 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
492 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
493 if (link & BIT_ULL(port))
494 state->link = 1;
495
496 if (priv->family_id == RTL9310_FAMILY_ID)
497 media = priv->r->get_port_reg_le(RTL931X_MAC_LINK_MEDIA_STS);
498
499 if (priv->family_id == RTL9300_FAMILY_ID)
500 media = sw_r32(RTL930X_MAC_LINK_MEDIA_STS);
501
502 if (media & BIT_ULL(port))
503 state->link = 1;
504
505 pr_debug("%s: link state port %d: %llx, media %llx\n", __func__, port,
506 link & BIT_ULL(port), media);
507
508 state->duplex = 0;
509 if (priv->r->get_port_reg_le(priv->r->mac_link_dup_sts) & BIT_ULL(port))
510 state->duplex = 1;
511
512 speed = priv->r->get_port_reg_le(priv->r->mac_link_spd_sts(port));
513 speed >>= (port % 8) << 2;
514 switch (speed & 0xf) {
515 case 0:
516 state->speed = SPEED_10;
517 break;
518 case 1:
519 state->speed = SPEED_100;
520 break;
521 case 2:
522 case 7:
523 state->speed = SPEED_1000;
524 break;
525 case 4:
526 state->speed = SPEED_10000;
527 break;
528 case 5:
529 case 8:
530 state->speed = SPEED_2500;
531 break;
532 case 6:
533 state->speed = SPEED_5000;
534 break;
535 default:
536 pr_err("%s: unknown speed: %d\n", __func__, (u32)speed & 0xf);
537 }
538
539 if (priv->family_id == RTL9310_FAMILY_ID
540 && (port >= 52 || port <= 55)) { /* Internal serdes */
541 state->speed = SPEED_10000;
542 state->link = 1;
543 state->duplex = 1;
544 }
545
546 pr_debug("%s: speed is: %d %d\n", __func__, (u32)speed & 0xf, state->speed);
547 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
548 if (priv->r->get_port_reg_le(priv->r->mac_rx_pause_sts) & BIT_ULL(port))
549 state->pause |= MLO_PAUSE_RX;
550 if (priv->r->get_port_reg_le(priv->r->mac_tx_pause_sts) & BIT_ULL(port))
551 state->pause |= MLO_PAUSE_TX;
552 return 1;
553 }
554
555 static void rtl83xx_config_interface(int port, phy_interface_t interface)
556 {
557 u32 old, int_shift, sds_shift;
558
559 switch (port) {
560 case 24:
561 int_shift = 0;
562 sds_shift = 5;
563 break;
564 case 26:
565 int_shift = 3;
566 sds_shift = 0;
567 break;
568 default:
569 return;
570 }
571
572 old = sw_r32(RTL838X_SDS_MODE_SEL);
573 switch (interface) {
574 case PHY_INTERFACE_MODE_1000BASEX:
575 if ((old >> sds_shift & 0x1f) == 4)
576 return;
577 sw_w32_mask(0x7 << int_shift, 1 << int_shift, RTL838X_INT_MODE_CTRL);
578 sw_w32_mask(0x1f << sds_shift, 4 << sds_shift, RTL838X_SDS_MODE_SEL);
579 break;
580 case PHY_INTERFACE_MODE_SGMII:
581 if ((old >> sds_shift & 0x1f) == 2)
582 return;
583 sw_w32_mask(0x7 << int_shift, 2 << int_shift, RTL838X_INT_MODE_CTRL);
584 sw_w32_mask(0x1f << sds_shift, 2 << sds_shift, RTL838X_SDS_MODE_SEL);
585 break;
586 default:
587 return;
588 }
589 pr_debug("configured port %d for interface %s\n", port, phy_modes(interface));
590 }
591
592 static void rtl83xx_phylink_mac_config(struct dsa_switch *ds, int port,
593 unsigned int mode,
594 const struct phylink_link_state *state)
595 {
596 struct rtl838x_switch_priv *priv = ds->priv;
597 u32 reg;
598 int speed_bit = priv->family_id == RTL8380_FAMILY_ID ? 4 : 3;
599
600 pr_debug("%s port %d, mode %x\n", __func__, port, mode);
601
602 if (port == priv->cpu_port) {
603 /* Set Speed, duplex, flow control
604 * FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL
605 * | SPD_SEL = 0b10 | FORCE_FC_EN | PHY_MASTER_SLV_MANUAL_EN
606 * | MEDIA_SEL
607 */
608 if (priv->family_id == RTL8380_FAMILY_ID) {
609 sw_w32(0x6192F, priv->r->mac_force_mode_ctrl(priv->cpu_port));
610 /* allow CRC errors on CPU-port */
611 sw_w32_mask(0, 0x8, RTL838X_MAC_PORT_CTRL(priv->cpu_port));
612 } else {
613 sw_w32_mask(0, 3, priv->r->mac_force_mode_ctrl(priv->cpu_port));
614 }
615 return;
616 }
617
618 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
619 /* Auto-Negotiation does not work for MAC in RTL8390 */
620 if (priv->family_id == RTL8380_FAMILY_ID) {
621 if (mode == MLO_AN_PHY || phylink_autoneg_inband(mode)) {
622 pr_debug("PHY autonegotiates\n");
623 reg |= RTL838X_NWAY_EN;
624 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
625 rtl83xx_config_interface(port, state->interface);
626 return;
627 }
628 }
629
630 if (mode != MLO_AN_FIXED)
631 pr_debug("Fixed state.\n");
632
633 /* Clear id_mode_dis bit, and the existing port mode, let
634 * RGMII_MODE_EN bet set by mac_link_{up,down} */
635 if (priv->family_id == RTL8380_FAMILY_ID) {
636 reg &= ~(RTL838X_RX_PAUSE_EN | RTL838X_TX_PAUSE_EN);
637 if (state->pause & MLO_PAUSE_TXRX_MASK) {
638 if (state->pause & MLO_PAUSE_TX)
639 reg |= RTL838X_TX_PAUSE_EN;
640 reg |= RTL838X_RX_PAUSE_EN;
641 }
642 } else if (priv->family_id == RTL8390_FAMILY_ID) {
643 reg &= ~(RTL839X_RX_PAUSE_EN | RTL839X_TX_PAUSE_EN);
644 if (state->pause & MLO_PAUSE_TXRX_MASK) {
645 if (state->pause & MLO_PAUSE_TX)
646 reg |= RTL839X_TX_PAUSE_EN;
647 reg |= RTL839X_RX_PAUSE_EN;
648 }
649 }
650
651
652 reg &= ~(3 << speed_bit);
653 switch (state->speed) {
654 case SPEED_1000:
655 reg |= 2 << speed_bit;
656 break;
657 case SPEED_100:
658 reg |= 1 << speed_bit;
659 break;
660 default:
661 break; // Ignore, including 10MBit which has a speed value of 0
662 }
663
664 if (priv->family_id == RTL8380_FAMILY_ID) {
665 reg &= ~(RTL838X_DUPLEX_MODE | RTL838X_FORCE_LINK_EN);
666 if (state->link)
667 reg |= RTL838X_FORCE_LINK_EN;
668 if (state->duplex == RTL838X_DUPLEX_MODE)
669 reg |= RTL838X_DUPLEX_MODE;
670 } else if (priv->family_id == RTL8390_FAMILY_ID) {
671 reg &= ~(RTL839X_DUPLEX_MODE | RTL839X_FORCE_LINK_EN);
672 if (state->link)
673 reg |= RTL839X_FORCE_LINK_EN;
674 if (state->duplex == RTL839X_DUPLEX_MODE)
675 reg |= RTL839X_DUPLEX_MODE;
676 }
677
678 // LAG members must use DUPLEX and we need to enable the link
679 if (priv->lagmembers & BIT_ULL(port)) {
680 switch(priv->family_id) {
681 case RTL8380_FAMILY_ID:
682 reg |= (RTL838X_DUPLEX_MODE | RTL838X_FORCE_LINK_EN);
683 break;
684 case RTL8390_FAMILY_ID:
685 reg |= (RTL839X_DUPLEX_MODE | RTL839X_FORCE_LINK_EN);
686 break;
687 }
688 }
689
690 // Disable AN
691 if (priv->family_id == RTL8380_FAMILY_ID)
692 reg &= ~RTL838X_NWAY_EN;
693 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
694 }
695
696 static void rtl931x_phylink_mac_config(struct dsa_switch *ds, int port,
697 unsigned int mode,
698 const struct phylink_link_state *state)
699 {
700 struct rtl838x_switch_priv *priv = ds->priv;
701 int sds_num;
702 u32 reg, band;
703
704 sds_num = priv->ports[port].sds_num;
705 pr_info("%s: speed %d sds_num %d\n", __func__, state->speed, sds_num);
706
707 switch (state->interface) {
708 case PHY_INTERFACE_MODE_HSGMII:
709 pr_info("%s setting mode PHY_INTERFACE_MODE_HSGMII\n", __func__);
710 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_HSGMII);
711 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_HSGMII);
712 band = rtl931x_sds_cmu_band_set(sds_num, true, 62, PHY_INTERFACE_MODE_HSGMII);
713 break;
714 case PHY_INTERFACE_MODE_1000BASEX:
715 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_1000BASEX);
716 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_1000BASEX);
717 break;
718 case PHY_INTERFACE_MODE_XGMII:
719 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_XGMII);
720 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_XGMII);
721 break;
722 case PHY_INTERFACE_MODE_10GBASER:
723 case PHY_INTERFACE_MODE_10GKR:
724 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_10GBASER);
725 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_10GBASER);
726 break;
727 case PHY_INTERFACE_MODE_USXGMII:
728 // Translates to MII_USXGMII_10GSXGMII
729 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_USXGMII);
730 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_USXGMII);
731 break;
732 case PHY_INTERFACE_MODE_SGMII:
733 pr_info("%s setting mode PHY_INTERFACE_MODE_SGMII\n", __func__);
734 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_SGMII);
735 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_SGMII);
736 band = rtl931x_sds_cmu_band_set(sds_num, true, 62, PHY_INTERFACE_MODE_SGMII);
737 break;
738 case PHY_INTERFACE_MODE_QSGMII:
739 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_QSGMII);
740 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_QSGMII);
741 break;
742 default:
743 pr_err("%s: unknown serdes mode: %s\n",
744 __func__, phy_modes(state->interface));
745 return;
746 }
747
748 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
749 pr_info("%s reading FORCE_MODE_CTRL: %08x\n", __func__, reg);
750
751 reg &= ~(RTL931X_DUPLEX_MODE | RTL931X_FORCE_EN | RTL931X_FORCE_LINK_EN);
752
753 reg &= ~(0xf << 12);
754 reg |= 0x2 << 12; // Set SMI speed to 0x2
755
756 reg |= RTL931X_TX_PAUSE_EN | RTL931X_RX_PAUSE_EN;
757
758 if (priv->lagmembers & BIT_ULL(port))
759 reg |= RTL931X_DUPLEX_MODE;
760
761 if (state->duplex == DUPLEX_FULL)
762 reg |= RTL931X_DUPLEX_MODE;
763
764 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
765
766 }
767
768 static void rtl93xx_phylink_mac_config(struct dsa_switch *ds, int port,
769 unsigned int mode,
770 const struct phylink_link_state *state)
771 {
772 struct rtl838x_switch_priv *priv = ds->priv;
773 int sds_num, sds_mode;
774 u32 reg;
775
776 pr_info("%s port %d, mode %x, phy-mode: %s, speed %d, link %d\n", __func__,
777 port, mode, phy_modes(state->interface), state->speed, state->link);
778
779 // Nothing to be done for the CPU-port
780 if (port == priv->cpu_port)
781 return;
782
783 if (priv->family_id == RTL9310_FAMILY_ID)
784 return rtl931x_phylink_mac_config(ds, port, mode, state);
785
786 sds_num = priv->ports[port].sds_num;
787 pr_info("%s SDS is %d\n", __func__, sds_num);
788 if (sds_num >= 0) {
789 switch (state->interface) {
790 case PHY_INTERFACE_MODE_HSGMII:
791 sds_mode = 0x12;
792 break;
793 case PHY_INTERFACE_MODE_1000BASEX:
794 sds_mode = 0x04;
795 break;
796 case PHY_INTERFACE_MODE_XGMII:
797 sds_mode = 0x10;
798 break;
799 case PHY_INTERFACE_MODE_10GBASER:
800 case PHY_INTERFACE_MODE_10GKR:
801 sds_mode = 0x1b; // 10G 1000X Auto
802 break;
803 case PHY_INTERFACE_MODE_USXGMII:
804 sds_mode = 0x0d;
805 break;
806 default:
807 pr_err("%s: unknown serdes mode: %s\n",
808 __func__, phy_modes(state->interface));
809 return;
810 }
811 rtl9300_sds_rst(sds_num, sds_mode);
812 }
813
814 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
815 reg &= ~(0xf << 3);
816
817 switch (state->speed) {
818 case SPEED_10000:
819 reg |= 4 << 3;
820 break;
821 case SPEED_5000:
822 reg |= 6 << 3;
823 break;
824 case SPEED_2500:
825 reg |= 5 << 3;
826 break;
827 case SPEED_1000:
828 reg |= 2 << 3;
829 break;
830 default:
831 reg |= 2 << 3;
832 break;
833 }
834
835 if (state->link)
836 reg |= RTL930X_FORCE_LINK_EN;
837
838 if (priv->lagmembers & BIT_ULL(port))
839 reg |= RTL930X_DUPLEX_MODE | RTL930X_FORCE_LINK_EN;
840
841 if (state->duplex == DUPLEX_FULL)
842 reg |= RTL930X_DUPLEX_MODE;
843
844 if (priv->ports[port].phy_is_integrated)
845 reg &= ~RTL930X_FORCE_EN; // Clear MAC_FORCE_EN to allow SDS-MAC link
846 else
847 reg |= RTL930X_FORCE_EN;
848
849 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
850 }
851
852 static void rtl83xx_phylink_mac_link_down(struct dsa_switch *ds, int port,
853 unsigned int mode,
854 phy_interface_t interface)
855 {
856 struct rtl838x_switch_priv *priv = ds->priv;
857 u32 v;
858
859 /* Stop TX/RX to port */
860 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port));
861
862 // No longer force link
863 if (priv->family_id == RTL9300_FAMILY_ID)
864 v = RTL930X_FORCE_EN | RTL930X_FORCE_LINK_EN;
865 else if (priv->family_id == RTL9310_FAMILY_ID)
866 v = RTL931X_FORCE_EN | RTL931X_FORCE_LINK_EN;
867 sw_w32_mask(v, 0, priv->r->mac_port_ctrl(port));
868 }
869
870 static void rtl93xx_phylink_mac_link_down(struct dsa_switch *ds, int port,
871 unsigned int mode,
872 phy_interface_t interface)
873 {
874 struct rtl838x_switch_priv *priv = ds->priv;
875 /* Stop TX/RX to port */
876 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port));
877
878 // No longer force link
879 sw_w32_mask(3, 0, priv->r->mac_force_mode_ctrl(port));
880 }
881
882 static void rtl83xx_phylink_mac_link_up(struct dsa_switch *ds, int port,
883 unsigned int mode,
884 phy_interface_t interface,
885 struct phy_device *phydev,
886 int speed, int duplex,
887 bool tx_pause, bool rx_pause)
888 {
889 struct rtl838x_switch_priv *priv = ds->priv;
890 /* Restart TX/RX to port */
891 sw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port));
892 // TODO: Set speed/duplex/pauses
893 }
894
895 static void rtl93xx_phylink_mac_link_up(struct dsa_switch *ds, int port,
896 unsigned int mode,
897 phy_interface_t interface,
898 struct phy_device *phydev,
899 int speed, int duplex,
900 bool tx_pause, bool rx_pause)
901 {
902 struct rtl838x_switch_priv *priv = ds->priv;
903
904 /* Restart TX/RX to port */
905 sw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port));
906 // TODO: Set speed/duplex/pauses
907 }
908
909 static void rtl83xx_get_strings(struct dsa_switch *ds,
910 int port, u32 stringset, u8 *data)
911 {
912 int i;
913
914 if (stringset != ETH_SS_STATS)
915 return;
916
917 for (i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++)
918 strncpy(data + i * ETH_GSTRING_LEN, rtl83xx_mib[i].name,
919 ETH_GSTRING_LEN);
920 }
921
922 static void rtl83xx_get_ethtool_stats(struct dsa_switch *ds, int port,
923 uint64_t *data)
924 {
925 struct rtl838x_switch_priv *priv = ds->priv;
926 const struct rtl83xx_mib_desc *mib;
927 int i;
928 u64 h;
929
930 for (i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++) {
931 mib = &rtl83xx_mib[i];
932
933 data[i] = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 252 - mib->offset);
934 if (mib->size == 2) {
935 h = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 248 - mib->offset);
936 data[i] |= h << 32;
937 }
938 }
939 }
940
941 static int rtl83xx_get_sset_count(struct dsa_switch *ds, int port, int sset)
942 {
943 if (sset != ETH_SS_STATS)
944 return 0;
945
946 return ARRAY_SIZE(rtl83xx_mib);
947 }
948
949 static int rtl83xx_mc_group_alloc(struct rtl838x_switch_priv *priv, int port)
950 {
951 int mc_group = find_first_zero_bit(priv->mc_group_bm, MAX_MC_GROUPS - 1);
952 u64 portmask;
953
954 if (mc_group >= MAX_MC_GROUPS - 1)
955 return -1;
956
957 if (priv->is_lagmember[port]) {
958 pr_info("%s: %d is lag slave. ignore\n", __func__, port);
959 return 0;
960 }
961
962 set_bit(mc_group, priv->mc_group_bm);
963 mc_group++; // We cannot use group 0, as this is used for lookup miss flooding
964 portmask = BIT_ULL(port) | BIT_ULL(priv->cpu_port);
965 priv->r->write_mcast_pmask(mc_group, portmask);
966
967 return mc_group;
968 }
969
970 static u64 rtl83xx_mc_group_add_port(struct rtl838x_switch_priv *priv, int mc_group, int port)
971 {
972 u64 portmask = priv->r->read_mcast_pmask(mc_group);
973
974 pr_debug("%s: %d\n", __func__, port);
975 if (priv->is_lagmember[port]) {
976 pr_info("%s: %d is lag slave. ignore\n", __func__, port);
977 return portmask;
978 }
979 portmask |= BIT_ULL(port);
980 priv->r->write_mcast_pmask(mc_group, portmask);
981
982 return portmask;
983 }
984
985 static u64 rtl83xx_mc_group_del_port(struct rtl838x_switch_priv *priv, int mc_group, int port)
986 {
987 u64 portmask = priv->r->read_mcast_pmask(mc_group);
988
989 pr_debug("%s: %d\n", __func__, port);
990 if (priv->is_lagmember[port]) {
991 pr_info("%s: %d is lag slave. ignore\n", __func__, port);
992 return portmask;
993 }
994 priv->r->write_mcast_pmask(mc_group, portmask);
995 if (portmask == BIT_ULL(priv->cpu_port)) {
996 portmask &= ~BIT_ULL(priv->cpu_port);
997 priv->r->write_mcast_pmask(mc_group, portmask);
998 clear_bit(mc_group, priv->mc_group_bm);
999 }
1000
1001 return portmask;
1002 }
1003
1004 static void store_mcgroups(struct rtl838x_switch_priv *priv, int port)
1005 {
1006 int mc_group;
1007
1008 for (mc_group = 0; mc_group < MAX_MC_GROUPS; mc_group++) {
1009 u64 portmask = priv->r->read_mcast_pmask(mc_group);
1010 if (portmask & BIT_ULL(port)) {
1011 priv->mc_group_saves[mc_group] = port;
1012 rtl83xx_mc_group_del_port(priv, mc_group, port);
1013 }
1014 }
1015 }
1016
1017 static void load_mcgroups(struct rtl838x_switch_priv *priv, int port)
1018 {
1019 int mc_group;
1020
1021 for (mc_group = 0; mc_group < MAX_MC_GROUPS; mc_group++) {
1022 if (priv->mc_group_saves[mc_group] == port) {
1023 rtl83xx_mc_group_add_port(priv, mc_group, port);
1024 priv->mc_group_saves[mc_group] = -1;
1025 }
1026 }
1027 }
1028
1029 static int rtl83xx_port_enable(struct dsa_switch *ds, int port,
1030 struct phy_device *phydev)
1031 {
1032 struct rtl838x_switch_priv *priv = ds->priv;
1033 u64 v;
1034
1035 pr_debug("%s: %x %d", __func__, (u32) priv, port);
1036 priv->ports[port].enable = true;
1037
1038 /* enable inner tagging on egress, do not keep any tags */
1039 if (priv->family_id == RTL9310_FAMILY_ID)
1040 sw_w32(BIT(4), priv->r->vlan_port_tag_sts_ctrl + (port << 2));
1041 else
1042 sw_w32(1, priv->r->vlan_port_tag_sts_ctrl + (port << 2));
1043
1044 if (dsa_is_cpu_port(ds, port))
1045 return 0;
1046
1047 /* add port to switch mask of CPU_PORT */
1048 priv->r->traffic_enable(priv->cpu_port, port);
1049
1050 load_mcgroups(priv, port);
1051
1052 if (priv->is_lagmember[port]) {
1053 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1054 return 0;
1055 }
1056
1057 /* add all other ports in the same bridge to switch mask of port */
1058 v = priv->r->traffic_get(port);
1059 v |= priv->ports[port].pm;
1060 priv->r->traffic_set(port, v);
1061
1062 // TODO: Figure out if this is necessary
1063 if (priv->family_id == RTL9300_FAMILY_ID) {
1064 sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_SABLK_CTRL);
1065 sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_DABLK_CTRL);
1066 }
1067
1068 if (priv->ports[port].sds_num < 0)
1069 priv->ports[port].sds_num = rtl93xx_get_sds(phydev);
1070
1071 return 0;
1072 }
1073
1074 static void rtl83xx_port_disable(struct dsa_switch *ds, int port)
1075 {
1076 struct rtl838x_switch_priv *priv = ds->priv;
1077 u64 v;
1078
1079 pr_debug("%s %x: %d", __func__, (u32)priv, port);
1080 /* you can only disable user ports */
1081 if (!dsa_is_user_port(ds, port))
1082 return;
1083
1084 // BUG: This does not work on RTL931X
1085 /* remove port from switch mask of CPU_PORT */
1086 priv->r->traffic_disable(priv->cpu_port, port);
1087 store_mcgroups(priv, port);
1088
1089 /* remove all other ports in the same bridge from switch mask of port */
1090 v = priv->r->traffic_get(port);
1091 v &= ~priv->ports[port].pm;
1092 priv->r->traffic_set(port, v);
1093
1094 priv->ports[port].enable = false;
1095 }
1096
1097 static int rtl83xx_set_mac_eee(struct dsa_switch *ds, int port,
1098 struct ethtool_eee *e)
1099 {
1100 struct rtl838x_switch_priv *priv = ds->priv;
1101
1102 if (e->eee_enabled && !priv->eee_enabled) {
1103 pr_info("Globally enabling EEE\n");
1104 priv->r->init_eee(priv, true);
1105 }
1106
1107 priv->r->port_eee_set(priv, port, e->eee_enabled);
1108
1109 if (e->eee_enabled)
1110 pr_info("Enabled EEE for port %d\n", port);
1111 else
1112 pr_info("Disabled EEE for port %d\n", port);
1113 return 0;
1114 }
1115
1116 static int rtl83xx_get_mac_eee(struct dsa_switch *ds, int port,
1117 struct ethtool_eee *e)
1118 {
1119 struct rtl838x_switch_priv *priv = ds->priv;
1120
1121 e->supported = SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full;
1122
1123 priv->r->eee_port_ability(priv, e, port);
1124
1125 e->eee_enabled = priv->ports[port].eee_enabled;
1126
1127 e->eee_active = !!(e->advertised & e->lp_advertised);
1128
1129 return 0;
1130 }
1131
1132 static int rtl93xx_get_mac_eee(struct dsa_switch *ds, int port,
1133 struct ethtool_eee *e)
1134 {
1135 struct rtl838x_switch_priv *priv = ds->priv;
1136
1137 e->supported = SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full
1138 | SUPPORTED_2500baseX_Full;
1139
1140 priv->r->eee_port_ability(priv, e, port);
1141
1142 e->eee_enabled = priv->ports[port].eee_enabled;
1143
1144 e->eee_active = !!(e->advertised & e->lp_advertised);
1145
1146 return 0;
1147 }
1148
1149 static int rtl83xx_set_ageing_time(struct dsa_switch *ds, unsigned int msec)
1150 {
1151 struct rtl838x_switch_priv *priv = ds->priv;
1152
1153 priv->r->set_ageing_time(msec);
1154 return 0;
1155 }
1156
1157 static int rtl83xx_port_bridge_join(struct dsa_switch *ds, int port,
1158 struct net_device *bridge)
1159 {
1160 struct rtl838x_switch_priv *priv = ds->priv;
1161 u64 port_bitmap = BIT_ULL(priv->cpu_port), v;
1162 int i;
1163
1164 pr_debug("%s %x: %d %llx", __func__, (u32)priv, port, port_bitmap);
1165
1166 if (priv->is_lagmember[port]) {
1167 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1168 return 0;
1169 }
1170
1171 mutex_lock(&priv->reg_mutex);
1172 for (i = 0; i < ds->num_ports; i++) {
1173 /* Add this port to the port matrix of the other ports in the
1174 * same bridge. If the port is disabled, port matrix is kept
1175 * and not being setup until the port becomes enabled.
1176 */
1177 if (dsa_is_user_port(ds, i) && !priv->is_lagmember[i] && i != port) {
1178 if (dsa_to_port(ds, i)->bridge_dev != bridge)
1179 continue;
1180 if (priv->ports[i].enable)
1181 priv->r->traffic_enable(i, port);
1182
1183 priv->ports[i].pm |= BIT_ULL(port);
1184 port_bitmap |= BIT_ULL(i);
1185 }
1186 }
1187 load_mcgroups(priv, port);
1188
1189 /* Add all other ports to this port matrix. */
1190 if (priv->ports[port].enable) {
1191 priv->r->traffic_enable(priv->cpu_port, port);
1192 v = priv->r->traffic_get(port);
1193 v |= port_bitmap;
1194 priv->r->traffic_set(port, v);
1195 }
1196 priv->ports[port].pm |= port_bitmap;
1197 mutex_unlock(&priv->reg_mutex);
1198
1199 return 0;
1200 }
1201
1202 static void rtl83xx_port_bridge_leave(struct dsa_switch *ds, int port,
1203 struct net_device *bridge)
1204 {
1205 struct rtl838x_switch_priv *priv = ds->priv;
1206 u64 port_bitmap = BIT_ULL(priv->cpu_port), v;
1207 int i;
1208
1209 pr_debug("%s %x: %d", __func__, (u32)priv, port);
1210 mutex_lock(&priv->reg_mutex);
1211 for (i = 0; i < ds->num_ports; i++) {
1212 /* Remove this port from the port matrix of the other ports
1213 * in the same bridge. If the port is disabled, port matrix
1214 * is kept and not being setup until the port becomes enabled.
1215 * And the other port's port matrix cannot be broken when the
1216 * other port is still a VLAN-aware port.
1217 */
1218 if (dsa_is_user_port(ds, i) && i != port) {
1219 if (dsa_to_port(ds, i)->bridge_dev != bridge)
1220 continue;
1221 if (priv->ports[i].enable)
1222 priv->r->traffic_disable(i, port);
1223
1224 priv->ports[i].pm |= BIT_ULL(port);
1225 port_bitmap &= ~BIT_ULL(i);
1226 }
1227 }
1228 store_mcgroups(priv, port);
1229
1230 /* Add all other ports to this port matrix. */
1231 if (priv->ports[port].enable) {
1232 v = priv->r->traffic_get(port);
1233 v |= port_bitmap;
1234 priv->r->traffic_set(port, v);
1235 }
1236 priv->ports[port].pm &= ~port_bitmap;
1237
1238 mutex_unlock(&priv->reg_mutex);
1239 }
1240
1241 void rtl83xx_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1242 {
1243 u32 msti = 0;
1244 u32 port_state[4];
1245 int index, bit;
1246 int pos = port;
1247 struct rtl838x_switch_priv *priv = ds->priv;
1248 int n = priv->port_width << 1;
1249
1250 /* Ports above or equal CPU port can never be configured */
1251 if (port >= priv->cpu_port)
1252 return;
1253
1254 mutex_lock(&priv->reg_mutex);
1255
1256 /* For the RTL839x and following, the bits are left-aligned, 838x and 930x
1257 * have 64 bit fields, 839x and 931x have 128 bit fields
1258 */
1259 if (priv->family_id == RTL8390_FAMILY_ID)
1260 pos += 12;
1261 if (priv->family_id == RTL9300_FAMILY_ID)
1262 pos += 3;
1263 if (priv->family_id == RTL9310_FAMILY_ID)
1264 pos += 8;
1265
1266 index = n - (pos >> 4) - 1;
1267 bit = (pos << 1) % 32;
1268
1269 priv->r->stp_get(priv, msti, port_state);
1270
1271 pr_debug("Current state, port %d: %d\n", port, (port_state[index] >> bit) & 3);
1272 port_state[index] &= ~(3 << bit);
1273
1274 switch (state) {
1275 case BR_STATE_DISABLED: /* 0 */
1276 port_state[index] |= (0 << bit);
1277 break;
1278 case BR_STATE_BLOCKING: /* 4 */
1279 case BR_STATE_LISTENING: /* 1 */
1280 port_state[index] |= (1 << bit);
1281 break;
1282 case BR_STATE_LEARNING: /* 2 */
1283 port_state[index] |= (2 << bit);
1284 break;
1285 case BR_STATE_FORWARDING: /* 3*/
1286 port_state[index] |= (3 << bit);
1287 default:
1288 break;
1289 }
1290
1291 priv->r->stp_set(priv, msti, port_state);
1292
1293 mutex_unlock(&priv->reg_mutex);
1294 }
1295
1296 void rtl83xx_fast_age(struct dsa_switch *ds, int port)
1297 {
1298 struct rtl838x_switch_priv *priv = ds->priv;
1299 int s = priv->family_id == RTL8390_FAMILY_ID ? 2 : 0;
1300
1301 pr_debug("FAST AGE port %d\n", port);
1302 mutex_lock(&priv->reg_mutex);
1303 /* RTL838X_L2_TBL_FLUSH_CTRL register bits, 839x has 1 bit larger
1304 * port fields:
1305 * 0-4: Replacing port
1306 * 5-9: Flushed/replaced port
1307 * 10-21: FVID
1308 * 22: Entry types: 1: dynamic, 0: also static
1309 * 23: Match flush port
1310 * 24: Match FVID
1311 * 25: Flush (0) or replace (1) L2 entries
1312 * 26: Status of action (1: Start, 0: Done)
1313 */
1314 sw_w32(1 << (26 + s) | 1 << (23 + s) | port << (5 + (s / 2)), priv->r->l2_tbl_flush_ctrl);
1315
1316 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(26 + s));
1317
1318 mutex_unlock(&priv->reg_mutex);
1319 }
1320
1321 void rtl931x_fast_age(struct dsa_switch *ds, int port)
1322 {
1323 struct rtl838x_switch_priv *priv = ds->priv;
1324
1325 pr_info("%s port %d\n", __func__, port);
1326 mutex_lock(&priv->reg_mutex);
1327 sw_w32(port << 11, RTL931X_L2_TBL_FLUSH_CTRL + 4);
1328
1329 sw_w32(BIT(24) | BIT(28), RTL931X_L2_TBL_FLUSH_CTRL);
1330
1331 do { } while (sw_r32(RTL931X_L2_TBL_FLUSH_CTRL) & BIT (28));
1332
1333 mutex_unlock(&priv->reg_mutex);
1334 }
1335
1336 void rtl930x_fast_age(struct dsa_switch *ds, int port)
1337 {
1338 struct rtl838x_switch_priv *priv = ds->priv;
1339
1340 if (priv->family_id == RTL9310_FAMILY_ID)
1341 return rtl931x_fast_age(ds, port);
1342
1343 pr_debug("FAST AGE port %d\n", port);
1344 mutex_lock(&priv->reg_mutex);
1345 sw_w32(port << 11, RTL930X_L2_TBL_FLUSH_CTRL + 4);
1346
1347 sw_w32(BIT(26) | BIT(30), RTL930X_L2_TBL_FLUSH_CTRL);
1348
1349 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(30));
1350
1351 mutex_unlock(&priv->reg_mutex);
1352 }
1353
1354 static int rtl83xx_vlan_filtering(struct dsa_switch *ds, int port,
1355 bool vlan_filtering,
1356 struct switchdev_trans *trans)
1357 {
1358 struct rtl838x_switch_priv *priv = ds->priv;
1359
1360 pr_debug("%s: port %d\n", __func__, port);
1361 mutex_lock(&priv->reg_mutex);
1362
1363 if (vlan_filtering) {
1364 /* Enable ingress and egress filtering
1365 * The VLAN_PORT_IGR_FILTER register uses 2 bits for each port to define
1366 * the filter action:
1367 * 0: Always Forward
1368 * 1: Drop packet
1369 * 2: Trap packet to CPU port
1370 * The Egress filter used 1 bit per state (0: DISABLED, 1: ENABLED)
1371 */
1372 if (port != priv->cpu_port)
1373 priv->r->set_vlan_igr_filter(port, IGR_DROP);
1374
1375 priv->r->set_vlan_egr_filter(port, EGR_ENABLE);
1376 } else {
1377 /* Disable ingress and egress filtering */
1378 if (port != priv->cpu_port)
1379 priv->r->set_vlan_igr_filter(port, IGR_FORWARD);
1380
1381 priv->r->set_vlan_egr_filter(port, EGR_DISABLE);
1382 }
1383
1384 /* Do we need to do something to the CPU-Port, too? */
1385 mutex_unlock(&priv->reg_mutex);
1386
1387 return 0;
1388 }
1389
1390 static int rtl83xx_vlan_prepare(struct dsa_switch *ds, int port,
1391 const struct switchdev_obj_port_vlan *vlan)
1392 {
1393 struct rtl838x_vlan_info info;
1394 struct rtl838x_switch_priv *priv = ds->priv;
1395
1396 priv->r->vlan_tables_read(0, &info);
1397
1398 pr_debug("VLAN 0: Tagged ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\n",
1399 info.tagged_ports, info.untagged_ports, info.profile_id,
1400 info.hash_mc_fid, info.hash_uc_fid, info.fid);
1401
1402 priv->r->vlan_tables_read(1, &info);
1403 pr_debug("VLAN 1: Tagged ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\n",
1404 info.tagged_ports, info.untagged_ports, info.profile_id,
1405 info.hash_mc_fid, info.hash_uc_fid, info.fid);
1406 priv->r->vlan_set_untagged(1, info.untagged_ports);
1407 pr_debug("SET: Untagged ports, VLAN %d: %llx\n", 1, info.untagged_ports);
1408
1409 priv->r->vlan_set_tagged(1, &info);
1410 pr_debug("SET: Tagged ports, VLAN %d: %llx\n", 1, info.tagged_ports);
1411
1412 mutex_unlock(&priv->reg_mutex);
1413 return 0;
1414 }
1415
1416 static void rtl83xx_vlan_add(struct dsa_switch *ds, int port,
1417 const struct switchdev_obj_port_vlan *vlan)
1418 {
1419 struct rtl838x_vlan_info info;
1420 struct rtl838x_switch_priv *priv = ds->priv;
1421 int v;
1422
1423 pr_debug("%s port %d, vid_end %d, vid_end %d, flags %x\n", __func__,
1424 port, vlan->vid_begin, vlan->vid_end, vlan->flags);
1425
1426 if (vlan->vid_begin > 4095 || vlan->vid_end > 4095) {
1427 dev_err(priv->dev, "VLAN out of range: %d - %d",
1428 vlan->vid_begin, vlan->vid_end);
1429 return;
1430 }
1431
1432 mutex_lock(&priv->reg_mutex);
1433
1434 if (vlan->flags & BRIDGE_VLAN_INFO_PVID) {
1435 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
1436 if (!v)
1437 continue;
1438 /* Set both inner and outer PVID of the port */
1439 priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_INNER, v);
1440 priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_OUTER, v);
1441 priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_INNER,
1442 PBVLAN_MODE_UNTAG_AND_PRITAG);
1443 priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_OUTER,
1444 PBVLAN_MODE_UNTAG_AND_PRITAG);
1445
1446 priv->ports[port].pvid = vlan->vid_end;
1447 }
1448 }
1449
1450 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
1451 /* Get port memberships of this vlan */
1452 priv->r->vlan_tables_read(v, &info);
1453
1454 /* new VLAN? */
1455 if (!info.tagged_ports) {
1456 info.fid = 0;
1457 info.hash_mc_fid = false;
1458 info.hash_uc_fid = false;
1459 info.profile_id = 0;
1460 }
1461
1462 /* sanitize untagged_ports - must be a subset */
1463 if (info.untagged_ports & ~info.tagged_ports)
1464 info.untagged_ports = 0;
1465
1466 info.tagged_ports |= BIT_ULL(port);
1467 if (vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED)
1468 info.untagged_ports |= BIT_ULL(port);
1469
1470 priv->r->vlan_set_untagged(v, info.untagged_ports);
1471 pr_debug("Untagged ports, VLAN %d: %llx\n", v, info.untagged_ports);
1472
1473 priv->r->vlan_set_tagged(v, &info);
1474 pr_debug("Tagged ports, VLAN %d: %llx\n", v, info.tagged_ports);
1475 }
1476
1477 mutex_unlock(&priv->reg_mutex);
1478 }
1479
1480 static int rtl83xx_vlan_del(struct dsa_switch *ds, int port,
1481 const struct switchdev_obj_port_vlan *vlan)
1482 {
1483 struct rtl838x_vlan_info info;
1484 struct rtl838x_switch_priv *priv = ds->priv;
1485 int v;
1486 u16 pvid;
1487
1488 pr_debug("%s: port %d, vid_end %d, vid_end %d, flags %x\n", __func__,
1489 port, vlan->vid_begin, vlan->vid_end, vlan->flags);
1490
1491 if (vlan->vid_begin > 4095 || vlan->vid_end > 4095) {
1492 dev_err(priv->dev, "VLAN out of range: %d - %d",
1493 vlan->vid_begin, vlan->vid_end);
1494 return -ENOTSUPP;
1495 }
1496
1497 mutex_lock(&priv->reg_mutex);
1498 pvid = priv->ports[port].pvid;
1499
1500 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
1501 /* Reset to default if removing the current PVID */
1502 if (v == pvid) {
1503 priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_INNER, 0);
1504 priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_OUTER, 0);
1505 priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_INNER,
1506 PBVLAN_MODE_UNTAG_AND_PRITAG);
1507 priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_OUTER,
1508 PBVLAN_MODE_UNTAG_AND_PRITAG);
1509 }
1510 /* Get port memberships of this vlan */
1511 priv->r->vlan_tables_read(v, &info);
1512
1513 /* remove port from both tables */
1514 info.untagged_ports &= (~BIT_ULL(port));
1515 info.tagged_ports &= (~BIT_ULL(port));
1516
1517 priv->r->vlan_set_untagged(v, info.untagged_ports);
1518 pr_debug("Untagged ports, VLAN %d: %llx\n", v, info.untagged_ports);
1519
1520 priv->r->vlan_set_tagged(v, &info);
1521 pr_debug("Tagged ports, VLAN %d: %llx\n", v, info.tagged_ports);
1522 }
1523 mutex_unlock(&priv->reg_mutex);
1524
1525 return 0;
1526 }
1527
1528 static void dump_l2_entry(struct rtl838x_l2_entry *e)
1529 {
1530 pr_info("MAC: %02x:%02x:%02x:%02x:%02x:%02x vid: %d, rvid: %d, port: %d, valid: %d\n",
1531 e->mac[0], e->mac[1], e->mac[2], e->mac[3], e->mac[4], e->mac[5],
1532 e->vid, e->rvid, e->port, e->valid);
1533
1534 if (e->type != L2_MULTICAST) {
1535 pr_info("Type: %d, is_static: %d, is_ip_mc: %d, is_ipv6_mc: %d, block_da: %d\n",
1536 e->type, e->is_static, e->is_ip_mc, e->is_ipv6_mc, e->block_da);
1537 pr_info(" block_sa: %d, susp: %d, nh: %d, age: %d, is_trunk: %d, trunk: %d\n",
1538 e->block_sa, e->suspended, e->next_hop, e->age, e->is_trunk, e->trunk);
1539 }
1540 if (e->type == L2_MULTICAST)
1541 pr_info(" L2_MULTICAST mc_portmask_index: %d\n", e->mc_portmask_index);
1542 if (e->is_ip_mc || e->is_ipv6_mc)
1543 pr_info(" mc_portmask_index: %d, mc_gip: %d, mc_sip: %d\n",
1544 e->mc_portmask_index, e->mc_gip, e->mc_sip);
1545 pr_info(" stack_dev: %d\n", e->stack_dev);
1546 if (e->next_hop)
1547 pr_info(" nh_route_id: %d\n", e->nh_route_id);
1548 }
1549
1550 static void rtl83xx_setup_l2_uc_entry(struct rtl838x_l2_entry *e, int port, int vid, u64 mac)
1551 {
1552 e->is_ip_mc = e->is_ipv6_mc = false;
1553 e->valid = true;
1554 e->age = 3;
1555 e->port = port,
1556 e->vid = vid;
1557 u64_to_ether_addr(mac, e->mac);
1558 }
1559
1560 static void rtl83xx_setup_l2_mc_entry(struct rtl838x_switch_priv *priv,
1561 struct rtl838x_l2_entry *e, int vid, u64 mac, int mc_group)
1562 {
1563 e->is_ip_mc = e->is_ipv6_mc = false;
1564 e->valid = true;
1565 e->mc_portmask_index = mc_group;
1566 e->type = L2_MULTICAST;
1567 e->rvid = e->vid = vid;
1568 pr_debug("%s: vid: %d, rvid: %d\n", __func__, e->vid, e->rvid);
1569 u64_to_ether_addr(mac, e->mac);
1570 }
1571
1572 /*
1573 * Uses the seed to identify a hash bucket in the L2 using the derived hash key and then loops
1574 * over the entries in the bucket until either a matching entry is found or an empty slot
1575 * Returns the filled in rtl838x_l2_entry and the index in the bucket when an entry was found
1576 * when an empty slot was found and must exist is false, the index of the slot is returned
1577 * when no slots are available returns -1
1578 */
1579 static int rtl83xx_find_l2_hash_entry(struct rtl838x_switch_priv *priv, u64 seed,
1580 bool must_exist, struct rtl838x_l2_entry *e)
1581 {
1582 int i, idx = -1;
1583 u32 key = priv->r->l2_hash_key(priv, seed);
1584 u64 entry;
1585
1586 pr_debug("%s: using key %x, for seed %016llx\n", __func__, key, seed);
1587 // Loop over all entries in the hash-bucket and over the second block on 93xx SoCs
1588 for (i = 0; i < priv->l2_bucket_size; i++) {
1589 entry = priv->r->read_l2_entry_using_hash(key, i, e);
1590 pr_debug("valid %d, mac %016llx\n", e->valid, ether_addr_to_u64(&e->mac[0]));
1591 if (must_exist && !e->valid)
1592 continue;
1593 if (!e->valid || ((entry & 0x0fffffffffffffffULL) == seed)) {
1594 idx = i > 3 ? ((key >> 14) & 0xffff) | i >> 1 : ((key << 2) | i) & 0xffff;
1595 break;
1596 }
1597 }
1598
1599 return idx;
1600 }
1601
1602 /*
1603 * Uses the seed to identify an entry in the CAM by looping over all its entries
1604 * Returns the filled in rtl838x_l2_entry and the index in the CAM when an entry was found
1605 * when an empty slot was found the index of the slot is returned
1606 * when no slots are available returns -1
1607 */
1608 static int rtl83xx_find_l2_cam_entry(struct rtl838x_switch_priv *priv, u64 seed,
1609 bool must_exist, struct rtl838x_l2_entry *e)
1610 {
1611 int i, idx = -1;
1612 u64 entry;
1613
1614 for (i = 0; i < 64; i++) {
1615 entry = priv->r->read_cam(i, e);
1616 if (!must_exist && !e->valid) {
1617 if (idx < 0) /* First empty entry? */
1618 idx = i;
1619 break;
1620 } else if ((entry & 0x0fffffffffffffffULL) == seed) {
1621 pr_debug("Found entry in CAM\n");
1622 idx = i;
1623 break;
1624 }
1625 }
1626 return idx;
1627 }
1628
1629 static int rtl83xx_port_fdb_add(struct dsa_switch *ds, int port,
1630 const unsigned char *addr, u16 vid)
1631 {
1632 struct rtl838x_switch_priv *priv = ds->priv;
1633 u64 mac = ether_addr_to_u64(addr);
1634 struct rtl838x_l2_entry e;
1635 int err = 0, idx;
1636 u64 seed = priv->r->l2_hash_seed(mac, vid);
1637
1638 if (priv->is_lagmember[port]) {
1639 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1640 return 0;
1641 }
1642
1643 mutex_lock(&priv->reg_mutex);
1644
1645 idx = rtl83xx_find_l2_hash_entry(priv, seed, false, &e);
1646
1647 // Found an existing or empty entry
1648 if (idx >= 0) {
1649 rtl83xx_setup_l2_uc_entry(&e, port, vid, mac);
1650 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1651 goto out;
1652 }
1653
1654 // Hash buckets full, try CAM
1655 rtl83xx_find_l2_cam_entry(priv, seed, false, &e);
1656
1657 if (idx >= 0) {
1658 rtl83xx_setup_l2_uc_entry(&e, port, vid, mac);
1659 priv->r->write_cam(idx, &e);
1660 goto out;
1661 }
1662
1663 err = -ENOTSUPP;
1664 out:
1665 mutex_unlock(&priv->reg_mutex);
1666 return err;
1667 }
1668
1669 static int rtl83xx_port_fdb_del(struct dsa_switch *ds, int port,
1670 const unsigned char *addr, u16 vid)
1671 {
1672 struct rtl838x_switch_priv *priv = ds->priv;
1673 u64 mac = ether_addr_to_u64(addr);
1674 struct rtl838x_l2_entry e;
1675 int err = 0, idx;
1676 u64 seed = priv->r->l2_hash_seed(mac, vid);
1677
1678 pr_info("In %s, mac %llx, vid: %d\n", __func__, mac, vid);
1679 mutex_lock(&priv->reg_mutex);
1680
1681 idx = rtl83xx_find_l2_hash_entry(priv, seed, true, &e);
1682
1683 pr_info("Found entry index %d, key %d and bucket %d\n", idx, idx >> 2, idx & 3);
1684 if (idx >= 0) {
1685 e.valid = false;
1686 dump_l2_entry(&e);
1687 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1688 goto out;
1689 }
1690
1691 /* Check CAM for spillover from hash buckets */
1692 rtl83xx_find_l2_cam_entry(priv, seed, true, &e);
1693
1694 if (idx >= 0) {
1695 e.valid = false;
1696 priv->r->write_cam(idx, &e);
1697 goto out;
1698 }
1699 err = -ENOENT;
1700 out:
1701 mutex_unlock(&priv->reg_mutex);
1702 return err;
1703 }
1704
1705 static int rtl83xx_port_fdb_dump(struct dsa_switch *ds, int port,
1706 dsa_fdb_dump_cb_t *cb, void *data)
1707 {
1708 struct rtl838x_l2_entry e;
1709 struct rtl838x_switch_priv *priv = ds->priv;
1710 int i;
1711 u32 fid, pkey;
1712 u64 mac;
1713
1714 mutex_lock(&priv->reg_mutex);
1715
1716 for (i = 0; i < priv->fib_entries; i++) {
1717 priv->r->read_l2_entry_using_hash(i >> 2, i & 0x3, &e);
1718
1719 if (!e.valid)
1720 continue;
1721
1722 if (e.port == port || e.port == RTL930X_PORT_IGNORE) {
1723 u64 seed;
1724 u32 key;
1725
1726 fid = ((i >> 2) & 0x3ff) | (e.rvid & ~0x3ff);
1727 mac = ether_addr_to_u64(&e.mac[0]);
1728 pkey = priv->r->l2_hash_key(priv, priv->r->l2_hash_seed(mac, fid));
1729 fid = (pkey & 0x3ff) | (fid & ~0x3ff);
1730 pr_info("-> index %d, key %x, bucket %d, dmac %016llx, fid: %x rvid: %x\n",
1731 i, i >> 2, i & 0x3, mac, fid, e.rvid);
1732 dump_l2_entry(&e);
1733 seed = priv->r->l2_hash_seed(mac, e.rvid);
1734 key = priv->r->l2_hash_key(priv, seed);
1735 pr_info("seed: %016llx, key based on rvid: %08x\n", seed, key);
1736 cb(e.mac, e.vid, e.is_static, data);
1737 }
1738 if (e.type == L2_MULTICAST) {
1739 u64 portmask = priv->r->read_mcast_pmask(e.mc_portmask_index);
1740
1741 if (portmask & BIT_ULL(port)) {
1742 dump_l2_entry(&e);
1743 pr_info(" PM: %016llx\n", portmask);
1744 }
1745 }
1746 }
1747
1748 for (i = 0; i < 64; i++) {
1749 priv->r->read_cam(i, &e);
1750
1751 if (!e.valid)
1752 continue;
1753
1754 if (e.port == port)
1755 cb(e.mac, e.vid, e.is_static, data);
1756 }
1757
1758 mutex_unlock(&priv->reg_mutex);
1759 return 0;
1760 }
1761
1762 static int rtl83xx_port_mdb_prepare(struct dsa_switch *ds, int port,
1763 const struct switchdev_obj_port_mdb *mdb)
1764 {
1765 struct rtl838x_switch_priv *priv = ds->priv;
1766
1767 if (priv->id >= 0x9300)
1768 return -EOPNOTSUPP;
1769
1770 return 0;
1771 }
1772
1773 static void rtl83xx_port_mdb_add(struct dsa_switch *ds, int port,
1774 const struct switchdev_obj_port_mdb *mdb)
1775 {
1776 struct rtl838x_switch_priv *priv = ds->priv;
1777 u64 mac = ether_addr_to_u64(mdb->addr);
1778 struct rtl838x_l2_entry e;
1779 int err = 0, idx;
1780 int vid = mdb->vid;
1781 u64 seed = priv->r->l2_hash_seed(mac, vid);
1782 int mc_group;
1783
1784 pr_debug("In %s port %d, mac %llx, vid: %d\n", __func__, port, mac, vid);
1785
1786 if (priv->is_lagmember[port]) {
1787 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1788 return;
1789 }
1790
1791 mutex_lock(&priv->reg_mutex);
1792
1793 idx = rtl83xx_find_l2_hash_entry(priv, seed, false, &e);
1794
1795 // Found an existing or empty entry
1796 if (idx >= 0) {
1797 if (e.valid) {
1798 pr_debug("Found an existing entry %016llx, mc_group %d\n",
1799 ether_addr_to_u64(e.mac), e.mc_portmask_index);
1800 rtl83xx_mc_group_add_port(priv, e.mc_portmask_index, port);
1801 } else {
1802 pr_debug("New entry for seed %016llx\n", seed);
1803 mc_group = rtl83xx_mc_group_alloc(priv, port);
1804 if (mc_group < 0) {
1805 err = -ENOTSUPP;
1806 goto out;
1807 }
1808 rtl83xx_setup_l2_mc_entry(priv, &e, vid, mac, mc_group);
1809 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1810 }
1811 goto out;
1812 }
1813
1814 // Hash buckets full, try CAM
1815 rtl83xx_find_l2_cam_entry(priv, seed, false, &e);
1816
1817 if (idx >= 0) {
1818 if (e.valid) {
1819 pr_debug("Found existing CAM entry %016llx, mc_group %d\n",
1820 ether_addr_to_u64(e.mac), e.mc_portmask_index);
1821 rtl83xx_mc_group_add_port(priv, e.mc_portmask_index, port);
1822 } else {
1823 pr_debug("New entry\n");
1824 mc_group = rtl83xx_mc_group_alloc(priv, port);
1825 if (mc_group < 0) {
1826 err = -ENOTSUPP;
1827 goto out;
1828 }
1829 rtl83xx_setup_l2_mc_entry(priv, &e, vid, mac, mc_group);
1830 priv->r->write_cam(idx, &e);
1831 }
1832 goto out;
1833 }
1834
1835 err = -ENOTSUPP;
1836 out:
1837 mutex_unlock(&priv->reg_mutex);
1838 if (err)
1839 dev_err(ds->dev, "failed to add MDB entry\n");
1840 }
1841
1842 int rtl83xx_port_mdb_del(struct dsa_switch *ds, int port,
1843 const struct switchdev_obj_port_mdb *mdb)
1844 {
1845 struct rtl838x_switch_priv *priv = ds->priv;
1846 u64 mac = ether_addr_to_u64(mdb->addr);
1847 struct rtl838x_l2_entry e;
1848 int err = 0, idx;
1849 int vid = mdb->vid;
1850 u64 seed = priv->r->l2_hash_seed(mac, vid);
1851 u64 portmask;
1852
1853 pr_debug("In %s, port %d, mac %llx, vid: %d\n", __func__, port, mac, vid);
1854
1855 if (priv->is_lagmember[port]) {
1856 pr_info("%s: %d is lag slave. ignore\n", __func__, port);
1857 return 0;
1858 }
1859
1860 mutex_lock(&priv->reg_mutex);
1861
1862 idx = rtl83xx_find_l2_hash_entry(priv, seed, true, &e);
1863
1864 pr_debug("Found entry index %d, key %d and bucket %d\n", idx, idx >> 2, idx & 3);
1865 if (idx >= 0) {
1866 portmask = rtl83xx_mc_group_del_port(priv, e.mc_portmask_index, port);
1867 if (!portmask) {
1868 e.valid = false;
1869 // dump_l2_entry(&e);
1870 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1871 }
1872 goto out;
1873 }
1874
1875 /* Check CAM for spillover from hash buckets */
1876 rtl83xx_find_l2_cam_entry(priv, seed, true, &e);
1877
1878 if (idx >= 0) {
1879 portmask = rtl83xx_mc_group_del_port(priv, e.mc_portmask_index, port);
1880 if (!portmask) {
1881 e.valid = false;
1882 // dump_l2_entry(&e);
1883 priv->r->write_cam(idx, &e);
1884 }
1885 goto out;
1886 }
1887 // TODO: Re-enable with a newer kernel: err = -ENOENT;
1888 out:
1889 mutex_unlock(&priv->reg_mutex);
1890 return err;
1891 }
1892
1893 static int rtl83xx_port_mirror_add(struct dsa_switch *ds, int port,
1894 struct dsa_mall_mirror_tc_entry *mirror,
1895 bool ingress)
1896 {
1897 /* We support 4 mirror groups, one destination port per group */
1898 int group;
1899 struct rtl838x_switch_priv *priv = ds->priv;
1900 int ctrl_reg, dpm_reg, spm_reg;
1901
1902 pr_debug("In %s\n", __func__);
1903
1904 for (group = 0; group < 4; group++) {
1905 if (priv->mirror_group_ports[group] == mirror->to_local_port)
1906 break;
1907 }
1908 if (group >= 4) {
1909 for (group = 0; group < 4; group++) {
1910 if (priv->mirror_group_ports[group] < 0)
1911 break;
1912 }
1913 }
1914
1915 if (group >= 4)
1916 return -ENOSPC;
1917
1918 ctrl_reg = priv->r->mir_ctrl + group * 4;
1919 dpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width;
1920 spm_reg = priv->r->mir_spm + group * 4 * priv->port_width;
1921
1922 pr_debug("Using group %d\n", group);
1923 mutex_lock(&priv->reg_mutex);
1924
1925 if (priv->family_id == RTL8380_FAMILY_ID) {
1926 /* Enable mirroring to port across VLANs (bit 11) */
1927 sw_w32(1 << 11 | (mirror->to_local_port << 4) | 1, ctrl_reg);
1928 } else {
1929 /* Enable mirroring to destination port */
1930 sw_w32((mirror->to_local_port << 4) | 1, ctrl_reg);
1931 }
1932
1933 if (ingress && (priv->r->get_port_reg_be(spm_reg) & (1ULL << port))) {
1934 mutex_unlock(&priv->reg_mutex);
1935 return -EEXIST;
1936 }
1937 if ((!ingress) && (priv->r->get_port_reg_be(dpm_reg) & (1ULL << port))) {
1938 mutex_unlock(&priv->reg_mutex);
1939 return -EEXIST;
1940 }
1941
1942 if (ingress)
1943 priv->r->mask_port_reg_be(0, 1ULL << port, spm_reg);
1944 else
1945 priv->r->mask_port_reg_be(0, 1ULL << port, dpm_reg);
1946
1947 priv->mirror_group_ports[group] = mirror->to_local_port;
1948 mutex_unlock(&priv->reg_mutex);
1949 return 0;
1950 }
1951
1952 static void rtl83xx_port_mirror_del(struct dsa_switch *ds, int port,
1953 struct dsa_mall_mirror_tc_entry *mirror)
1954 {
1955 int group = 0;
1956 struct rtl838x_switch_priv *priv = ds->priv;
1957 int ctrl_reg, dpm_reg, spm_reg;
1958
1959 pr_debug("In %s\n", __func__);
1960 for (group = 0; group < 4; group++) {
1961 if (priv->mirror_group_ports[group] == mirror->to_local_port)
1962 break;
1963 }
1964 if (group >= 4)
1965 return;
1966
1967 ctrl_reg = priv->r->mir_ctrl + group * 4;
1968 dpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width;
1969 spm_reg = priv->r->mir_spm + group * 4 * priv->port_width;
1970
1971 mutex_lock(&priv->reg_mutex);
1972 if (mirror->ingress) {
1973 /* Ingress, clear source port matrix */
1974 priv->r->mask_port_reg_be(1ULL << port, 0, spm_reg);
1975 } else {
1976 /* Egress, clear destination port matrix */
1977 priv->r->mask_port_reg_be(1ULL << port, 0, dpm_reg);
1978 }
1979
1980 if (!(sw_r32(spm_reg) || sw_r32(dpm_reg))) {
1981 priv->mirror_group_ports[group] = -1;
1982 sw_w32(0, ctrl_reg);
1983 }
1984
1985 mutex_unlock(&priv->reg_mutex);
1986 }
1987
1988 static int rtl83xx_port_pre_bridge_flags(struct dsa_switch *ds, int port, unsigned long flags, struct netlink_ext_ack *extack)
1989 {
1990 struct rtl838x_switch_priv *priv = ds->priv;
1991 unsigned long features = 0;
1992 pr_debug("%s: %d %lX\n", __func__, port, flags);
1993 if (priv->r->enable_learning)
1994 features |= BR_LEARNING;
1995 if (priv->r->enable_flood)
1996 features |= BR_FLOOD;
1997 if (priv->r->enable_mcast_flood)
1998 features |= BR_MCAST_FLOOD;
1999 if (priv->r->enable_bcast_flood)
2000 features |= BR_BCAST_FLOOD;
2001 if (flags & ~(features))
2002 return -EINVAL;
2003
2004 return 0;
2005 }
2006
2007 static int rtl83xx_port_bridge_flags(struct dsa_switch *ds, int port, unsigned long flags, struct netlink_ext_ack *extack)
2008 {
2009 struct rtl838x_switch_priv *priv = ds->priv;
2010
2011 pr_debug("%s: %d %lX\n", __func__, port, flags);
2012 if (priv->r->enable_learning)
2013 priv->r->enable_learning(port, !!(flags & BR_LEARNING));
2014
2015 if (priv->r->enable_flood)
2016 priv->r->enable_flood(port, !!(flags & BR_FLOOD));
2017
2018 if (priv->r->enable_mcast_flood)
2019 priv->r->enable_mcast_flood(port, !!(flags & BR_MCAST_FLOOD));
2020
2021 if (priv->r->enable_bcast_flood)
2022 priv->r->enable_bcast_flood(port, !!(flags & BR_BCAST_FLOOD));
2023
2024 return 0;
2025 }
2026
2027 static bool rtl83xx_lag_can_offload(struct dsa_switch *ds,
2028 struct net_device *lag,
2029 struct netdev_lag_upper_info *info)
2030 {
2031 int id;
2032
2033 id = dsa_lag_id(ds->dst, lag);
2034 if (id < 0 || id >= ds->num_lag_ids)
2035 return false;
2036
2037 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
2038 return false;
2039 }
2040 if (info->hash_type != NETDEV_LAG_HASH_L2 && info->hash_type != NETDEV_LAG_HASH_L23)
2041 return false;
2042
2043 return true;
2044 }
2045
2046 static int rtl83xx_port_lag_change(struct dsa_switch *ds, int port)
2047 {
2048 struct rtl838x_switch_priv *priv = ds->priv;
2049
2050 pr_debug("%s: %d\n", __func__, port);
2051 // Nothing to be done...
2052
2053 return 0;
2054 }
2055
2056 static int rtl83xx_port_lag_join(struct dsa_switch *ds, int port,
2057 struct net_device *lag,
2058 struct netdev_lag_upper_info *info)
2059 {
2060 struct rtl838x_switch_priv *priv = ds->priv;
2061 int i, err = 0;
2062
2063 if (!rtl83xx_lag_can_offload(ds, lag, info))
2064 return -EOPNOTSUPP;
2065
2066 mutex_lock(&priv->reg_mutex);
2067
2068 for (i = 0; i < priv->n_lags; i++) {
2069 if ((!priv->lag_devs[i]) || (priv->lag_devs[i] == lag))
2070 break;
2071 }
2072 if (port >= priv->cpu_port) {
2073 err = -EINVAL;
2074 goto out;
2075 }
2076 pr_info("port_lag_join: group %d, port %d\n",i, port);
2077 if (!priv->lag_devs[i])
2078 priv->lag_devs[i] = lag;
2079
2080 if (priv->lag_primary[i]==-1) {
2081 priv->lag_primary[i]=port;
2082 } else
2083 priv->is_lagmember[port] = 1;
2084
2085 priv->lagmembers |= (1ULL << port);
2086
2087 pr_debug("lag_members = %llX\n", priv->lagmembers);
2088 err = rtl83xx_lag_add(priv->ds, i, port, info);
2089 if (err) {
2090 err = -EINVAL;
2091 goto out;
2092 }
2093
2094 out:
2095 mutex_unlock(&priv->reg_mutex);
2096 return err;
2097
2098 }
2099
2100 static int rtl83xx_port_lag_leave(struct dsa_switch *ds, int port,
2101 struct net_device *lag)
2102 {
2103 int i, group = -1, err;
2104 struct rtl838x_switch_priv *priv = ds->priv;
2105
2106 mutex_lock(&priv->reg_mutex);
2107 for (i=0;i<priv->n_lags;i++) {
2108 if (priv->lags_port_members[i] & BIT_ULL(port)) {
2109 group = i;
2110 break;
2111 }
2112 }
2113
2114 if (group == -1) {
2115 pr_info("port_lag_leave: port %d is not a member\n", port);
2116 err = -EINVAL;
2117 goto out;
2118 }
2119
2120 if (port >= priv->cpu_port) {
2121 err = -EINVAL;
2122 goto out;
2123 }
2124 pr_info("port_lag_del: group %d, port %d\n",group, port);
2125 priv->lagmembers &=~ (1ULL << port);
2126 priv->lag_primary[i] = -1;
2127 priv->is_lagmember[port] = 0;
2128 pr_debug("lag_members = %llX\n", priv->lagmembers);
2129 err = rtl83xx_lag_del(priv->ds, group, port);
2130 if (err) {
2131 err = -EINVAL;
2132 goto out;
2133 }
2134 if (!priv->lags_port_members[i])
2135 priv->lag_devs[i] = NULL;
2136
2137 out:
2138 mutex_unlock(&priv->reg_mutex);
2139 return 0;
2140 }
2141
2142 int dsa_phy_read(struct dsa_switch *ds, int phy_addr, int phy_reg)
2143 {
2144 u32 val;
2145 u32 offset = 0;
2146 struct rtl838x_switch_priv *priv = ds->priv;
2147
2148 if (phy_addr >= 24 && phy_addr <= 27
2149 && priv->ports[24].phy == PHY_RTL838X_SDS) {
2150 if (phy_addr == 26)
2151 offset = 0x100;
2152 val = sw_r32(RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2)) & 0xffff;
2153 return val;
2154 }
2155
2156 read_phy(phy_addr, 0, phy_reg, &val);
2157 return val;
2158 }
2159
2160 int dsa_phy_write(struct dsa_switch *ds, int phy_addr, int phy_reg, u16 val)
2161 {
2162 u32 offset = 0;
2163 struct rtl838x_switch_priv *priv = ds->priv;
2164
2165 if (phy_addr >= 24 && phy_addr <= 27
2166 && priv->ports[24].phy == PHY_RTL838X_SDS) {
2167 if (phy_addr == 26)
2168 offset = 0x100;
2169 sw_w32(val, RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2));
2170 return 0;
2171 }
2172 return write_phy(phy_addr, 0, phy_reg, val);
2173 }
2174
2175 const struct dsa_switch_ops rtl83xx_switch_ops = {
2176 .get_tag_protocol = rtl83xx_get_tag_protocol,
2177 .setup = rtl83xx_setup,
2178
2179 .phy_read = dsa_phy_read,
2180 .phy_write = dsa_phy_write,
2181
2182 .phylink_validate = rtl83xx_phylink_validate,
2183 .phylink_mac_link_state = rtl83xx_phylink_mac_link_state,
2184 .phylink_mac_config = rtl83xx_phylink_mac_config,
2185 .phylink_mac_link_down = rtl83xx_phylink_mac_link_down,
2186 .phylink_mac_link_up = rtl83xx_phylink_mac_link_up,
2187
2188 .get_strings = rtl83xx_get_strings,
2189 .get_ethtool_stats = rtl83xx_get_ethtool_stats,
2190 .get_sset_count = rtl83xx_get_sset_count,
2191
2192 .port_enable = rtl83xx_port_enable,
2193 .port_disable = rtl83xx_port_disable,
2194
2195 .get_mac_eee = rtl83xx_get_mac_eee,
2196 .set_mac_eee = rtl83xx_set_mac_eee,
2197
2198 .set_ageing_time = rtl83xx_set_ageing_time,
2199 .port_bridge_join = rtl83xx_port_bridge_join,
2200 .port_bridge_leave = rtl83xx_port_bridge_leave,
2201 .port_stp_state_set = rtl83xx_port_stp_state_set,
2202 .port_fast_age = rtl83xx_fast_age,
2203
2204 .port_vlan_filtering = rtl83xx_vlan_filtering,
2205 .port_vlan_prepare = rtl83xx_vlan_prepare,
2206 .port_vlan_add = rtl83xx_vlan_add,
2207 .port_vlan_del = rtl83xx_vlan_del,
2208
2209 .port_fdb_add = rtl83xx_port_fdb_add,
2210 .port_fdb_del = rtl83xx_port_fdb_del,
2211 .port_fdb_dump = rtl83xx_port_fdb_dump,
2212
2213 .port_mdb_prepare = rtl83xx_port_mdb_prepare,
2214 .port_mdb_add = rtl83xx_port_mdb_add,
2215 .port_mdb_del = rtl83xx_port_mdb_del,
2216
2217 .port_mirror_add = rtl83xx_port_mirror_add,
2218 .port_mirror_del = rtl83xx_port_mirror_del,
2219
2220 .port_lag_change = rtl83xx_port_lag_change,
2221 .port_lag_join = rtl83xx_port_lag_join,
2222 .port_lag_leave = rtl83xx_port_lag_leave,
2223
2224 .port_pre_bridge_flags = rtl83xx_port_pre_bridge_flags,
2225 .port_bridge_flags = rtl83xx_port_bridge_flags,
2226 };
2227
2228 const struct dsa_switch_ops rtl930x_switch_ops = {
2229 .get_tag_protocol = rtl83xx_get_tag_protocol,
2230 .setup = rtl93xx_setup,
2231
2232 .phy_read = dsa_phy_read,
2233 .phy_write = dsa_phy_write,
2234
2235 .phylink_validate = rtl93xx_phylink_validate,
2236 .phylink_mac_link_state = rtl93xx_phylink_mac_link_state,
2237 .phylink_mac_config = rtl93xx_phylink_mac_config,
2238 .phylink_mac_link_down = rtl93xx_phylink_mac_link_down,
2239 .phylink_mac_link_up = rtl93xx_phylink_mac_link_up,
2240
2241 .get_strings = rtl83xx_get_strings,
2242 .get_ethtool_stats = rtl83xx_get_ethtool_stats,
2243 .get_sset_count = rtl83xx_get_sset_count,
2244
2245 .port_enable = rtl83xx_port_enable,
2246 .port_disable = rtl83xx_port_disable,
2247
2248 .get_mac_eee = rtl93xx_get_mac_eee,
2249 .set_mac_eee = rtl83xx_set_mac_eee,
2250
2251 .set_ageing_time = rtl83xx_set_ageing_time,
2252 .port_bridge_join = rtl83xx_port_bridge_join,
2253 .port_bridge_leave = rtl83xx_port_bridge_leave,
2254 .port_stp_state_set = rtl83xx_port_stp_state_set,
2255 .port_fast_age = rtl930x_fast_age,
2256
2257 .port_vlan_filtering = rtl83xx_vlan_filtering,
2258 .port_vlan_prepare = rtl83xx_vlan_prepare,
2259 .port_vlan_add = rtl83xx_vlan_add,
2260 .port_vlan_del = rtl83xx_vlan_del,
2261
2262 .port_fdb_add = rtl83xx_port_fdb_add,
2263 .port_fdb_del = rtl83xx_port_fdb_del,
2264 .port_fdb_dump = rtl83xx_port_fdb_dump,
2265
2266 .port_mdb_prepare = rtl83xx_port_mdb_prepare,
2267 .port_mdb_add = rtl83xx_port_mdb_add,
2268 .port_mdb_del = rtl83xx_port_mdb_del,
2269
2270 .port_lag_change = rtl83xx_port_lag_change,
2271 .port_lag_join = rtl83xx_port_lag_join,
2272 .port_lag_leave = rtl83xx_port_lag_leave,
2273
2274 .port_pre_bridge_flags = rtl83xx_port_pre_bridge_flags,
2275 .port_bridge_flags = rtl83xx_port_bridge_flags,
2276 };
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