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realtek: Fix bug when accessing external PHYs on SoCs older than Revision C
[openwrt/openwrt.git] / target / linux / realtek / files-5.10 / drivers / net / dsa / rtl83xx / rtl839x.c
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <asm/mach-rtl838x/mach-rtl83xx.h>
4 #include "rtl83xx.h"
5
6 extern struct mutex smi_lock;
7 extern struct rtl83xx_soc_info soc_info;
8
9 /* Definition of the RTL839X-specific template field IDs as used in the PIE */
10 enum template_field_id {
11 TEMPLATE_FIELD_SPMMASK = 0,
12 TEMPLATE_FIELD_SPM0 = 1, // Source portmask ports 0-15
13 TEMPLATE_FIELD_SPM1 = 2, // Source portmask ports 16-31
14 TEMPLATE_FIELD_SPM2 = 3, // Source portmask ports 32-47
15 TEMPLATE_FIELD_SPM3 = 4, // Source portmask ports 48-56
16 TEMPLATE_FIELD_DMAC0 = 5, // Destination MAC [15:0]
17 TEMPLATE_FIELD_DMAC1 = 6, // Destination MAC [31:16]
18 TEMPLATE_FIELD_DMAC2 = 7, // Destination MAC [47:32]
19 TEMPLATE_FIELD_SMAC0 = 8, // Source MAC [15:0]
20 TEMPLATE_FIELD_SMAC1 = 9, // Source MAC [31:16]
21 TEMPLATE_FIELD_SMAC2 = 10, // Source MAC [47:32]
22 TEMPLATE_FIELD_ETHERTYPE = 11, // Ethernet frame type field
23 // Field-ID 12 is not used
24 TEMPLATE_FIELD_OTAG = 13,
25 TEMPLATE_FIELD_ITAG = 14,
26 TEMPLATE_FIELD_SIP0 = 15,
27 TEMPLATE_FIELD_SIP1 = 16,
28 TEMPLATE_FIELD_DIP0 = 17,
29 TEMPLATE_FIELD_DIP1 = 18,
30 TEMPLATE_FIELD_IP_TOS_PROTO = 19,
31 TEMPLATE_FIELD_IP_FLAG = 20,
32 TEMPLATE_FIELD_L4_SPORT = 21,
33 TEMPLATE_FIELD_L4_DPORT = 22,
34 TEMPLATE_FIELD_L34_HEADER = 23,
35 TEMPLATE_FIELD_ICMP_IGMP = 24,
36 TEMPLATE_FIELD_VID_RANG0 = 25,
37 TEMPLATE_FIELD_VID_RANG1 = 26,
38 TEMPLATE_FIELD_L4_PORT_RANG = 27,
39 TEMPLATE_FIELD_FIELD_SELECTOR_VALID = 28,
40 TEMPLATE_FIELD_FIELD_SELECTOR_0 = 29,
41 TEMPLATE_FIELD_FIELD_SELECTOR_1 = 30,
42 TEMPLATE_FIELD_FIELD_SELECTOR_2 = 31,
43 TEMPLATE_FIELD_FIELD_SELECTOR_3 = 32,
44 TEMPLATE_FIELD_FIELD_SELECTOR_4 = 33,
45 TEMPLATE_FIELD_FIELD_SELECTOR_5 = 34,
46 TEMPLATE_FIELD_SIP2 = 35,
47 TEMPLATE_FIELD_SIP3 = 36,
48 TEMPLATE_FIELD_SIP4 = 37,
49 TEMPLATE_FIELD_SIP5 = 38,
50 TEMPLATE_FIELD_SIP6 = 39,
51 TEMPLATE_FIELD_SIP7 = 40,
52 TEMPLATE_FIELD_OLABEL = 41,
53 TEMPLATE_FIELD_ILABEL = 42,
54 TEMPLATE_FIELD_OILABEL = 43,
55 TEMPLATE_FIELD_DPMMASK = 44,
56 TEMPLATE_FIELD_DPM0 = 45,
57 TEMPLATE_FIELD_DPM1 = 46,
58 TEMPLATE_FIELD_DPM2 = 47,
59 TEMPLATE_FIELD_DPM3 = 48,
60 TEMPLATE_FIELD_L2DPM0 = 49,
61 TEMPLATE_FIELD_L2DPM1 = 50,
62 TEMPLATE_FIELD_L2DPM2 = 51,
63 TEMPLATE_FIELD_L2DPM3 = 52,
64 TEMPLATE_FIELD_IVLAN = 53,
65 TEMPLATE_FIELD_OVLAN = 54,
66 TEMPLATE_FIELD_FWD_VID = 55,
67 TEMPLATE_FIELD_DIP2 = 56,
68 TEMPLATE_FIELD_DIP3 = 57,
69 TEMPLATE_FIELD_DIP4 = 58,
70 TEMPLATE_FIELD_DIP5 = 59,
71 TEMPLATE_FIELD_DIP6 = 60,
72 TEMPLATE_FIELD_DIP7 = 61,
73 };
74
75 // Number of fixed templates predefined in the SoC
76 #define N_FIXED_TEMPLATES 5
77 static enum template_field_id fixed_templates[N_FIXED_TEMPLATES][N_FIXED_FIELDS] =
78 {
79 {
80 TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1, TEMPLATE_FIELD_ITAG,
81 TEMPLATE_FIELD_SMAC0, TEMPLATE_FIELD_SMAC1, TEMPLATE_FIELD_SMAC2,
82 TEMPLATE_FIELD_DMAC0, TEMPLATE_FIELD_DMAC1, TEMPLATE_FIELD_DMAC2,
83 TEMPLATE_FIELD_ETHERTYPE, TEMPLATE_FIELD_SPM2, TEMPLATE_FIELD_SPM3
84 }, {
85 TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_DIP0,
86 TEMPLATE_FIELD_DIP1,TEMPLATE_FIELD_IP_TOS_PROTO, TEMPLATE_FIELD_L4_SPORT,
87 TEMPLATE_FIELD_L4_DPORT, TEMPLATE_FIELD_ICMP_IGMP, TEMPLATE_FIELD_SPM0,
88 TEMPLATE_FIELD_SPM1, TEMPLATE_FIELD_SPM2, TEMPLATE_FIELD_SPM3
89 }, {
90 TEMPLATE_FIELD_DMAC0, TEMPLATE_FIELD_DMAC1, TEMPLATE_FIELD_DMAC2,
91 TEMPLATE_FIELD_ITAG, TEMPLATE_FIELD_ETHERTYPE, TEMPLATE_FIELD_IP_TOS_PROTO,
92 TEMPLATE_FIELD_L4_DPORT, TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_SIP0,
93 TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_DIP0, TEMPLATE_FIELD_DIP1
94 }, {
95 TEMPLATE_FIELD_DIP0, TEMPLATE_FIELD_DIP1, TEMPLATE_FIELD_DIP2,
96 TEMPLATE_FIELD_DIP3, TEMPLATE_FIELD_DIP4, TEMPLATE_FIELD_DIP5,
97 TEMPLATE_FIELD_DIP6, TEMPLATE_FIELD_DIP7, TEMPLATE_FIELD_L4_DPORT,
98 TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_ICMP_IGMP, TEMPLATE_FIELD_IP_TOS_PROTO
99 }, {
100 TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_SIP2,
101 TEMPLATE_FIELD_SIP3, TEMPLATE_FIELD_SIP4, TEMPLATE_FIELD_SIP5,
102 TEMPLATE_FIELD_SIP6, TEMPLATE_FIELD_SIP7, TEMPLATE_FIELD_SPM0,
103 TEMPLATE_FIELD_SPM1, TEMPLATE_FIELD_SPM2, TEMPLATE_FIELD_SPM3
104 },
105 };
106
107 void rtl839x_print_matrix(void)
108 {
109 volatile u64 *ptr9;
110 int i;
111
112 ptr9 = RTL838X_SW_BASE + RTL839X_PORT_ISO_CTRL(0);
113 for (i = 0; i < 52; i += 4)
114 pr_debug("> %16llx %16llx %16llx %16llx\n",
115 ptr9[i + 0], ptr9[i + 1], ptr9[i + 2], ptr9[i + 3]);
116 pr_debug("CPU_PORT> %16llx\n", ptr9[52]);
117 }
118
119 static inline int rtl839x_port_iso_ctrl(int p)
120 {
121 return RTL839X_PORT_ISO_CTRL(p);
122 }
123
124 static inline void rtl839x_exec_tbl0_cmd(u32 cmd)
125 {
126 sw_w32(cmd, RTL839X_TBL_ACCESS_CTRL_0);
127 do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_0) & BIT(16));
128 }
129
130 static inline void rtl839x_exec_tbl1_cmd(u32 cmd)
131 {
132 sw_w32(cmd, RTL839X_TBL_ACCESS_CTRL_1);
133 do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_1) & BIT(16));
134 }
135
136 inline void rtl839x_exec_tbl2_cmd(u32 cmd)
137 {
138 sw_w32(cmd, RTL839X_TBL_ACCESS_CTRL_2);
139 do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_2) & (1 << 9));
140 }
141
142 static inline int rtl839x_tbl_access_data_0(int i)
143 {
144 return RTL839X_TBL_ACCESS_DATA_0(i);
145 }
146
147 static void rtl839x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info)
148 {
149 u32 u, v, w;
150 // Read VLAN table (0) via register 0
151 struct table_reg *r = rtl_table_get(RTL8390_TBL_0, 0);
152
153 rtl_table_read(r, vlan);
154 u = sw_r32(rtl_table_data(r, 0));
155 v = sw_r32(rtl_table_data(r, 1));
156 w = sw_r32(rtl_table_data(r, 2));
157 rtl_table_release(r);
158
159 info->tagged_ports = u;
160 info->tagged_ports = (info->tagged_ports << 21) | ((v >> 11) & 0x1fffff);
161 info->profile_id = w >> 30 | ((v & 1) << 2);
162 info->hash_mc_fid = !!(w & BIT(2));
163 info->hash_uc_fid = !!(w & BIT(3));
164 info->fid = (v >> 3) & 0xff;
165
166 // Read UNTAG table (0) via table register 1
167 r = rtl_table_get(RTL8390_TBL_1, 0);
168 rtl_table_read(r, vlan);
169 u = sw_r32(rtl_table_data(r, 0));
170 v = sw_r32(rtl_table_data(r, 1));
171 rtl_table_release(r);
172
173 info->untagged_ports = u;
174 info->untagged_ports = (info->untagged_ports << 21) | ((v >> 11) & 0x1fffff);
175 }
176
177 static void rtl839x_vlan_set_tagged(u32 vlan, struct rtl838x_vlan_info *info)
178 {
179 u32 u, v, w;
180 // Access VLAN table (0) via register 0
181 struct table_reg *r = rtl_table_get(RTL8390_TBL_0, 0);
182
183 u = info->tagged_ports >> 21;
184 v = info->tagged_ports << 11;
185 v |= ((u32)info->fid) << 3;
186 v |= info->hash_uc_fid ? BIT(2) : 0;
187 v |= info->hash_mc_fid ? BIT(1) : 0;
188 v |= (info->profile_id & 0x4) ? 1 : 0;
189 w = ((u32)(info->profile_id & 3)) << 30;
190
191 sw_w32(u, rtl_table_data(r, 0));
192 sw_w32(v, rtl_table_data(r, 1));
193 sw_w32(w, rtl_table_data(r, 2));
194
195 rtl_table_write(r, vlan);
196 rtl_table_release(r);
197 }
198
199 static void rtl839x_vlan_set_untagged(u32 vlan, u64 portmask)
200 {
201 u32 u, v;
202
203 // Access UNTAG table (0) via table register 1
204 struct table_reg *r = rtl_table_get(RTL8390_TBL_1, 0);
205
206 u = portmask >> 21;
207 v = portmask << 11;
208
209 sw_w32(u, rtl_table_data(r, 0));
210 sw_w32(v, rtl_table_data(r, 1));
211 rtl_table_write(r, vlan);
212
213 rtl_table_release(r);
214 }
215
216 /* Sets the L2 forwarding to be based on either the inner VLAN tag or the outer
217 */
218 static void rtl839x_vlan_fwd_on_inner(int port, bool is_set)
219 {
220 if (is_set)
221 rtl839x_mask_port_reg_be(BIT_ULL(port), 0ULL, RTL839X_VLAN_PORT_FWD);
222 else
223 rtl839x_mask_port_reg_be(0ULL, BIT_ULL(port), RTL839X_VLAN_PORT_FWD);
224 }
225
226 /*
227 * Hash seed is vid (actually rvid) concatenated with the MAC address
228 */
229 static u64 rtl839x_l2_hash_seed(u64 mac, u32 vid)
230 {
231 u64 v = vid;
232
233 v <<= 48;
234 v |= mac;
235
236 return v;
237 }
238
239 /*
240 * Applies the same hash algorithm as the one used currently by the ASIC to the seed
241 * and returns a key into the L2 hash table
242 */
243 static u32 rtl839x_l2_hash_key(struct rtl838x_switch_priv *priv, u64 seed)
244 {
245 u32 h1, h2, h;
246
247 if (sw_r32(priv->r->l2_ctrl_0) & 1) {
248 h1 = (u32) (((seed >> 60) & 0x3f) ^ ((seed >> 54) & 0x3f)
249 ^ ((seed >> 36) & 0x3f) ^ ((seed >> 30) & 0x3f)
250 ^ ((seed >> 12) & 0x3f) ^ ((seed >> 6) & 0x3f));
251 h2 = (u32) (((seed >> 48) & 0x3f) ^ ((seed >> 42) & 0x3f)
252 ^ ((seed >> 24) & 0x3f) ^ ((seed >> 18) & 0x3f)
253 ^ (seed & 0x3f));
254 h = (h1 << 6) | h2;
255 } else {
256 h = (seed >> 60)
257 ^ ((((seed >> 48) & 0x3f) << 6) | ((seed >> 54) & 0x3f))
258 ^ ((seed >> 36) & 0xfff) ^ ((seed >> 24) & 0xfff)
259 ^ ((seed >> 12) & 0xfff) ^ (seed & 0xfff);
260 }
261
262 return h;
263 }
264
265 static inline int rtl839x_mac_force_mode_ctrl(int p)
266 {
267 return RTL839X_MAC_FORCE_MODE_CTRL + (p << 2);
268 }
269
270 static inline int rtl839x_mac_port_ctrl(int p)
271 {
272 return RTL839X_MAC_PORT_CTRL(p);
273 }
274
275 static inline int rtl839x_l2_port_new_salrn(int p)
276 {
277 return RTL839X_L2_PORT_NEW_SALRN(p);
278 }
279
280 static inline int rtl839x_l2_port_new_sa_fwd(int p)
281 {
282 return RTL839X_L2_PORT_NEW_SA_FWD(p);
283 }
284
285 static inline int rtl839x_mac_link_spd_sts(int p)
286 {
287 return RTL839X_MAC_LINK_SPD_STS(p);
288 }
289
290 static inline int rtl839x_trk_mbr_ctr(int group)
291 {
292 return RTL839X_TRK_MBR_CTR + (group << 3);
293 }
294
295 static void rtl839x_fill_l2_entry(u32 r[], struct rtl838x_l2_entry *e)
296 {
297 /* Table contains different entry types, we need to identify the right one:
298 * Check for MC entries, first
299 */
300 e->is_ip_mc = !!(r[2] & BIT(31));
301 e->is_ipv6_mc = !!(r[2] & BIT(30));
302 e->type = L2_INVALID;
303 if (!e->is_ip_mc && !e->is_ipv6_mc) {
304 e->mac[0] = (r[0] >> 12);
305 e->mac[1] = (r[0] >> 4);
306 e->mac[2] = ((r[1] >> 28) | (r[0] << 4));
307 e->mac[3] = (r[1] >> 20);
308 e->mac[4] = (r[1] >> 12);
309 e->mac[5] = (r[1] >> 4);
310
311 e->vid = (r[2] >> 4) & 0xfff;
312 e->rvid = (r[0] >> 20) & 0xfff;
313
314 /* Is it a unicast entry? check multicast bit */
315 if (!(e->mac[0] & 1)) {
316 e->is_static = !!((r[2] >> 18) & 1);
317 e->port = (r[2] >> 24) & 0x3f;
318 e->block_da = !!(r[2] & (1 << 19));
319 e->block_sa = !!(r[2] & (1 << 20));
320 e->suspended = !!(r[2] & (1 << 17));
321 e->next_hop = !!(r[2] & (1 << 16));
322 if (e->next_hop) {
323 pr_debug("Found next hop entry, need to read data\n");
324 e->nh_vlan_target = !!(r[2] & BIT(15));
325 e->nh_route_id = (r[2] >> 4) & 0x1ff;
326 e->vid = e->rvid;
327 }
328 e->age = (r[2] >> 21) & 3;
329 e->valid = true;
330 if (!(r[2] & 0xc0fd0000)) /* Check for valid entry */
331 e->valid = false;
332 else
333 e->type = L2_UNICAST;
334 } else {
335 e->valid = true;
336 e->type = L2_MULTICAST;
337 e->mc_portmask_index = (r[2] >> 6) & 0xfff;
338 e->vid = e->rvid;
339 }
340 } else { // IPv4 and IPv6 multicast
341 e->vid = e->rvid = (r[0] << 20) & 0xfff;
342 e->mc_gip = r[1];
343 e->mc_portmask_index = (r[2] >> 6) & 0xfff;
344 }
345 if (e->is_ip_mc) {
346 e->valid = true;
347 e->type = IP4_MULTICAST;
348 }
349 if (e->is_ipv6_mc) {
350 e->valid = true;
351 e->type = IP6_MULTICAST;
352 }
353 // pr_info("%s: vid %d, rvid: %d\n", __func__, e->vid, e->rvid);
354 }
355
356 /*
357 * Fills the 3 SoC table registers r[] with the information in the rtl838x_l2_entry
358 */
359 static void rtl839x_fill_l2_row(u32 r[], struct rtl838x_l2_entry *e)
360 {
361 if (!e->valid) {
362 r[0] = r[1] = r[2] = 0;
363 return;
364 }
365
366 r[2] = e->is_ip_mc ? BIT(31) : 0;
367 r[2] |= e->is_ipv6_mc ? BIT(30) : 0;
368
369 if (!e->is_ip_mc && !e->is_ipv6_mc) {
370 r[0] = ((u32)e->mac[0]) << 12;
371 r[0] |= ((u32)e->mac[1]) << 4;
372 r[0] |= ((u32)e->mac[2]) >> 4;
373 r[1] = ((u32)e->mac[2]) << 28;
374 r[1] |= ((u32)e->mac[3]) << 20;
375 r[1] |= ((u32)e->mac[4]) << 12;
376 r[1] |= ((u32)e->mac[5]) << 4;
377
378 if (!(e->mac[0] & 1)) { // Not multicast
379 r[2] |= e->is_static ? BIT(18) : 0;
380 r[0] |= ((u32)e->rvid) << 20;
381 r[2] |= e->port << 24;
382 r[2] |= e->block_da ? BIT(19) : 0;
383 r[2] |= e->block_sa ? BIT(20) : 0;
384 r[2] |= e->suspended ? BIT(17) : 0;
385 r[2] |= ((u32)e->age) << 21;
386 if (e->next_hop) {
387 r[2] |= BIT(16);
388 r[2] |= e->nh_vlan_target ? BIT(15) : 0;
389 r[2] |= (e->nh_route_id & 0x7ff) << 4;
390 } else {
391 r[2] |= e->vid << 4;
392 }
393 pr_debug("Write L2 NH: %08x %08x %08x\n", r[0], r[1], r[2]);
394 } else { // L2 Multicast
395 r[0] |= ((u32)e->rvid) << 20;
396 r[2] |= ((u32)e->mc_portmask_index) << 6;
397 }
398 } else { // IPv4 or IPv6 MC entry
399 r[0] = ((u32)e->rvid) << 20;
400 r[1] = e->mc_gip;
401 r[2] |= ((u32)e->mc_portmask_index) << 6;
402 }
403 }
404
405 /*
406 * Read an L2 UC or MC entry out of a hash bucket of the L2 forwarding table
407 * hash is the id of the bucket and pos is the position of the entry in that bucket
408 * The data read from the SoC is filled into rtl838x_l2_entry
409 */
410 static u64 rtl839x_read_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e)
411 {
412 u32 r[3];
413 struct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 0);
414 u32 idx = (0 << 14) | (hash << 2) | pos; // Search SRAM, with hash and at pos in bucket
415 int i;
416
417 rtl_table_read(q, idx);
418 for (i= 0; i < 3; i++)
419 r[i] = sw_r32(rtl_table_data(q, i));
420
421 rtl_table_release(q);
422
423 rtl839x_fill_l2_entry(r, e);
424 if (!e->valid)
425 return 0;
426
427 return rtl839x_l2_hash_seed(ether_addr_to_u64(&e->mac[0]), e->rvid);
428 }
429
430 static void rtl839x_write_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e)
431 {
432 u32 r[3];
433 struct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 0);
434 int i;
435
436 u32 idx = (0 << 14) | (hash << 2) | pos; // Access SRAM, with hash and at pos in bucket
437
438 rtl839x_fill_l2_row(r, e);
439
440 for (i= 0; i < 3; i++)
441 sw_w32(r[i], rtl_table_data(q, i));
442
443 rtl_table_write(q, idx);
444 rtl_table_release(q);
445 }
446
447 static u64 rtl839x_read_cam(int idx, struct rtl838x_l2_entry *e)
448 {
449 u32 r[3];
450 struct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 1); // Access L2 Table 1
451 int i;
452
453 rtl_table_read(q, idx);
454 for (i= 0; i < 3; i++)
455 r[i] = sw_r32(rtl_table_data(q, i));
456
457 rtl_table_release(q);
458
459 rtl839x_fill_l2_entry(r, e);
460 if (!e->valid)
461 return 0;
462
463 pr_debug("Found in CAM: R1 %x R2 %x R3 %x\n", r[0], r[1], r[2]);
464
465 // Return MAC with concatenated VID ac concatenated ID
466 return rtl839x_l2_hash_seed(ether_addr_to_u64(&e->mac[0]), e->rvid);
467 }
468
469 static void rtl839x_write_cam(int idx, struct rtl838x_l2_entry *e)
470 {
471 u32 r[3];
472 struct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 1); // Access L2 Table 1
473 int i;
474
475 rtl839x_fill_l2_row(r, e);
476
477 for (i= 0; i < 3; i++)
478 sw_w32(r[i], rtl_table_data(q, i));
479
480 rtl_table_write(q, idx);
481 rtl_table_release(q);
482 }
483
484 static u64 rtl839x_read_mcast_pmask(int idx)
485 {
486 u64 portmask;
487 // Read MC_PMSK (2) via register RTL8390_TBL_L2
488 struct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 2);
489
490 rtl_table_read(q, idx);
491 portmask = sw_r32(rtl_table_data(q, 0));
492 portmask <<= 32;
493 portmask |= sw_r32(rtl_table_data(q, 1));
494 portmask >>= 11; // LSB is bit 11 in data registers
495 rtl_table_release(q);
496
497 return portmask;
498 }
499
500 static void rtl839x_write_mcast_pmask(int idx, u64 portmask)
501 {
502 // Access MC_PMSK (2) via register RTL8380_TBL_L2
503 struct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 2);
504
505 portmask <<= 11; // LSB is bit 11 in data registers
506 sw_w32((u32)(portmask >> 32), rtl_table_data(q, 0));
507 sw_w32((u32)((portmask & 0xfffff800)), rtl_table_data(q, 1));
508 rtl_table_write(q, idx);
509 rtl_table_release(q);
510 }
511
512 static void rtl839x_vlan_profile_setup(int profile)
513 {
514 u32 p[2];
515 u32 pmask_id = UNKNOWN_MC_PMASK;
516
517 p[0] = pmask_id; // Use portmaks 0xfff for unknown IPv6 MC flooding
518 // Enable L2 Learning BIT 0, portmask UNKNOWN_MC_PMASK for IP/L2-MC traffic flooding
519 p[1] = 1 | pmask_id << 1 | pmask_id << 13;
520
521 sw_w32(p[0], RTL839X_VLAN_PROFILE(profile));
522 sw_w32(p[1], RTL839X_VLAN_PROFILE(profile) + 4);
523
524 rtl839x_write_mcast_pmask(UNKNOWN_MC_PMASK, 0x001fffffffffffff);
525 }
526
527 u64 rtl839x_traffic_get(int source)
528 {
529 return rtl839x_get_port_reg_be(rtl839x_port_iso_ctrl(source));
530 }
531
532 void rtl839x_traffic_set(int source, u64 dest_matrix)
533 {
534 rtl839x_set_port_reg_be(dest_matrix, rtl839x_port_iso_ctrl(source));
535 }
536
537 void rtl839x_traffic_enable(int source, int dest)
538 {
539 rtl839x_mask_port_reg_be(0, BIT_ULL(dest), rtl839x_port_iso_ctrl(source));
540 }
541
542 void rtl839x_traffic_disable(int source, int dest)
543 {
544 rtl839x_mask_port_reg_be(BIT_ULL(dest), 0, rtl839x_port_iso_ctrl(source));
545 }
546
547 static void rtl839x_l2_learning_setup(void)
548 {
549 /* Set portmask for broadcast (offset bit 12) and unknown unicast (offset 0)
550 * address flooding to the reserved entry in the portmask table used
551 * also for multicast flooding */
552 sw_w32(UNKNOWN_MC_PMASK << 12 | UNKNOWN_MC_PMASK, RTL839X_L2_FLD_PMSK);
553
554 // Limit learning to maximum: 32k entries, after that just flood (bits 0-1)
555 sw_w32((0x7fff << 2) | 0, RTL839X_L2_LRN_CONSTRT);
556
557 // Do not trap ARP packets to CPU_PORT
558 sw_w32(0, RTL839X_SPCL_TRAP_ARP_CTRL);
559 }
560
561 irqreturn_t rtl839x_switch_irq(int irq, void *dev_id)
562 {
563 struct dsa_switch *ds = dev_id;
564 u32 status = sw_r32(RTL839X_ISR_GLB_SRC);
565 u64 ports = rtl839x_get_port_reg_le(RTL839X_ISR_PORT_LINK_STS_CHG);
566 u64 link;
567 int i;
568
569 /* Clear status */
570 rtl839x_set_port_reg_le(ports, RTL839X_ISR_PORT_LINK_STS_CHG);
571 pr_debug("RTL8390 Link change: status: %x, ports %llx\n", status, ports);
572
573 for (i = 0; i < RTL839X_CPU_PORT; i++) {
574 if (ports & BIT_ULL(i)) {
575 link = rtl839x_get_port_reg_le(RTL839X_MAC_LINK_STS);
576 if (link & BIT_ULL(i))
577 dsa_port_phylink_mac_change(ds, i, true);
578 else
579 dsa_port_phylink_mac_change(ds, i, false);
580 }
581 }
582 return IRQ_HANDLED;
583 }
584
585 // TODO: unused
586 int rtl8390_sds_power(int mac, int val)
587 {
588 u32 offset = (mac == 48) ? 0x0 : 0x100;
589 u32 mode = val ? 0 : 1;
590
591 pr_debug("In %s: mac %d, set %d\n", __func__, mac, val);
592
593 if ((mac != 48) && (mac != 49)) {
594 pr_err("%s: not an SFP port: %d\n", __func__, mac);
595 return -1;
596 }
597
598 // Set bit 1003. 1000 starts at 7c
599 sw_w32_mask(BIT(11), mode << 11, RTL839X_SDS12_13_PWR0 + offset);
600
601 return 0;
602 }
603
604 int rtl839x_read_phy(u32 port, u32 page, u32 reg, u32 *val)
605 {
606 u32 v;
607
608 if (port > 63 || page > 4095 || reg > 31)
609 return -ENOTSUPP;
610
611 // Take bug on RTL839x Rev <= C into account
612 if (port >= RTL839X_CPU_PORT)
613 return -EIO;
614
615 mutex_lock(&smi_lock);
616
617 sw_w32_mask(0xffff0000, port << 16, RTL839X_PHYREG_DATA_CTRL);
618 v = reg << 5 | page << 10 | ((page == 0x1fff) ? 0x1f : 0) << 23;
619 sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
620
621 sw_w32(0x1ff, RTL839X_PHYREG_CTRL);
622
623 v |= 1;
624 sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
625
626 do {
627 } while (sw_r32(RTL839X_PHYREG_ACCESS_CTRL) & 0x1);
628
629 *val = sw_r32(RTL839X_PHYREG_DATA_CTRL) & 0xffff;
630
631 mutex_unlock(&smi_lock);
632 return 0;
633 }
634
635 int rtl839x_write_phy(u32 port, u32 page, u32 reg, u32 val)
636 {
637 u32 v;
638 int err = 0;
639
640 val &= 0xffff;
641 if (port > 63 || page > 4095 || reg > 31)
642 return -ENOTSUPP;
643
644 // Take bug on RTL839x Rev <= C into account
645 if (port >= RTL839X_CPU_PORT)
646 return -EIO;
647
648 mutex_lock(&smi_lock);
649
650 // Set PHY to access
651 rtl839x_set_port_reg_le(BIT_ULL(port), RTL839X_PHYREG_PORT_CTRL);
652
653 sw_w32_mask(0xffff0000, val << 16, RTL839X_PHYREG_DATA_CTRL);
654
655 v = reg << 5 | page << 10 | ((page == 0x1fff) ? 0x1f : 0) << 23;
656 sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
657
658 sw_w32(0x1ff, RTL839X_PHYREG_CTRL);
659
660 v |= BIT(3) | 1; /* Write operation and execute */
661 sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
662
663 do {
664 } while (sw_r32(RTL839X_PHYREG_ACCESS_CTRL) & 0x1);
665
666 if (sw_r32(RTL839X_PHYREG_ACCESS_CTRL) & 0x2)
667 err = -EIO;
668
669 mutex_unlock(&smi_lock);
670 return err;
671 }
672
673 /*
674 * Read an mmd register of the PHY
675 */
676 int rtl839x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val)
677 {
678 int err = 0;
679 u32 v;
680
681 // Take bug on RTL839x Rev <= C into account
682 if (port >= RTL839X_CPU_PORT)
683 return -EIO;
684
685 mutex_lock(&smi_lock);
686
687 // Set PHY to access
688 sw_w32_mask(0xffff << 16, port << 16, RTL839X_PHYREG_DATA_CTRL);
689
690 // Set MMD device number and register to write to
691 sw_w32(devnum << 16 | (regnum & 0xffff), RTL839X_PHYREG_MMD_CTRL);
692
693 v = BIT(2) | BIT(0); // MMD-access | EXEC
694 sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
695
696 do {
697 v = sw_r32(RTL839X_PHYREG_ACCESS_CTRL);
698 } while (v & BIT(0));
699 // There is no error-checking via BIT 1 of v, as it does not seem to be set correctly
700 *val = (sw_r32(RTL839X_PHYREG_DATA_CTRL) & 0xffff);
701 pr_debug("%s: port %d, regnum: %x, val: %x (err %d)\n", __func__, port, regnum, *val, err);
702
703 mutex_unlock(&smi_lock);
704
705 return err;
706 }
707
708 /*
709 * Write to an mmd register of the PHY
710 */
711 int rtl839x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val)
712 {
713 int err = 0;
714 u32 v;
715
716 // Take bug on RTL839x Rev <= C into account
717 if (port >= RTL839X_CPU_PORT)
718 return -EIO;
719
720 mutex_lock(&smi_lock);
721
722 // Set PHY to access
723 rtl839x_set_port_reg_le(BIT_ULL(port), RTL839X_PHYREG_PORT_CTRL);
724
725 // Set data to write
726 sw_w32_mask(0xffff << 16, val << 16, RTL839X_PHYREG_DATA_CTRL);
727
728 // Set MMD device number and register to write to
729 sw_w32(devnum << 16 | (regnum & 0xffff), RTL839X_PHYREG_MMD_CTRL);
730
731 v = BIT(3) | BIT(2) | BIT(0); // WRITE | MMD-access | EXEC
732 sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
733
734 do {
735 v = sw_r32(RTL839X_PHYREG_ACCESS_CTRL);
736 } while (v & BIT(0));
737
738 pr_debug("%s: port %d, regnum: %x, val: %x (err %d)\n", __func__, port, regnum, val, err);
739 mutex_unlock(&smi_lock);
740 return err;
741 }
742
743 void rtl8390_get_version(struct rtl838x_switch_priv *priv)
744 {
745 u32 info, model;
746
747 sw_w32_mask(0xf << 28, 0xa << 28, RTL839X_CHIP_INFO);
748 info = sw_r32(RTL839X_CHIP_INFO);
749
750 model = sw_r32(RTL839X_MODEL_NAME_INFO);
751 priv->version = RTL8390_VERSION_A + ((model & 0x3f) >> 1);
752
753 pr_info("RTL839X Chip-Info: %x, version %c\n", info, priv->version);
754 }
755
756 void rtl839x_vlan_profile_dump(int profile)
757 {
758 u32 p[2];
759
760 if (profile < 0 || profile > 7)
761 return;
762
763 p[0] = sw_r32(RTL839X_VLAN_PROFILE(profile));
764 p[1] = sw_r32(RTL839X_VLAN_PROFILE(profile) + 4);
765
766 pr_info("VLAN profile %d: L2 learning: %d, UNKN L2MC FLD PMSK %d, \
767 UNKN IPMC FLD PMSK %d, UNKN IPv6MC FLD PMSK: %d",
768 profile, p[1] & 1, (p[1] >> 1) & 0xfff, (p[1] >> 13) & 0xfff,
769 (p[0]) & 0xfff);
770 pr_info("VLAN profile %d: raw %08x, %08x\n", profile, p[0], p[1]);
771 }
772
773 static void rtl839x_stp_get(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])
774 {
775 int i;
776 u32 cmd = 1 << 16 /* Execute cmd */
777 | 0 << 15 /* Read */
778 | 5 << 12 /* Table type 0b101 */
779 | (msti & 0xfff);
780 priv->r->exec_tbl0_cmd(cmd);
781
782 for (i = 0; i < 4; i++)
783 port_state[i] = sw_r32(priv->r->tbl_access_data_0(i));
784 }
785
786 static void rtl839x_stp_set(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])
787 {
788 int i;
789 u32 cmd = 1 << 16 /* Execute cmd */
790 | 1 << 15 /* Write */
791 | 5 << 12 /* Table type 0b101 */
792 | (msti & 0xfff);
793 for (i = 0; i < 4; i++)
794 sw_w32(port_state[i], priv->r->tbl_access_data_0(i));
795 priv->r->exec_tbl0_cmd(cmd);
796 }
797
798 /*
799 * Enables or disables the EEE/EEEP capability of a port
800 */
801 void rtl839x_port_eee_set(struct rtl838x_switch_priv *priv, int port, bool enable)
802 {
803 u32 v;
804
805 // This works only for Ethernet ports, and on the RTL839X, ports above 47 are SFP
806 if (port >= 48)
807 return;
808
809 enable = true;
810 pr_debug("In %s: setting port %d to %d\n", __func__, port, enable);
811 v = enable ? 0xf : 0x0;
812
813 // Set EEE for 100, 500, 1000MBit and 10GBit
814 sw_w32_mask(0xf << 8, v << 8, rtl839x_mac_force_mode_ctrl(port));
815
816 // Set TX/RX EEE state
817 v = enable ? 0x3 : 0x0;
818 sw_w32(v, RTL839X_EEE_CTRL(port));
819
820 priv->ports[port].eee_enabled = enable;
821 }
822
823 /*
824 * Get EEE own capabilities and negotiation result
825 */
826 int rtl839x_eee_port_ability(struct rtl838x_switch_priv *priv, struct ethtool_eee *e, int port)
827 {
828 u64 link, a;
829
830 if (port >= 48)
831 return 0;
832
833 link = rtl839x_get_port_reg_le(RTL839X_MAC_LINK_STS);
834 if (!(link & BIT_ULL(port)))
835 return 0;
836
837 if (sw_r32(rtl839x_mac_force_mode_ctrl(port)) & BIT(8))
838 e->advertised |= ADVERTISED_100baseT_Full;
839
840 if (sw_r32(rtl839x_mac_force_mode_ctrl(port)) & BIT(10))
841 e->advertised |= ADVERTISED_1000baseT_Full;
842
843 a = rtl839x_get_port_reg_le(RTL839X_MAC_EEE_ABLTY);
844 pr_info("Link partner: %016llx\n", a);
845 if (rtl839x_get_port_reg_le(RTL839X_MAC_EEE_ABLTY) & BIT_ULL(port)) {
846 e->lp_advertised = ADVERTISED_100baseT_Full;
847 e->lp_advertised |= ADVERTISED_1000baseT_Full;
848 return 1;
849 }
850
851 return 0;
852 }
853
854 static void rtl839x_init_eee(struct rtl838x_switch_priv *priv, bool enable)
855 {
856 int i;
857
858 pr_info("Setting up EEE, state: %d\n", enable);
859
860 // Set wake timer for TX and pause timer both to 0x21
861 sw_w32_mask(0xff << 20| 0xff, 0x21 << 20| 0x21, RTL839X_EEE_TX_TIMER_GELITE_CTRL);
862 // Set pause wake timer for GIGA-EEE to 0x11
863 sw_w32_mask(0xff << 20, 0x11 << 20, RTL839X_EEE_TX_TIMER_GIGA_CTRL);
864 // Set pause wake timer for 10GBit ports to 0x11
865 sw_w32_mask(0xff << 20, 0x11 << 20, RTL839X_EEE_TX_TIMER_10G_CTRL);
866
867 // Setup EEE on all ports
868 for (i = 0; i < priv->cpu_port; i++) {
869 if (priv->ports[i].phy)
870 rtl839x_port_eee_set(priv, i, enable);
871 }
872 priv->eee_enabled = enable;
873 }
874
875 static void rtl839x_pie_lookup_enable(struct rtl838x_switch_priv *priv, int index)
876 {
877 int block = index / PIE_BLOCK_SIZE;
878
879 sw_w32_mask(0, BIT(block), RTL839X_ACL_BLK_LOOKUP_CTRL);
880 }
881
882 /*
883 * Delete a range of Packet Inspection Engine rules
884 */
885 static int rtl839x_pie_rule_del(struct rtl838x_switch_priv *priv, int index_from, int index_to)
886 {
887 u32 v = (index_from << 1)| (index_to << 13 ) | BIT(0);
888
889 pr_debug("%s: from %d to %d\n", __func__, index_from, index_to);
890 mutex_lock(&priv->reg_mutex);
891
892 // Write from-to and execute bit into control register
893 sw_w32(v, RTL839X_ACL_CLR_CTRL);
894
895 // Wait until command has completed
896 do {
897 } while (sw_r32(RTL839X_ACL_CLR_CTRL) & BIT(0));
898
899 mutex_unlock(&priv->reg_mutex);
900 return 0;
901 }
902
903 /*
904 * Reads the intermediate representation of the templated match-fields of the
905 * PIE rule in the pie_rule structure and fills in the raw data fields in the
906 * raw register space r[].
907 * The register space configuration size is identical for the RTL8380/90 and RTL9300,
908 * however the RTL9310 has 2 more registers / fields and the physical field-ids are different
909 * on all SoCs
910 * On the RTL8390 the template mask registers are not word-aligned!
911 */
912 static void rtl839x_write_pie_templated(u32 r[], struct pie_rule *pr, enum template_field_id t[])
913 {
914 int i;
915 enum template_field_id field_type;
916 u16 data, data_m;
917
918 for (i = 0; i < N_FIXED_FIELDS; i++) {
919 field_type = t[i];
920 data = data_m = 0;
921
922 switch (field_type) {
923 case TEMPLATE_FIELD_SPM0:
924 data = pr->spm;
925 data_m = pr->spm_m;
926 break;
927 case TEMPLATE_FIELD_SPM1:
928 data = pr->spm >> 16;
929 data_m = pr->spm_m >> 16;
930 break;
931 case TEMPLATE_FIELD_SPM2:
932 data = pr->spm >> 32;
933 data_m = pr->spm_m >> 32;
934 break;
935 case TEMPLATE_FIELD_SPM3:
936 data = pr->spm >> 48;
937 data_m = pr->spm_m >> 48;
938 break;
939 case TEMPLATE_FIELD_OTAG:
940 data = pr->otag;
941 data_m = pr->otag_m;
942 break;
943 case TEMPLATE_FIELD_SMAC0:
944 data = pr->smac[4];
945 data = (data << 8) | pr->smac[5];
946 data_m = pr->smac_m[4];
947 data_m = (data_m << 8) | pr->smac_m[5];
948 break;
949 case TEMPLATE_FIELD_SMAC1:
950 data = pr->smac[2];
951 data = (data << 8) | pr->smac[3];
952 data_m = pr->smac_m[2];
953 data_m = (data_m << 8) | pr->smac_m[3];
954 break;
955 case TEMPLATE_FIELD_SMAC2:
956 data = pr->smac[0];
957 data = (data << 8) | pr->smac[1];
958 data_m = pr->smac_m[0];
959 data_m = (data_m << 8) | pr->smac_m[1];
960 break;
961 case TEMPLATE_FIELD_DMAC0:
962 data = pr->dmac[4];
963 data = (data << 8) | pr->dmac[5];
964 data_m = pr->dmac_m[4];
965 data_m = (data_m << 8) | pr->dmac_m[5];
966 break;
967 case TEMPLATE_FIELD_DMAC1:
968 data = pr->dmac[2];
969 data = (data << 8) | pr->dmac[3];
970 data_m = pr->dmac_m[2];
971 data_m = (data_m << 8) | pr->dmac_m[3];
972 break;
973 case TEMPLATE_FIELD_DMAC2:
974 data = pr->dmac[0];
975 data = (data << 8) | pr->dmac[1];
976 data_m = pr->dmac_m[0];
977 data_m = (data_m << 8) | pr->dmac_m[1];
978 break;
979 case TEMPLATE_FIELD_ETHERTYPE:
980 data = pr->ethertype;
981 data_m = pr->ethertype_m;
982 break;
983 case TEMPLATE_FIELD_ITAG:
984 data = pr->itag;
985 data_m = pr->itag_m;
986 break;
987 case TEMPLATE_FIELD_SIP0:
988 if (pr->is_ipv6) {
989 data = pr->sip6.s6_addr16[7];
990 data_m = pr->sip6_m.s6_addr16[7];
991 } else {
992 data = pr->sip;
993 data_m = pr->sip_m;
994 }
995 break;
996 case TEMPLATE_FIELD_SIP1:
997 if (pr->is_ipv6) {
998 data = pr->sip6.s6_addr16[6];
999 data_m = pr->sip6_m.s6_addr16[6];
1000 } else {
1001 data = pr->sip >> 16;
1002 data_m = pr->sip_m >> 16;
1003 }
1004 break;
1005
1006 case TEMPLATE_FIELD_SIP2:
1007 case TEMPLATE_FIELD_SIP3:
1008 case TEMPLATE_FIELD_SIP4:
1009 case TEMPLATE_FIELD_SIP5:
1010 case TEMPLATE_FIELD_SIP6:
1011 case TEMPLATE_FIELD_SIP7:
1012 data = pr->sip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)];
1013 data_m = pr->sip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)];
1014 break;
1015
1016 case TEMPLATE_FIELD_DIP0:
1017 if (pr->is_ipv6) {
1018 data = pr->dip6.s6_addr16[7];
1019 data_m = pr->dip6_m.s6_addr16[7];
1020 } else {
1021 data = pr->dip;
1022 data_m = pr->dip_m;
1023 }
1024 break;
1025
1026 case TEMPLATE_FIELD_DIP1:
1027 if (pr->is_ipv6) {
1028 data = pr->dip6.s6_addr16[6];
1029 data_m = pr->dip6_m.s6_addr16[6];
1030 } else {
1031 data = pr->dip >> 16;
1032 data_m = pr->dip_m >> 16;
1033 }
1034 break;
1035
1036 case TEMPLATE_FIELD_DIP2:
1037 case TEMPLATE_FIELD_DIP3:
1038 case TEMPLATE_FIELD_DIP4:
1039 case TEMPLATE_FIELD_DIP5:
1040 case TEMPLATE_FIELD_DIP6:
1041 case TEMPLATE_FIELD_DIP7:
1042 data = pr->dip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)];
1043 data_m = pr->dip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)];
1044 break;
1045
1046 case TEMPLATE_FIELD_IP_TOS_PROTO:
1047 data = pr->tos_proto;
1048 data_m = pr->tos_proto_m;
1049 break;
1050 case TEMPLATE_FIELD_L4_SPORT:
1051 data = pr->sport;
1052 data_m = pr->sport_m;
1053 break;
1054 case TEMPLATE_FIELD_L4_DPORT:
1055 data = pr->dport;
1056 data_m = pr->dport_m;
1057 break;
1058 case TEMPLATE_FIELD_ICMP_IGMP:
1059 data = pr->icmp_igmp;
1060 data_m = pr->icmp_igmp_m;
1061 break;
1062 default:
1063 pr_info("%s: unknown field %d\n", __func__, field_type);
1064 }
1065
1066 // On the RTL8390, the mask fields are not word aligned!
1067 if (!(i % 2)) {
1068 r[5 - i / 2] = data;
1069 r[12 - i / 2] |= ((u32)data_m << 8);
1070 } else {
1071 r[5 - i / 2] |= ((u32)data) << 16;
1072 r[12 - i / 2] |= ((u32)data_m) << 24;
1073 r[11 - i / 2] |= ((u32)data_m) >> 8;
1074 }
1075 }
1076 }
1077
1078 /*
1079 * Creates the intermediate representation of the templated match-fields of the
1080 * PIE rule in the pie_rule structure by reading the raw data fields in the
1081 * raw register space r[].
1082 * The register space configuration size is identical for the RTL8380/90 and RTL9300,
1083 * however the RTL9310 has 2 more registers / fields and the physical field-ids
1084 * On the RTL8390 the template mask registers are not word-aligned!
1085 */
1086 void rtl839x_read_pie_templated(u32 r[], struct pie_rule *pr, enum template_field_id t[])
1087 {
1088 int i;
1089 enum template_field_id field_type;
1090 u16 data, data_m;
1091
1092 for (i = 0; i < N_FIXED_FIELDS; i++) {
1093 field_type = t[i];
1094 if (!(i % 2)) {
1095 data = r[5 - i / 2];
1096 data_m = r[12 - i / 2];
1097 } else {
1098 data = r[5 - i / 2] >> 16;
1099 data_m = r[12 - i / 2] >> 16;
1100 }
1101
1102 switch (field_type) {
1103 case TEMPLATE_FIELD_SPM0:
1104 pr->spm = (pr->spn << 16) | data;
1105 pr->spm_m = (pr->spn << 16) | data_m;
1106 break;
1107 case TEMPLATE_FIELD_SPM1:
1108 pr->spm = data;
1109 pr->spm_m = data_m;
1110 break;
1111 case TEMPLATE_FIELD_OTAG:
1112 pr->otag = data;
1113 pr->otag_m = data_m;
1114 break;
1115 case TEMPLATE_FIELD_SMAC0:
1116 pr->smac[4] = data >> 8;
1117 pr->smac[5] = data;
1118 pr->smac_m[4] = data >> 8;
1119 pr->smac_m[5] = data;
1120 break;
1121 case TEMPLATE_FIELD_SMAC1:
1122 pr->smac[2] = data >> 8;
1123 pr->smac[3] = data;
1124 pr->smac_m[2] = data >> 8;
1125 pr->smac_m[3] = data;
1126 break;
1127 case TEMPLATE_FIELD_SMAC2:
1128 pr->smac[0] = data >> 8;
1129 pr->smac[1] = data;
1130 pr->smac_m[0] = data >> 8;
1131 pr->smac_m[1] = data;
1132 break;
1133 case TEMPLATE_FIELD_DMAC0:
1134 pr->dmac[4] = data >> 8;
1135 pr->dmac[5] = data;
1136 pr->dmac_m[4] = data >> 8;
1137 pr->dmac_m[5] = data;
1138 break;
1139 case TEMPLATE_FIELD_DMAC1:
1140 pr->dmac[2] = data >> 8;
1141 pr->dmac[3] = data;
1142 pr->dmac_m[2] = data >> 8;
1143 pr->dmac_m[3] = data;
1144 break;
1145 case TEMPLATE_FIELD_DMAC2:
1146 pr->dmac[0] = data >> 8;
1147 pr->dmac[1] = data;
1148 pr->dmac_m[0] = data >> 8;
1149 pr->dmac_m[1] = data;
1150 break;
1151 case TEMPLATE_FIELD_ETHERTYPE:
1152 pr->ethertype = data;
1153 pr->ethertype_m = data_m;
1154 break;
1155 case TEMPLATE_FIELD_ITAG:
1156 pr->itag = data;
1157 pr->itag_m = data_m;
1158 break;
1159 case TEMPLATE_FIELD_SIP0:
1160 pr->sip = data;
1161 pr->sip_m = data_m;
1162 break;
1163 case TEMPLATE_FIELD_SIP1:
1164 pr->sip = (pr->sip << 16) | data;
1165 pr->sip_m = (pr->sip << 16) | data_m;
1166 break;
1167 case TEMPLATE_FIELD_SIP2:
1168 pr->is_ipv6 = true;
1169 // Make use of limitiations on the position of the match values
1170 ipv6_addr_set(&pr->sip6, pr->sip, r[5 - i / 2],
1171 r[4 - i / 2], r[3 - i / 2]);
1172 ipv6_addr_set(&pr->sip6_m, pr->sip_m, r[5 - i / 2],
1173 r[4 - i / 2], r[3 - i / 2]);
1174 case TEMPLATE_FIELD_SIP3:
1175 case TEMPLATE_FIELD_SIP4:
1176 case TEMPLATE_FIELD_SIP5:
1177 case TEMPLATE_FIELD_SIP6:
1178 case TEMPLATE_FIELD_SIP7:
1179 break;
1180
1181 case TEMPLATE_FIELD_DIP0:
1182 pr->dip = data;
1183 pr->dip_m = data_m;
1184 break;
1185
1186 case TEMPLATE_FIELD_DIP1:
1187 pr->dip = (pr->dip << 16) | data;
1188 pr->dip_m = (pr->dip << 16) | data_m;
1189 break;
1190
1191 case TEMPLATE_FIELD_DIP2:
1192 pr->is_ipv6 = true;
1193 ipv6_addr_set(&pr->dip6, pr->dip, r[5 - i / 2],
1194 r[4 - i / 2], r[3 - i / 2]);
1195 ipv6_addr_set(&pr->dip6_m, pr->dip_m, r[5 - i / 2],
1196 r[4 - i / 2], r[3 - i / 2]);
1197 case TEMPLATE_FIELD_DIP3:
1198 case TEMPLATE_FIELD_DIP4:
1199 case TEMPLATE_FIELD_DIP5:
1200 case TEMPLATE_FIELD_DIP6:
1201 case TEMPLATE_FIELD_DIP7:
1202 break;
1203 case TEMPLATE_FIELD_IP_TOS_PROTO:
1204 pr->tos_proto = data;
1205 pr->tos_proto_m = data_m;
1206 break;
1207 case TEMPLATE_FIELD_L4_SPORT:
1208 pr->sport = data;
1209 pr->sport_m = data_m;
1210 break;
1211 case TEMPLATE_FIELD_L4_DPORT:
1212 pr->dport = data;
1213 pr->dport_m = data_m;
1214 break;
1215 case TEMPLATE_FIELD_ICMP_IGMP:
1216 pr->icmp_igmp = data;
1217 pr->icmp_igmp_m = data_m;
1218 break;
1219 default:
1220 pr_info("%s: unknown field %d\n", __func__, field_type);
1221 }
1222 }
1223 }
1224
1225 static void rtl839x_read_pie_fixed_fields(u32 r[], struct pie_rule *pr)
1226 {
1227 pr->spmmask_fix = (r[6] >> 30) & 0x3;
1228 pr->spn = (r[6] >> 24) & 0x3f;
1229 pr->mgnt_vlan = (r[6] >> 23) & 1;
1230 pr->dmac_hit_sw = (r[6] >> 22) & 1;
1231 pr->not_first_frag = (r[6] >> 21) & 1;
1232 pr->frame_type_l4 = (r[6] >> 18) & 7;
1233 pr->frame_type = (r[6] >> 16) & 3;
1234 pr->otag_fmt = (r[6] >> 15) & 1;
1235 pr->itag_fmt = (r[6] >> 14) & 1;
1236 pr->otag_exist = (r[6] >> 13) & 1;
1237 pr->itag_exist = (r[6] >> 12) & 1;
1238 pr->frame_type_l2 = (r[6] >> 10) & 3;
1239 pr->tid = (r[6] >> 8) & 3;
1240
1241 pr->spmmask_fix_m = (r[12] >> 6) & 0x3;
1242 pr->spn_m = r[12] & 0x3f;
1243 pr->mgnt_vlan_m = (r[13] >> 31) & 1;
1244 pr->dmac_hit_sw_m = (r[13] >> 30) & 1;
1245 pr->not_first_frag_m = (r[13] >> 29) & 1;
1246 pr->frame_type_l4_m = (r[13] >> 26) & 7;
1247 pr->frame_type_m = (r[13] >> 24) & 3;
1248 pr->otag_fmt_m = (r[13] >> 23) & 1;
1249 pr->itag_fmt_m = (r[13] >> 22) & 1;
1250 pr->otag_exist_m = (r[13] >> 21) & 1;
1251 pr->itag_exist_m = (r[13] >> 20) & 1;
1252 pr->frame_type_l2_m = (r[13] >> 18) & 3;
1253 pr->tid_m = (r[13] >> 16) & 3;
1254
1255 pr->valid = r[13] & BIT(15);
1256 pr->cond_not = r[13] & BIT(14);
1257 pr->cond_and1 = r[13] & BIT(13);
1258 pr->cond_and2 = r[13] & BIT(12);
1259 }
1260
1261 static void rtl839x_write_pie_fixed_fields(u32 r[], struct pie_rule *pr)
1262 {
1263 r[6] = ((u32) (pr->spmmask_fix & 0x3)) << 30;
1264 r[6] |= ((u32) (pr->spn & 0x3f)) << 24;
1265 r[6] |= pr->mgnt_vlan ? BIT(23) : 0;
1266 r[6] |= pr->dmac_hit_sw ? BIT(22) : 0;
1267 r[6] |= pr->not_first_frag ? BIT(21) : 0;
1268 r[6] |= ((u32) (pr->frame_type_l4 & 0x7)) << 18;
1269 r[6] |= ((u32) (pr->frame_type & 0x3)) << 16;
1270 r[6] |= pr->otag_fmt ? BIT(15) : 0;
1271 r[6] |= pr->itag_fmt ? BIT(14) : 0;
1272 r[6] |= pr->otag_exist ? BIT(13) : 0;
1273 r[6] |= pr->itag_exist ? BIT(12) : 0;
1274 r[6] |= ((u32) (pr->frame_type_l2 & 0x3)) << 10;
1275 r[6] |= ((u32) (pr->tid & 0x3)) << 8;
1276
1277 r[12] |= ((u32) (pr->spmmask_fix_m & 0x3)) << 6;
1278 r[12] |= (u32) (pr->spn_m & 0x3f);
1279 r[13] |= pr->mgnt_vlan_m ? BIT(31) : 0;
1280 r[13] |= pr->dmac_hit_sw_m ? BIT(30) : 0;
1281 r[13] |= pr->not_first_frag_m ? BIT(29) : 0;
1282 r[13] |= ((u32) (pr->frame_type_l4_m & 0x7)) << 26;
1283 r[13] |= ((u32) (pr->frame_type_m & 0x3)) << 24;
1284 r[13] |= pr->otag_fmt_m ? BIT(23) : 0;
1285 r[13] |= pr->itag_fmt_m ? BIT(22) : 0;
1286 r[13] |= pr->otag_exist_m ? BIT(21) : 0;
1287 r[13] |= pr->itag_exist_m ? BIT(20) : 0;
1288 r[13] |= ((u32) (pr->frame_type_l2_m & 0x3)) << 18;
1289 r[13] |= ((u32) (pr->tid_m & 0x3)) << 16;
1290
1291 r[13] |= pr->valid ? BIT(15) : 0;
1292 r[13] |= pr->cond_not ? BIT(14) : 0;
1293 r[13] |= pr->cond_and1 ? BIT(13) : 0;
1294 r[13] |= pr->cond_and2 ? BIT(12) : 0;
1295 }
1296
1297 static void rtl839x_write_pie_action(u32 r[], struct pie_rule *pr)
1298 {
1299 if (pr->drop) {
1300 r[13] |= 0x9; // Set ACT_MASK_FWD & FWD_ACT = DROP
1301 r[13] |= BIT(3);
1302 } else {
1303 r[13] |= pr->fwd_sel ? BIT(3) : 0;
1304 r[13] |= pr->fwd_act;
1305 }
1306 r[13] |= pr->bypass_sel ? BIT(11) : 0;
1307 r[13] |= pr->mpls_sel ? BIT(10) : 0;
1308 r[13] |= pr->nopri_sel ? BIT(9) : 0;
1309 r[13] |= pr->ovid_sel ? BIT(8) : 0;
1310 r[13] |= pr->ivid_sel ? BIT(7) : 0;
1311 r[13] |= pr->meter_sel ? BIT(6) : 0;
1312 r[13] |= pr->mir_sel ? BIT(5) : 0;
1313 r[13] |= pr->log_sel ? BIT(4) : 0;
1314
1315 r[14] |= ((u32)(pr->fwd_data & 0x3fff)) << 18;
1316 r[14] |= pr->log_octets ? BIT(17) : 0;
1317 r[14] |= ((u32)(pr->log_data & 0x7ff)) << 4;
1318 r[14] |= (pr->mir_data & 0x3) << 3;
1319 r[14] |= ((u32)(pr->meter_data >> 7)) & 0x7;
1320 r[15] |= (u32)(pr->meter_data) << 26;
1321 r[15] |= ((u32)(pr->ivid_act) << 23) & 0x3;
1322 r[15] |= ((u32)(pr->ivid_data) << 9) & 0xfff;
1323 r[15] |= ((u32)(pr->ovid_act) << 6) & 0x3;
1324 r[15] |= ((u32)(pr->ovid_data) >> 4) & 0xff;
1325 r[16] |= ((u32)(pr->ovid_data) & 0xf) << 28;
1326 r[16] |= ((u32)(pr->nopri_data) & 0x7) << 20;
1327 r[16] |= ((u32)(pr->mpls_act) & 0x7) << 20;
1328 r[16] |= ((u32)(pr->mpls_lib_idx) & 0x7) << 20;
1329 r[16] |= pr->bypass_all ? BIT(9) : 0;
1330 r[16] |= pr->bypass_igr_stp ? BIT(8) : 0;
1331 r[16] |= pr->bypass_ibc_sc ? BIT(7) : 0;
1332 }
1333
1334 static void rtl839x_read_pie_action(u32 r[], struct pie_rule *pr)
1335 {
1336 if (r[13] & BIT(3)) { // ACT_MASK_FWD set, is it a drop?
1337 if ((r[14] & 0x7) == 1) {
1338 pr->drop = true;
1339 } else {
1340 pr->fwd_sel = true;
1341 pr->fwd_act = r[14] & 0x7;
1342 }
1343 }
1344
1345 pr->bypass_sel = r[13] & BIT(11);
1346 pr->mpls_sel = r[13] & BIT(10);
1347 pr->nopri_sel = r[13] & BIT(9);
1348 pr->ovid_sel = r[13] & BIT(8);
1349 pr->ivid_sel = r[13] & BIT(7);
1350 pr->meter_sel = r[13] & BIT(6);
1351 pr->mir_sel = r[13] & BIT(5);
1352 pr->log_sel = r[13] & BIT(4);
1353
1354 // TODO: Read in data fields
1355
1356 pr->bypass_all = r[16] & BIT(9);
1357 pr->bypass_igr_stp = r[16] & BIT(8);
1358 pr->bypass_ibc_sc = r[16] & BIT(7);
1359 }
1360
1361 void rtl839x_pie_rule_dump_raw(u32 r[])
1362 {
1363 pr_info("Raw IACL table entry:\n");
1364 pr_info("Match : %08x %08x %08x %08x %08x %08x\n", r[0], r[1], r[2], r[3], r[4], r[5]);
1365 pr_info("Fixed : %06x\n", r[6] >> 8);
1366 pr_info("Match M: %08x %08x %08x %08x %08x %08x\n",
1367 (r[6] << 24) | (r[7] >> 8), (r[7] << 24) | (r[8] >> 8), (r[8] << 24) | (r[9] >> 8),
1368 (r[9] << 24) | (r[10] >> 8), (r[10] << 24) | (r[11] >> 8),
1369 (r[11] << 24) | (r[12] >> 8));
1370 pr_info("R[13]: %08x\n", r[13]);
1371 pr_info("Fixed M: %06x\n", ((r[12] << 16) | (r[13] >> 16)) & 0xffffff);
1372 pr_info("Valid / not / and1 / and2 : %1x\n", (r[13] >> 12) & 0xf);
1373 pr_info("r 13-16: %08x %08x %08x %08x\n", r[13], r[14], r[15], r[16]);
1374 }
1375
1376 void rtl839x_pie_rule_dump(struct pie_rule *pr)
1377 {
1378 pr_info("Drop: %d, fwd: %d, ovid: %d, ivid: %d, flt: %d, log: %d, rmk: %d, meter: %d tagst: %d, mir: %d, nopri: %d, cpupri: %d, otpid: %d, itpid: %d, shape: %d\n",
1379 pr->drop, pr->fwd_sel, pr->ovid_sel, pr->ivid_sel, pr->flt_sel, pr->log_sel, pr->rmk_sel, pr->log_sel, pr->tagst_sel, pr->mir_sel, pr->nopri_sel,
1380 pr->cpupri_sel, pr->otpid_sel, pr->itpid_sel, pr->shaper_sel);
1381 if (pr->fwd_sel)
1382 pr_info("FWD: %08x\n", pr->fwd_data);
1383 pr_info("TID: %x, %x\n", pr->tid, pr->tid_m);
1384 }
1385
1386 static int rtl839x_pie_rule_read(struct rtl838x_switch_priv *priv, int idx, struct pie_rule *pr)
1387 {
1388 // Read IACL table (2) via register 0
1389 struct table_reg *q = rtl_table_get(RTL8380_TBL_0, 2);
1390 u32 r[17];
1391 int i;
1392 int block = idx / PIE_BLOCK_SIZE;
1393 u32 t_select = sw_r32(RTL839X_ACL_BLK_TMPLTE_CTRL(block));
1394
1395 memset(pr, 0, sizeof(*pr));
1396 rtl_table_read(q, idx);
1397 for (i = 0; i < 17; i++)
1398 r[i] = sw_r32(rtl_table_data(q, i));
1399
1400 rtl_table_release(q);
1401
1402 rtl839x_read_pie_fixed_fields(r, pr);
1403 if (!pr->valid)
1404 return 0;
1405
1406 pr_debug("%s: template_selectors %08x, tid: %d\n", __func__, t_select, pr->tid);
1407 rtl839x_pie_rule_dump_raw(r);
1408
1409 rtl839x_read_pie_templated(r, pr, fixed_templates[(t_select >> (pr->tid * 3)) & 0x7]);
1410
1411 rtl839x_read_pie_action(r, pr);
1412
1413 return 0;
1414 }
1415
1416 static int rtl839x_pie_rule_write(struct rtl838x_switch_priv *priv, int idx, struct pie_rule *pr)
1417 {
1418 // Access IACL table (2) via register 0
1419 struct table_reg *q = rtl_table_get(RTL8390_TBL_0, 2);
1420 u32 r[17];
1421 int i;
1422 int block = idx / PIE_BLOCK_SIZE;
1423 u32 t_select = sw_r32(RTL839X_ACL_BLK_TMPLTE_CTRL(block));
1424
1425 pr_debug("%s: %d, t_select: %08x\n", __func__, idx, t_select);
1426
1427 for (i = 0; i < 17; i++)
1428 r[i] = 0;
1429
1430 if (!pr->valid) {
1431 rtl_table_write(q, idx);
1432 rtl_table_release(q);
1433 return 0;
1434 }
1435 rtl839x_write_pie_fixed_fields(r, pr);
1436
1437 pr_debug("%s: template %d\n", __func__, (t_select >> (pr->tid * 3)) & 0x7);
1438 rtl839x_write_pie_templated(r, pr, fixed_templates[(t_select >> (pr->tid * 3)) & 0x7]);
1439
1440 rtl839x_write_pie_action(r, pr);
1441
1442 // rtl839x_pie_rule_dump_raw(r);
1443
1444 for (i = 0; i < 17; i++)
1445 sw_w32(r[i], rtl_table_data(q, i));
1446
1447 rtl_table_write(q, idx);
1448 rtl_table_release(q);
1449
1450 return 0;
1451 }
1452
1453 static bool rtl839x_pie_templ_has(int t, enum template_field_id field_type)
1454 {
1455 int i;
1456 enum template_field_id ft;
1457
1458 for (i = 0; i < N_FIXED_FIELDS; i++) {
1459 ft = fixed_templates[t][i];
1460 if (field_type == ft)
1461 return true;
1462 }
1463
1464 return false;
1465 }
1466
1467 static int rtl839x_pie_verify_template(struct rtl838x_switch_priv *priv,
1468 struct pie_rule *pr, int t, int block)
1469 {
1470 int i;
1471
1472 if (!pr->is_ipv6 && pr->sip_m && !rtl839x_pie_templ_has(t, TEMPLATE_FIELD_SIP0))
1473 return -1;
1474
1475 if (!pr->is_ipv6 && pr->dip_m && !rtl839x_pie_templ_has(t, TEMPLATE_FIELD_DIP0))
1476 return -1;
1477
1478 if (pr->is_ipv6) {
1479 if ((pr->sip6_m.s6_addr32[0] || pr->sip6_m.s6_addr32[1]
1480 || pr->sip6_m.s6_addr32[2] || pr->sip6_m.s6_addr32[3])
1481 && !rtl839x_pie_templ_has(t, TEMPLATE_FIELD_SIP2))
1482 return -1;
1483 if ((pr->dip6_m.s6_addr32[0] || pr->dip6_m.s6_addr32[1]
1484 || pr->dip6_m.s6_addr32[2] || pr->dip6_m.s6_addr32[3])
1485 && !rtl839x_pie_templ_has(t, TEMPLATE_FIELD_DIP2))
1486 return -1;
1487 }
1488
1489 if (ether_addr_to_u64(pr->smac) && !rtl839x_pie_templ_has(t, TEMPLATE_FIELD_SMAC0))
1490 return -1;
1491
1492 if (ether_addr_to_u64(pr->dmac) && !rtl839x_pie_templ_has(t, TEMPLATE_FIELD_DMAC0))
1493 return -1;
1494
1495 // TODO: Check more
1496
1497 i = find_first_zero_bit(&priv->pie_use_bm[block * 4], PIE_BLOCK_SIZE);
1498
1499 if (i >= PIE_BLOCK_SIZE)
1500 return -1;
1501
1502 return i + PIE_BLOCK_SIZE * block;
1503 }
1504
1505 static int rtl839x_pie_rule_add(struct rtl838x_switch_priv *priv, struct pie_rule *pr)
1506 {
1507 int idx, block, j, t;
1508 int min_block = 0;
1509 int max_block = priv->n_pie_blocks / 2;
1510
1511 if (pr->is_egress) {
1512 min_block = max_block;
1513 max_block = priv->n_pie_blocks;
1514 }
1515
1516 mutex_lock(&priv->pie_mutex);
1517
1518 for (block = min_block; block < max_block; block++) {
1519 for (j = 0; j < 2; j++) {
1520 t = (sw_r32(RTL839X_ACL_BLK_TMPLTE_CTRL(block)) >> (j * 3)) & 0x7;
1521 idx = rtl839x_pie_verify_template(priv, pr, t, block);
1522 if (idx >= 0)
1523 break;
1524 }
1525 if (j < 2)
1526 break;
1527 }
1528
1529 if (block >= priv->n_pie_blocks) {
1530 mutex_unlock(&priv->pie_mutex);
1531 return -EOPNOTSUPP;
1532 }
1533
1534 set_bit(idx, priv->pie_use_bm);
1535
1536 pr->valid = true;
1537 pr->tid = j; // Mapped to template number
1538 pr->tid_m = 0x3;
1539 pr->id = idx;
1540
1541 rtl839x_pie_lookup_enable(priv, idx);
1542 rtl839x_pie_rule_write(priv, idx, pr);
1543
1544 mutex_unlock(&priv->pie_mutex);
1545 return 0;
1546 }
1547
1548 static void rtl839x_pie_rule_rm(struct rtl838x_switch_priv *priv, struct pie_rule *pr)
1549 {
1550 int idx = pr->id;
1551
1552 rtl839x_pie_rule_del(priv, idx, idx);
1553 clear_bit(idx, priv->pie_use_bm);
1554 }
1555
1556 static void rtl839x_pie_init(struct rtl838x_switch_priv *priv)
1557 {
1558 int i;
1559 u32 template_selectors;
1560
1561 mutex_init(&priv->pie_mutex);
1562
1563 // Power on all PIE blocks
1564 for (i = 0; i < priv->n_pie_blocks; i++)
1565 sw_w32_mask(0, BIT(i), RTL839X_PS_ACL_PWR_CTRL);
1566
1567 // Set ingress and egress ACL blocks to 50/50: first Egress block is 9
1568 sw_w32_mask(0x1f, 9, RTL839X_ACL_CTRL); // Writes 9 to cutline field
1569
1570 // Include IPG in metering
1571 sw_w32(1, RTL839X_METER_GLB_CTRL);
1572
1573 // Delete all present rules
1574 rtl839x_pie_rule_del(priv, 0, priv->n_pie_blocks * PIE_BLOCK_SIZE - 1);
1575
1576 // Enable predefined templates 0, 1 for blocks 0-2
1577 template_selectors = 0 | (1 << 3);
1578 for (i = 0; i < 3; i++)
1579 sw_w32(template_selectors, RTL839X_ACL_BLK_TMPLTE_CTRL(i));
1580
1581 // Enable predefined templates 2, 3 for blocks 3-5
1582 template_selectors = 2 | (3 << 3);
1583 for (i = 3; i < 6; i++)
1584 sw_w32(template_selectors, RTL839X_ACL_BLK_TMPLTE_CTRL(i));
1585
1586 // Enable predefined templates 1, 4 for blocks 6-8
1587 template_selectors = 2 | (3 << 3);
1588 for (i = 6; i < 9; i++)
1589 sw_w32(template_selectors, RTL839X_ACL_BLK_TMPLTE_CTRL(i));
1590
1591 // Enable predefined templates 0, 1 for blocks 9-11
1592 template_selectors = 0 | (1 << 3);
1593 for (i = 9; i < 12; i++)
1594 sw_w32(template_selectors, RTL839X_ACL_BLK_TMPLTE_CTRL(i));
1595
1596 // Enable predefined templates 2, 3 for blocks 12-14
1597 template_selectors = 2 | (3 << 3);
1598 for (i = 12; i < 15; i++)
1599 sw_w32(template_selectors, RTL839X_ACL_BLK_TMPLTE_CTRL(i));
1600
1601 // Enable predefined templates 1, 4 for blocks 15-17
1602 template_selectors = 2 | (3 << 3);
1603 for (i = 15; i < 18; i++)
1604 sw_w32(template_selectors, RTL839X_ACL_BLK_TMPLTE_CTRL(i));
1605 }
1606
1607 static u32 rtl839x_packet_cntr_read(int counter)
1608 {
1609 u32 v;
1610
1611 // Read LOG table (4) via register RTL8390_TBL_0
1612 struct table_reg *r = rtl_table_get(RTL8390_TBL_0, 4);
1613
1614 pr_debug("In %s, id %d\n", __func__, counter);
1615 rtl_table_read(r, counter / 2);
1616
1617 // The table has a size of 2 registers
1618 if (counter % 2)
1619 v = sw_r32(rtl_table_data(r, 0));
1620 else
1621 v = sw_r32(rtl_table_data(r, 1));
1622
1623 rtl_table_release(r);
1624
1625 return v;
1626 }
1627
1628 static void rtl839x_packet_cntr_clear(int counter)
1629 {
1630 // Access LOG table (4) via register RTL8390_TBL_0
1631 struct table_reg *r = rtl_table_get(RTL8390_TBL_0, 4);
1632
1633 pr_debug("In %s, id %d\n", __func__, counter);
1634 // The table has a size of 2 registers
1635 if (counter % 2)
1636 sw_w32(0, rtl_table_data(r, 0));
1637 else
1638 sw_w32(0, rtl_table_data(r, 1));
1639
1640 rtl_table_write(r, counter / 2);
1641
1642 rtl_table_release(r);
1643 }
1644
1645 static void rtl839x_route_read(int idx, struct rtl83xx_route *rt)
1646 {
1647 u64 v;
1648 // Read ROUTING table (2) via register RTL8390_TBL_1
1649 struct table_reg *r = rtl_table_get(RTL8390_TBL_1, 2);
1650
1651 pr_debug("In %s\n", __func__);
1652 rtl_table_read(r, idx);
1653
1654 // The table has a size of 2 registers
1655 v = sw_r32(rtl_table_data(r, 0));
1656 v <<= 32;
1657 v |= sw_r32(rtl_table_data(r, 1));
1658 rt->switch_mac_id = (v >> 12) & 0xf;
1659 rt->nh.gw = v >> 16;
1660
1661 rtl_table_release(r);
1662 }
1663
1664 static void rtl839x_route_write(int idx, struct rtl83xx_route *rt)
1665 {
1666 u32 v;
1667
1668 // Read ROUTING table (2) via register RTL8390_TBL_1
1669 struct table_reg *r = rtl_table_get(RTL8390_TBL_1, 2);
1670
1671 pr_debug("In %s\n", __func__);
1672 sw_w32(rt->nh.gw >> 16, rtl_table_data(r, 0));
1673 v = rt->nh.gw << 16;
1674 v |= rt->switch_mac_id << 12;
1675 sw_w32(v, rtl_table_data(r, 1));
1676 rtl_table_write(r, idx);
1677
1678 rtl_table_release(r);
1679 }
1680
1681 /*
1682 * Configure the switch's own MAC addresses used when routing packets
1683 */
1684 static void rtl839x_setup_port_macs(struct rtl838x_switch_priv *priv)
1685 {
1686 int i;
1687 struct net_device *dev;
1688 u64 mac;
1689
1690 pr_debug("%s: got port %08x\n", __func__, (u32)priv->ports[priv->cpu_port].dp);
1691 dev = priv->ports[priv->cpu_port].dp->slave;
1692 mac = ether_addr_to_u64(dev->dev_addr);
1693
1694 for (i = 0; i < 15; i++) {
1695 mac++; // BUG: VRRP for testing
1696 sw_w32(mac >> 32, RTL839X_ROUTING_SA_CTRL + i * 8);
1697 sw_w32(mac, RTL839X_ROUTING_SA_CTRL + i * 8 + 4);
1698 }
1699 }
1700
1701 int rtl839x_l3_setup(struct rtl838x_switch_priv *priv)
1702 {
1703 rtl839x_setup_port_macs(priv);
1704
1705 return 0;
1706 }
1707
1708 const struct rtl838x_reg rtl839x_reg = {
1709 .mask_port_reg_be = rtl839x_mask_port_reg_be,
1710 .set_port_reg_be = rtl839x_set_port_reg_be,
1711 .get_port_reg_be = rtl839x_get_port_reg_be,
1712 .mask_port_reg_le = rtl839x_mask_port_reg_le,
1713 .set_port_reg_le = rtl839x_set_port_reg_le,
1714 .get_port_reg_le = rtl839x_get_port_reg_le,
1715 .stat_port_rst = RTL839X_STAT_PORT_RST,
1716 .stat_rst = RTL839X_STAT_RST,
1717 .stat_port_std_mib = RTL839X_STAT_PORT_STD_MIB,
1718 .traffic_enable = rtl839x_traffic_enable,
1719 .traffic_disable = rtl839x_traffic_disable,
1720 .traffic_get = rtl839x_traffic_get,
1721 .traffic_set = rtl839x_traffic_set,
1722 .port_iso_ctrl = rtl839x_port_iso_ctrl,
1723 .l2_ctrl_0 = RTL839X_L2_CTRL_0,
1724 .l2_ctrl_1 = RTL839X_L2_CTRL_1,
1725 .l2_port_aging_out = RTL839X_L2_PORT_AGING_OUT,
1726 .smi_poll_ctrl = RTL839X_SMI_PORT_POLLING_CTRL,
1727 .l2_tbl_flush_ctrl = RTL839X_L2_TBL_FLUSH_CTRL,
1728 .exec_tbl0_cmd = rtl839x_exec_tbl0_cmd,
1729 .exec_tbl1_cmd = rtl839x_exec_tbl1_cmd,
1730 .tbl_access_data_0 = rtl839x_tbl_access_data_0,
1731 .isr_glb_src = RTL839X_ISR_GLB_SRC,
1732 .isr_port_link_sts_chg = RTL839X_ISR_PORT_LINK_STS_CHG,
1733 .imr_port_link_sts_chg = RTL839X_IMR_PORT_LINK_STS_CHG,
1734 .imr_glb = RTL839X_IMR_GLB,
1735 .vlan_tables_read = rtl839x_vlan_tables_read,
1736 .vlan_set_tagged = rtl839x_vlan_set_tagged,
1737 .vlan_set_untagged = rtl839x_vlan_set_untagged,
1738 .vlan_profile_dump = rtl839x_vlan_profile_dump,
1739 .vlan_profile_setup = rtl839x_vlan_profile_setup,
1740 .vlan_fwd_on_inner = rtl839x_vlan_fwd_on_inner,
1741 .stp_get = rtl839x_stp_get,
1742 .stp_set = rtl839x_stp_set,
1743 .mac_force_mode_ctrl = rtl839x_mac_force_mode_ctrl,
1744 .mac_port_ctrl = rtl839x_mac_port_ctrl,
1745 .l2_port_new_salrn = rtl839x_l2_port_new_salrn,
1746 .l2_port_new_sa_fwd = rtl839x_l2_port_new_sa_fwd,
1747 .mir_ctrl = RTL839X_MIR_CTRL,
1748 .mir_dpm = RTL839X_MIR_DPM_CTRL,
1749 .mir_spm = RTL839X_MIR_SPM_CTRL,
1750 .mac_link_sts = RTL839X_MAC_LINK_STS,
1751 .mac_link_dup_sts = RTL839X_MAC_LINK_DUP_STS,
1752 .mac_link_spd_sts = rtl839x_mac_link_spd_sts,
1753 .mac_rx_pause_sts = RTL839X_MAC_RX_PAUSE_STS,
1754 .mac_tx_pause_sts = RTL839X_MAC_TX_PAUSE_STS,
1755 .read_l2_entry_using_hash = rtl839x_read_l2_entry_using_hash,
1756 .write_l2_entry_using_hash = rtl839x_write_l2_entry_using_hash,
1757 .read_cam = rtl839x_read_cam,
1758 .write_cam = rtl839x_write_cam,
1759 .vlan_port_egr_filter = RTL839X_VLAN_PORT_EGR_FLTR,
1760 .vlan_port_igr_filter = RTL839X_VLAN_PORT_IGR_FLTR,
1761 .vlan_port_pb = RTL839X_VLAN_PORT_PB_VLAN,
1762 .vlan_port_tag_sts_ctrl = RTL839X_VLAN_PORT_TAG_STS_CTRL,
1763 .trk_mbr_ctr = rtl839x_trk_mbr_ctr,
1764 .rma_bpdu_fld_pmask = RTL839X_RMA_BPDU_FLD_PMSK,
1765 .spcl_trap_eapol_ctrl = RTL839X_SPCL_TRAP_EAPOL_CTRL,
1766 .init_eee = rtl839x_init_eee,
1767 .port_eee_set = rtl839x_port_eee_set,
1768 .eee_port_ability = rtl839x_eee_port_ability,
1769 .l2_hash_seed = rtl839x_l2_hash_seed,
1770 .l2_hash_key = rtl839x_l2_hash_key,
1771 .read_mcast_pmask = rtl839x_read_mcast_pmask,
1772 .write_mcast_pmask = rtl839x_write_mcast_pmask,
1773 .pie_init = rtl839x_pie_init,
1774 .pie_rule_read = rtl839x_pie_rule_read,
1775 .pie_rule_write = rtl839x_pie_rule_write,
1776 .pie_rule_add = rtl839x_pie_rule_add,
1777 .pie_rule_rm = rtl839x_pie_rule_rm,
1778 .l2_learning_setup = rtl839x_l2_learning_setup,
1779 .packet_cntr_read = rtl839x_packet_cntr_read,
1780 .packet_cntr_clear = rtl839x_packet_cntr_clear,
1781 .route_read = rtl839x_route_read,
1782 .route_write = rtl839x_route_write,
1783 .l3_setup = rtl839x_l3_setup,
1784 };
OpenWrt Source Repository