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realtek: Replace C++ style comments
[openwrt/openwrt.git] / target / linux / realtek / files-5.15 / drivers / net / dsa / rtl83xx / rtl838x.c
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <asm/mach-rtl838x/mach-rtl83xx.h>
4 #include <linux/iopoll.h>
5 #include <net/nexthop.h>
6
7 #include "rtl83xx.h"
8
9 #define RTL838X_VLAN_PORT_TAG_STS_UNTAG 0x0
10 #define RTL838X_VLAN_PORT_TAG_STS_TAGGED 0x1
11 #define RTL838X_VLAN_PORT_TAG_STS_PRIORITY_TAGGED 0x2
12
13 #define RTL838X_VLAN_PORT_TAG_STS_CTRL_BASE 0xA530
14 /* port 0-28 */
15 #define RTL838X_VLAN_PORT_TAG_STS_CTRL(port) \
16 RTL838X_VLAN_PORT_TAG_STS_CTRL_BASE + (port << 2)
17
18 #define RTL838X_VLAN_PORT_TAG_STS_CTRL_EGR_P_OTAG_KEEP_MASK GENMASK(11,10)
19 #define RTL838X_VLAN_PORT_TAG_STS_CTRL_EGR_P_ITAG_KEEP_MASK GENMASK(9,8)
20 #define RTL838X_VLAN_PORT_TAG_STS_CTRL_IGR_P_OTAG_KEEP_MASK GENMASK(7,6)
21 #define RTL838X_VLAN_PORT_TAG_STS_CTRL_IGR_P_ITAG_KEEP_MASK GENMASK(5,4)
22 #define RTL838X_VLAN_PORT_TAG_STS_CTRL_OTAG_STS_MASK GENMASK(3,2)
23 #define RTL838X_VLAN_PORT_TAG_STS_CTRL_ITAG_STS_MASK GENMASK(1,0)
24
25 extern struct mutex smi_lock;
26
27 /* see_dal_maple_acl_log2PhyTmplteField and src/app/diag_v2/src/diag_acl.c */
28 /* Definition of the RTL838X-specific template field IDs as used in the PIE */
29 enum template_field_id {
30 TEMPLATE_FIELD_SPMMASK = 0,
31 TEMPLATE_FIELD_SPM0 = 1, /* Source portmask ports 0-15 */
32 TEMPLATE_FIELD_SPM1 = 2, /* Source portmask ports 16-28 */
33 TEMPLATE_FIELD_RANGE_CHK = 3,
34 TEMPLATE_FIELD_DMAC0 = 4, /* Destination MAC [15:0] */
35 TEMPLATE_FIELD_DMAC1 = 5, /* Destination MAC [31:16] */
36 TEMPLATE_FIELD_DMAC2 = 6, /* Destination MAC [47:32] */
37 TEMPLATE_FIELD_SMAC0 = 7, /* Source MAC [15:0] */
38 TEMPLATE_FIELD_SMAC1 = 8, /* Source MAC [31:16] */
39 TEMPLATE_FIELD_SMAC2 = 9, /* Source MAC [47:32] */
40 TEMPLATE_FIELD_ETHERTYPE = 10, /* Ethernet typ */
41 TEMPLATE_FIELD_OTAG = 11, /* Outer VLAN tag */
42 TEMPLATE_FIELD_ITAG = 12, /* Inner VLAN tag */
43 TEMPLATE_FIELD_SIP0 = 13, /* IPv4 or IPv6 source IP[15:0] or ARP/RARP */
44 /* source protocol address in header */
45 TEMPLATE_FIELD_SIP1 = 14, /* IPv4 or IPv6 source IP[31:16] or ARP/RARP */
46 TEMPLATE_FIELD_DIP0 = 15, /* IPv4 or IPv6 destination IP[15:0] */
47 TEMPLATE_FIELD_DIP1 = 16, /* IPv4 or IPv6 destination IP[31:16] */
48 TEMPLATE_FIELD_IP_TOS_PROTO = 17, /* IPv4 TOS/IPv6 traffic class and */
49 /* IPv4 proto/IPv6 next header fields */
50 TEMPLATE_FIELD_L34_HEADER = 18, /* packet with extra tag and IPv6 with auth, dest, */
51 /* frag, route, hop-by-hop option header, */
52 /* IGMP type, TCP flag */
53 TEMPLATE_FIELD_L4_SPORT = 19, /* TCP/UDP source port */
54 TEMPLATE_FIELD_L4_DPORT = 20, /* TCP/UDP destination port */
55 TEMPLATE_FIELD_ICMP_IGMP = 21,
56 TEMPLATE_FIELD_IP_RANGE = 22,
57 TEMPLATE_FIELD_FIELD_SELECTOR_VALID = 23, /* Field selector mask */
58 TEMPLATE_FIELD_FIELD_SELECTOR_0 = 24,
59 TEMPLATE_FIELD_FIELD_SELECTOR_1 = 25,
60 TEMPLATE_FIELD_FIELD_SELECTOR_2 = 26,
61 TEMPLATE_FIELD_FIELD_SELECTOR_3 = 27,
62 TEMPLATE_FIELD_SIP2 = 28, /* IPv6 source IP[47:32] */
63 TEMPLATE_FIELD_SIP3 = 29, /* IPv6 source IP[63:48] */
64 TEMPLATE_FIELD_SIP4 = 30, /* IPv6 source IP[79:64] */
65 TEMPLATE_FIELD_SIP5 = 31, /* IPv6 source IP[95:80] */
66 TEMPLATE_FIELD_SIP6 = 32, /* IPv6 source IP[111:96] */
67 TEMPLATE_FIELD_SIP7 = 33, /* IPv6 source IP[127:112] */
68 TEMPLATE_FIELD_DIP2 = 34, /* IPv6 destination IP[47:32] */
69 TEMPLATE_FIELD_DIP3 = 35, /* IPv6 destination IP[63:48] */
70 TEMPLATE_FIELD_DIP4 = 36, /* IPv6 destination IP[79:64] */
71 TEMPLATE_FIELD_DIP5 = 37, /* IPv6 destination IP[95:80] */
72 TEMPLATE_FIELD_DIP6 = 38, /* IPv6 destination IP[111:96] */
73 TEMPLATE_FIELD_DIP7 = 39, /* IPv6 destination IP[127:112] */
74 TEMPLATE_FIELD_FWD_VID = 40, /* Forwarding VLAN-ID */
75 TEMPLATE_FIELD_FLOW_LABEL = 41,
76 };
77
78 /* The RTL838X SoCs use 5 fixed templates with definitions for which data fields are to
79 * be copied from the Ethernet Frame header into the 12 User-definable fields of the Packet
80 * Inspection Engine's buffer. The following defines the field contents for each of the fixed
81 * templates. Additionally, 3 user-definable templates can be set up via the definitions
82 * in RTL838X_ACL_TMPLTE_CTRL control registers.
83 * TODO: See all src/app/diag_v2/src/diag_pie.c
84 */
85 #define N_FIXED_TEMPLATES 5
86 static enum template_field_id fixed_templates[N_FIXED_TEMPLATES][N_FIXED_FIELDS] =
87 {
88 {
89 TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1, TEMPLATE_FIELD_OTAG,
90 TEMPLATE_FIELD_SMAC0, TEMPLATE_FIELD_SMAC1, TEMPLATE_FIELD_SMAC2,
91 TEMPLATE_FIELD_DMAC0, TEMPLATE_FIELD_DMAC1, TEMPLATE_FIELD_DMAC2,
92 TEMPLATE_FIELD_ETHERTYPE, TEMPLATE_FIELD_ITAG, TEMPLATE_FIELD_RANGE_CHK
93 }, {
94 TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_DIP0,
95 TEMPLATE_FIELD_DIP1,TEMPLATE_FIELD_IP_TOS_PROTO, TEMPLATE_FIELD_L4_SPORT,
96 TEMPLATE_FIELD_L4_DPORT, TEMPLATE_FIELD_ICMP_IGMP, TEMPLATE_FIELD_ITAG,
97 TEMPLATE_FIELD_RANGE_CHK, TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1
98 }, {
99 TEMPLATE_FIELD_DMAC0, TEMPLATE_FIELD_DMAC1, TEMPLATE_FIELD_DMAC2,
100 TEMPLATE_FIELD_ITAG, TEMPLATE_FIELD_ETHERTYPE, TEMPLATE_FIELD_IP_TOS_PROTO,
101 TEMPLATE_FIELD_L4_DPORT, TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_SIP0,
102 TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_DIP0, TEMPLATE_FIELD_DIP1
103 }, {
104 TEMPLATE_FIELD_DIP0, TEMPLATE_FIELD_DIP1, TEMPLATE_FIELD_DIP2,
105 TEMPLATE_FIELD_DIP3, TEMPLATE_FIELD_DIP4, TEMPLATE_FIELD_DIP5,
106 TEMPLATE_FIELD_DIP6, TEMPLATE_FIELD_DIP7, TEMPLATE_FIELD_L4_DPORT,
107 TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_ICMP_IGMP, TEMPLATE_FIELD_IP_TOS_PROTO
108 }, {
109 TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_SIP2,
110 TEMPLATE_FIELD_SIP3, TEMPLATE_FIELD_SIP4, TEMPLATE_FIELD_SIP5,
111 TEMPLATE_FIELD_SIP6, TEMPLATE_FIELD_SIP7, TEMPLATE_FIELD_ITAG,
112 TEMPLATE_FIELD_RANGE_CHK, TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1
113 },
114 };
115
116 void rtl838x_print_matrix(void)
117 {
118 unsigned volatile int *ptr8;
119 int i;
120
121 ptr8 = RTL838X_SW_BASE + RTL838X_PORT_ISO_CTRL(0);
122 for (i = 0; i < 28; i += 8)
123 pr_debug("> %8x %8x %8x %8x %8x %8x %8x %8x\n",
124 ptr8[i + 0], ptr8[i + 1], ptr8[i + 2], ptr8[i + 3],
125 ptr8[i + 4], ptr8[i + 5], ptr8[i + 6], ptr8[i + 7]);
126 pr_debug("CPU_PORT> %8x\n", ptr8[28]);
127 }
128
129 static inline int rtl838x_port_iso_ctrl(int p)
130 {
131 return RTL838X_PORT_ISO_CTRL(p);
132 }
133
134 static inline void rtl838x_exec_tbl0_cmd(u32 cmd)
135 {
136 sw_w32(cmd, RTL838X_TBL_ACCESS_CTRL_0);
137 do { } while (sw_r32(RTL838X_TBL_ACCESS_CTRL_0) & BIT(15));
138 }
139
140 static inline void rtl838x_exec_tbl1_cmd(u32 cmd)
141 {
142 sw_w32(cmd, RTL838X_TBL_ACCESS_CTRL_1);
143 do { } while (sw_r32(RTL838X_TBL_ACCESS_CTRL_1) & BIT(15));
144 }
145
146 static inline int rtl838x_tbl_access_data_0(int i)
147 {
148 return RTL838X_TBL_ACCESS_DATA_0(i);
149 }
150
151 static void rtl838x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info)
152 {
153 u32 v;
154 /* Read VLAN table (0) via register 0 */
155 struct table_reg *r = rtl_table_get(RTL8380_TBL_0, 0);
156
157 rtl_table_read(r, vlan);
158 info->tagged_ports = sw_r32(rtl_table_data(r, 0));
159 v = sw_r32(rtl_table_data(r, 1));
160 pr_debug("VLAN_READ %d: %016llx %08x\n", vlan, info->tagged_ports, v);
161 rtl_table_release(r);
162
163 info->profile_id = v & 0x7;
164 info->hash_mc_fid = !!(v & 0x8);
165 info->hash_uc_fid = !!(v & 0x10);
166 info->fid = (v >> 5) & 0x3f;
167
168 /* Read UNTAG table (0) via table register 1 */
169 r = rtl_table_get(RTL8380_TBL_1, 0);
170 rtl_table_read(r, vlan);
171 info->untagged_ports = sw_r32(rtl_table_data(r, 0));
172 rtl_table_release(r);
173 }
174
175 static void rtl838x_vlan_set_tagged(u32 vlan, struct rtl838x_vlan_info *info)
176 {
177 u32 v;
178 /* Access VLAN table (0) via register 0 */
179 struct table_reg *r = rtl_table_get(RTL8380_TBL_0, 0);
180
181 sw_w32(info->tagged_ports, rtl_table_data(r, 0));
182
183 v = info->profile_id;
184 v |= info->hash_mc_fid ? 0x8 : 0;
185 v |= info->hash_uc_fid ? 0x10 : 0;
186 v |= ((u32)info->fid) << 5;
187 sw_w32(v, rtl_table_data(r, 1));
188
189 rtl_table_write(r, vlan);
190 rtl_table_release(r);
191 }
192
193 static void rtl838x_vlan_set_untagged(u32 vlan, u64 portmask)
194 {
195 /* Access UNTAG table (0) via register 1 */
196 struct table_reg *r = rtl_table_get(RTL8380_TBL_1, 0);
197
198 sw_w32(portmask & 0x1fffffff, rtl_table_data(r, 0));
199 rtl_table_write(r, vlan);
200 rtl_table_release(r);
201 }
202
203 /* Sets the L2 forwarding to be based on either the inner VLAN tag or the outer
204 */
205 static void rtl838x_vlan_fwd_on_inner(int port, bool is_set)
206 {
207 if (is_set)
208 sw_w32_mask(BIT(port), 0, RTL838X_VLAN_PORT_FWD);
209 else
210 sw_w32_mask(0, BIT(port), RTL838X_VLAN_PORT_FWD);
211 }
212
213 static u64 rtl838x_l2_hash_seed(u64 mac, u32 vid)
214 {
215 return mac << 12 | vid;
216 }
217
218 /* Applies the same hash algorithm as the one used currently by the ASIC to the seed
219 * and returns a key into the L2 hash table
220 */
221 static u32 rtl838x_l2_hash_key(struct rtl838x_switch_priv *priv, u64 seed)
222 {
223 u32 h1, h2, h3, h;
224
225 if (sw_r32(priv->r->l2_ctrl_0) & 1) {
226 h1 = (seed >> 11) & 0x7ff;
227 h1 = ((h1 & 0x1f) << 6) | ((h1 >> 5) & 0x3f);
228
229 h2 = (seed >> 33) & 0x7ff;
230 h2 = ((h2 & 0x3f) << 5) | ((h2 >> 6) & 0x1f);
231
232 h3 = (seed >> 44) & 0x7ff;
233 h3 = ((h3 & 0x7f) << 4) | ((h3 >> 7) & 0xf);
234
235 h = h1 ^ h2 ^ h3 ^ ((seed >> 55) & 0x1ff);
236 h ^= ((seed >> 22) & 0x7ff) ^ (seed & 0x7ff);
237 } else {
238 h = ((seed >> 55) & 0x1ff) ^ ((seed >> 44) & 0x7ff) ^
239 ((seed >> 33) & 0x7ff) ^ ((seed >> 22) & 0x7ff) ^
240 ((seed >> 11) & 0x7ff) ^ (seed & 0x7ff);
241 }
242
243 return h;
244 }
245
246 static inline int rtl838x_mac_force_mode_ctrl(int p)
247 {
248 return RTL838X_MAC_FORCE_MODE_CTRL + (p << 2);
249 }
250
251 static inline int rtl838x_mac_port_ctrl(int p)
252 {
253 return RTL838X_MAC_PORT_CTRL(p);
254 }
255
256 static inline int rtl838x_l2_port_new_salrn(int p)
257 {
258 return RTL838X_L2_PORT_NEW_SALRN(p);
259 }
260
261 static inline int rtl838x_l2_port_new_sa_fwd(int p)
262 {
263 return RTL838X_L2_PORT_NEW_SA_FWD(p);
264 }
265
266 static inline int rtl838x_mac_link_spd_sts(int p)
267 {
268 return RTL838X_MAC_LINK_SPD_STS(p);
269 }
270
271 inline static int rtl838x_trk_mbr_ctr(int group)
272 {
273 return RTL838X_TRK_MBR_CTR + (group << 2);
274 }
275
276 /* Fills an L2 entry structure from the SoC registers */
277 static void rtl838x_fill_l2_entry(u32 r[], struct rtl838x_l2_entry *e)
278 {
279 /* Table contains different entry types, we need to identify the right one:
280 * Check for MC entries, first
281 * In contrast to the RTL93xx SoCs, there is no valid bit, use heuristics to
282 * identify valid entries
283 */
284 e->is_ip_mc = !!(r[0] & BIT(22));
285 e->is_ipv6_mc = !!(r[0] & BIT(21));
286 e->type = L2_INVALID;
287
288 if (!e->is_ip_mc && !e->is_ipv6_mc) {
289 e->mac[0] = (r[1] >> 20);
290 e->mac[1] = (r[1] >> 12);
291 e->mac[2] = (r[1] >> 4);
292 e->mac[3] = (r[1] & 0xf) << 4 | (r[2] >> 28);
293 e->mac[4] = (r[2] >> 20);
294 e->mac[5] = (r[2] >> 12);
295
296 e->rvid = r[2] & 0xfff;
297 e->vid = r[0] & 0xfff;
298
299 /* Is it a unicast entry? check multicast bit */
300 if (!(e->mac[0] & 1)) {
301 e->is_static = !!((r[0] >> 19) & 1);
302 e->port = (r[0] >> 12) & 0x1f;
303 e->block_da = !!(r[1] & BIT(30));
304 e->block_sa = !!(r[1] & BIT(31));
305 e->suspended = !!(r[1] & BIT(29));
306 e->next_hop = !!(r[1] & BIT(28));
307 if (e->next_hop) {
308 pr_debug("Found next hop entry, need to read extra data\n");
309 e->nh_vlan_target = !!(r[0] & BIT(9));
310 e->nh_route_id = r[0] & 0x1ff;
311 e->vid = e->rvid;
312 }
313 e->age = (r[0] >> 17) & 0x3;
314 e->valid = true;
315
316 /* A valid entry has one of mutli-cast, aging, sa/da-blocking,
317 * next-hop or static entry bit set
318 */
319 if (!(r[0] & 0x007c0000) && !(r[1] & 0xd0000000))
320 e->valid = false;
321 else
322 e->type = L2_UNICAST;
323 } else { /* L2 multicast */
324 pr_debug("Got L2 MC entry: %08x %08x %08x\n", r[0], r[1], r[2]);
325 e->valid = true;
326 e->type = L2_MULTICAST;
327 e->mc_portmask_index = (r[0] >> 12) & 0x1ff;
328 }
329 } else { /* IPv4 and IPv6 multicast */
330 e->valid = true;
331 e->mc_portmask_index = (r[0] >> 12) & 0x1ff;
332 e->mc_gip = (r[1] << 20) | (r[2] >> 12);
333 e->rvid = r[2] & 0xfff;
334 }
335 if (e->is_ip_mc)
336 e->type = IP4_MULTICAST;
337 if (e->is_ipv6_mc)
338 e->type = IP6_MULTICAST;
339 }
340
341 /* Fills the 3 SoC table registers r[] with the information of in the rtl838x_l2_entry */
342 static void rtl838x_fill_l2_row(u32 r[], struct rtl838x_l2_entry *e)
343 {
344 u64 mac = ether_addr_to_u64(e->mac);
345
346 if (!e->valid) {
347 r[0] = r[1] = r[2] = 0;
348 return;
349 }
350
351 r[0] = e->is_ip_mc ? BIT(22) : 0;
352 r[0] |= e->is_ipv6_mc ? BIT(21) : 0;
353
354 if (!e->is_ip_mc && !e->is_ipv6_mc) {
355 r[1] = mac >> 20;
356 r[2] = (mac & 0xfffff) << 12;
357
358 /* Is it a unicast entry? check multicast bit */
359 if (!(e->mac[0] & 1)) {
360 r[0] |= e->is_static ? BIT(19) : 0;
361 r[0] |= (e->port & 0x3f) << 12;
362 r[0] |= e->vid;
363 r[1] |= e->block_da ? BIT(30) : 0;
364 r[1] |= e->block_sa ? BIT(31) : 0;
365 r[1] |= e->suspended ? BIT(29) : 0;
366 r[2] |= e->rvid & 0xfff;
367 if (e->next_hop) {
368 r[1] |= BIT(28);
369 r[0] |= e->nh_vlan_target ? BIT(9) : 0;
370 r[0] |= e->nh_route_id & 0x1ff;
371 }
372 r[0] |= (e->age & 0x3) << 17;
373 } else { /* L2 Multicast */
374 r[0] |= (e->mc_portmask_index & 0x1ff) << 12;
375 r[2] |= e->rvid & 0xfff;
376 r[0] |= e->vid & 0xfff;
377 pr_debug("FILL MC: %08x %08x %08x\n", r[0], r[1], r[2]);
378 }
379 } else { /* IPv4 and IPv6 multicast */
380 r[0] |= (e->mc_portmask_index & 0x1ff) << 12;
381 r[1] = e->mc_gip >> 20;
382 r[2] = e->mc_gip << 12;
383 r[2] |= e->rvid;
384 }
385 }
386
387 /* Read an L2 UC or MC entry out of a hash bucket of the L2 forwarding table
388 * hash is the id of the bucket and pos is the position of the entry in that bucket
389 * The data read from the SoC is filled into rtl838x_l2_entry
390 */
391 static u64 rtl838x_read_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e)
392 {
393 u32 r[3];
394 struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 0); /* Access L2 Table 0 */
395 u32 idx = (0 << 14) | (hash << 2) | pos; /* Search SRAM, with hash and at pos in bucket */
396 int i;
397
398 rtl_table_read(q, idx);
399 for (i = 0; i < 3; i++)
400 r[i] = sw_r32(rtl_table_data(q, i));
401
402 rtl_table_release(q);
403
404 rtl838x_fill_l2_entry(r, e);
405 if (!e->valid)
406 return 0;
407
408 return (((u64) r[1]) << 32) | (r[2]); /* mac and vid concatenated as hash seed */
409 }
410
411 static void rtl838x_write_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e)
412 {
413 u32 r[3];
414 struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 0);
415 int i;
416
417 u32 idx = (0 << 14) | (hash << 2) | pos; /* Access SRAM, with hash and at pos in bucket */
418
419 rtl838x_fill_l2_row(r, e);
420
421 for (i = 0; i < 3; i++)
422 sw_w32(r[i], rtl_table_data(q, i));
423
424 rtl_table_write(q, idx);
425 rtl_table_release(q);
426 }
427
428 static u64 rtl838x_read_cam(int idx, struct rtl838x_l2_entry *e)
429 {
430 u32 r[3];
431 struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 1); /* Access L2 Table 1 */
432 int i;
433
434 rtl_table_read(q, idx);
435 for (i = 0; i < 3; i++)
436 r[i] = sw_r32(rtl_table_data(q, i));
437
438 rtl_table_release(q);
439
440 rtl838x_fill_l2_entry(r, e);
441 if (!e->valid)
442 return 0;
443
444 pr_debug("Found in CAM: R1 %x R2 %x R3 %x\n", r[0], r[1], r[2]);
445
446 /* Return MAC with concatenated VID ac concatenated ID */
447 return (((u64) r[1]) << 32) | r[2];
448 }
449
450 static void rtl838x_write_cam(int idx, struct rtl838x_l2_entry *e)
451 {
452 u32 r[3];
453 struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 1); /* Access L2 Table 1 */
454 int i;
455
456 rtl838x_fill_l2_row(r, e);
457
458 for (i = 0; i < 3; i++)
459 sw_w32(r[i], rtl_table_data(q, i));
460
461 rtl_table_write(q, idx);
462 rtl_table_release(q);
463 }
464
465 static u64 rtl838x_read_mcast_pmask(int idx)
466 {
467 u32 portmask;
468 /* Read MC_PMSK (2) via register RTL8380_TBL_L2 */
469 struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 2);
470
471 rtl_table_read(q, idx);
472 portmask = sw_r32(rtl_table_data(q, 0));
473 rtl_table_release(q);
474
475 return portmask;
476 }
477
478 static void rtl838x_write_mcast_pmask(int idx, u64 portmask)
479 {
480 /* Access MC_PMSK (2) via register RTL8380_TBL_L2 */
481 struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 2);
482
483 sw_w32(((u32)portmask) & 0x1fffffff, rtl_table_data(q, 0));
484 rtl_table_write(q, idx);
485 rtl_table_release(q);
486 }
487
488 static void rtl838x_vlan_profile_setup(int profile)
489 {
490 u32 pmask_id = UNKNOWN_MC_PMASK;
491 /* Enable L2 Learning BIT 0, portmask UNKNOWN_MC_PMASK for unknown MC traffic flooding */
492 u32 p = 1 | pmask_id << 1 | pmask_id << 10 | pmask_id << 19;
493
494 sw_w32(p, RTL838X_VLAN_PROFILE(profile));
495
496 /* RTL8380 and RTL8390 use an index into the portmask table to set the
497 * unknown multicast portmask, setup a default at a safe location
498 * On RTL93XX, the portmask is directly set in the profile,
499 * see e.g. rtl9300_vlan_profile_setup
500 */
501 rtl838x_write_mcast_pmask(UNKNOWN_MC_PMASK, 0x1fffffff);
502 }
503
504 static void rtl838x_l2_learning_setup(void)
505 {
506 /* Set portmask for broadcast traffic and unknown unicast address flooding
507 * to the reserved entry in the portmask table used also for
508 * multicast flooding */
509 sw_w32(UNKNOWN_MC_PMASK << 12 | UNKNOWN_MC_PMASK, RTL838X_L2_FLD_PMSK);
510
511 /* Enable learning constraint system-wide (bit 0), per-port (bit 1)
512 * and per vlan (bit 2) */
513 sw_w32(0x7, RTL838X_L2_LRN_CONSTRT_EN);
514
515 /* Limit learning to maximum: 16k entries, after that just flood (bits 0-1) */
516 sw_w32((0x3fff << 2) | 0, RTL838X_L2_LRN_CONSTRT);
517
518 /* Do not trap ARP packets to CPU_PORT */
519 sw_w32(0, RTL838X_SPCL_TRAP_ARP_CTRL);
520 }
521
522 static void rtl838x_enable_learning(int port, bool enable)
523 {
524 /* Limit learning to maximum: 16k entries */
525
526 sw_w32_mask(0x3fff << 2, enable ? (0x3fff << 2) : 0,
527 RTL838X_L2_PORT_LRN_CONSTRT + (port << 2));
528 }
529
530 static void rtl838x_enable_flood(int port, bool enable)
531 {
532 /* 0: Forward
533 * 1: Disable
534 * 2: to CPU
535 * 3: Copy to CPU
536 */
537 sw_w32_mask(0x3, enable ? 0 : 1,
538 RTL838X_L2_PORT_LRN_CONSTRT + (port << 2));
539 }
540
541 static void rtl838x_enable_mcast_flood(int port, bool enable)
542 {
543
544 }
545
546 static void rtl838x_enable_bcast_flood(int port, bool enable)
547 {
548
549 }
550
551 static void rtl838x_stp_get(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])
552 {
553 int i;
554 u32 cmd = 1 << 15 | /* Execute cmd */
555 1 << 14 | /* Read */
556 2 << 12 | /* Table type 0b10 */
557 (msti & 0xfff);
558 priv->r->exec_tbl0_cmd(cmd);
559
560 for (i = 0; i < 2; i++)
561 port_state[i] = sw_r32(priv->r->tbl_access_data_0(i));
562 }
563
564 static void rtl838x_stp_set(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])
565 {
566 int i;
567 u32 cmd = 1 << 15 | /* Execute cmd */
568 0 << 14 | /* Write */
569 2 << 12 | /* Table type 0b10 */
570 (msti & 0xfff);
571
572 for (i = 0; i < 2; i++)
573 sw_w32(port_state[i], priv->r->tbl_access_data_0(i));
574 priv->r->exec_tbl0_cmd(cmd);
575 }
576
577 u64 rtl838x_traffic_get(int source)
578 {
579 return rtl838x_get_port_reg(rtl838x_port_iso_ctrl(source));
580 }
581
582 void rtl838x_traffic_set(int source, u64 dest_matrix)
583 {
584 rtl838x_set_port_reg(dest_matrix, rtl838x_port_iso_ctrl(source));
585 }
586
587 void rtl838x_traffic_enable(int source, int dest)
588 {
589 rtl838x_mask_port_reg(0, BIT(dest), rtl838x_port_iso_ctrl(source));
590 }
591
592 void rtl838x_traffic_disable(int source, int dest)
593 {
594 rtl838x_mask_port_reg(BIT(dest), 0, rtl838x_port_iso_ctrl(source));
595 }
596
597 /* Enables or disables the EEE/EEEP capability of a port */
598 static void rtl838x_port_eee_set(struct rtl838x_switch_priv *priv, int port, bool enable)
599 {
600 u32 v;
601
602 /* This works only for Ethernet ports, and on the RTL838X, ports from 24 are SFP */
603 if (port >= 24)
604 return;
605
606 pr_debug("In %s: setting port %d to %d\n", __func__, port, enable);
607 v = enable ? 0x3 : 0x0;
608
609 /* Set EEE state for 100 (bit 9) & 1000MBit (bit 10) */
610 sw_w32_mask(0x3 << 9, v << 9, priv->r->mac_force_mode_ctrl(port));
611
612 /* Set TX/RX EEE state */
613 if (enable) {
614 sw_w32_mask(0, BIT(port), RTL838X_EEE_PORT_TX_EN);
615 sw_w32_mask(0, BIT(port), RTL838X_EEE_PORT_RX_EN);
616 } else {
617 sw_w32_mask(BIT(port), 0, RTL838X_EEE_PORT_TX_EN);
618 sw_w32_mask(BIT(port), 0, RTL838X_EEE_PORT_RX_EN);
619 }
620 priv->ports[port].eee_enabled = enable;
621 }
622
623
624 /* Get EEE own capabilities and negotiation result */
625 static int rtl838x_eee_port_ability(struct rtl838x_switch_priv *priv,
626 struct ethtool_eee *e, int port)
627 {
628 u64 link;
629
630 if (port >= 24)
631 return 0;
632
633 link = rtl839x_get_port_reg_le(RTL838X_MAC_LINK_STS);
634 if (!(link & BIT(port)))
635 return 0;
636
637 if (sw_r32(rtl838x_mac_force_mode_ctrl(port)) & BIT(9))
638 e->advertised |= ADVERTISED_100baseT_Full;
639
640 if (sw_r32(rtl838x_mac_force_mode_ctrl(port)) & BIT(10))
641 e->advertised |= ADVERTISED_1000baseT_Full;
642
643 if (sw_r32(RTL838X_MAC_EEE_ABLTY) & BIT(port)) {
644 e->lp_advertised = ADVERTISED_100baseT_Full;
645 e->lp_advertised |= ADVERTISED_1000baseT_Full;
646 return 1;
647 }
648
649 return 0;
650 }
651
652 static void rtl838x_init_eee(struct rtl838x_switch_priv *priv, bool enable)
653 {
654 int i;
655
656 pr_info("Setting up EEE, state: %d\n", enable);
657 sw_w32_mask(0x4, 0, RTL838X_SMI_GLB_CTRL);
658
659 /* Set timers for EEE */
660 sw_w32(0x5001411, RTL838X_EEE_TX_TIMER_GIGA_CTRL);
661 sw_w32(0x5001417, RTL838X_EEE_TX_TIMER_GELITE_CTRL);
662
663 /* Enable EEE MAC support on ports */
664 for (i = 0; i < priv->cpu_port; i++) {
665 if (priv->ports[i].phy)
666 rtl838x_port_eee_set(priv, i, enable);
667 }
668 priv->eee_enabled = enable;
669 }
670
671 static void rtl838x_pie_lookup_enable(struct rtl838x_switch_priv *priv, int index)
672 {
673 int block = index / PIE_BLOCK_SIZE;
674 u32 block_state = sw_r32(RTL838X_ACL_BLK_LOOKUP_CTRL);
675
676 /* Make sure rule-lookup is enabled in the block */
677 if (!(block_state & BIT(block)))
678 sw_w32(block_state | BIT(block), RTL838X_ACL_BLK_LOOKUP_CTRL);
679 }
680
681 static void rtl838x_pie_rule_del(struct rtl838x_switch_priv *priv, int index_from, int index_to)
682 {
683 int block_from = index_from / PIE_BLOCK_SIZE;
684 int block_to = index_to / PIE_BLOCK_SIZE;
685 u32 v = (index_from << 1)| (index_to << 12 ) | BIT(0);
686 int block;
687 u32 block_state;
688
689 pr_debug("%s: from %d to %d\n", __func__, index_from, index_to);
690 mutex_lock(&priv->reg_mutex);
691
692 /* Remember currently active blocks */
693 block_state = sw_r32(RTL838X_ACL_BLK_LOOKUP_CTRL);
694
695 /* Make sure rule-lookup is disabled in the relevant blocks */
696 for (block = block_from; block <= block_to; block++) {
697 if (block_state & BIT(block))
698 sw_w32(block_state & (~BIT(block)), RTL838X_ACL_BLK_LOOKUP_CTRL);
699 }
700
701 /* Write from-to and execute bit into control register */
702 sw_w32(v, RTL838X_ACL_CLR_CTRL);
703
704 /* Wait until command has completed */
705 do {
706 } while (sw_r32(RTL838X_ACL_CLR_CTRL) & BIT(0));
707
708 /* Re-enable rule lookup */
709 for (block = block_from; block <= block_to; block++) {
710 if (!(block_state & BIT(block)))
711 sw_w32(block_state | BIT(block), RTL838X_ACL_BLK_LOOKUP_CTRL);
712 }
713
714 mutex_unlock(&priv->reg_mutex);
715 }
716
717 /* Reads the intermediate representation of the templated match-fields of the
718 * PIE rule in the pie_rule structure and fills in the raw data fields in the
719 * raw register space r[].
720 * The register space configuration size is identical for the RTL8380/90 and RTL9300,
721 * however the RTL9310 has 2 more registers / fields and the physical field-ids
722 * are specific to every platform.
723 */
724 static void rtl838x_write_pie_templated(u32 r[], struct pie_rule *pr, enum template_field_id t[])
725 {
726 int i;
727 enum template_field_id field_type;
728 u16 data, data_m;
729
730 for (i = 0; i < N_FIXED_FIELDS; i++) {
731 field_type = t[i];
732 data = data_m = 0;
733
734 switch (field_type) {
735 case TEMPLATE_FIELD_SPM0:
736 data = pr->spm;
737 data_m = pr->spm_m;
738 break;
739 case TEMPLATE_FIELD_SPM1:
740 data = pr->spm >> 16;
741 data_m = pr->spm_m >> 16;
742 break;
743 case TEMPLATE_FIELD_OTAG:
744 data = pr->otag;
745 data_m = pr->otag_m;
746 break;
747 case TEMPLATE_FIELD_SMAC0:
748 data = pr->smac[4];
749 data = (data << 8) | pr->smac[5];
750 data_m = pr->smac_m[4];
751 data_m = (data_m << 8) | pr->smac_m[5];
752 break;
753 case TEMPLATE_FIELD_SMAC1:
754 data = pr->smac[2];
755 data = (data << 8) | pr->smac[3];
756 data_m = pr->smac_m[2];
757 data_m = (data_m << 8) | pr->smac_m[3];
758 break;
759 case TEMPLATE_FIELD_SMAC2:
760 data = pr->smac[0];
761 data = (data << 8) | pr->smac[1];
762 data_m = pr->smac_m[0];
763 data_m = (data_m << 8) | pr->smac_m[1];
764 break;
765 case TEMPLATE_FIELD_DMAC0:
766 data = pr->dmac[4];
767 data = (data << 8) | pr->dmac[5];
768 data_m = pr->dmac_m[4];
769 data_m = (data_m << 8) | pr->dmac_m[5];
770 break;
771 case TEMPLATE_FIELD_DMAC1:
772 data = pr->dmac[2];
773 data = (data << 8) | pr->dmac[3];
774 data_m = pr->dmac_m[2];
775 data_m = (data_m << 8) | pr->dmac_m[3];
776 break;
777 case TEMPLATE_FIELD_DMAC2:
778 data = pr->dmac[0];
779 data = (data << 8) | pr->dmac[1];
780 data_m = pr->dmac_m[0];
781 data_m = (data_m << 8) | pr->dmac_m[1];
782 break;
783 case TEMPLATE_FIELD_ETHERTYPE:
784 data = pr->ethertype;
785 data_m = pr->ethertype_m;
786 break;
787 case TEMPLATE_FIELD_ITAG:
788 data = pr->itag;
789 data_m = pr->itag_m;
790 break;
791 case TEMPLATE_FIELD_RANGE_CHK:
792 data = pr->field_range_check;
793 data_m = pr->field_range_check_m;
794 break;
795 case TEMPLATE_FIELD_SIP0:
796 if (pr->is_ipv6) {
797 data = pr->sip6.s6_addr16[7];
798 data_m = pr->sip6_m.s6_addr16[7];
799 } else {
800 data = pr->sip;
801 data_m = pr->sip_m;
802 }
803 break;
804 case TEMPLATE_FIELD_SIP1:
805 if (pr->is_ipv6) {
806 data = pr->sip6.s6_addr16[6];
807 data_m = pr->sip6_m.s6_addr16[6];
808 } else {
809 data = pr->sip >> 16;
810 data_m = pr->sip_m >> 16;
811 }
812 break;
813 case TEMPLATE_FIELD_SIP2:
814 case TEMPLATE_FIELD_SIP3:
815 case TEMPLATE_FIELD_SIP4:
816 case TEMPLATE_FIELD_SIP5:
817 case TEMPLATE_FIELD_SIP6:
818 case TEMPLATE_FIELD_SIP7:
819 data = pr->sip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)];
820 data_m = pr->sip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)];
821 break;
822 case TEMPLATE_FIELD_DIP0:
823 if (pr->is_ipv6) {
824 data = pr->dip6.s6_addr16[7];
825 data_m = pr->dip6_m.s6_addr16[7];
826 } else {
827 data = pr->dip;
828 data_m = pr->dip_m;
829 }
830 break;
831 case TEMPLATE_FIELD_DIP1:
832 if (pr->is_ipv6) {
833 data = pr->dip6.s6_addr16[6];
834 data_m = pr->dip6_m.s6_addr16[6];
835 } else {
836 data = pr->dip >> 16;
837 data_m = pr->dip_m >> 16;
838 }
839 break;
840 case TEMPLATE_FIELD_DIP2:
841 case TEMPLATE_FIELD_DIP3:
842 case TEMPLATE_FIELD_DIP4:
843 case TEMPLATE_FIELD_DIP5:
844 case TEMPLATE_FIELD_DIP6:
845 case TEMPLATE_FIELD_DIP7:
846 data = pr->dip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)];
847 data_m = pr->dip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)];
848 break;
849 case TEMPLATE_FIELD_IP_TOS_PROTO:
850 data = pr->tos_proto;
851 data_m = pr->tos_proto_m;
852 break;
853 case TEMPLATE_FIELD_L4_SPORT:
854 data = pr->sport;
855 data_m = pr->sport_m;
856 break;
857 case TEMPLATE_FIELD_L4_DPORT:
858 data = pr->dport;
859 data_m = pr->dport_m;
860 break;
861 case TEMPLATE_FIELD_ICMP_IGMP:
862 data = pr->icmp_igmp;
863 data_m = pr->icmp_igmp_m;
864 break;
865 default:
866 pr_info("%s: unknown field %d\n", __func__, field_type);
867 continue;
868 }
869 if (!(i % 2)) {
870 r[5 - i / 2] = data;
871 r[12 - i / 2] = data_m;
872 } else {
873 r[5 - i / 2] |= ((u32)data) << 16;
874 r[12 - i / 2] |= ((u32)data_m) << 16;
875 }
876 }
877 }
878
879 /* Creates the intermediate representation of the templated match-fields of the
880 * PIE rule in the pie_rule structure by reading the raw data fields in the
881 * raw register space r[].
882 * The register space configuration size is identical for the RTL8380/90 and RTL9300,
883 * however the RTL9310 has 2 more registers / fields and the physical field-ids
884 */
885 static void rtl838x_read_pie_templated(u32 r[], struct pie_rule *pr, enum template_field_id t[])
886 {
887 int i;
888 enum template_field_id field_type;
889 u16 data, data_m;
890
891 for (i = 0; i < N_FIXED_FIELDS; i++) {
892 field_type = t[i];
893 if (!(i % 2)) {
894 data = r[5 - i / 2];
895 data_m = r[12 - i / 2];
896 } else {
897 data = r[5 - i / 2] >> 16;
898 data_m = r[12 - i / 2] >> 16;
899 }
900
901 switch (field_type) {
902 case TEMPLATE_FIELD_SPM0:
903 pr->spm = (pr->spn << 16) | data;
904 pr->spm_m = (pr->spn << 16) | data_m;
905 break;
906 case TEMPLATE_FIELD_SPM1:
907 pr->spm = data;
908 pr->spm_m = data_m;
909 break;
910 case TEMPLATE_FIELD_OTAG:
911 pr->otag = data;
912 pr->otag_m = data_m;
913 break;
914 case TEMPLATE_FIELD_SMAC0:
915 pr->smac[4] = data >> 8;
916 pr->smac[5] = data;
917 pr->smac_m[4] = data >> 8;
918 pr->smac_m[5] = data;
919 break;
920 case TEMPLATE_FIELD_SMAC1:
921 pr->smac[2] = data >> 8;
922 pr->smac[3] = data;
923 pr->smac_m[2] = data >> 8;
924 pr->smac_m[3] = data;
925 break;
926 case TEMPLATE_FIELD_SMAC2:
927 pr->smac[0] = data >> 8;
928 pr->smac[1] = data;
929 pr->smac_m[0] = data >> 8;
930 pr->smac_m[1] = data;
931 break;
932 case TEMPLATE_FIELD_DMAC0:
933 pr->dmac[4] = data >> 8;
934 pr->dmac[5] = data;
935 pr->dmac_m[4] = data >> 8;
936 pr->dmac_m[5] = data;
937 break;
938 case TEMPLATE_FIELD_DMAC1:
939 pr->dmac[2] = data >> 8;
940 pr->dmac[3] = data;
941 pr->dmac_m[2] = data >> 8;
942 pr->dmac_m[3] = data;
943 break;
944 case TEMPLATE_FIELD_DMAC2:
945 pr->dmac[0] = data >> 8;
946 pr->dmac[1] = data;
947 pr->dmac_m[0] = data >> 8;
948 pr->dmac_m[1] = data;
949 break;
950 case TEMPLATE_FIELD_ETHERTYPE:
951 pr->ethertype = data;
952 pr->ethertype_m = data_m;
953 break;
954 case TEMPLATE_FIELD_ITAG:
955 pr->itag = data;
956 pr->itag_m = data_m;
957 break;
958 case TEMPLATE_FIELD_RANGE_CHK:
959 pr->field_range_check = data;
960 pr->field_range_check_m = data_m;
961 break;
962 case TEMPLATE_FIELD_SIP0:
963 pr->sip = data;
964 pr->sip_m = data_m;
965 break;
966 case TEMPLATE_FIELD_SIP1:
967 pr->sip = (pr->sip << 16) | data;
968 pr->sip_m = (pr->sip << 16) | data_m;
969 break;
970 case TEMPLATE_FIELD_SIP2:
971 pr->is_ipv6 = true;
972 /* Make use of limitiations on the position of the match values */
973 ipv6_addr_set(&pr->sip6, pr->sip, r[5 - i / 2],
974 r[4 - i / 2], r[3 - i / 2]);
975 ipv6_addr_set(&pr->sip6_m, pr->sip_m, r[5 - i / 2],
976 r[4 - i / 2], r[3 - i / 2]);
977 case TEMPLATE_FIELD_SIP3:
978 case TEMPLATE_FIELD_SIP4:
979 case TEMPLATE_FIELD_SIP5:
980 case TEMPLATE_FIELD_SIP6:
981 case TEMPLATE_FIELD_SIP7:
982 break;
983 case TEMPLATE_FIELD_DIP0:
984 pr->dip = data;
985 pr->dip_m = data_m;
986 break;
987 case TEMPLATE_FIELD_DIP1:
988 pr->dip = (pr->dip << 16) | data;
989 pr->dip_m = (pr->dip << 16) | data_m;
990 break;
991 case TEMPLATE_FIELD_DIP2:
992 pr->is_ipv6 = true;
993 ipv6_addr_set(&pr->dip6, pr->dip, r[5 - i / 2],
994 r[4 - i / 2], r[3 - i / 2]);
995 ipv6_addr_set(&pr->dip6_m, pr->dip_m, r[5 - i / 2],
996 r[4 - i / 2], r[3 - i / 2]);
997 case TEMPLATE_FIELD_DIP3:
998 case TEMPLATE_FIELD_DIP4:
999 case TEMPLATE_FIELD_DIP5:
1000 case TEMPLATE_FIELD_DIP6:
1001 case TEMPLATE_FIELD_DIP7:
1002 break;
1003 case TEMPLATE_FIELD_IP_TOS_PROTO:
1004 pr->tos_proto = data;
1005 pr->tos_proto_m = data_m;
1006 break;
1007 case TEMPLATE_FIELD_L4_SPORT:
1008 pr->sport = data;
1009 pr->sport_m = data_m;
1010 break;
1011 case TEMPLATE_FIELD_L4_DPORT:
1012 pr->dport = data;
1013 pr->dport_m = data_m;
1014 break;
1015 case TEMPLATE_FIELD_ICMP_IGMP:
1016 pr->icmp_igmp = data;
1017 pr->icmp_igmp_m = data_m;
1018 break;
1019 default:
1020 pr_info("%s: unknown field %d\n", __func__, field_type);
1021 }
1022 }
1023 }
1024
1025 static void rtl838x_read_pie_fixed_fields(u32 r[], struct pie_rule *pr)
1026 {
1027 pr->spmmask_fix = (r[6] >> 22) & 0x3;
1028 pr->spn = (r[6] >> 16) & 0x3f;
1029 pr->mgnt_vlan = (r[6] >> 15) & 1;
1030 pr->dmac_hit_sw = (r[6] >> 14) & 1;
1031 pr->not_first_frag = (r[6] >> 13) & 1;
1032 pr->frame_type_l4 = (r[6] >> 10) & 7;
1033 pr->frame_type = (r[6] >> 8) & 3;
1034 pr->otag_fmt = (r[6] >> 7) & 1;
1035 pr->itag_fmt = (r[6] >> 6) & 1;
1036 pr->otag_exist = (r[6] >> 5) & 1;
1037 pr->itag_exist = (r[6] >> 4) & 1;
1038 pr->frame_type_l2 = (r[6] >> 2) & 3;
1039 pr->tid = r[6] & 3;
1040
1041 pr->spmmask_fix_m = (r[13] >> 22) & 0x3;
1042 pr->spn_m = (r[13] >> 16) & 0x3f;
1043 pr->mgnt_vlan_m = (r[13] >> 15) & 1;
1044 pr->dmac_hit_sw_m = (r[13] >> 14) & 1;
1045 pr->not_first_frag_m = (r[13] >> 13) & 1;
1046 pr->frame_type_l4_m = (r[13] >> 10) & 7;
1047 pr->frame_type_m = (r[13] >> 8) & 3;
1048 pr->otag_fmt_m = (r[13] >> 7) & 1;
1049 pr->itag_fmt_m = (r[13] >> 6) & 1;
1050 pr->otag_exist_m = (r[13] >> 5) & 1;
1051 pr->itag_exist_m = (r[13] >> 4) & 1;
1052 pr->frame_type_l2_m = (r[13] >> 2) & 3;
1053 pr->tid_m = r[13] & 3;
1054
1055 pr->valid = r[14] & BIT(31);
1056 pr->cond_not = r[14] & BIT(30);
1057 pr->cond_and1 = r[14] & BIT(29);
1058 pr->cond_and2 = r[14] & BIT(28);
1059 pr->ivalid = r[14] & BIT(27);
1060
1061 pr->drop = (r[17] >> 14) & 3;
1062 pr->fwd_sel = r[17] & BIT(13);
1063 pr->ovid_sel = r[17] & BIT(12);
1064 pr->ivid_sel = r[17] & BIT(11);
1065 pr->flt_sel = r[17] & BIT(10);
1066 pr->log_sel = r[17] & BIT(9);
1067 pr->rmk_sel = r[17] & BIT(8);
1068 pr->meter_sel = r[17] & BIT(7);
1069 pr->tagst_sel = r[17] & BIT(6);
1070 pr->mir_sel = r[17] & BIT(5);
1071 pr->nopri_sel = r[17] & BIT(4);
1072 pr->cpupri_sel = r[17] & BIT(3);
1073 pr->otpid_sel = r[17] & BIT(2);
1074 pr->itpid_sel = r[17] & BIT(1);
1075 pr->shaper_sel = r[17] & BIT(0);
1076 }
1077
1078 static void rtl838x_write_pie_fixed_fields(u32 r[], struct pie_rule *pr)
1079 {
1080 r[6] = ((u32) (pr->spmmask_fix & 0x3)) << 22;
1081 r[6] |= ((u32) (pr->spn & 0x3f)) << 16;
1082 r[6] |= pr->mgnt_vlan ? BIT(15) : 0;
1083 r[6] |= pr->dmac_hit_sw ? BIT(14) : 0;
1084 r[6] |= pr->not_first_frag ? BIT(13) : 0;
1085 r[6] |= ((u32) (pr->frame_type_l4 & 0x7)) << 10;
1086 r[6] |= ((u32) (pr->frame_type & 0x3)) << 8;
1087 r[6] |= pr->otag_fmt ? BIT(7) : 0;
1088 r[6] |= pr->itag_fmt ? BIT(6) : 0;
1089 r[6] |= pr->otag_exist ? BIT(5) : 0;
1090 r[6] |= pr->itag_exist ? BIT(4) : 0;
1091 r[6] |= ((u32) (pr->frame_type_l2 & 0x3)) << 2;
1092 r[6] |= ((u32) (pr->tid & 0x3));
1093
1094 r[13] = ((u32) (pr->spmmask_fix_m & 0x3)) << 22;
1095 r[13] |= ((u32) (pr->spn_m & 0x3f)) << 16;
1096 r[13] |= pr->mgnt_vlan_m ? BIT(15) : 0;
1097 r[13] |= pr->dmac_hit_sw_m ? BIT(14) : 0;
1098 r[13] |= pr->not_first_frag_m ? BIT(13) : 0;
1099 r[13] |= ((u32) (pr->frame_type_l4_m & 0x7)) << 10;
1100 r[13] |= ((u32) (pr->frame_type_m & 0x3)) << 8;
1101 r[13] |= pr->otag_fmt_m ? BIT(7) : 0;
1102 r[13] |= pr->itag_fmt_m ? BIT(6) : 0;
1103 r[13] |= pr->otag_exist_m ? BIT(5) : 0;
1104 r[13] |= pr->itag_exist_m ? BIT(4) : 0;
1105 r[13] |= ((u32) (pr->frame_type_l2_m & 0x3)) << 2;
1106 r[13] |= ((u32) (pr->tid_m & 0x3));
1107
1108 r[14] = pr->valid ? BIT(31) : 0;
1109 r[14] |= pr->cond_not ? BIT(30) : 0;
1110 r[14] |= pr->cond_and1 ? BIT(29) : 0;
1111 r[14] |= pr->cond_and2 ? BIT(28) : 0;
1112 r[14] |= pr->ivalid ? BIT(27) : 0;
1113
1114 if (pr->drop)
1115 r[17] = 0x1 << 14; /* Standard drop action */
1116 else
1117 r[17] = 0;
1118 r[17] |= pr->fwd_sel ? BIT(13) : 0;
1119 r[17] |= pr->ovid_sel ? BIT(12) : 0;
1120 r[17] |= pr->ivid_sel ? BIT(11) : 0;
1121 r[17] |= pr->flt_sel ? BIT(10) : 0;
1122 r[17] |= pr->log_sel ? BIT(9) : 0;
1123 r[17] |= pr->rmk_sel ? BIT(8) : 0;
1124 r[17] |= pr->meter_sel ? BIT(7) : 0;
1125 r[17] |= pr->tagst_sel ? BIT(6) : 0;
1126 r[17] |= pr->mir_sel ? BIT(5) : 0;
1127 r[17] |= pr->nopri_sel ? BIT(4) : 0;
1128 r[17] |= pr->cpupri_sel ? BIT(3) : 0;
1129 r[17] |= pr->otpid_sel ? BIT(2) : 0;
1130 r[17] |= pr->itpid_sel ? BIT(1) : 0;
1131 r[17] |= pr->shaper_sel ? BIT(0) : 0;
1132 }
1133
1134 static int rtl838x_write_pie_action(u32 r[], struct pie_rule *pr)
1135 {
1136 u16 *aif = (u16 *)&r[17];
1137 u16 data;
1138 int fields_used = 0;
1139
1140 aif--;
1141
1142 pr_debug("%s, at %08x\n", __func__, (u32)aif);
1143 /* Multiple actions can be linked to a match of a PIE rule,
1144 * they have different precedence depending on their type and this precedence
1145 * defines which Action Information Field (0-4) in the IACL table stores
1146 * the additional data of the action (like e.g. the port number a packet is
1147 * forwarded to) */
1148 /* TODO: count bits in selectors to limit to a maximum number of actions */
1149 if (pr->fwd_sel) { /* Forwarding action */
1150 data = pr->fwd_act << 13;
1151 data |= pr->fwd_data;
1152 data |= pr->bypass_all ? BIT(12) : 0;
1153 data |= pr->bypass_ibc_sc ? BIT(11) : 0;
1154 data |= pr->bypass_igr_stp ? BIT(10) : 0;
1155 *aif-- = data;
1156 fields_used++;
1157 }
1158
1159 if (pr->ovid_sel) { /* Outer VID action */
1160 data = (pr->ovid_act & 0x3) << 12;
1161 data |= pr->ovid_data;
1162 *aif-- = data;
1163 fields_used++;
1164 }
1165
1166 if (pr->ivid_sel) { /* Inner VID action */
1167 data = (pr->ivid_act & 0x3) << 12;
1168 data |= pr->ivid_data;
1169 *aif-- = data;
1170 fields_used++;
1171 }
1172
1173 if (pr->flt_sel) { /* Filter action */
1174 *aif-- = pr->flt_data;
1175 fields_used++;
1176 }
1177
1178 if (pr->log_sel) { /* Log action */
1179 if (fields_used >= 4)
1180 return -1;
1181 *aif-- = pr->log_data;
1182 fields_used++;
1183 }
1184
1185 if (pr->rmk_sel) { /* Remark action */
1186 if (fields_used >= 4)
1187 return -1;
1188 *aif-- = pr->rmk_data;
1189 fields_used++;
1190 }
1191
1192 if (pr->meter_sel) { /* Meter action */
1193 if (fields_used >= 4)
1194 return -1;
1195 *aif-- = pr->meter_data;
1196 fields_used++;
1197 }
1198
1199 if (pr->tagst_sel) { /* Egress Tag Status action */
1200 if (fields_used >= 4)
1201 return -1;
1202 *aif-- = pr->tagst_data;
1203 fields_used++;
1204 }
1205
1206 if (pr->mir_sel) { /* Mirror action */
1207 if (fields_used >= 4)
1208 return -1;
1209 *aif-- = pr->mir_data;
1210 fields_used++;
1211 }
1212
1213 if (pr->nopri_sel) { /* Normal Priority action */
1214 if (fields_used >= 4)
1215 return -1;
1216 *aif-- = pr->nopri_data;
1217 fields_used++;
1218 }
1219
1220 if (pr->cpupri_sel) { /* CPU Priority action */
1221 if (fields_used >= 4)
1222 return -1;
1223 *aif-- = pr->nopri_data;
1224 fields_used++;
1225 }
1226
1227 if (pr->otpid_sel) { /* OTPID action */
1228 if (fields_used >= 4)
1229 return -1;
1230 *aif-- = pr->otpid_data;
1231 fields_used++;
1232 }
1233
1234 if (pr->itpid_sel) { /* ITPID action */
1235 if (fields_used >= 4)
1236 return -1;
1237 *aif-- = pr->itpid_data;
1238 fields_used++;
1239 }
1240
1241 if (pr->shaper_sel) { /* Traffic shaper action */
1242 if (fields_used >= 4)
1243 return -1;
1244 *aif-- = pr->shaper_data;
1245 fields_used++;
1246 }
1247
1248 return 0;
1249 }
1250
1251 static void rtl838x_read_pie_action(u32 r[], struct pie_rule *pr)
1252 {
1253 u16 *aif = (u16 *)&r[17];
1254
1255 aif--;
1256
1257 pr_debug("%s, at %08x\n", __func__, (u32)aif);
1258 if (pr->drop)
1259 pr_debug("%s: Action Drop: %d", __func__, pr->drop);
1260
1261 if (pr->fwd_sel){ /* Forwarding action */
1262 pr->fwd_act = *aif >> 13;
1263 pr->fwd_data = *aif--;
1264 pr->bypass_all = pr->fwd_data & BIT(12);
1265 pr->bypass_ibc_sc = pr->fwd_data & BIT(11);
1266 pr->bypass_igr_stp = pr->fwd_data & BIT(10);
1267 if (pr->bypass_all || pr->bypass_ibc_sc || pr->bypass_igr_stp)
1268 pr->bypass_sel = true;
1269 }
1270 if (pr->ovid_sel) /* Outer VID action */
1271 pr->ovid_data = *aif--;
1272 if (pr->ivid_sel) /* Inner VID action */
1273 pr->ivid_data = *aif--;
1274 if (pr->flt_sel) /* Filter action */
1275 pr->flt_data = *aif--;
1276 if (pr->log_sel) /* Log action */
1277 pr->log_data = *aif--;
1278 if (pr->rmk_sel) /* Remark action */
1279 pr->rmk_data = *aif--;
1280 if (pr->meter_sel) /* Meter action */
1281 pr->meter_data = *aif--;
1282 if (pr->tagst_sel) /* Egress Tag Status action */
1283 pr->tagst_data = *aif--;
1284 if (pr->mir_sel) /* Mirror action */
1285 pr->mir_data = *aif--;
1286 if (pr->nopri_sel) /* Normal Priority action */
1287 pr->nopri_data = *aif--;
1288 if (pr->cpupri_sel) /* CPU Priority action */
1289 pr->nopri_data = *aif--;
1290 if (pr->otpid_sel) /* OTPID action */
1291 pr->otpid_data = *aif--;
1292 if (pr->itpid_sel) /* ITPID action */
1293 pr->itpid_data = *aif--;
1294 if (pr->shaper_sel) /* Traffic shaper action */
1295 pr->shaper_data = *aif--;
1296 }
1297
1298 static void rtl838x_pie_rule_dump_raw(u32 r[])
1299 {
1300 pr_info("Raw IACL table entry:\n");
1301 pr_info("Match : %08x %08x %08x %08x %08x %08x\n", r[0], r[1], r[2], r[3], r[4], r[5]);
1302 pr_info("Fixed : %08x\n", r[6]);
1303 pr_info("Match M: %08x %08x %08x %08x %08x %08x\n", r[7], r[8], r[9], r[10], r[11], r[12]);
1304 pr_info("Fixed M: %08x\n", r[13]);
1305 pr_info("AIF : %08x %08x %08x\n", r[14], r[15], r[16]);
1306 pr_info("Sel : %08x\n", r[17]);
1307 }
1308
1309 static void rtl838x_pie_rule_dump(struct pie_rule *pr)
1310 {
1311 pr_info("Drop: %d, fwd: %d, ovid: %d, ivid: %d, flt: %d, log: %d, rmk: %d, meter: %d tagst: %d, mir: %d, nopri: %d, cpupri: %d, otpid: %d, itpid: %d, shape: %d\n",
1312 pr->drop, pr->fwd_sel, pr->ovid_sel, pr->ivid_sel, pr->flt_sel, pr->log_sel, pr->rmk_sel, pr->log_sel, pr->tagst_sel, pr->mir_sel, pr->nopri_sel,
1313 pr->cpupri_sel, pr->otpid_sel, pr->itpid_sel, pr->shaper_sel);
1314 if (pr->fwd_sel)
1315 pr_info("FWD: %08x\n", pr->fwd_data);
1316 pr_info("TID: %x, %x\n", pr->tid, pr->tid_m);
1317 }
1318
1319 static int rtl838x_pie_rule_read(struct rtl838x_switch_priv *priv, int idx, struct pie_rule *pr)
1320 {
1321 /* Read IACL table (1) via register 0 */
1322 struct table_reg *q = rtl_table_get(RTL8380_TBL_0, 1);
1323 u32 r[18];
1324 int i;
1325 int block = idx / PIE_BLOCK_SIZE;
1326 u32 t_select = sw_r32(RTL838X_ACL_BLK_TMPLTE_CTRL(block));
1327
1328 memset(pr, 0, sizeof(*pr));
1329 rtl_table_read(q, idx);
1330 for (i = 0; i < 18; i++)
1331 r[i] = sw_r32(rtl_table_data(q, i));
1332
1333 rtl_table_release(q);
1334
1335 rtl838x_read_pie_fixed_fields(r, pr);
1336 if (!pr->valid)
1337 return 0;
1338
1339 pr_info("%s: template_selectors %08x, tid: %d\n", __func__, t_select, pr->tid);
1340 rtl838x_pie_rule_dump_raw(r);
1341
1342 rtl838x_read_pie_templated(r, pr, fixed_templates[(t_select >> (pr->tid * 3)) & 0x7]);
1343
1344 rtl838x_read_pie_action(r, pr);
1345
1346 return 0;
1347 }
1348
1349 static int rtl838x_pie_rule_write(struct rtl838x_switch_priv *priv, int idx, struct pie_rule *pr)
1350 {
1351 /* Access IACL table (1) via register 0 */
1352 struct table_reg *q = rtl_table_get(RTL8380_TBL_0, 1);
1353 u32 r[18];
1354 int i, err = 0;
1355 int block = idx / PIE_BLOCK_SIZE;
1356 u32 t_select = sw_r32(RTL838X_ACL_BLK_TMPLTE_CTRL(block));
1357
1358 pr_debug("%s: %d, t_select: %08x\n", __func__, idx, t_select);
1359
1360 for (i = 0; i < 18; i++)
1361 r[i] = 0;
1362
1363 if (!pr->valid)
1364 goto err_out;
1365
1366 rtl838x_write_pie_fixed_fields(r, pr);
1367
1368 pr_debug("%s: template %d\n", __func__, (t_select >> (pr->tid * 3)) & 0x7);
1369 rtl838x_write_pie_templated(r, pr, fixed_templates[(t_select >> (pr->tid * 3)) & 0x7]);
1370
1371 if (rtl838x_write_pie_action(r, pr)) {
1372 pr_err("Rule actions too complex\n");
1373 goto err_out;
1374 }
1375
1376 /* rtl838x_pie_rule_dump_raw(r); */
1377
1378 for (i = 0; i < 18; i++)
1379 sw_w32(r[i], rtl_table_data(q, i));
1380
1381 err_out:
1382 rtl_table_write(q, idx);
1383 rtl_table_release(q);
1384
1385 return err;
1386 }
1387
1388 static bool rtl838x_pie_templ_has(int t, enum template_field_id field_type)
1389 {
1390 int i;
1391 enum template_field_id ft;
1392
1393 for (i = 0; i < N_FIXED_FIELDS; i++) {
1394 ft = fixed_templates[t][i];
1395 if (field_type == ft)
1396 return true;
1397 }
1398
1399 return false;
1400 }
1401
1402 static int rtl838x_pie_verify_template(struct rtl838x_switch_priv *priv,
1403 struct pie_rule *pr, int t, int block)
1404 {
1405 int i;
1406
1407 if (!pr->is_ipv6 && pr->sip_m && !rtl838x_pie_templ_has(t, TEMPLATE_FIELD_SIP0))
1408 return -1;
1409
1410 if (!pr->is_ipv6 && pr->dip_m && !rtl838x_pie_templ_has(t, TEMPLATE_FIELD_DIP0))
1411 return -1;
1412
1413 if (pr->is_ipv6) {
1414 if ((pr->sip6_m.s6_addr32[0] ||
1415 pr->sip6_m.s6_addr32[1] ||
1416 pr->sip6_m.s6_addr32[2] ||
1417 pr->sip6_m.s6_addr32[3]) &&
1418 !rtl838x_pie_templ_has(t, TEMPLATE_FIELD_SIP2))
1419 return -1;
1420 if ((pr->dip6_m.s6_addr32[0] ||
1421 pr->dip6_m.s6_addr32[1] ||
1422 pr->dip6_m.s6_addr32[2] ||
1423 pr->dip6_m.s6_addr32[3]) &&
1424 !rtl838x_pie_templ_has(t, TEMPLATE_FIELD_DIP2))
1425 return -1;
1426 }
1427
1428 if (ether_addr_to_u64(pr->smac) && !rtl838x_pie_templ_has(t, TEMPLATE_FIELD_SMAC0))
1429 return -1;
1430
1431 if (ether_addr_to_u64(pr->dmac) && !rtl838x_pie_templ_has(t, TEMPLATE_FIELD_DMAC0))
1432 return -1;
1433
1434 /* TODO: Check more */
1435
1436 i = find_first_zero_bit(&priv->pie_use_bm[block * 4], PIE_BLOCK_SIZE);
1437
1438 if (i >= PIE_BLOCK_SIZE)
1439 return -1;
1440
1441 return i + PIE_BLOCK_SIZE * block;
1442 }
1443
1444 static int rtl838x_pie_rule_add(struct rtl838x_switch_priv *priv, struct pie_rule *pr)
1445 {
1446 int idx, block, j, t;
1447
1448 pr_debug("In %s\n", __func__);
1449
1450 mutex_lock(&priv->pie_mutex);
1451
1452 for (block = 0; block < priv->n_pie_blocks; block++) {
1453 for (j = 0; j < 3; j++) {
1454 t = (sw_r32(RTL838X_ACL_BLK_TMPLTE_CTRL(block)) >> (j * 3)) & 0x7;
1455 pr_debug("Testing block %d, template %d, template id %d\n", block, j, t);
1456 idx = rtl838x_pie_verify_template(priv, pr, t, block);
1457 if (idx >= 0)
1458 break;
1459 }
1460 if (j < 3)
1461 break;
1462 }
1463
1464 if (block >= priv->n_pie_blocks) {
1465 mutex_unlock(&priv->pie_mutex);
1466 return -EOPNOTSUPP;
1467 }
1468
1469 pr_debug("Using block: %d, index %d, template-id %d\n", block, idx, j);
1470 set_bit(idx, priv->pie_use_bm);
1471
1472 pr->valid = true;
1473 pr->tid = j; /* Mapped to template number */
1474 pr->tid_m = 0x3;
1475 pr->id = idx;
1476
1477 rtl838x_pie_lookup_enable(priv, idx);
1478 rtl838x_pie_rule_write(priv, idx, pr);
1479
1480 mutex_unlock(&priv->pie_mutex);
1481
1482 return 0;
1483 }
1484
1485 static void rtl838x_pie_rule_rm(struct rtl838x_switch_priv *priv, struct pie_rule *pr)
1486 {
1487 int idx = pr->id;
1488
1489 rtl838x_pie_rule_del(priv, idx, idx);
1490 clear_bit(idx, priv->pie_use_bm);
1491 }
1492
1493 /* Initializes the Packet Inspection Engine:
1494 * powers it up, enables default matching templates for all blocks
1495 * and clears all rules possibly installed by u-boot
1496 */
1497 static void rtl838x_pie_init(struct rtl838x_switch_priv *priv)
1498 {
1499 int i;
1500 u32 template_selectors;
1501
1502 mutex_init(&priv->pie_mutex);
1503
1504 /* Enable ACL lookup on all ports, including CPU_PORT */
1505 for (i = 0; i <= priv->cpu_port; i++)
1506 sw_w32(1, RTL838X_ACL_PORT_LOOKUP_CTRL(i));
1507
1508 /* Power on all PIE blocks */
1509 for (i = 0; i < priv->n_pie_blocks; i++)
1510 sw_w32_mask(0, BIT(i), RTL838X_ACL_BLK_PWR_CTRL);
1511
1512 /* Include IPG in metering */
1513 sw_w32(1, RTL838X_METER_GLB_CTRL);
1514
1515 /* Delete all present rules */
1516 rtl838x_pie_rule_del(priv, 0, priv->n_pie_blocks * PIE_BLOCK_SIZE - 1);
1517
1518 /* Routing bypasses source port filter: disable write-protection, first */
1519 sw_w32_mask(0, 3, RTL838X_INT_RW_CTRL);
1520 sw_w32_mask(0, 1, RTL838X_DMY_REG27);
1521 sw_w32_mask(3, 0, RTL838X_INT_RW_CTRL);
1522
1523 /* Enable predefined templates 0, 1 and 2 for even blocks */
1524 template_selectors = 0 | (1 << 3) | (2 << 6);
1525 for (i = 0; i < 6; i += 2)
1526 sw_w32(template_selectors, RTL838X_ACL_BLK_TMPLTE_CTRL(i));
1527
1528 /* Enable predefined templates 0, 3 and 4 (IPv6 support) for odd blocks */
1529 template_selectors = 0 | (3 << 3) | (4 << 6);
1530 for (i = 1; i < priv->n_pie_blocks; i += 2)
1531 sw_w32(template_selectors, RTL838X_ACL_BLK_TMPLTE_CTRL(i));
1532
1533 /* Group each pair of physical blocks together to a logical block */
1534 sw_w32(0b10101010101, RTL838X_ACL_BLK_GROUP_CTRL);
1535 }
1536
1537 static u32 rtl838x_packet_cntr_read(int counter)
1538 {
1539 u32 v;
1540
1541 /* Read LOG table (3) via register RTL8380_TBL_0 */
1542 struct table_reg *r = rtl_table_get(RTL8380_TBL_0, 3);
1543
1544 pr_debug("In %s, id %d\n", __func__, counter);
1545 rtl_table_read(r, counter / 2);
1546
1547 pr_debug("Registers: %08x %08x\n",
1548 sw_r32(rtl_table_data(r, 0)), sw_r32(rtl_table_data(r, 1)));
1549 /* The table has a size of 2 registers */
1550 if (counter % 2)
1551 v = sw_r32(rtl_table_data(r, 0));
1552 else
1553 v = sw_r32(rtl_table_data(r, 1));
1554
1555 rtl_table_release(r);
1556
1557 return v;
1558 }
1559
1560 static void rtl838x_packet_cntr_clear(int counter)
1561 {
1562 /* Access LOG table (3) via register RTL8380_TBL_0 */
1563 struct table_reg *r = rtl_table_get(RTL8380_TBL_0, 3);
1564
1565 pr_debug("In %s, id %d\n", __func__, counter);
1566 /* The table has a size of 2 registers */
1567 if (counter % 2)
1568 sw_w32(0, rtl_table_data(r, 0));
1569 else
1570 sw_w32(0, rtl_table_data(r, 1));
1571
1572 rtl_table_write(r, counter / 2);
1573
1574 rtl_table_release(r);
1575 }
1576
1577 static void rtl838x_route_read(int idx, struct rtl83xx_route *rt)
1578 {
1579 /* Read ROUTING table (2) via register RTL8380_TBL_1 */
1580 struct table_reg *r = rtl_table_get(RTL8380_TBL_1, 2);
1581
1582 pr_debug("In %s, id %d\n", __func__, idx);
1583 rtl_table_read(r, idx);
1584
1585 /* The table has a size of 2 registers */
1586 rt->nh.gw = sw_r32(rtl_table_data(r, 0));
1587 rt->nh.gw <<= 32;
1588 rt->nh.gw |= sw_r32(rtl_table_data(r, 1));
1589
1590 rtl_table_release(r);
1591 }
1592
1593 static void rtl838x_route_write(int idx, struct rtl83xx_route *rt)
1594 {
1595 /* Access ROUTING table (2) via register RTL8380_TBL_1 */
1596 struct table_reg *r = rtl_table_get(RTL8380_TBL_1, 2);
1597
1598 pr_debug("In %s, id %d, gw: %016llx\n", __func__, idx, rt->nh.gw);
1599 sw_w32(rt->nh.gw >> 32, rtl_table_data(r, 0));
1600 sw_w32(rt->nh.gw, rtl_table_data(r, 1));
1601 rtl_table_write(r, idx);
1602
1603 rtl_table_release(r);
1604 }
1605
1606 static int rtl838x_l3_setup(struct rtl838x_switch_priv *priv)
1607 {
1608 /* Nothing to be done */
1609 return 0;
1610 }
1611
1612 void rtl838x_vlan_port_keep_tag_set(int port, bool keep_outer, bool keep_inner)
1613 {
1614 sw_w32(FIELD_PREP(RTL838X_VLAN_PORT_TAG_STS_CTRL_OTAG_STS_MASK,
1615 keep_outer ? RTL838X_VLAN_PORT_TAG_STS_TAGGED : RTL838X_VLAN_PORT_TAG_STS_UNTAG) |
1616 FIELD_PREP(RTL838X_VLAN_PORT_TAG_STS_CTRL_ITAG_STS_MASK,
1617 keep_inner ? RTL838X_VLAN_PORT_TAG_STS_TAGGED : RTL838X_VLAN_PORT_TAG_STS_UNTAG),
1618 RTL838X_VLAN_PORT_TAG_STS_CTRL(port));
1619 }
1620
1621 void rtl838x_vlan_port_pvidmode_set(int port, enum pbvlan_type type, enum pbvlan_mode mode)
1622 {
1623 if (type == PBVLAN_TYPE_INNER)
1624 sw_w32_mask(0x3, mode, RTL838X_VLAN_PORT_PB_VLAN + (port << 2));
1625 else
1626 sw_w32_mask(0x3 << 14, mode << 14, RTL838X_VLAN_PORT_PB_VLAN + (port << 2));
1627 }
1628
1629 void rtl838x_vlan_port_pvid_set(int port, enum pbvlan_type type, int pvid)
1630 {
1631 if (type == PBVLAN_TYPE_INNER)
1632 sw_w32_mask(0xfff << 2, pvid << 2, RTL838X_VLAN_PORT_PB_VLAN + (port << 2));
1633 else
1634 sw_w32_mask(0xfff << 16, pvid << 16, RTL838X_VLAN_PORT_PB_VLAN + (port << 2));
1635 }
1636
1637 static int rtl838x_set_ageing_time(unsigned long msec)
1638 {
1639 int t = sw_r32(RTL838X_L2_CTRL_1);
1640
1641 t &= 0x7FFFFF;
1642 t = t * 128 / 625; /* Aging time in seconds. 0: L2 aging disabled */
1643 pr_debug("L2 AGING time: %d sec\n", t);
1644
1645 t = (msec * 625 + 127000) / 128000;
1646 t = t > 0x7FFFFF ? 0x7FFFFF : t;
1647 sw_w32_mask(0x7FFFFF, t, RTL838X_L2_CTRL_1);
1648 pr_debug("Dynamic aging for ports: %x\n", sw_r32(RTL838X_L2_PORT_AGING_OUT));
1649
1650 return 0;
1651 }
1652
1653 static void rtl838x_set_igr_filter(int port, enum igr_filter state)
1654 {
1655 sw_w32_mask(0x3 << ((port & 0xf)<<1), state << ((port & 0xf)<<1),
1656 RTL838X_VLAN_PORT_IGR_FLTR + (((port >> 4) << 2)));
1657 }
1658
1659 static void rtl838x_set_egr_filter(int port, enum egr_filter state)
1660 {
1661 sw_w32_mask(0x1 << (port % 0x1d), state << (port % 0x1d),
1662 RTL838X_VLAN_PORT_EGR_FLTR + (((port / 29) << 2)));
1663 }
1664
1665 void rtl838x_set_distribution_algorithm(int group, int algoidx, u32 algomsk)
1666 {
1667 algoidx &= 1; /* RTL838X only supports 2 concurrent algorithms */
1668 sw_w32_mask(1 << (group % 8), algoidx << (group % 8),
1669 RTL838X_TRK_HASH_IDX_CTRL + ((group >> 3) << 2));
1670 sw_w32(algomsk, RTL838X_TRK_HASH_CTRL + (algoidx << 2));
1671 }
1672
1673 void rtl838x_set_receive_management_action(int port, rma_ctrl_t type, action_type_t action)
1674 {
1675 switch(type) {
1676 case BPDU:
1677 sw_w32_mask(3 << ((port & 0xf) << 1), (action & 0x3) << ((port & 0xf) << 1),
1678 RTL838X_RMA_BPDU_CTRL + ((port >> 4) << 2));
1679 break;
1680 case PTP:
1681 sw_w32_mask(3 << ((port & 0xf) << 1), (action & 0x3) << ((port & 0xf) << 1),
1682 RTL838X_RMA_PTP_CTRL + ((port >> 4) << 2));
1683 break;
1684 case LLTP:
1685 sw_w32_mask(3 << ((port & 0xf) << 1), (action & 0x3) << ((port & 0xf) << 1),
1686 RTL838X_RMA_LLTP_CTRL + ((port >> 4) << 2));
1687 break;
1688 default:
1689 break;
1690 }
1691 }
1692
1693 const struct rtl838x_reg rtl838x_reg = {
1694 .mask_port_reg_be = rtl838x_mask_port_reg,
1695 .set_port_reg_be = rtl838x_set_port_reg,
1696 .get_port_reg_be = rtl838x_get_port_reg,
1697 .mask_port_reg_le = rtl838x_mask_port_reg,
1698 .set_port_reg_le = rtl838x_set_port_reg,
1699 .get_port_reg_le = rtl838x_get_port_reg,
1700 .stat_port_rst = RTL838X_STAT_PORT_RST,
1701 .stat_rst = RTL838X_STAT_RST,
1702 .stat_port_std_mib = RTL838X_STAT_PORT_STD_MIB,
1703 .port_iso_ctrl = rtl838x_port_iso_ctrl,
1704 .traffic_enable = rtl838x_traffic_enable,
1705 .traffic_disable = rtl838x_traffic_disable,
1706 .traffic_get = rtl838x_traffic_get,
1707 .traffic_set = rtl838x_traffic_set,
1708 .l2_ctrl_0 = RTL838X_L2_CTRL_0,
1709 .l2_ctrl_1 = RTL838X_L2_CTRL_1,
1710 .l2_port_aging_out = RTL838X_L2_PORT_AGING_OUT,
1711 .set_ageing_time = rtl838x_set_ageing_time,
1712 .smi_poll_ctrl = RTL838X_SMI_POLL_CTRL,
1713 .l2_tbl_flush_ctrl = RTL838X_L2_TBL_FLUSH_CTRL,
1714 .exec_tbl0_cmd = rtl838x_exec_tbl0_cmd,
1715 .exec_tbl1_cmd = rtl838x_exec_tbl1_cmd,
1716 .tbl_access_data_0 = rtl838x_tbl_access_data_0,
1717 .isr_glb_src = RTL838X_ISR_GLB_SRC,
1718 .isr_port_link_sts_chg = RTL838X_ISR_PORT_LINK_STS_CHG,
1719 .imr_port_link_sts_chg = RTL838X_IMR_PORT_LINK_STS_CHG,
1720 .imr_glb = RTL838X_IMR_GLB,
1721 .vlan_tables_read = rtl838x_vlan_tables_read,
1722 .vlan_set_tagged = rtl838x_vlan_set_tagged,
1723 .vlan_set_untagged = rtl838x_vlan_set_untagged,
1724 .mac_force_mode_ctrl = rtl838x_mac_force_mode_ctrl,
1725 .vlan_profile_dump = rtl838x_vlan_profile_dump,
1726 .vlan_profile_setup = rtl838x_vlan_profile_setup,
1727 .vlan_fwd_on_inner = rtl838x_vlan_fwd_on_inner,
1728 .set_vlan_igr_filter = rtl838x_set_igr_filter,
1729 .set_vlan_egr_filter = rtl838x_set_egr_filter,
1730 .enable_learning = rtl838x_enable_learning,
1731 .enable_flood = rtl838x_enable_flood,
1732 .enable_mcast_flood = rtl838x_enable_mcast_flood,
1733 .enable_bcast_flood = rtl838x_enable_bcast_flood,
1734 .stp_get = rtl838x_stp_get,
1735 .stp_set = rtl838x_stp_set,
1736 .mac_port_ctrl = rtl838x_mac_port_ctrl,
1737 .l2_port_new_salrn = rtl838x_l2_port_new_salrn,
1738 .l2_port_new_sa_fwd = rtl838x_l2_port_new_sa_fwd,
1739 .mir_ctrl = RTL838X_MIR_CTRL,
1740 .mir_dpm = RTL838X_MIR_DPM_CTRL,
1741 .mir_spm = RTL838X_MIR_SPM_CTRL,
1742 .mac_link_sts = RTL838X_MAC_LINK_STS,
1743 .mac_link_dup_sts = RTL838X_MAC_LINK_DUP_STS,
1744 .mac_link_spd_sts = rtl838x_mac_link_spd_sts,
1745 .mac_rx_pause_sts = RTL838X_MAC_RX_PAUSE_STS,
1746 .mac_tx_pause_sts = RTL838X_MAC_TX_PAUSE_STS,
1747 .read_l2_entry_using_hash = rtl838x_read_l2_entry_using_hash,
1748 .write_l2_entry_using_hash = rtl838x_write_l2_entry_using_hash,
1749 .read_cam = rtl838x_read_cam,
1750 .write_cam = rtl838x_write_cam,
1751 .vlan_port_keep_tag_set = rtl838x_vlan_port_keep_tag_set,
1752 .vlan_port_pvidmode_set = rtl838x_vlan_port_pvidmode_set,
1753 .vlan_port_pvid_set = rtl838x_vlan_port_pvid_set,
1754 .trk_mbr_ctr = rtl838x_trk_mbr_ctr,
1755 .rma_bpdu_fld_pmask = RTL838X_RMA_BPDU_FLD_PMSK,
1756 .spcl_trap_eapol_ctrl = RTL838X_SPCL_TRAP_EAPOL_CTRL,
1757 .init_eee = rtl838x_init_eee,
1758 .port_eee_set = rtl838x_port_eee_set,
1759 .eee_port_ability = rtl838x_eee_port_ability,
1760 .l2_hash_seed = rtl838x_l2_hash_seed,
1761 .l2_hash_key = rtl838x_l2_hash_key,
1762 .read_mcast_pmask = rtl838x_read_mcast_pmask,
1763 .write_mcast_pmask = rtl838x_write_mcast_pmask,
1764 .pie_init = rtl838x_pie_init,
1765 .pie_rule_read = rtl838x_pie_rule_read,
1766 .pie_rule_write = rtl838x_pie_rule_write,
1767 .pie_rule_add = rtl838x_pie_rule_add,
1768 .pie_rule_rm = rtl838x_pie_rule_rm,
1769 .l2_learning_setup = rtl838x_l2_learning_setup,
1770 .packet_cntr_read = rtl838x_packet_cntr_read,
1771 .packet_cntr_clear = rtl838x_packet_cntr_clear,
1772 .route_read = rtl838x_route_read,
1773 .route_write = rtl838x_route_write,
1774 .l3_setup = rtl838x_l3_setup,
1775 .set_distribution_algorithm = rtl838x_set_distribution_algorithm,
1776 .set_receive_management_action = rtl838x_set_receive_management_action,
1777 };
1778
1779 irqreturn_t rtl838x_switch_irq(int irq, void *dev_id)
1780 {
1781 struct dsa_switch *ds = dev_id;
1782 u32 status = sw_r32(RTL838X_ISR_GLB_SRC);
1783 u32 ports = sw_r32(RTL838X_ISR_PORT_LINK_STS_CHG);
1784 u32 link;
1785 int i;
1786
1787 /* Clear status */
1788 sw_w32(ports, RTL838X_ISR_PORT_LINK_STS_CHG);
1789 pr_info("RTL8380 Link change: status: %x, ports %x\n", status, ports);
1790
1791 for (i = 0; i < 28; i++) {
1792 if (ports & BIT(i)) {
1793 link = sw_r32(RTL838X_MAC_LINK_STS);
1794 if (link & BIT(i))
1795 dsa_port_phylink_mac_change(ds, i, true);
1796 else
1797 dsa_port_phylink_mac_change(ds, i, false);
1798 }
1799 }
1800
1801 return IRQ_HANDLED;
1802 }
1803
1804 int rtl838x_smi_wait_op(int timeout)
1805 {
1806 int ret = 0;
1807 u32 val;
1808
1809 ret = readx_poll_timeout(sw_r32, RTL838X_SMI_ACCESS_PHY_CTRL_1,
1810 val, !(val & 0x1), 20, timeout);
1811 if (ret)
1812 pr_err("%s: timeout\n", __func__);
1813
1814 return ret;
1815 }
1816
1817 /* Reads a register in a page from the PHY */
1818 int rtl838x_read_phy(u32 port, u32 page, u32 reg, u32 *val)
1819 {
1820 int err = -ETIMEDOUT;
1821 u32 v;
1822 u32 park_page;
1823
1824 if (port > 31) {
1825 *val = 0xffff;
1826 return 0;
1827 }
1828
1829 if (page > 4095 || reg > 31)
1830 return -ENOTSUPP;
1831
1832 mutex_lock(&smi_lock);
1833
1834 if (rtl838x_smi_wait_op(100000))
1835 goto timeout;
1836
1837 sw_w32_mask(0xffff0000, port << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2);
1838
1839 park_page = sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_1) & ((0x1f << 15) | 0x2);
1840 v = reg << 20 | page << 3;
1841 sw_w32(v | park_page, RTL838X_SMI_ACCESS_PHY_CTRL_1);
1842 sw_w32_mask(0, 1, RTL838X_SMI_ACCESS_PHY_CTRL_1);
1843
1844 if (rtl838x_smi_wait_op(100000))
1845 goto timeout;
1846
1847 *val = sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_2) & 0xffff;
1848
1849 err = 0;
1850
1851 timeout:
1852 mutex_unlock(&smi_lock);
1853
1854 return -ETIMEDOUT;
1855 }
1856
1857 /* Write to a register in a page of the PHY */
1858 int rtl838x_write_phy(u32 port, u32 page, u32 reg, u32 val)
1859 {
1860 int err = -ETIMEDOUT;
1861 u32 v;
1862 u32 park_page;
1863
1864 val &= 0xffff;
1865 if (port > 31 || page > 4095 || reg > 31)
1866 return -ENOTSUPP;
1867
1868 mutex_lock(&smi_lock);
1869 if (rtl838x_smi_wait_op(100000))
1870 goto timeout;
1871
1872 sw_w32(BIT(port), RTL838X_SMI_ACCESS_PHY_CTRL_0);
1873 mdelay(10);
1874
1875 sw_w32_mask(0xffff0000, val << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2);
1876
1877 park_page = sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_1) & ((0x1f << 15) | 0x2);
1878 v = reg << 20 | page << 3 | 0x4;
1879 sw_w32(v | park_page, RTL838X_SMI_ACCESS_PHY_CTRL_1);
1880 sw_w32_mask(0, 1, RTL838X_SMI_ACCESS_PHY_CTRL_1);
1881
1882 if (rtl838x_smi_wait_op(100000))
1883 goto timeout;
1884
1885 err = 0;
1886
1887 timeout:
1888 mutex_unlock(&smi_lock);
1889
1890 return -ETIMEDOUT;
1891 }
1892
1893 /* Read an mmd register of a PHY */
1894 int rtl838x_read_mmd_phy(u32 port, u32 addr, u32 reg, u32 *val)
1895 {
1896 int err = -ETIMEDOUT;
1897 u32 v;
1898
1899 mutex_lock(&smi_lock);
1900
1901 if (rtl838x_smi_wait_op(100000))
1902 goto timeout;
1903
1904 sw_w32(1 << port, RTL838X_SMI_ACCESS_PHY_CTRL_0);
1905 mdelay(10);
1906
1907 sw_w32_mask(0xffff0000, port << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2);
1908
1909 v = addr << 16 | reg;
1910 sw_w32(v, RTL838X_SMI_ACCESS_PHY_CTRL_3);
1911
1912 /* mmd-access | read | cmd-start */
1913 v = 1 << 1 | 0 << 2 | 1;
1914 sw_w32(v, RTL838X_SMI_ACCESS_PHY_CTRL_1);
1915
1916 if (rtl838x_smi_wait_op(100000))
1917 goto timeout;
1918
1919 *val = sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_2) & 0xffff;
1920
1921 err = 0;
1922
1923 timeout:
1924 mutex_unlock(&smi_lock);
1925
1926 return err;
1927 }
1928
1929 /* Write to an mmd register of a PHY */
1930 int rtl838x_write_mmd_phy(u32 port, u32 addr, u32 reg, u32 val)
1931 {
1932 int err = -ETIMEDOUT;
1933 u32 v;
1934
1935 pr_debug("MMD write: port %d, dev %d, reg %d, val %x\n", port, addr, reg, val);
1936 val &= 0xffff;
1937 mutex_lock(&smi_lock);
1938
1939 if (rtl838x_smi_wait_op(100000))
1940 goto timeout;
1941
1942 sw_w32(1 << port, RTL838X_SMI_ACCESS_PHY_CTRL_0);
1943 mdelay(10);
1944
1945 sw_w32_mask(0xffff0000, val << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2);
1946
1947 sw_w32_mask(0x1f << 16, addr << 16, RTL838X_SMI_ACCESS_PHY_CTRL_3);
1948 sw_w32_mask(0xffff, reg, RTL838X_SMI_ACCESS_PHY_CTRL_3);
1949 /* mmd-access | write | cmd-start */
1950 v = 1 << 1 | 1 << 2 | 1;
1951 sw_w32(v, RTL838X_SMI_ACCESS_PHY_CTRL_1);
1952
1953 if (rtl838x_smi_wait_op(100000))
1954 goto timeout;
1955
1956 err = 0;
1957
1958 timeout:
1959 mutex_unlock(&smi_lock);
1960 return err;
1961 }
1962
1963 void rtl8380_get_version(struct rtl838x_switch_priv *priv)
1964 {
1965 u32 rw_save, info_save;
1966 u32 info;
1967
1968 rw_save = sw_r32(RTL838X_INT_RW_CTRL);
1969 sw_w32(rw_save | 0x3, RTL838X_INT_RW_CTRL);
1970
1971 info_save = sw_r32(RTL838X_CHIP_INFO);
1972 sw_w32(info_save | 0xA0000000, RTL838X_CHIP_INFO);
1973
1974 info = sw_r32(RTL838X_CHIP_INFO);
1975 sw_w32(info_save, RTL838X_CHIP_INFO);
1976 sw_w32(rw_save, RTL838X_INT_RW_CTRL);
1977
1978 if ((info & 0xFFFF) == 0x6275) {
1979 if (((info >> 16) & 0x1F) == 0x1)
1980 priv->version = RTL8380_VERSION_A;
1981 else if (((info >> 16) & 0x1F) == 0x2)
1982 priv->version = RTL8380_VERSION_B;
1983 else
1984 priv->version = RTL8380_VERSION_B;
1985 } else {
1986 priv->version = '-';
1987 }
1988 }
1989
1990 void rtl838x_vlan_profile_dump(int profile)
1991 {
1992 u32 p;
1993
1994 if (profile < 0 || profile > 7)
1995 return;
1996
1997 p = sw_r32(RTL838X_VLAN_PROFILE(profile));
1998
1999 pr_info("VLAN profile %d: L2 learning: %d, UNKN L2MC FLD PMSK %d, \
2000 UNKN IPMC FLD PMSK %d, UNKN IPv6MC FLD PMSK: %d",
2001 profile, p & 1, (p >> 1) & 0x1ff, (p >> 10) & 0x1ff, (p >> 19) & 0x1ff);
2002 }
2003
2004 void rtl8380_sds_rst(int mac)
2005 {
2006 u32 offset = (mac == 24) ? 0 : 0x100;
2007
2008 sw_w32_mask(1 << 11, 0, RTL838X_SDS4_FIB_REG0 + offset);
2009 sw_w32_mask(0x3, 0, RTL838X_SDS4_REG28 + offset);
2010 sw_w32_mask(0x3, 0x3, RTL838X_SDS4_REG28 + offset);
2011 sw_w32_mask(0, 0x1 << 6, RTL838X_SDS4_DUMMY0 + offset);
2012 sw_w32_mask(0x1 << 6, 0, RTL838X_SDS4_DUMMY0 + offset);
2013 pr_debug("SERDES reset: %d\n", mac);
2014 }
2015
2016 int rtl8380_sds_power(int mac, int val)
2017 {
2018 u32 mode = (val == 1) ? 0x4 : 0x9;
2019 u32 offset = (mac == 24) ? 5 : 0;
2020
2021 if ((mac != 24) && (mac != 26)) {
2022 pr_err("%s: not a fibre port: %d\n", __func__, mac);
2023 return -1;
2024 }
2025
2026 sw_w32_mask(0x1f << offset, mode << offset, RTL838X_SDS_MODE_SEL);
2027
2028 rtl8380_sds_rst(mac);
2029
2030 return 0;
2031 }
OpenWrt Source Repository