target/linux/rockchip/patches-5.4/101-dts-rockchip-add-usb3-controller-node-for-RK3328-SoCs.patch

   1 From: William Wu <william.wu@rock-chips.com>
   2
   3 RK3328 has one USB 3.0 OTG controller which uses DWC_USB3
   4 core's general architecture. It can act as static xHCI host
   5 controller, static device controller, USB 3.0/2.0 OTG basing
   6 on ID of USB3.0 PHY.
   7
   8 Signed-off-by: William Wu <william.wu@rock-chips.com>
   9 Signed-off-by: Leonidas P. Papadakos <papadakospan@gmail.com>
  10
  11 ---
  12
  13 NOTE: This binding still has issues. From the original thread:
  14
  15 the rk3328 usb3-phy has an issue with detecting any plugin events
  16 after a previous device got removed - see the inno-usb3-phy driver
  17 in the vendor kernel.
  18
  19 The current state is good-enough for enabling the USB3 attached LAN
  20 port of the NanoPi R2S. However, it might explode depending on your
  21 use-case. You've been warned.
  22
  23 ---
  24  arch/arm64/boot/dts/rockchip/rk3328.dtsi | 27 ++++++++++++++++++++++++
  25  1 file changed, 27 insertions(+)
  26
  27 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
  28 +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
  29 @@ -936,6 +936,33 @@
  30                 status = "disabled";
  31         };
  32
  33 +       usbdrd3: usb@ff600000 {
  34 +               compatible = "rockchip,rk3328-dwc3", "rockchip,rk3399-dwc3";
  35 +               clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>,
  36 +                        <&cru ACLK_USB3OTG>;
  37 +               clock-names = "ref_clk", "suspend_clk",
  38 +                             "bus_clk";
  39 +               #address-cells = <2>;
  40 +               #size-cells = <2>;
  41 +               ranges;
  42 +               status = "disabled";
  43 +
  44 +               usbdrd_dwc3: dwc3@ff600000 {
  45 +                       compatible = "snps,dwc3";
  46 +                       reg = <0x0 0xff600000 0x0 0x100000>;
  47 +                       interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
  48 +                       dr_mode = "otg";
  49 +                       phy_type = "utmi_wide";
  50 +                       snps,dis_enblslpm_quirk;
  51 +                       snps,dis-u2-freeclk-exists-quirk;
  52 +                       snps,dis_u2_susphy_quirk;
  53 +                       snps,dis_u3_susphy_quirk;
  54 +                       snps,dis-del-phy-power-chg-quirk;
  55 +                       snps,dis-tx-ipgap-linecheck-quirk;
  56 +                       status = "disabled";
  57 +               };
  58 +       };
  59 +
  60         gic: interrupt-controller@ff811000 {
  61                 compatible = "arm,gic-400";
  62                 #interrupt-cells = <3>;