projects / openwrt / openwrt.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
* refresh storm patches * disable BX in uClibc config, add ethernet and watchdog...
[openwrt/openwrt.git] / target / linux / storm / patches / 1006-gmac-napi-tx.patch
1 --- a/drivers/net/sl351x_gmac.c
2 +++ b/drivers/net/sl351x_gmac.c
3 @@ -43,9 +43,13 @@
4
5 #include <linux/mtd/kvctl.h>
6
7 +#define GET_RPTR(x) ((x) & 0xFFFF)
8 +#define GET_WPTR(x) ((x) >> 16)
9 +
10 #define MIDWAY
11 #define SL_LEPUS
12 -#define VITESSE_G5SWITCH 1
13 +// #define VITESSE_G5SWITCH 1
14 +#undef VITESSE_G5SWITCH
15
16 #ifndef CONFIG_SL351x_RXTOE
17 //#define CONFIG_SL351x_RXTOE 1
18 @@ -126,7 +130,6 @@
19 *************************************************************/
20 static int gmac_initialized = 0;
21 TOE_INFO_T toe_private_data;
22 -static int do_again = 0;
23 static int rx_poll_enabled;
24 spinlock_t gmac_fq_lock;
25 unsigned int FLAG_SWITCH;
26 @@ -190,7 +193,7 @@
27 void mac_set_sw_tx_weight(struct net_device *dev, char *weight);
28 void mac_get_hw_tx_weight(struct net_device *dev, char *weight);
29 void mac_set_hw_tx_weight(struct net_device *dev, char *weight);
30 -static inline void toe_gmac_fill_free_q(void);
31 +static inline void toe_gmac_fill_free_q(int count);
32
33 #ifdef VITESSE_G5SWITCH
34 extern int Get_Set_port_status(void);
35 @@ -295,12 +298,14 @@
36 for(j = 0; i<CONFIG_MAC_NUM; j++)
37 {
38 i=j;
39 +#ifdef VITESSE_G5SWITCH
40 if(Giga_switch){ // if gswitch present, swap eth0/1
41 if(j==0)
42 i=1;
43 else if(j==1)
44 i=0;
45 }
46 +#endif
47
48 tp = (GMAC_INFO_T *)&toe_private_data.gmac[i];
49 tp->dev = NULL;
50 @@ -459,7 +464,7 @@
51 toe->gmac[1].dma_base_addr = TOE_GMAC1_DMA_BASE;
52 toe->gmac[0].auto_nego_cfg = 1;
53 toe->gmac[1].auto_nego_cfg = 1;
54 -#ifdef CONFIG_SL3516_ASIC
55 +#ifndef CONFIG_SL3516_ASIC
56 toe->gmac[0].speed_cfg = GMAC_SPEED_1000;
57 toe->gmac[1].speed_cfg = GMAC_SPEED_1000;
58 #else
59 @@ -508,7 +513,7 @@
60 // Write GLOBAL_QUEUE_THRESHOLD_REG
61 threshold.bits32 = 0;
62 threshold.bits.swfq_empty = (TOE_SW_FREEQ_DESC_NUM > 256) ? 255 :
63 - TOE_SW_FREEQ_DESC_NUM/2;
64 + TOE_SW_FREEQ_DESC_NUM/16;
65 threshold.bits.hwfq_empty = (TOE_HW_FREEQ_DESC_NUM > 256) ? 256/4 :
66 TOE_HW_FREEQ_DESC_NUM/4;
67 threshold.bits.toe_class = (TOE_TOE_DESC_NUM > 256) ? 256/4 :
68 @@ -613,18 +618,25 @@
69 rwptr_reg.bits.rptr = 0;
70 toe->fq_rx_rwptr.bits32 = rwptr_reg.bits32;
71 writel(rwptr_reg.bits32, TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
72 + printk("SWFQ: %08X\n", readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG));
73
74 // SW Free Queue Descriptors
75 for (i=0; i<TOE_SW_FREEQ_DESC_NUM; i++)
76 {
77 + void *data = NULL;
78 sw_desc_ptr->word0.bits.buffer_size = SW_RX_BUF_SIZE;
79 - sw_desc_ptr->word1.bits.sw_id = i; // used to locate skb
80 + sw_desc_ptr->word1.bits.sw_id = 0; // used to locate skb
81 if ( (skb = dev_alloc_skb(SW_RX_BUF_SIZE))==NULL) /* allocate socket buffer */
82 {
83 printk("%s::skb buffer allocation fail !\n",__func__); while(1);
84 }
85 - REG32(skb->data) = (unsigned int)skb;
86 +
87 + data = skb->data;
88 skb_reserve(skb, SKB_RESERVE_BYTES);
89 +
90 + REG32(data + 0) = (unsigned int)skb;
91 + REG32(data + 4) = (unsigned short)i;
92 +
93 // toe->rx_skb[i] = skb;
94 sw_desc_ptr->word2.buf_adr = (unsigned int)__pa(skb->data);
95 // consistent_sync((unsigned int)desc_ptr, sizeof(GMAC_RXDESC_T), PCI_DMA_TODEVICE);
96 @@ -851,14 +863,14 @@
97 *----------------------------------------------------------------------*/
98 static void toe_init_default_queue(void)
99 {
100 - TOE_INFO_T *toe;
101 + TOE_INFO_T *toe;
102 volatile NONTOE_QHDR_T *qhdr;
103 - GMAC_RXDESC_T *desc_ptr;
104 - DMA_SKB_SIZE_T skb_size;
105 + GMAC_RXDESC_T *desc_ptr;
106 + DMA_SKB_SIZE_T skb_size;
107
108 toe = (TOE_INFO_T *)&toe_private_data;
109 desc_ptr = (GMAC_RXDESC_T *)DMA_MALLOC((TOE_DEFAULT_Q0_DESC_NUM * sizeof(GMAC_RXDESC_T)),
110 - (dma_addr_t *)&toe->gmac[0].default_desc_base_dma);
111 + (dma_addr_t *)&toe->gmac[0].default_desc_base_dma);
112 if (!desc_ptr)
113 {
114 printk("%s::DMA_MALLOC fail !\n",__func__);
115 @@ -866,14 +878,17 @@
116 }
117 memset((void *)desc_ptr, 0, TOE_DEFAULT_Q0_DESC_NUM * sizeof(GMAC_RXDESC_T));
118 toe->gmac[0].default_desc_base = (unsigned int)desc_ptr;
119 + printk("toe->gmac[0].default_desc_base_dma: %08X\n", toe->gmac[0].default_desc_base_dma);
120 +
121 toe->gmac[0].default_desc_num = TOE_DEFAULT_Q0_DESC_NUM;
122 qhdr = (volatile NONTOE_QHDR_T *)TOE_DEFAULT_Q0_HDR_BASE;
123 qhdr->word0.base_size = ((unsigned int)toe->gmac[0].default_desc_base_dma & NONTOE_QHDR0_BASE_MASK) | TOE_DEFAULT_Q0_DESC_POWER;
124 qhdr->word1.bits32 = 0;
125 toe->gmac[0].rx_rwptr.bits32 = 0;
126 toe->gmac[0].default_qhdr = (NONTOE_QHDR_T *)qhdr;
127 +
128 desc_ptr = (GMAC_RXDESC_T *)DMA_MALLOC((TOE_DEFAULT_Q1_DESC_NUM * sizeof(GMAC_RXDESC_T)),
129 - (dma_addr_t *)&toe->gmac[1].default_desc_base_dma);
130 + (dma_addr_t *)&toe->gmac[1].default_desc_base_dma);
131 if (!desc_ptr)
132 {
133 printk("%s::DMA_MALLOC fail !\n",__func__);
134 @@ -1071,12 +1086,16 @@
135
136 data = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_0_REG) & ~tp->intr0_selected;
137 writel(data, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_0_REG);
138 +
139 data = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_1_REG) & ~tp->intr1_selected;
140 writel(data, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_1_REG);
141 +
142 data = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_2_REG) & ~tp->intr2_selected;
143 writel(data, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_2_REG);
144 +
145 data = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_3_REG) & ~tp->intr3_selected;
146 writel(data, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_3_REG);
147 +
148 data = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG) & ~tp->intr4_selected;
149 writel(data, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG);
150 }
151 @@ -1176,11 +1195,11 @@
152 GMAC_CONFIG2_T config2_val;
153 GMAC_CONFIG0_T config0,config0_mask;
154 GMAC_CONFIG1_T config1;
155 - #ifdef CONFIG_SL351x_NAT
156 GMAC_CONFIG3_T config3_val;
157 - #endif
158 GMAC_TX_WCR0_T hw_weigh;
159 GMAC_TX_WCR1_T sw_weigh;
160 +
161 + uint32_t weight = 0;
162 // GMAC_HASH_ENABLE_REG0_T hash_ctrl;
163 //
164 #if 0 /* mac address will be set in late_initcall */
165 @@ -1202,24 +1221,23 @@
166 // config1.bits32 = 0x002004; //next version
167 /* set flow control threshold */
168 config1.bits32 = 0;
169 - config1.bits.set_threshold = 32 / 2;
170 - config1.bits.rel_threshold = 32 / 4 * 3;
171 + config1.bits.set_threshold = (32 / 2);
172 + config1.bits.rel_threshold = (32 / 4) * 3;
173 gmac_write_reg(tp->base_addr, GMAC_CONFIG1, config1.bits32, 0xffffffff);
174
175 - /* set flow control threshold */
176 + /* TODO: set flow control threshold */
177 config2_val.bits32 = 0;
178 - config2_val.bits.set_threshold = TOE_SW_FREEQ_DESC_NUM/2;
179 - config2_val.bits.rel_threshold = TOE_SW_FREEQ_DESC_NUM*3/4;
180 + config2_val.bits.set_threshold = TOE_SW_FREEQ_DESC_NUM/4;
181 + config2_val.bits.rel_threshold = TOE_SW_FREEQ_DESC_NUM/2;
182 gmac_write_reg(tp->base_addr, GMAC_CONFIG2, config2_val.bits32,0xffffffff);
183
184 - #ifdef CONFIG_SL351x_NAT
185 - /* set HW free queue flow control threshold */
186 + /* TODO: set HW free queue flow control threshold */
187 config3_val.bits32 = 0;
188 config3_val.bits.set_threshold = PAUSE_SET_HW_FREEQ;
189 config3_val.bits.rel_threshold = PAUSE_REL_HW_FREEQ;
190 gmac_write_reg(tp->base_addr, GMAC_CONFIG3, config3_val.bits32,0xffffffff);
191 - #endif
192 - /* set_mcast_filter mask*/
193 +
194 + /* TODO: set_mcast_filter mask*/
195 // gmac_write_reg(tp->base_addr,GMAC_MCAST_FIL0,0x0,0xffffffff);
196 // gmac_write_reg(tp->base_addr,GMAC_MCAST_FIL1,0x0,0xffffffff);
197
198 @@ -1249,7 +1267,7 @@
199 config0.bits.dis_rx = 1; /* disable rx */
200 config0.bits.dis_tx = 1; /* disable tx */
201 config0.bits.loop_back = 0; /* enable/disable GMAC loopback */
202 - config0.bits.rx_err_detect = 1;
203 + config0.bits.rx_err_detect = 1; /* TODO: was 1, means disabled, 0 enabled ! */
204 config0.bits.rgmii_en = 0;
205 config0.bits.rgmm_edge = 1;
206 config0.bits.rxc_inv = 0;
207 @@ -1342,6 +1360,9 @@
208 gmac_write_reg(tp->dma_base_addr, GMAC_AHB_WEIGHT_REG, ahb_weight.bits32, ahb_weight_mask.bits32);
209 #endif
210
211 + weight = gmac_read_reg(tp->dma_base_addr, GMAC_AHB_WEIGHT_REG);
212 + printk("====> %08X\n", weight);
213 +
214 #if defined(CONFIG_SL351x_NAT) || defined(CONFIG_SL351x_RXTOE)
215 gmac_write_reg(tp->dma_base_addr, GMAC_SPR0, IPPROTO_TCP, 0xffffffff);
216 #endif
217 @@ -1552,7 +1573,7 @@
218 rwptr.bits32 = readl(swtxq->rwptr_reg);
219 if (rwptr.bits.rptr == swtxq->finished_idx)
220 break;
221 - curr_desc = (volatile GMAC_TXDESC_T *)swtxq->desc_base + swtxq->finished_idx;
222 + curr_desc = (volatile GMAC_TXDESC_T *)swtxq->desc_base + swtxq->finished_idx;
223 // consistent_sync((void *)curr_desc, sizeof(GMAC_TXDESC_T), PCI_DMA_FROMDEVICE);
224 word0.bits32 = curr_desc->word0.bits32;
225 word1.bits32 = curr_desc->word1.bits32;
226 @@ -1573,6 +1594,7 @@
227 swtxq->finished_idx = RWPTR_ADVANCE_ONE(swtxq->finished_idx, swtxq->total_desc_num);
228 curr_desc = (GMAC_TXDESC_T *)swtxq->desc_base + swtxq->finished_idx;
229 word0.bits32 = curr_desc->word0.bits32;
230 +
231 #ifdef _DUMP_TX_TCP_CONTENT
232 if (curr_desc->word0.bits.buffer_size < 16)
233 {
234 @@ -1592,12 +1614,12 @@
235 word0.bits.status_tx_ok = 0;
236 if (swtxq->tx_skb[swtxq->finished_idx])
237 {
238 - if (interrupt)
239 - dev_kfree_skb_irq(swtxq->tx_skb[swtxq->finished_idx]);
240 - else
241 - dev_kfree_skb(swtxq->tx_skb[swtxq->finished_idx]);
242 + dev_kfree_skb(swtxq->tx_skb[swtxq->finished_idx]);
243 swtxq->tx_skb[swtxq->finished_idx] = NULL;
244 + } else {
245 + BUG();
246 }
247 +
248 curr_desc->word0.bits32 = word0.bits32;
249 swtxq->curr_finished_desc = (GMAC_TXDESC_T *)curr_desc;
250 swtxq->total_finished++;
251 @@ -1624,31 +1646,29 @@
252 *----------------------------------------------------------------------*/
253 static int gmac_start_xmit(struct sk_buff *skb, struct net_device *dev)
254 {
255 - GMAC_INFO_T *tp= dev->priv;
256 -// static unsigned int pcount = 0;
257 -// unsigned int tx_qid;
258 - DMA_RWPTR_T rwptr;
259 - volatile GMAC_TXDESC_T *curr_desc;
260 - int snd_pages = skb_shinfo(skb)->nr_frags + 1; /* get number of descriptor */
261 - int frag_id = 0;
262 - int len, total_len = skb->len;
263 + GMAC_INFO_T *tp= dev->priv;
264 + DMA_RWPTR_T rwptr;
265 + GMAC_TXDESC_T *curr_desc;
266 + int snd_pages = skb_shinfo(skb)->nr_frags + 1; /* get number of descriptor */
267 + int frag_id = 0;
268 + int len, total_len = skb->len;
269 struct net_device_stats *isPtr;
270 - unsigned int free_desc;
271 - GMAC_SWTXQ_T *swtxq;
272 + unsigned int free_desc;
273 + GMAC_SWTXQ_T *swtxq;
274 register unsigned long word0, word1, word2, word3;
275 unsigned short wptr, rptr;
276 #ifdef L2_jumbo_frame
277 int header_len = skb->len;
278 struct iphdr *ip_hdr;
279 - struct tcphdr *tcp_hdr;
280 - int tcp_hdr_len;
281 - unsigned char *ptr;
282 - int data_len,a;
283 - unsigned int val;
284 + struct tcphdr *tcp_hdr;
285 + int tcp_hdr_len;
286 + unsigned char *ptr;
287 + int data_len,a;
288 + unsigned int val;
289 #endif
290
291 #ifdef GMAC_LEN_1_2_ISSUE
292 - int total_pages;
293 + int total_pages;
294 total_pages = snd_pages;
295 #endif
296
297 @@ -1664,13 +1684,6 @@
298 }
299 #endif
300
301 -#if 0
302 - if (storlink_ctl.recvfile==2)
303 - {
304 - printk("snd_pages=%d skb->len=%d\n",snd_pages,skb->len);
305 - }
306 -#endif
307 -
308 #ifdef GMAC_USE_TXQ0
309 #define tx_qid 0
310 #endif
311 @@ -1703,9 +1716,9 @@
312 toe_gmac_tx_complete(tp, tx_qid, dev, 0);
313
314 if (wptr >= swtxq->finished_idx)
315 - free_desc = swtxq->total_desc_num - wptr - 1 + swtxq->finished_idx;
316 + free_desc = swtxq->total_desc_num - wptr + swtxq->finished_idx;
317 else
318 - free_desc = swtxq->finished_idx - wptr - 1;
319 + free_desc = swtxq->finished_idx - wptr;
320 if (free_desc < snd_pages)
321 {
322 // spin_unlock(&tp->tx_mutex);
323 @@ -2063,9 +2076,10 @@
324 struct net_device_stats * gmac_get_stats(struct net_device *dev)
325 {
326 GMAC_INFO_T *tp = (GMAC_INFO_T *)dev->priv;
327 +#if 0 /* don't read stats from hardware, scary numbers. */
328 // unsigned int flags;
329 - unsigned int pkt_drop;
330 - unsigned int pkt_error;
331 + unsigned int pkt_drop = 0;
332 + unsigned int pkt_error = 0;
333
334 if (netif_running(dev))
335 {
336 @@ -2073,10 +2087,14 @@
337 // spin_lock_irqsave(&tp->lock,flags);
338 pkt_drop = gmac_read_reg(tp->base_addr,GMAC_IN_DISCARDS);
339 pkt_error = gmac_read_reg(tp->base_addr,GMAC_IN_ERRORS);
340 + printk("**** stack: %lu, hw: %lu\n", tp->ifStatics.rx_dropped, pkt_drop);
341 +
342 tp->ifStatics.rx_dropped = tp->ifStatics.rx_dropped + pkt_drop;
343 tp->ifStatics.rx_errors = tp->ifStatics.rx_errors + pkt_error;
344 // spin_unlock_irqrestore(&tp->lock,flags);
345 }
346 +#endif
347 +
348 return &tp->ifStatics;
349 }
350
351 @@ -2401,36 +2419,63 @@
352 * toe_gmac_fill_free_q
353 * allocate buffers for free queue.
354 *----------------------------------------------------------------------*/
355 -static inline void toe_gmac_fill_free_q(void)
356 +static inline void toe_gmac_fill_free_q(int count)
357 {
358 struct sk_buff *skb;
359 volatile DMA_RWPTR_T fq_rwptr;
360 volatile GMAC_RXDESC_T *fq_desc;
361 - unsigned long flags;
362 + unsigned long flags;
363 + unsigned short index;
364 + int filled = 0;
365 + static int entered;
366 // unsigned short max_cnt=TOE_SW_FREEQ_DESC_NUM>>1;
367
368 + BUG_ON(entered == 1);
369 +
370 + entered = 1;
371 +
372 +
373 fq_rwptr.bits32 = readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
374 // spin_lock_irqsave(&gmac_fq_lock, flags);
375 //while ((max_cnt--) && (unsigned short)RWPTR_ADVANCE_ONE(fq_rwptr.bits.wptr,
376 // TOE_SW_FREEQ_DESC_NUM) != fq_rwptr.bits.rptr) {
377 - while ((unsigned short)RWPTR_ADVANCE_ONE(fq_rwptr.bits.wptr,
378 - TOE_SW_FREEQ_DESC_NUM) != fq_rwptr.bits.rptr) {
379 + index = fq_rwptr.bits.wptr;
380 +#if 0
381 + printk("wptr: %hu, rptr: %hu, refill idx: %hu\n",
382 + GET_RPTR(fq_rwptr.bits32),
383 + GET_WPTR(fq_rwptr.bits32),
384 + index);
385 +#endif
386 +
387 + index = RWPTR_ADVANCE_ONE(index, TOE_SW_FREEQ_DESC_NUM);
388 + fq_desc = (GMAC_RXDESC_T*)toe_private_data.swfq_desc_base + index;
389 + while (fq_desc->word2.buf_adr == 0) {
390 + void *data = NULL;
391 +
392 if ((skb = dev_alloc_skb(SW_RX_BUF_SIZE)) == NULL) {
393 printk("%s::skb allocation fail!\n", __func__);
394 - //while(1);
395 - break;
396 + goto out;
397 }
398 - REG32(skb->data) = (unsigned int)skb;
399 + ++ filled;
400 + data = skb->data;
401 skb_reserve(skb, SKB_RESERVE_BYTES);
402 - // fq_rwptr.bits32 = readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
403 - fq_rwptr.bits.wptr = RWPTR_ADVANCE_ONE(fq_rwptr.bits.wptr,
404 - TOE_SW_FREEQ_DESC_NUM);
405 - fq_desc = (GMAC_RXDESC_T*)toe_private_data.swfq_desc_base+fq_rwptr.bits.wptr;
406 +
407 + REG32(data + 0) = (unsigned int)skb;
408 + REG32(data + 4) = (unsigned short)index;
409 +
410 + // printk("refill skb: %p, idx: %hu\n", skb, index);
411 fq_desc->word2.buf_adr = (unsigned int)__pa(skb->data);
412 - SET_WPTR(TOE_GLOBAL_BASE+GLOBAL_SWFQ_RWPTR_REG, fq_rwptr.bits.wptr);
413 - toe_private_data.fq_rx_rwptr.bits32 = fq_rwptr.bits32;
414 + writel(0x07960202, TOE_GMAC0_BASE+GMAC_CONFIG0);
415 + SET_WPTR(TOE_GLOBAL_BASE+GLOBAL_SWFQ_RWPTR_REG, index);
416 + writel(0x07960200, TOE_GMAC0_BASE+GMAC_CONFIG0);
417 +
418 + index = RWPTR_ADVANCE_ONE(index, TOE_SW_FREEQ_DESC_NUM);
419 + fq_desc = (GMAC_RXDESC_T*)toe_private_data.swfq_desc_base+index;
420 }
421 +out:
422 // spin_unlock_irqrestore(&gmac_fq_lock, flags);
423 +
424 + entered = 0;
425 }
426 // EXPORT_SYMBOL(toe_gmac_fill_free_q);
427
428 @@ -2442,14 +2487,14 @@
429 unsigned int status3;
430 unsigned int status4;
431
432 - printk("%s\n", message);
433 -
434 status0 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_0_REG);
435 status1 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_1_REG);
436 status2 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_2_REG);
437 status3 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_3_REG);
438 status4 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_4_REG);
439
440 + printk("%s\n", message);
441 +
442 printk("status: s0:%08X, s1:%08X, s2:%08X, s3:%08X, s4:%08X\n",
443 status0, status1, status2, status3, status4);
444
445 @@ -2468,8 +2513,9 @@
446 status3 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_3_REG);
447 status4 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG);
448
449 - printk("select: s0:%08X, s1:%08X, s2:%08X, s3:%08X, s4:%08X\n",
450 - status0, status1, status2, status3, status4);
451 + if (status0 || status1 || status2 || status3 || status4)
452 + printk("select: s0:%08X, s1:%08X, s2:%08X, s3:%08X, s4:%08X\n",
453 + status0, status1, status2, status3, status4);
454 }
455 /*----------------------------------------------------------------------
456 * toe_gmac_interrupt
457 @@ -2485,75 +2531,44 @@
458 unsigned int status3;
459 unsigned int status4;
460
461 -// struct net_device_stats *isPtr = (struct net_device_stats *)&tp->ifStatics;
462 toe = (TOE_INFO_T *)&toe_private_data;
463 -// handle NAPI
464 -#ifdef CONFIG_SL_NAPI
465 - /* XXX: check this, changed from 'storlink_ctl.pauseoff == 1' to if (1) */
466 -if (1)
467 -{
468 -/* disable GMAC interrupt */
469 - //toe_gmac_disable_interrupt(tp->irq);
470
471 -// isPtr->interrupts++;
472 + if (0 && rx_poll_enabled) {
473 + gmac_registers("interrupt handler");
474 + }
475 +
476 /* read Interrupt status */
477 status0 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_0_REG);
478 status1 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_1_REG);
479 status2 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_2_REG);
480 status3 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_3_REG);
481 status4 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_4_REG);
482 - // prompt warning if status bit ON but not enabled
483 +
484 #if 0
485 - if (status0 & ~tp->intr0_enabled)
486 - printk("Intr 0 Status error. status = 0x%X, enable = 0x%X\n",
487 - status0, tp->intr0_enabled);
488 - if (status1 & ~tp->intr1_enabled)
489 - printk("Intr 1 Status error. status = 0x%X, enable = 0x%X\n",
490 - status1, tp->intr1_enabled);
491 - if (status2 & ~tp->intr2_enabled)
492 - printk("Intr 2 Status error. status = 0x%X, enable = 0x%X\n",
493 - status2, tp->intr2_enabled);
494 - if (status3 & ~tp->intr3_enabled)
495 - printk("Intr 3 Status error. status = 0x%X, enable = 0x%X\n",
496 - status3, tp->intr3_enabled);
497 - if (status4 & ~tp->intr4_enabled)
498 - printk("Intr 4 Status error. status = 0x%X, enable = 0x%X\n",
499 - status4, tp->intr4_enabled);
500 + /* handle freeq interrupt first */
501 + if (status4 & SWFQ_EMPTY_INT_BIT)
502 + {
503 + toe_gmac_fill_free_q();
504 + writel(status4 & SWFQ_EMPTY_INT_BIT, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_4_REG);
505 + tp->sw_fq_empty_cnt++;
506 + }
507 #endif
508
509 + if (status4 & GMAC0_MIB_INT_BIT)
510 + writel(GMAC0_MIB_INT_BIT, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_4_REG);
511 +
512 + if (status4 & GMAC0_RX_OVERRUN_INT_BIT)
513 + writel(GMAC0_RX_OVERRUN_INT_BIT, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_4_REG);
514 +
515 if (status0)
516 writel(status0 & tp->intr0_enabled, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_0_REG);
517 - if (status1)
518 - writel(status1 & tp->intr1_enabled, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_1_REG);
519 if (status2)
520 writel(status2 & tp->intr2_enabled, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_2_REG);
521 if (status3)
522 writel(status3 & tp->intr3_enabled, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_3_REG);
523 - if (status4)
524 - writel(status4 & tp->intr4_enabled, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_4_REG);
525 -
526 -#if 0
527 - /* handle freeq interrupt first */
528 - if (status4 & tp->intr4_enabled) {
529 - if ((status4 & SWFQ_EMPTY_INT_BIT) && (tp->intr4_enabled & SWFQ_EMPTY_INT_BIT))
530 - {
531 - // unsigned long data = REG32(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
532 - //gmac_write_reg(TOE_GLOBAL_BASE, GLOBAL_INTERRUPT_ENABLE_4_REG,
533 - // tp->intr4_enabled & ~SWFQ_EMPTY_INT_BIT, SWFQ_EMPTY_INT_BIT);
534 -
535 - if (toe->gmac[0].dev && netif_running(toe->gmac[0].dev))
536 - toe_gmac_handle_default_rxq(toe->gmac[0].dev,&toe->gmac[0]);
537 - if (toe->gmac[1].dev && netif_running(toe->gmac[1].dev))
538 - toe_gmac_handle_default_rxq(toe->gmac[1].dev,&toe->gmac[1]);
539 - printk("\nfreeq int\n");
540 - toe_gmac_fill_free_q();
541 - tp->sw_fq_empty_cnt++;
542
543 - }
544 - }
545 -#endif
546 // Interrupt Status 1
547 - if (status1 & tp->intr1_enabled)
548 + if ((status1 & 3) || (status4 & 1))
549 {
550 #define G1_INTR0_BITS (GMAC1_HWTQ13_EOF_INT_BIT | GMAC1_HWTQ12_EOF_INT_BIT | GMAC1_HWTQ11_EOF_INT_BIT | GMAC1_HWTQ10_EOF_INT_BIT)
551 #define G0_INTR0_BITS (GMAC0_HWTQ03_EOF_INT_BIT | GMAC0_HWTQ02_EOF_INT_BIT | GMAC0_HWTQ01_EOF_INT_BIT | GMAC0_HWTQ00_EOF_INT_BIT)
552 @@ -2563,7 +2578,7 @@
553 // because they should pass packets to upper layer
554 if (tp->port_id == 0)
555 {
556 - if (netif_running(dev) && (status1 & G0_INTR0_BITS) && (tp->intr1_enabled & G0_INTR0_BITS))
557 + if (((status1 & G0_INTR0_BITS) && (tp->intr1_enabled & G0_INTR0_BITS)) || (status4 & 1))
558 {
559 if (status1 & GMAC0_HWTQ03_EOF_INT_BIT)
560 tp->hwtxq[3].eof_cnt++;
561 @@ -2574,50 +2589,51 @@
562 if (status1 & GMAC0_HWTQ00_EOF_INT_BIT)
563 tp->hwtxq[0].eof_cnt++;
564 }
565 - if (netif_running(dev) && (status1 & DEFAULT_Q0_INT_BIT) && (tp->intr1_enabled & DEFAULT_Q0_INT_BIT))
566 + if (status1 & DEFAULT_Q0_INT_BIT || status4 & 1)
567 + {
568 + if (likely(netif_rx_schedule_prep(dev)))
569 {
570 - if (!rx_poll_enabled && likely(netif_rx_schedule_prep(dev)))
571 - {
572 - unsigned int data32;
573 + unsigned int data32;
574 +
575 + BUG_ON(rx_poll_enabled == 1);
576
577 - if (rx_poll_enabled)
578 - gmac_registers("check #1");
579 + /* Masks GMAC-0 rx interrupt */
580 + data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
581 + data32 &= ~(DEFAULT_Q0_INT_BIT);
582 + writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
583
584 - BUG_ON(rx_poll_enabled == 1);
585 + /* Masks GMAC-0 queue empty interrupt */
586 + data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_4_REG);
587 + data32 &= ~DEFAULT_Q0_INT_BIT;
588 + writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_4_REG);
589
590 + __netif_rx_schedule(dev);
591 + rx_poll_enabled = 1;
592 + } else {
593 #if 0
594 - /* Masks GMAC-0 rx interrupt */
595 - data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
596 - data32 &= ~(DEFAULT_Q0_INT_BIT);
597 - writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
598 -
599 - /* Masks GMAC-0 queue empty interrupt */
600 - data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_4_REG);
601 - data32 &= ~DEFAULT_Q0_INT_BIT;
602 - writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_4_REG);
603 -
604 - data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG);
605 - data32 &= ~DEFAULT_Q0_INT_BIT;
606 - writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG);
607 -#endif
608 -
609 - // class-Q & TOE-Q are implemented in future
610 - //data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
611 - //data32 &= ~DEFAULT_Q0_INT_BIT;
612 - //writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
613 - //printk("\%s: DEFAULT_Q0_INT_BIT===================>>>>>>>>>>>>\n",__func__);
614 - writel(0x0, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_ENABLE_1_REG);
615 - //tp->total_q_cnt_napi=0;
616 - //rx_time = jiffies;
617 - //rx_old_bytes = isPtr->rx_bytes;
618 - __netif_rx_schedule(dev);
619 - rx_poll_enabled = 1;
620 - }
621 + unsigned int data32;
622 +
623 + if (rx_poll_enabled)
624 + gmac_registers("->poll() running.");
625 + /* Masks GMAC-0 rx interrupt */
626 + data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
627 + data32 &= ~(DEFAULT_Q0_INT_BIT);
628 + writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
629 +
630 + /* Masks GMAC-0 queue empty interrupt */
631 + data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_4_REG);
632 + data32 &= ~DEFAULT_Q0_INT_BIT;
633 + writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_4_REG);
634 +#endif
635 + }
636 + } else {
637 + if (0)
638 + gmac_registers("status1 & DEFAULT_Q0_INT_BIT || status4 & 1");
639 }
640 }
641 - else if (tp->port_id == 1)
642 + else if (tp->port_id == 1 && netif_running(dev))
643 {
644 - if (netif_running(dev) && (status1 & G1_INTR0_BITS) && (tp->intr1_enabled & G1_INTR0_BITS))
645 + if ((status1 & G1_INTR0_BITS) && (tp->intr1_enabled & G1_INTR0_BITS))
646 {
647 if (status1 & GMAC1_HWTQ13_EOF_INT_BIT)
648 tp->hwtxq[3].eof_cnt++;
649 @@ -2629,14 +2645,14 @@
650 tp->hwtxq[0].eof_cnt++;
651 }
652
653 - if (netif_running(dev) && (status1 & DEFAULT_Q1_INT_BIT) && (tp->intr1_enabled & DEFAULT_Q1_INT_BIT))
654 + if ((status1 & DEFAULT_Q1_INT_BIT) && (tp->intr1_enabled & DEFAULT_Q1_INT_BIT))
655 {
656 if (!rx_poll_enabled && likely(netif_rx_schedule_prep(dev)))
657 - {
658 - unsigned int data32;
659 + {
660 + unsigned int data32;
661
662 if (rx_poll_enabled)
663 - gmac_registers("check #2");
664 + gmac_registers("check #2");
665
666 BUG_ON(rx_poll_enabled == 1);
667
668 @@ -2646,7 +2662,7 @@
669 data32 &= ~(DEFAULT_Q1_INT_BIT);
670 writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
671
672 - /* Masks GMAC-1 queue empty interrupt */
673 + /* Masks GMAC-1 queue empty interrupt */
674 data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_4_REG);
675 data32 &= ~DEFAULT_Q1_INT_BIT;
676 writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_4_REG);
677 @@ -2656,24 +2672,21 @@
678 writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG);
679 #endif
680
681 - // disable GMAC-0 rx interrupt
682 - // class-Q & TOE-Q are implemented in future
683 - //data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
684 - //data32 &= ~DEFAULT_Q1_INT_BIT;
685 + // disable GMAC-0 rx interrupt
686 + // class-Q & TOE-Q are implemented in future
687 + //data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
688 + //data32 &= ~DEFAULT_Q1_INT_BIT;
689 //writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
690 //printk("\%s: 1111111111--->DEFAULT_Q1_INT_BIT===================>>>>>>>>>>>>\n",__func__);
691 writel(0x0, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_ENABLE_1_REG);
692 //tp->total_q_cnt_napi=0;
693 //rx_time = jiffies;
694 //rx_old_bytes = isPtr->rx_bytes;
695 - __netif_rx_schedule(dev);
696 - rx_poll_enabled = 1;
697 - }
698 + __netif_rx_schedule(dev);
699 + rx_poll_enabled = 1;
700 + }
701 }
702 }
703 - } else {
704 -
705 - gmac_registers("check #3");
706 }
707
708 // Interrupt Status 0
709 @@ -2814,676 +2827,93 @@
710 }
711 }
712
713 - //toe_gmac_enable_interrupt(tp->irq);
714 -#ifdef IxscriptMate_1518
715 - if (storlink_ctl.pauseoff == 1)
716 - {
717 - GMAC_CONFIG0_T config0;
718 - config0.bits32 = readl(TOE_GMAC0_BASE+GMAC_CONFIG0);
719 - config0.bits.dis_rx = 0;
720 - writel(config0.bits32, TOE_GMAC0_BASE+GMAC_CONFIG0);
721 - config0.bits32 = readl(TOE_GMAC1_BASE+GMAC_CONFIG0);
722 - config0.bits.dis_rx = 0;
723 - writel(config0.bits32, TOE_GMAC1_BASE+GMAC_CONFIG0);
724 - }
725 -#endif
726 -// enable_irq(gmac_irq[dev_index]);
727 - //printk("gmac_interrupt complete!\n\n");
728 -// return IRQ_RETVAL(handled);
729 return IRQ_RETVAL(1);
730 }
731 -else
732 -{
733 -#endif //endif NAPI
734
735 +/*----------------------------------------------------------------------
736 +* gmac_get_phy_vendor
737 +*----------------------------------------------------------------------*/
738 +static unsigned int gmac_get_phy_vendor(int phy_addr)
739 +{
740 + unsigned int reg_val;
741 + reg_val=(mii_read(phy_addr,0x02) << 16) + mii_read(phy_addr,0x03);
742 + return reg_val;
743 +}
744
745 - /* disable GMAC interrupt */
746 - toe_gmac_disable_interrupt(tp->irq);
747 +/*----------------------------------------------------------------------
748 +* gmac_set_phy_status
749 +*----------------------------------------------------------------------*/
750 +void gmac_set_phy_status(struct net_device *dev)
751 +{
752 + GMAC_INFO_T *tp = dev->priv;
753 + GMAC_STATUS_T status;
754 + unsigned int reg_val, ability,wan_port_id;
755 + unsigned int i = 0;
756
757 -// isPtr->interrupts++;
758 - /* read Interrupt status */
759 - status0 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_0_REG);
760 - status1 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_1_REG);
761 - status2 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_2_REG);
762 - status3 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_3_REG);
763 - status4 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_4_REG);
764 - // prompt warning if status bit ON but not enabled
765 +#ifdef VITESSE_G5SWITCH
766 + if((tp->port_id == GMAC_PORT1)&&(Giga_switch==1)){
767 #if 0
768 - if (status0 & ~tp->intr0_enabled)
769 - printk("Intr 0 Status error. status = 0x%X, enable = 0x%X\n",
770 - status0, tp->intr0_enabled);
771 - if (status1 & ~tp->intr1_enabled)
772 - printk("Intr 1 Status error. status = 0x%X, enable = 0x%X\n",
773 - status1, tp->intr1_enabled);
774 - if (status2 & ~tp->intr2_enabled)
775 - printk("Intr 2 Status error. status = 0x%X, enable = 0x%X\n",
776 - status2, tp->intr2_enabled);
777 - if (status3 & ~tp->intr3_enabled)
778 - printk("Intr 3 Status error. status = 0x%X, enable = 0x%X\n",
779 - status3, tp->intr3_enabled);
780 - if (status4 & ~tp->intr4_enabled)
781 - printk("Intr 4 Status error. status = 0x%X, enable = 0x%X\n",
782 - status4, tp->intr4_enabled);
783 -#endif
784 -#define INTERRUPT_SELECT 1
785 - if (status0)
786 - writel(status0 & tp->intr0_enabled, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_0_REG);
787 - if (status1)
788 - writel(status1 & tp->intr1_enabled, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_1_REG);
789 - if (status2)
790 - writel(status2 & tp->intr2_enabled, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_2_REG);
791 - if (status3)
792 - writel(status3 & tp->intr3_enabled, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_3_REG);
793 - if (status4)
794 - writel(status4 & tp->intr4_enabled, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_4_REG);
795 -
796 - /* handle freeq interrupt first */
797 - if (status4 & tp->intr4_enabled) {
798 - if ((status4 & SWFQ_EMPTY_INT_BIT) && (tp->intr4_enabled & SWFQ_EMPTY_INT_BIT))
799 - {
800 - // unsigned long data = REG32(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
801 - //gmac_write_reg(TOE_GLOBAL_BASE, GLOBAL_INTERRUPT_ENABLE_4_REG,
802 - // tp->intr4_enabled & ~SWFQ_EMPTY_INT_BIT, SWFQ_EMPTY_INT_BIT);
803 -
804 - //gmac_write_reg(TOE_GLOBAL_BASE, GLOBAL_INTERRUPT_STATUS_4_REG,
805 - // SWFQ_EMPTY_INT_BIT, SWFQ_EMPTY_INT_BIT);
806 - if (toe->gmac[0].dev && netif_running(toe->gmac[0].dev))
807 - toe_gmac_handle_default_rxq(toe->gmac[0].dev,&toe->gmac[0]);
808 - if (toe->gmac[1].dev && netif_running(toe->gmac[1].dev))
809 - toe_gmac_handle_default_rxq(toe->gmac[1].dev,&toe->gmac[1]);
810 - printk("\nfreeq int\n");
811 - toe_gmac_fill_free_q();
812 - tp->sw_fq_empty_cnt++;
813 -
814 - gmac_write_reg(TOE_GLOBAL_BASE, GLOBAL_INTERRUPT_STATUS_4_REG, status4,
815 - SWFQ_EMPTY_INT_BIT);
816 - }
817 - }
818 -
819 - // Interrupt Status 1
820 - if (status1 & tp->intr1_enabled)
821 - {
822 - #define G1_INTR0_BITS (GMAC1_HWTQ13_EOF_INT_BIT | GMAC1_HWTQ12_EOF_INT_BIT | GMAC1_HWTQ11_EOF_INT_BIT | GMAC1_HWTQ10_EOF_INT_BIT)
823 - #define G0_INTR0_BITS (GMAC0_HWTQ03_EOF_INT_BIT | GMAC0_HWTQ02_EOF_INT_BIT | GMAC0_HWTQ01_EOF_INT_BIT | GMAC0_HWTQ00_EOF_INT_BIT)
824 - // Handle GMAC 0/1 HW Tx queue 0-3 EOF events
825 - // Only count
826 - // TOE, Classification, and default queues interrupts are handled by ISR
827 - // because they should pass packets to upper layer
828 - if (tp->port_id == 0)
829 - {
830 -#ifndef INTERRUPT_SELECT
831 - if (netif_running(dev) && (status1 & G0_INTR0_BITS) && (tp->intr1_enabled & G0_INTR0_BITS))
832 - {
833 - if (status1 & GMAC0_HWTQ03_EOF_INT_BIT)
834 - tp->hwtxq[3].eof_cnt++;
835 - if (status1 & GMAC0_HWTQ02_EOF_INT_BIT)
836 - tp->hwtxq[2].eof_cnt++;
837 - if (status1 & GMAC0_HWTQ01_EOF_INT_BIT)
838 - tp->hwtxq[1].eof_cnt++;
839 - if (status1 & GMAC0_HWTQ00_EOF_INT_BIT)
840 - tp->hwtxq[0].eof_cnt++;
841 -#endif //INTERRUPT_SELECT
842 -#ifndef INTERRUPT_SELECT
843 - }
844 -#endif //INTERRUPT_SELECT
845 - if (netif_running(dev) && (status1 & DEFAULT_Q0_INT_BIT) && (tp->intr1_enabled & DEFAULT_Q0_INT_BIT))
846 - {
847 - tp->default_q_intr_cnt++;
848 - toe_gmac_handle_default_rxq(dev, tp);
849 + rcv_mask = SPI_read(2,0,0x10); // Receive mask
850 + rcv_mask |= 0x4F;
851 + for(i=0;i<4;i++){
852 + reg_val = BIT(26)|(i<<21)|(10<<16);
853 + SPI_write(3,0,1,reg_val);
854 + msleep(10);
855 + reg_val = SPI_read(3,0,2);
856 + if(reg_val & 0x0c00){
857 + printk("Port%d:Giga mode\n",i);
858 + SPI_write(1,i,0x00,0x300701B1);
859 + SPI_write(1,i,0x00,0x10070181);
860 + switch_pre_link[i]=LINK_UP;
861 + switch_pre_speed[i]=GMAC_SPEED_1000;
862 }
863 -#ifdef CONFIG_SL351x_RXTOE
864 - if (netif_running(dev) && (status1 & TOE_IQ_ALL_BITS) &&
865 - (tp->intr1_enabled & TOE_IQ_ALL_BITS)) {
866 - //printk("status %x, bits %x, slct %x\n", status1, TOE_IQ_ALL_BITS, tp->intr1_selected);
867 - toe_gmac_handle_toeq(dev, tp, status1);
868 - //toe_gmac_handle_toeq(dev, toe, tp, status1);
869 + else{
870 + reg_val = BIT(26)|(i<<21)|(5<<16);
871 + SPI_write(3,0,1,reg_val);
872 + msleep(10);
873 + ability = (reg_val = SPI_read(3,0,2)&0x5e0) >>5;
874 + if ((ability & 0x0C)) /* 100M full duplex */
875 + {
876 + SPI_write(1,i,0x00,0x30050472);
877 + SPI_write(1,i,0x00,0x10050442);
878 + printk("Port%d:100M\n",i);
879 + switch_pre_link[i]=LINK_UP;
880 + switch_pre_speed[i]=GMAC_SPEED_100;
881 + }
882 + else if((ability & 0x03)) /* 10M full duplex */
883 + {
884 + SPI_write(1,i,0x00,0x30050473);
885 + SPI_write(1,i,0x00,0x10050443);
886 + printk("Port%d:10M\n",i);
887 + switch_pre_link[i]=LINK_UP;
888 + switch_pre_speed[i]=GMAC_SPEED_10;
889 + }
890 + else{
891 + SPI_write(1,i,0x00,BIT(16)); // disable RX
892 + SPI_write(5,0,0x0E,BIT(i)); // dicard packet
893 + while((SPI_read(5,0,0x0C)&BIT(i))==0) // wait to be empty
894 + msleep(1);
895 +
896 + SPI_write(1,i,0x00,0x20000030); // PORT_RST
897 + switch_pre_link[i]=LINK_DOWN;
898 + switch_pre_speed[i]=GMAC_SPEED_10;
899 + rcv_mask &= ~BIT(i);
900 + SPI_write(2,0,0x10,rcv_mask); // Disable Receive
901 + }
902 }
903 -#endif
904 }
905 - else if (tp->port_id == 1)
906 - {
907 -#ifndef INTERRUPT_SELECT
908 - if (netif_running(dev) && (status1 & G1_INTR0_BITS) && (tp->intr1_enabled & G1_INTR0_BITS))
909 - {
910 - if (status1 & GMAC1_HWTQ13_EOF_INT_BIT)
911 - tp->hwtxq[3].eof_cnt++;
912 - if (status1 & GMAC1_HWTQ12_EOF_INT_BIT)
913 - tp->hwtxq[2].eof_cnt++;
914 - if (status1 & GMAC1_HWTQ11_EOF_INT_BIT)
915 - tp->hwtxq[1].eof_cnt++;
916 - if (status1 & GMAC1_HWTQ10_EOF_INT_BIT)
917 - tp->hwtxq[0].eof_cnt++;
918 -#endif //INTERRUPT_SELECT
919 -#ifndef INTERRUPT_SELECT
920 - }
921 -#endif //INTERRUPT_SELECT
922 - if (netif_running(dev) && (status1 & DEFAULT_Q1_INT_BIT) && (tp->intr1_enabled & DEFAULT_Q1_INT_BIT))
923 - {
924 - tp->default_q_intr_cnt++;
925 - toe_gmac_handle_default_rxq(dev, tp);
926 - }
927 -#ifdef CONFIG_SL351x_RXTOE
928 - if (netif_running(dev) && (status1 & TOE_IQ_ALL_BITS) &&
929 - (tp->intr1_enabled & TOE_IQ_ALL_BITS)) {
930 - //printk("status %x, bits %x, slct %x\n", status1, TOE_IQ_ALL_BITS, tp->intr1_selected);
931 - toe_gmac_handle_toeq(dev, tp, status1);
932 - //toe_gmac_handle_toeq(dev, toe, tp, status1);
933 - }
934 #endif
935 - }
936 + gmac_get_switch_status(dev);
937 + gmac_write_reg(tp->base_addr, GMAC_STATUS, 0x7d, 0x0000007f);
938 +// SPI_write(2,0,0x10,rcv_mask); // Enable Receive
939 + return ;
940 }
941 +#endif
942
943 + reg_val = gmac_get_phy_vendor(tp->phy_addr);
944 + printk("GMAC-%d Addr %d Vendor ID: 0x%08x\n", tp->port_id, tp->phy_addr, reg_val);
945
946 - // Interrupt Status 0
947 - if (status0 & tp->intr0_enabled)
948 - {
949 -
950 - #define ERR_INTR_BITS (GMAC0_TXDERR_INT_BIT | GMAC0_TXPERR_INT_BIT | \
951 - GMAC1_TXDERR_INT_BIT | GMAC1_TXPERR_INT_BIT | \
952 - GMAC0_RXDERR_INT_BIT | GMAC0_RXPERR_INT_BIT | \
953 - GMAC1_RXDERR_INT_BIT | GMAC1_RXPERR_INT_BIT)
954 -#ifndef INTERRUPT_SELECT
955 - if (status0 & ERR_INTR_BITS)
956 - {
957 - if ((status0 & GMAC0_TXDERR_INT_BIT) && (tp->intr0_enabled & GMAC0_TXDERR_INT_BIT))
958 - {
959 - tp->txDerr_cnt[0]++;
960 - printk("GMAC0 TX AHB Bus Error!\n");
961 - }
962 - if ((status0 & GMAC0_TXPERR_INT_BIT) && (tp->intr0_enabled & GMAC0_TXPERR_INT_BIT))
963 - {
964 - tp->txPerr_cnt[0]++;
965 - printk("GMAC0 Tx Descriptor Protocol Error!\n");
966 - }
967 - if ((status0 & GMAC1_TXDERR_INT_BIT) && (tp->intr0_enabled & GMAC1_TXDERR_INT_BIT))
968 - {
969 - tp->txDerr_cnt[1]++;
970 - printk("GMAC1 Tx AHB Bus Error!\n");
971 - }
972 - if ((status0 & GMAC1_TXPERR_INT_BIT) && (tp->intr0_enabled & GMAC1_TXPERR_INT_BIT))
973 - {
974 - tp->txPerr_cnt[1]++;
975 - printk("GMAC1 Tx Descriptor Protocol Error!\n");
976 - }
977 -
978 - if ((status0 & GMAC0_RXDERR_INT_BIT) && (tp->intr0_enabled & GMAC0_RXDERR_INT_BIT))
979 - {
980 - tp->RxDerr_cnt[0]++;
981 - printk("GMAC0 Rx AHB Bus Error!\n");
982 - }
983 - if ((status0 & GMAC0_RXPERR_INT_BIT) && (tp->intr0_enabled & GMAC0_RXPERR_INT_BIT))
984 - {
985 - tp->RxPerr_cnt[0]++;
986 - printk("GMAC0 Rx Descriptor Protocol Error!\n");
987 - }
988 - if ((status0 & GMAC1_RXDERR_INT_BIT) && (tp->intr0_enabled & GMAC1_RXDERR_INT_BIT))
989 - {
990 - tp->RxDerr_cnt[1]++;
991 - printk("GMAC1 Rx AHB Bus Error!\n");
992 - }
993 - if ((status0 & GMAC1_RXPERR_INT_BIT) && (tp->intr0_enabled & GMAC1_RXPERR_INT_BIT))
994 - {
995 - tp->RxPerr_cnt[1]++;
996 - printk("GMAC1 Rx Descriptor Protocol Error!\n");
997 - }
998 - }
999 -#endif //INTERRUPT_SELECT
1000 -#ifndef GMAX_TX_INTR_DISABLED
1001 - if (tp->port_id == 1 && netif_running(dev) &&
1002 - (((status0 & GMAC1_SWTQ10_FIN_INT_BIT) && (tp->intr0_enabled & GMAC1_SWTQ10_FIN_INT_BIT))
1003 - ||
1004 - ((status0 & GMAC1_SWTQ10_EOF_INT_BIT) && (tp->intr0_enabled & GMAC1_SWTQ10_EOF_INT_BIT))))
1005 - {
1006 - toe_gmac_tx_complete(&toe_private_data.gmac[1], 0, dev, 1);
1007 - }
1008 -
1009 - if (tp->port_id == 0 && netif_running(dev) &&
1010 - (((status0 & GMAC0_SWTQ00_FIN_INT_BIT) && (tp->intr0_enabled & GMAC0_SWTQ00_FIN_INT_BIT))
1011 - ||
1012 - ((status0 & GMAC0_SWTQ00_EOF_INT_BIT) && (tp->intr0_enabled & GMAC0_SWTQ00_EOF_INT_BIT))))
1013 - {
1014 - toe_gmac_tx_complete(&toe_private_data.gmac[0], 0, dev, 1);
1015 - }
1016 -#endif
1017 - // clear enabled status bits
1018 - }
1019 - // Interrupt Status 4
1020 -#ifndef INTERRUPT_SELECT
1021 - if (status4 & tp->intr4_enabled)
1022 - {
1023 - #define G1_INTR4_BITS (0xff000000)
1024 - #define G0_INTR4_BITS (0x00ff0000)
1025 -
1026 - if (tp->port_id == 0)
1027 - {
1028 - if ((status4 & G0_INTR4_BITS) && (tp->intr4_enabled & G0_INTR4_BITS))
1029 - {
1030 - if (status4 & GMAC0_RESERVED_INT_BIT)
1031 - printk("GMAC0_RESERVED_INT_BIT is ON\n");
1032 - if (status4 & GMAC0_MIB_INT_BIT)
1033 - tp->mib_full_cnt++;
1034 - if (status4 & GMAC0_RX_PAUSE_ON_INT_BIT)
1035 - tp->rx_pause_on_cnt++;
1036 - if (status4 & GMAC0_TX_PAUSE_ON_INT_BIT)
1037 - tp->tx_pause_on_cnt++;
1038 - if (status4 & GMAC0_RX_PAUSE_OFF_INT_BIT)
1039 - tp->rx_pause_off_cnt++;
1040 - if (status4 & GMAC0_TX_PAUSE_OFF_INT_BIT)
1041 - tp->rx_pause_off_cnt++;
1042 - if (status4 & GMAC0_RX_OVERRUN_INT_BIT)
1043 - tp->rx_overrun_cnt++;
1044 - if (status4 & GMAC0_STATUS_CHANGE_INT_BIT)
1045 - tp->status_changed_cnt++;
1046 - }
1047 - }
1048 - else if (tp->port_id == 1)
1049 - {
1050 - if ((status4 & G1_INTR4_BITS) && (tp->intr4_enabled & G1_INTR4_BITS))
1051 - {
1052 - if (status4 & GMAC1_RESERVED_INT_BIT)
1053 - printk("GMAC1_RESERVED_INT_BIT is ON\n");
1054 - if (status4 & GMAC1_MIB_INT_BIT)
1055 - tp->mib_full_cnt++;
1056 - if (status4 & GMAC1_RX_PAUSE_ON_INT_BIT)
1057 - {
1058 - //printk("Gmac pause on\n");
1059 - tp->rx_pause_on_cnt++;
1060 - }
1061 - if (status4 & GMAC1_TX_PAUSE_ON_INT_BIT)
1062 - {
1063 - //printk("Gmac pause on\n");
1064 - tp->tx_pause_on_cnt++;
1065 - }
1066 - if (status4 & GMAC1_RX_PAUSE_OFF_INT_BIT)
1067 - {
1068 - //printk("Gmac pause off\n");
1069 - tp->rx_pause_off_cnt++;
1070 - }
1071 - if (status4 & GMAC1_TX_PAUSE_OFF_INT_BIT)
1072 - {
1073 - //printk("Gmac pause off\n");
1074 - tp->rx_pause_off_cnt++;
1075 - }
1076 - if (status4 & GMAC1_RX_OVERRUN_INT_BIT)
1077 - {
1078 - //printk("Gmac Rx Overrun \n");
1079 - tp->rx_overrun_cnt++;
1080 - }
1081 - if (status4 & GMAC1_STATUS_CHANGE_INT_BIT)
1082 - tp->status_changed_cnt++;
1083 - }
1084 - }
1085 -#if 0
1086 - if ((status4 & SWFQ_EMPTY_INT_BIT) && (tp->intr4_enabled & SWFQ_EMPTY_INT_BIT))
1087 - {
1088 - // unsigned long data = REG32(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
1089 -// mac_stop_rxdma(tp->sc);
1090 - gmac_write_reg(TOE_GLOBAL_BASE, GLOBAL_INTERRUPT_ENABLE_4_REG,
1091 - tp->intr4_enabled & ~SWFQ_EMPTY_INT_BIT, SWFQ_EMPTY_INT_BIT);
1092 -
1093 - gmac_write_reg(TOE_GLOBAL_BASE, GLOBAL_INTERRUPT_STATUS_4_REG,
1094 - SWFQ_EMPTY_INT_BIT, SWFQ_EMPTY_INT_BIT);
1095 - toe_gmac_fill_free_q();
1096 - tp->sw_fq_empty_cnt++;
1097 -
1098 - gmac_write_reg(TOE_GLOBAL_BASE, GLOBAL_INTERRUPT_STATUS_4_REG, status4,
1099 - SWFQ_EMPTY_INT_BIT);
1100 -//#if 0
1101 -/* if (netif_running(dev))
1102 - toe_gmac_handle_default_rxq(dev, tp);
1103 - printk("SWFQ_EMPTY_INT_BIT is ON!\n"); // should not be happened */
1104 -//#endif
1105 - }
1106 -#endif
1107 - }
1108 -#endif //INTERRUPT_SELECT
1109 - toe_gmac_enable_interrupt(tp->irq);
1110 -//enable gmac rx function when do RFC 2544
1111 -#ifdef IxscriptMate_1518
1112 - if (storlink_ctl.pauseoff == 1)
1113 - {
1114 - GMAC_CONFIG0_T config0;
1115 - config0.bits32 = readl(TOE_GMAC0_BASE+GMAC_CONFIG0);
1116 - config0.bits.dis_rx = 0;
1117 - writel(config0.bits32, TOE_GMAC0_BASE+GMAC_CONFIG0);
1118 - config0.bits32 = readl(TOE_GMAC1_BASE+GMAC_CONFIG0);
1119 - config0.bits.dis_rx = 0;
1120 - writel(config0.bits32, TOE_GMAC1_BASE+GMAC_CONFIG0);
1121 - }
1122 -#endif
1123 - //printk("gmac_interrupt complete!\n\n");
1124 -// return IRQ_RETVAL(handled);
1125 - return IRQ_RETVAL(1);
1126 -#ifdef CONFIG_SL_NAPI
1127 -}
1128 -#endif
1129 -}
1130 -
1131 -/*----------------------------------------------------------------------
1132 -* toe_gmac_handle_default_rxq
1133 -* (1) Get rx Buffer for default Rx queue
1134 -* (2) notify or call upper-routine to handle it
1135 -* (3) get a new buffer and insert it into SW free queue
1136 -* (4) Note: The SW free queue Read-Write Pointer should be locked when accessing
1137 -*----------------------------------------------------------------------*/
1138 -//static inline void toe_gmac_handle_default_rxq(struct net_device *dev, GMAC_INFO_T *tp)
1139 -static void toe_gmac_handle_default_rxq(struct net_device *dev, GMAC_INFO_T *tp)
1140 -{
1141 - TOE_INFO_T *toe;
1142 - GMAC_RXDESC_T *curr_desc;
1143 - struct sk_buff *skb;
1144 - DMA_RWPTR_T rwptr;
1145 - unsigned int pkt_size;
1146 - int max_cnt;
1147 - unsigned int desc_count;
1148 - unsigned int good_frame, chksum_status, rx_status;
1149 - struct net_device_stats *isPtr = (struct net_device_stats *)&tp->ifStatics;
1150 -
1151 -//when do ixia RFC 2544 test and packet size is select 1518 bytes,disable gmace rx function immediately after one interrupt come in.
1152 -#ifdef IxscriptMate_1518
1153 - if (storlink_ctl.pauseoff == 1)
1154 - {
1155 - GMAC_CONFIG0_T config0;
1156 - config0.bits32 = readl(TOE_GMAC0_BASE+GMAC_CONFIG0);
1157 - config0.bits.dis_rx = 1;
1158 - writel(config0.bits32, TOE_GMAC0_BASE+GMAC_CONFIG0);
1159 - config0.bits32 = readl(TOE_GMAC1_BASE+GMAC_CONFIG0);
1160 - config0.bits.dis_rx = 1;
1161 - writel(config0.bits32, TOE_GMAC1_BASE+GMAC_CONFIG0);
1162 - }
1163 -#endif
1164 - rwptr.bits32 = readl(&tp->default_qhdr->word1);
1165 -#if 0
1166 - if (rwptr.bits.rptr != tp->rx_rwptr.bits.rptr)
1167 - {
1168 - mac_stop_txdma((struct net_device *)tp->dev);
1169 - printk("Default Queue HW RD ptr (0x%x) != SW RD Ptr (0x%x)\n",
1170 - rwptr.bits32, tp->rx_rwptr.bits.rptr);
1171 - while(1);
1172 - }
1173 -#endif
1174 - toe = (TOE_INFO_T *)&toe_private_data;
1175 - max_cnt = DEFAULT_RXQ_MAX_CNT;
1176 - while ((--max_cnt) && rwptr.bits.rptr != rwptr.bits.wptr)
1177 -// while (rwptr.bits.rptr != rwptr.bits.wptr)
1178 - {
1179 -//if packet size is not 1518 for RFC 2544,enable gmac rx function.The other packet size have RX workaround.
1180 -#ifdef IxscriptMate_1518
1181 - if (storlink_ctl.pauseoff == 1)
1182 - {
1183 - if (pkt_size != 1514)
1184 - {
1185 - GMAC_CONFIG0_T config0;
1186 - config0.bits32 = readl(TOE_GMAC0_BASE+GMAC_CONFIG0);
1187 - config0.bits.dis_rx = 0;
1188 - writel(config0.bits32, TOE_GMAC0_BASE+GMAC_CONFIG0);
1189 - config0.bits32 = readl(TOE_GMAC1_BASE+GMAC_CONFIG0);
1190 - config0.bits.dis_rx = 0;
1191 - writel(config0.bits32, TOE_GMAC1_BASE+GMAC_CONFIG0);
1192 - }
1193 - }
1194 -#endif
1195 - curr_desc = (GMAC_RXDESC_T *)tp->default_desc_base + rwptr.bits.rptr;
1196 -// consistent_sync(curr_desc, sizeof(GMAC_RXDESC_T), PCI_DMA_FROMDEVICE);
1197 - tp->default_q_cnt++;
1198 - tp->rx_curr_desc = (unsigned int)curr_desc;
1199 - rx_status = curr_desc->word0.bits.status;
1200 - chksum_status = curr_desc->word0.bits.chksum_status;
1201 - tp->rx_status_cnt[rx_status]++;
1202 - tp->rx_chksum_cnt[chksum_status]++;
1203 - pkt_size = curr_desc->word1.bits.byte_count; /*total byte count in a frame*/
1204 - desc_count = curr_desc->word0.bits.desc_count; /* get descriptor count per frame */
1205 - good_frame=1;
1206 - if ((curr_desc->word0.bits32 & (GMAC_RXDESC_0_T_derr | GMAC_RXDESC_0_T_perr))
1207 - || (pkt_size < 60)
1208 - || (chksum_status & 0x4)
1209 - || rx_status)
1210 - {
1211 - good_frame = 0;
1212 - if (curr_desc->word0.bits32 & GMAC_RXDESC_0_T_derr)
1213 - printk("%s::derr (GMAC-%d)!!!\n", __func__, tp->port_id);
1214 - if (curr_desc->word0.bits32 & GMAC_RXDESC_0_T_perr)
1215 - printk("%s::perr (GMAC-%d)!!!\n", __func__, tp->port_id);
1216 - if (rx_status)
1217 - {
1218 - if (rx_status == 4 || rx_status == 7)
1219 - isPtr->rx_crc_errors++;
1220 -// printk("%s::Status=%d (GMAC-%d)!!!\n", __func__, rx_status, tp->port_id);
1221 - }
1222 -#ifdef SL351x_GMAC_WORKAROUND
1223 - else if (pkt_size < 60)
1224 - {
1225 - if (tp->short_frames_cnt < GMAC_SHORT_FRAME_THRESHOLD)
1226 - tp->short_frames_cnt++;
1227 - if (tp->short_frames_cnt >= GMAC_SHORT_FRAME_THRESHOLD)
1228 - {
1229 - GMAC_CONFIG0_T config0;
1230 - config0.bits32 = readl(TOE_GMAC0_BASE+GMAC_CONFIG0);
1231 - config0.bits.dis_rx = 1;
1232 - writel(config0.bits32, TOE_GMAC0_BASE+GMAC_CONFIG0);
1233 - config0.bits32 = readl(TOE_GMAC1_BASE+GMAC_CONFIG0);
1234 - config0.bits.dis_rx = 1;
1235 - writel(config0.bits32, TOE_GMAC1_BASE+GMAC_CONFIG0);
1236 - }
1237 - }
1238 -#endif
1239 -// if (chksum_status)
1240 -// printk("%s::Checksum Status=%d (GMAC-%d)!!!\n", __func__, chksum_status, tp->port_id);
1241 - skb = (struct sk_buff *)(REG32(__va(curr_desc->word2.buf_adr) - SKB_RESERVE_BYTES));
1242 - dev_kfree_skb_irq(skb);
1243 - }
1244 - if (good_frame)
1245 - {
1246 - if (curr_desc->word0.bits.drop)
1247 - printk("%s::Drop (GMAC-%d)!!!\n", __func__, tp->port_id);
1248 -// if (chksum_status)
1249 -// printk("%s::Checksum Status=%d (GMAC-%d)!!!\n", __func__, chksum_status, tp->port_id);
1250 -
1251 - /* get frame information from the first descriptor of the frame */
1252 -#ifdef SL351x_GMAC_WORKAROUND
1253 - if (tp->short_frames_cnt >= GMAC_SHORT_FRAME_THRESHOLD)
1254 - {
1255 - GMAC_CONFIG0_T config0;
1256 - config0.bits32 = readl(TOE_GMAC0_BASE+GMAC_CONFIG0);
1257 - config0.bits.dis_rx = 0;
1258 - writel(config0.bits32, TOE_GMAC0_BASE+GMAC_CONFIG0);
1259 - config0.bits32 = readl(TOE_GMAC1_BASE+GMAC_CONFIG0);
1260 - config0.bits.dis_rx = 0;
1261 - writel(config0.bits32, TOE_GMAC1_BASE+GMAC_CONFIG0);
1262 - }
1263 - tp->short_frames_cnt = 0;
1264 -#endif
1265 - isPtr->rx_packets++;
1266 - skb = (struct sk_buff *)(REG32(__va(curr_desc->word2.buf_adr - SKB_RESERVE_BYTES)));
1267 - if (!skb)
1268 - {
1269 - printk("Fatal Error!!skb==NULL\n");
1270 - goto next_rx;
1271 - }
1272 - tp->curr_rx_skb = skb;
1273 - // consistent_sync((void *)__va(curr_desc->word2.buf_adr), pkt_size, PCI_DMA_FROMDEVICE);
1274 -
1275 - // curr_desc->word2.buf_adr = 0;
1276 -
1277 - skb_reserve (skb, RX_INSERT_BYTES); /* 16 byte align the IP fields. */
1278 - skb_put(skb, pkt_size);
1279 - skb->dev = dev;
1280 - if (chksum_status == RX_CHKSUM_IP_UDP_TCP_OK)
1281 - {
1282 - skb->ip_summed = CHECKSUM_UNNECESSARY;
1283 -#ifdef CONFIG_SL351x_NAT
1284 - if (nat_cfg.enabled && curr_desc->word3.bits.l3_offset && curr_desc->word3.bits.l4_offset)
1285 - {
1286 - struct iphdr *ip_hdr;
1287 - ip_hdr = (struct iphdr *)&(skb->data[curr_desc->word3.bits.l3_offset]);
1288 - sl351x_nat_input(skb,
1289 - tp->port_id,
1290 - (void *)curr_desc->word3.bits.l3_offset,
1291 - (void *)curr_desc->word3.bits.l4_offset);
1292 - }
1293 -#endif
1294 - skb->protocol = eth_type_trans(skb,dev); /* set skb protocol */
1295 -#if 0
1296 -#ifdef CONFIG_SL351x_RXTOE
1297 - if (storlink_ctl.rx_max_pktsize) {
1298 - struct iphdr *ip_hdr;
1299 - struct tcphdr *tcp_hdr;
1300 - int ip_hdrlen;
1301 -
1302 - ip_hdr = (struct iphdr*)&(skb->data[0]);
1303 - if ((skb->protocol == __constant_htons(ETH_P_IP)) &&
1304 - ((ip_hdr->protocol & 0x00ff) == IPPROTO_TCP)) {
1305 - ip_hdrlen = ip_hdr->ihl << 2;
1306 - tcp_hdr = (struct tcphdr*)&(skb->data[ip_hdrlen]);
1307 - if (tcp_hdr->syn) {
1308 - struct toe_conn* connection = init_toeq(ip_hdr->version,
1309 - ip_hdr, tcp_hdr, toe, &(skb->data[0]) - 14);
1310 - TCP_SKB_CB(skb)->connection = connection;
1311 - // hash_dump_entry(TCP_SKB_CB(skb)->connection->hash_entry_index);
1312 - // printk("%s::skb data %x, conn %x, mode %x\n",
1313 - // __func__, skb->data, connection, connection->mode);
1314 - }
1315 - }
1316 - }
1317 -#endif
1318 -#endif
1319 - }
1320 - else if (chksum_status == RX_CHKSUM_IP_OK_ONLY)
1321 - {
1322 - skb->ip_summed = CHECKSUM_UNNECESSARY;
1323 -#ifdef CONFIG_SL351x_NAT
1324 - if (nat_cfg.enabled && curr_desc->word3.bits.l3_offset && curr_desc->word3.bits.l4_offset)
1325 - {
1326 - struct iphdr *ip_hdr;
1327 - //struct tcphdr *tcp_hdr;
1328 - ip_hdr = (struct iphdr *)&(skb->data[curr_desc->word3.bits.l3_offset]);
1329 - //tcp_hdr = (struct tcphdr *)&(skb->data[curr_desc->word3.bits.l4_offset]);
1330 - if (ip_hdr->protocol == IPPROTO_UDP)
1331 - {
1332 - sl351x_nat_input(skb,
1333 - tp->port_id,
1334 - (void *)curr_desc->word3.bits.l3_offset,
1335 - (void *)curr_desc->word3.bits.l4_offset);
1336 - }
1337 - else if (ip_hdr->protocol == IPPROTO_GRE)
1338 - {
1339 - sl351x_nat_input(skb,
1340 - tp->port_id,
1341 - (void *)curr_desc->word3.bits.l3_offset,
1342 - (void *)curr_desc->word3.bits.l4_offset);
1343 - }
1344 - }
1345 -#endif
1346 - skb->protocol = eth_type_trans(skb,dev); /* set skb protocol */
1347 - }
1348 - else
1349 - {
1350 - skb->protocol = eth_type_trans(skb,dev); /* set skb protocol */
1351 - }
1352 -
1353 - netif_rx(skb); /* socket rx */
1354 - dev->last_rx = jiffies;
1355 -
1356 - isPtr->rx_bytes += pkt_size;
1357 -
1358 - }
1359 -
1360 -next_rx:
1361 - // advance one for Rx default Q 0/1
1362 - rwptr.bits.rptr = RWPTR_ADVANCE_ONE(rwptr.bits.rptr, tp->default_desc_num);
1363 - SET_RPTR(&tp->default_qhdr->word1, rwptr.bits.rptr);
1364 - tp->rx_rwptr.bits32 = rwptr.bits32;
1365 -
1366 - }
1367 -
1368 - /* Handles first available packets only then refill the queue. */
1369 - toe_gmac_fill_free_q();
1370 -}
1371 -
1372 -/*----------------------------------------------------------------------
1373 -* gmac_get_phy_vendor
1374 -*----------------------------------------------------------------------*/
1375 -static unsigned int gmac_get_phy_vendor(int phy_addr)
1376 -{
1377 - unsigned int reg_val;
1378 - reg_val=(mii_read(phy_addr,0x02) << 16) + mii_read(phy_addr,0x03);
1379 - return reg_val;
1380 -}
1381 -
1382 -/*----------------------------------------------------------------------
1383 -* gmac_set_phy_status
1384 -*----------------------------------------------------------------------*/
1385 -void gmac_set_phy_status(struct net_device *dev)
1386 -{
1387 - GMAC_INFO_T *tp = dev->priv;
1388 - GMAC_STATUS_T status;
1389 - unsigned int reg_val, ability,wan_port_id;
1390 - unsigned int i = 0;
1391 -
1392 -#ifdef VITESSE_G5SWITCH
1393 - if((tp->port_id == GMAC_PORT1)&&(Giga_switch==1)){
1394 -#if 0
1395 - rcv_mask = SPI_read(2,0,0x10); // Receive mask
1396 - rcv_mask |= 0x4F;
1397 - for(i=0;i<4;i++){
1398 - reg_val = BIT(26)|(i<<21)|(10<<16);
1399 - SPI_write(3,0,1,reg_val);
1400 - msleep(10);
1401 - reg_val = SPI_read(3,0,2);
1402 - if(reg_val & 0x0c00){
1403 - printk("Port%d:Giga mode\n",i);
1404 - SPI_write(1,i,0x00,0x300701B1);
1405 - SPI_write(1,i,0x00,0x10070181);
1406 - switch_pre_link[i]=LINK_UP;
1407 - switch_pre_speed[i]=GMAC_SPEED_1000;
1408 - }
1409 - else{
1410 - reg_val = BIT(26)|(i<<21)|(5<<16);
1411 - SPI_write(3,0,1,reg_val);
1412 - msleep(10);
1413 - ability = (reg_val = SPI_read(3,0,2)&0x5e0) >>5;
1414 - if ((ability & 0x0C)) /* 100M full duplex */
1415 - {
1416 - SPI_write(1,i,0x00,0x30050472);
1417 - SPI_write(1,i,0x00,0x10050442);
1418 - printk("Port%d:100M\n",i);
1419 - switch_pre_link[i]=LINK_UP;
1420 - switch_pre_speed[i]=GMAC_SPEED_100;
1421 - }
1422 - else if((ability & 0x03)) /* 10M full duplex */
1423 - {
1424 - SPI_write(1,i,0x00,0x30050473);
1425 - SPI_write(1,i,0x00,0x10050443);
1426 - printk("Port%d:10M\n",i);
1427 - switch_pre_link[i]=LINK_UP;
1428 - switch_pre_speed[i]=GMAC_SPEED_10;
1429 - }
1430 - else{
1431 - SPI_write(1,i,0x00,BIT(16)); // disable RX
1432 - SPI_write(5,0,0x0E,BIT(i)); // dicard packet
1433 - while((SPI_read(5,0,0x0C)&BIT(i))==0) // wait to be empty
1434 - msleep(1);
1435 -
1436 - SPI_write(1,i,0x00,0x20000030); // PORT_RST
1437 - switch_pre_link[i]=LINK_DOWN;
1438 - switch_pre_speed[i]=GMAC_SPEED_10;
1439 - rcv_mask &= ~BIT(i);
1440 - SPI_write(2,0,0x10,rcv_mask); // Disable Receive
1441 - }
1442 - }
1443 - }
1444 -#endif
1445 - gmac_get_switch_status(dev);
1446 - gmac_write_reg(tp->base_addr, GMAC_STATUS, 0x7d, 0x0000007f);
1447 -// SPI_write(2,0,0x10,rcv_mask); // Enable Receive
1448 - return ;
1449 - }
1450 -#endif
1451 -
1452 - reg_val = gmac_get_phy_vendor(tp->phy_addr);
1453 - printk("GMAC-%d Addr %d Vendor ID: 0x%08x\n", tp->port_id, tp->phy_addr, reg_val);
1454 -
1455 - switch (tp->phy_mode)
1456 + switch (tp->phy_mode)
1457 {
1458 case GMAC_PHY_GMII:
1459 mii_write(tp->phy_addr,0x04,0x05e1); /* advertisement 100M full duplex, pause capable on */
1460 @@ -3552,6 +2982,7 @@
1461 status.bits.link = LINK_DOWN;
1462 // clear_bit(__LINK_STATE_START, &dev->state);
1463 printk("Link Down (0x%04x) ", reg_val);
1464 +#ifdef VITESSE_G5SWITCH
1465 if(Giga_switch == 1)
1466 {
1467 wan_port_id = 1;
1468 @@ -3565,6 +2996,7 @@
1469 storlink_ctl.link[ tp->port_id] = 0;
1470 #endif
1471 }
1472 +#endif
1473 }
1474 else
1475 {
1476 @@ -3572,6 +3004,7 @@
1477 status.bits.link = LINK_UP;
1478 // set_bit(__LINK_STATE_START, &dev->state);
1479 printk("Link Up (0x%04x) ",reg_val);
1480 +#ifdef VITESSE_G5SWITCH
1481 if(Giga_switch == 1)
1482 {
1483 wan_port_id = 1;
1484 @@ -3585,6 +3018,7 @@
1485 storlink_ctl.link[ tp->port_id] = 1;
1486 #endif
1487 }
1488 +#endif
1489 }
1490 // value = mii_read(PHY_ADDR,0x05);
1491
1492 @@ -3863,6 +3297,7 @@
1493 }
1494 }
1495 status.bits.link = LINK_UP; /* link up */
1496 +#ifdef VITESSE_G5SWITCH
1497 if(Giga_switch==1)
1498 {
1499 wan_port_id = 1;
1500 @@ -3874,6 +3309,7 @@
1501 storlink_ctl.link[ tp->port_id] = 1;
1502 #endif
1503 }
1504 +#endif
1505 if ((ability & 0x20)==0x20)
1506 {
1507 if (tp->flow_control_enable == 0)
1508 @@ -3914,6 +3350,7 @@
1509 else
1510 {
1511 status.bits.link = LINK_DOWN; /* link down */
1512 +#ifdef VITESSE_G5SWITCH
1513 if(Giga_switch == 1)
1514 {
1515 wan_port_id = 1;
1516 @@ -3925,6 +3362,7 @@
1517 storlink_ctl.link[ tp->port_id] = 0;
1518 #endif
1519 }
1520 +#endif
1521 if (tp->pre_phy_status == LINK_UP)
1522 {
1523 printk("GMAC-%d LINK_Down......\n",tp->port_id);
1524 @@ -4298,86 +3736,102 @@
1525 }
1526
1527 #ifdef CONFIG_SL_NAPI
1528 +
1529 +static int gmax_rx(struct net_device *dev, int *budget)
1530 +{
1531 + return 0;
1532 +}
1533 +
1534 +static int gmac_tx(struct net_device *dev, int *budget)
1535 +{
1536 + return 0;
1537 +}
1538 +
1539 /*----------------------------------------------------------------------
1540 * gmac_rx_poll
1541 *----------------------------------------------------------------------*/
1542 static int gmac_rx_poll(struct net_device *dev, int *budget)
1543 {
1544 - TOE_INFO_T *toe;
1545 - GMAC_RXDESC_T *curr_desc;
1546 - struct sk_buff *skb;
1547 - DMA_RWPTR_T rwptr;
1548 - unsigned int data32;
1549 - unsigned int pkt_size;
1550 - unsigned int desc_count;
1551 - unsigned int good_frame, chksum_status, rx_status;
1552 - int rx_pkts_num = 0;
1553 - int quota = min(dev->quota, *budget);
1554 - GMAC_INFO_T *tp = (GMAC_INFO_T *)dev->priv;
1555 - unsigned int status4;
1556 - volatile DMA_RWPTR_T fq_rwptr;
1557 - // int max_cnt = TOE_SW_FREEQ_DESC_NUM;//TOE_SW_FREEQ_DESC_NUM = 64
1558 - //unsigned long rx_old_bytes;
1559 + TOE_INFO_T *toe;
1560 + GMAC_RXDESC_T *curr_desc;
1561 + struct sk_buff *skb;
1562 + DMA_RWPTR_T rwptr;
1563 + unsigned int data32;
1564 + unsigned int pkt_size;
1565 + unsigned int desc_count;
1566 + unsigned int good_frame, chksum_status, rx_status;
1567 + int rx_pkts_num = 0;
1568 + int quota = min(dev->quota, *budget);
1569 + GMAC_INFO_T *tp = (GMAC_INFO_T *)dev->priv;
1570 + unsigned int status1;
1571 + unsigned int status4;
1572 struct net_device_stats *isPtr = (struct net_device_stats *)&tp->ifStatics;
1573 - //unsigned long long rx_time;
1574 -
1575
1576 BUG_ON(rx_poll_enabled == 0);
1577 -#if 1
1578 - if (do_again)
1579 - {
1580 - toe_gmac_fill_free_q();
1581 - status4 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_4_REG);
1582 - fq_rwptr.bits32 = readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
1583 - //printk("\n%s:: do_again toe_gmac_fill_free_q =======>status4=0x%x =====fq_rwptr =0x%8x======>JKJKJKJKJKJKJKJKJ \n", __func__,status4,fq_rwptr.bits32);
1584 - if (fq_rwptr.bits.wptr != fq_rwptr.bits.rptr)
1585 - {
1586 - //status4 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_4_REG);
1587 - do_again =0;
1588 - //netif_rx_complete(dev);
1589 - gmac_write_reg(TOE_GLOBAL_BASE, GLOBAL_INTERRUPT_STATUS_4_REG, status4, 0x1);
1590 - fq_rwptr.bits32 = readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
1591 - rwptr.bits32 = readl(&tp->default_qhdr->word1);
1592 - }
1593 - else
1594 - return 1;
1595 - }
1596 -#endif
1597 - rwptr.bits32 = readl(&tp->default_qhdr->word1);
1598 -#if 0
1599 - if (rwptr.bits.rptr != tp->rx_rwptr.bits.rptr)
1600 - {
1601 - mac_stop_txdma((struct net_device *)tp->dev);
1602 - printk("Default Queue HW RD ptr (0x%x) != SW RD Ptr (0x%x)\n",
1603 - rwptr.bits32, tp->rx_rwptr.bits.rptr);
1604 - while(1);
1605 - }
1606 -#endif
1607 +
1608 toe = (TOE_INFO_T *)&toe_private_data;
1609
1610 - fq_rwptr.bits32 = readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
1611 - //printk("%s:---Before-------------->Default Queue HW RW ptr (0x%8x), fq_rwptr =0x%8x \n",__func__,rwptr.bits32,fq_rwptr.bits32 );
1612 - //printk("%s:---Before while rx_pkts_num=%d------rx_finished_idx=0x%x------->Default_Q [rwptr.bits.rptr(SW)=0x%x, rwptr.bits.wptr(HW) = 0x%x ]---->Free_Q(SW_HW) = 0x%8x \n",__func__,rx_pkts_num,rx_finished_idx,rwptr.bits.rptr,rwptr.bits.wptr,fq_rwptr.bits32 );
1613 -// while ((--max_cnt) && (rwptr.bits.rptr != rwptr.bits.wptr) && (rx_pkts_num < quota))
1614 +rx_poll_retry:
1615 + status1 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_1_REG);
1616 + if (status1 & 1) {
1617 + writel(1, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_1_REG);
1618 + }
1619
1620 + rwptr.bits32 = readl(&tp->default_qhdr->word1);
1621 while ((rwptr.bits.rptr != rwptr.bits.wptr) && (rx_pkts_num < quota))
1622 {
1623 -
1624 - curr_desc = (GMAC_RXDESC_T *)tp->default_desc_base + rwptr.bits.rptr;
1625 + curr_desc = (GMAC_RXDESC_T *)tp->default_desc_base + rwptr.bits.rptr;
1626 tp->default_q_cnt++;
1627 - tp->rx_curr_desc = (unsigned int)curr_desc;
1628 - rx_status = curr_desc->word0.bits.status;
1629 - chksum_status = curr_desc->word0.bits.chksum_status;
1630 - tp->rx_status_cnt[rx_status]++;
1631 - tp->rx_chksum_cnt[chksum_status]++;
1632 - pkt_size = curr_desc->word1.bits.byte_count; /*total byte count in a frame*/
1633 + tp->rx_curr_desc = (unsigned int)curr_desc;
1634 + rx_status = curr_desc->word0.bits.status;
1635 + chksum_status = curr_desc->word0.bits.chksum_status;
1636 + tp->rx_status_cnt[rx_status]++;
1637 + tp->rx_chksum_cnt[chksum_status]++;
1638 + pkt_size = curr_desc->word1.bits.byte_count; /*total byte count in a frame*/
1639 desc_count = curr_desc->word0.bits.desc_count; /* get descriptor count per frame */
1640 good_frame=1;
1641 +
1642 + if (0) {
1643 +
1644 + int free, busy;
1645 + uint32_t rwptr1;
1646 + uint32_t rwptr2;
1647 +
1648 + rwptr1 = readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
1649 + free = (GET_WPTR(rwptr1) - GET_RPTR(rwptr1)) & 0xFF;
1650 +
1651 + rwptr2 = readl(&tp->default_qhdr->word1);
1652 + busy = (GET_RPTR(rwptr2) - GET_WPTR(rwptr2)) & 0xFF;
1653 +
1654 + if (GET_WPTR(rwptr1) == GET_RPTR(rwptr1)) {
1655 + printk("frame status: %d\n"
1656 + "SWFQ: wptr: %hu, rptr: %hu, free: %d\n"
1657 + "GMAC: wptr: %hu, rptr: %hu, free: %d\n",
1658 + rx_status,
1659 + GET_WPTR(rwptr1), GET_RPTR(rwptr1), free,
1660 + GET_WPTR(rwptr2), GET_RPTR(rwptr2), busy);
1661 + }
1662 + }
1663 +
1664 + {
1665 + GMAC_RXDESC_T *fq_desc;
1666 + void *data;
1667 + struct sk_buff *skb;
1668 + unsigned short idx;
1669 +
1670 + skb = (struct sk_buff *)(REG32(__va(curr_desc->word2.buf_adr) - SKB_RESERVE_BYTES));
1671 + idx = (unsigned short)(REG32(__va(curr_desc->word2.buf_adr) - SKB_RESERVE_BYTES + 4));
1672 +
1673 + BUG_ON(idx > TOE_SW_FREEQ_DESC_NUM);
1674 + BUG_ON(skb == NULL);
1675 + fq_desc = (GMAC_RXDESC_T*)toe->swfq_desc_base + idx;
1676 + fq_desc->word2.buf_adr = 0;
1677 + }
1678 +
1679 if ((curr_desc->word0.bits32 & (GMAC_RXDESC_0_T_derr | GMAC_RXDESC_0_T_perr))
1680 - || (pkt_size < 60)
1681 + || (pkt_size < 60)
1682 || (chksum_status & 0x4)
1683 || rx_status )
1684 -// || rx_status || (rwptr.bits.rptr > rwptr.bits.wptr ))
1685 {
1686 good_frame = 0;
1687 if (curr_desc->word0.bits32 & GMAC_RXDESC_0_T_derr)
1688 @@ -4388,7 +3842,6 @@
1689 {
1690 if (rx_status == 4 || rx_status == 7)
1691 isPtr->rx_crc_errors++;
1692 -// printk("%s::Status=%d (GMAC-%d)!!!\n", __func__, rx_status, tp->port_id);
1693 }
1694 #ifdef SL351x_GMAC_WORKAROUND
1695 else if (pkt_size < 60)
1696 @@ -4407,17 +3860,32 @@
1697 }
1698 }
1699 #endif
1700 -// if (chksum_status)
1701 -// printk("%s::Checksum Status=%d (GMAC-%d)!!!\n", __func__, chksum_status, tp->port_id);
1702 skb = (struct sk_buff *)(REG32(__va(curr_desc->word2.buf_adr) - SKB_RESERVE_BYTES));
1703 - dev_kfree_skb_irq(skb);
1704 + dev_kfree_skb(skb);
1705 +
1706 + if (0) {
1707 + int free, busy;
1708 + uint32_t rwptr1;
1709 + uint32_t rwptr2;
1710 +
1711 + rwptr1 = readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
1712 + free = (GET_WPTR(rwptr1) - GET_RPTR(rwptr1)) & 0xFF;
1713 +
1714 + rwptr2 = readl(&tp->default_qhdr->word1);
1715 + busy = (GET_RPTR(rwptr2) - GET_WPTR(rwptr2)) & 0xFF;
1716 +
1717 + printk("frame status: %d\n"
1718 + "SWFQ: wptr: %hu, rptr: %hu, free: %d\n"
1719 + "GMAC: wptr: %hu, rptr: %hu, free: %d\n",
1720 + rx_status,
1721 + GET_WPTR(rwptr1), GET_RPTR(rwptr1), free,
1722 + GET_WPTR(rwptr2), GET_RPTR(rwptr2), busy);
1723 + }
1724 }
1725 if (good_frame)
1726 {
1727 if (curr_desc->word0.bits.drop)
1728 printk("%s::Drop (GMAC-%d)!!!\n", __func__, tp->port_id);
1729 -// if (chksum_status)
1730 -// printk("%s::Checksum Status=%d (GMAC-%d)!!!\n", __func__, chksum_status, tp->port_id);
1731
1732 #ifdef SL351x_GMAC_WORKAROUND
1733 if (tp->short_frames_cnt >= GMAC_SHORT_FRAME_THRESHOLD)
1734 @@ -4432,225 +3900,118 @@
1735 }
1736 tp->short_frames_cnt = 0;
1737 #endif
1738 - /* get frame information from the first descriptor of the frame */
1739 + /* get frame information from the first descriptor of the frame */
1740 isPtr->rx_packets++;
1741 - //consistent_sync((void *)__va(curr_desc->word2.buf_adr), pkt_size, PCI_DMA_FROMDEVICE);
1742 + consistent_sync((void *)__va(curr_desc->word2.buf_adr), pkt_size, PCI_DMA_FROMDEVICE);
1743 skb = (struct sk_buff *)(REG32(__va(curr_desc->word2.buf_adr) - SKB_RESERVE_BYTES));
1744 tp->curr_rx_skb = skb;
1745 - // curr_desc->word2.buf_adr = 0;
1746
1747 - //skb_reserve (skb, SKB_RESERVE_BYTES);
1748 skb_reserve (skb, RX_INSERT_BYTES); /* 2 byte align the IP fields. */
1749 - //if ((skb->tail+pkt_size) > skb->end )
1750 - //printk("%s::------------->Here skb->len=%d,pkt_size= %d,skb->head=0x%x,skb->tail= 0x%x, skb->end= 0x%x\n", __func__, skb->len, pkt_size,skb->head,skb->tail,skb->end);
1751 skb_put(skb, pkt_size);
1752
1753 -
1754 skb->dev = dev;
1755 if (chksum_status == RX_CHKSUM_IP_UDP_TCP_OK)
1756 {
1757 skb->ip_summed = CHECKSUM_UNNECESSARY;
1758 -#ifdef CONFIG_SL351x_NAT
1759 - if (nat_cfg.enabled && curr_desc->word3.bits.l3_offset && curr_desc->word3.bits.l4_offset)
1760 - {
1761 - struct iphdr *ip_hdr;
1762 - ip_hdr = (struct iphdr *)&(skb->data[curr_desc->word3.bits.l3_offset]);
1763 - sl351x_nat_input(skb,
1764 - tp->port_id,
1765 - (void *)curr_desc->word3.bits.l3_offset,
1766 - (void *)curr_desc->word3.bits.l4_offset);
1767 - }
1768 -#endif
1769 skb->protocol = eth_type_trans(skb,dev); /* set skb protocol */
1770 -#if 0
1771 -#ifdef CONFIG_SL351x_RXTOE
1772 - if (storlink_ctl.rx_max_pktsize) {
1773 - struct iphdr *ip_hdr;
1774 - struct tcphdr *tcp_hdr;
1775 - int ip_hdrlen;
1776 -
1777 - ip_hdr = (struct iphdr*)&(skb->data[0]);
1778 - if ((skb->protocol == __constant_htons(ETH_P_IP)) &&
1779 - ((ip_hdr->protocol & 0x00ff) == IPPROTO_TCP)) {
1780 - ip_hdrlen = ip_hdr->ihl << 2;
1781 - tcp_hdr = (struct tcphdr*)&(skb->data[ip_hdrlen]);
1782 - if (tcp_hdr->syn) {
1783 - struct toe_conn* connection = init_toeq(ip_hdr->version,
1784 - ip_hdr, tcp_hdr, toe, &(skb->data[0]) - 14);
1785 - TCP_SKB_CB(skb)->connection = connection;
1786 - // hash_dump_entry(TCP_SKB_CB(skb)->connection->hash_entry_index);
1787 - // printk("%s::skb data %x, conn %x, mode %x\n",
1788 - // __func__, skb->data, connection, connection->mode);
1789 - }
1790 - }
1791 - }
1792 -#endif
1793 -#endif
1794 }
1795 else if (chksum_status == RX_CHKSUM_IP_OK_ONLY)
1796 {
1797 skb->ip_summed = CHECKSUM_UNNECESSARY;
1798 -#ifdef CONFIG_SL351x_NAT
1799 - if (nat_cfg.enabled && curr_desc->word3.bits.l3_offset && curr_desc->word3.bits.l4_offset)
1800 - {
1801 - struct iphdr *ip_hdr;
1802 - ip_hdr = (struct iphdr *)&(skb->data[curr_desc->word3.bits.l3_offset]);
1803 - if (ip_hdr->protocol == IPPROTO_UDP)
1804 - {
1805 - sl351x_nat_input(skb,
1806 - tp->port_id,
1807 - (void *)curr_desc->word3.bits.l3_offset,
1808 - (void *)curr_desc->word3.bits.l4_offset);
1809 - }
1810 - else if (ip_hdr->protocol == IPPROTO_GRE)
1811 - {
1812 - sl351x_nat_input(skb,
1813 - tp->port_id,
1814 - (void *)curr_desc->word3.bits.l3_offset,
1815 - (void *)curr_desc->word3.bits.l4_offset);
1816 - }
1817 - }
1818 -#endif
1819 skb->protocol = eth_type_trans(skb,dev); /* set skb protocol */
1820 }
1821 else
1822 {
1823 skb->protocol = eth_type_trans(skb,dev); /* set skb protocol */
1824 }
1825 - //netif_rx(skb); /* socket rx */
1826 +
1827 netif_receive_skb(skb); //For NAPI
1828 dev->last_rx = jiffies;
1829
1830 isPtr->rx_bytes += pkt_size;
1831 - //printk("------------------->isPtr->rx_bytes = %d\n",isPtr->rx_bytes);
1832 -
1833 + }
1834
1835 - }
1836 // advance one for Rx default Q 0/1
1837 rwptr.bits.rptr = RWPTR_ADVANCE_ONE(rwptr.bits.rptr, tp->default_desc_num);
1838 SET_RPTR(&tp->default_qhdr->word1, rwptr.bits.rptr);
1839 - tp->rx_rwptr.bits32 = rwptr.bits32;
1840 + tp->rx_rwptr.bits32 = rwptr.bits32;
1841 rx_pkts_num++;
1842 - //rwptr.bits32 = readl(&tp->default_qhdr->word1);//try read default_qhdr again
1843 - //fq_rwptr.bits32 = readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
1844 - //printk("%s:---Loop -------->rx_pkts_num=%d------------>Default Queue HW RW ptr = (0x%8x), fq_rwptr =0x%8x \n",__func__,rx_pkts_num,rwptr.bits32,fq_rwptr.bits32 );
1845 -#if 0
1846 - if ((status4 & 0x1) == 0)
1847 - {
1848 - //if (!((dev->last_rx <= (rx_time + 2)) && (isPtr->rx_bytes > (rx_old_bytes + 1000000 ))))
1849 - if (tp->total_q_cnt_napi < 1024)
1850 - {
1851 - tp->total_q_cnt_napi++;
1852 - toe_gmac_fill_free_q(); //for iperf test disable
1853 - }
1854 - //else
1855 - //printk("%s:---isPtr->rx_bytes =%u , rx_old_bytes =%u\n",__func__,isPtr->rx_bytes,rx_old_bytes );
1856 + // rwptr.bits32 = readl(&tp->default_qhdr->word1);
1857
1858 + status4 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_4_REG);
1859 + if (status4 & 1) {
1860 + writel(status4 & SWFQ_EMPTY_INT_BIT, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_4_REG);
1861 }
1862 +
1863 + toe_gmac_fill_free_q(5);
1864 + }
1865 +
1866 +#if 0
1867 + /* avoid races with hard_start_xmit() */
1868 +
1869 + spin_lock(&gmac_fq_lock);
1870 + toe_gmac_tx_complete(&toe_private_data.gmac[0], 0, dev, 1);
1871 + spin_unlock(&gmac_fq_lock);
1872 #endif
1873 - //rwptr.bits.rptr = RWPTR_ADVANCE_ONE(rwptr.bits.rptr, tp->default_desc_num);
1874 - //printk("%s:---Loop -------->rx_pkts_num=%d----rwptr.bits.rptr=0x%x-------->Default Queue HW RW ptr = (0x%8x), fq_rwptr =0x%8x \n",__func__,rx_pkts_num,rwptr.bits.rptr,rwptr.bits32,fq_rwptr.bits32 );
1875 - //printk("%s:---Loop rx_pkts_num=%d------rwptr.bits.rptr=0x%x------->Default_Q [rwptr.bits.rptr(SW)=0x%x, rwptr.bits.wptr(HW) = 0x%x ]---->Free_Q(SW_HW) = 0x%8x \n",__func__,rx_pkts_num,rwptr.bits.rptr,rwptr.bits.rptr,rwptr.bits.wptr,fq_rwptr.bits32 );
1876 +
1877 + status4 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_4_REG);
1878 + if (status4 & 1)
1879 + {
1880 + writel(status4 & SWFQ_EMPTY_INT_BIT, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_4_REG);
1881 + status4 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_4_REG);
1882 + toe_gmac_fill_free_q(rx_pkts_num);
1883 }
1884 - // advance one for Rx default Q 0/1
1885
1886 - //rwptr.bits.rptr = RWPTR_ADVANCE_ONE(rwptr.bits.rptr, tp->default_desc_num);
1887 - //SET_RPTR(&tp->default_qhdr->word1, rwptr.bits.rptr);
1888 - //tp->rx_rwptr.bits32 = rwptr.bits32;
1889 - //rwptr.bits.rptr = rwptr.bits.rptr;
1890 + rwptr.bits32 = readl(&tp->default_qhdr->word1);
1891 + if (rwptr.bits.rptr != rwptr.bits.wptr &&
1892 + quota > rx_pkts_num)
1893 + goto rx_poll_retry;
1894
1895 dev->quota -= rx_pkts_num;
1896 *budget -= rx_pkts_num;
1897
1898 - status4 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_4_REG);//try read SWFQ empty again
1899 - //fq_rwptr.bits32 = readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
1900 - rwptr.bits32 = readl(&tp->default_qhdr->word1); //try read default_qhdr again
1901 - //printk("%s:---After rx_pkts_num=%d------rwptr.bits.rptr=0x%x------->Default_Q [rwptr.bits.rptr(SW)=0x%x, rwptr.bits.wptr(HW) = 0x%x ]---->Free_Q(SW_HW) = 0x%8x \n",__func__,rx_pkts_num,rwptr.bits.rptr,rwptr.bits.rptr,rwptr.bits.wptr,fq_rwptr.bits32 );
1902 -// if (rwptr.bits.rptr > rwptr.bits.wptr )
1903 -// {
1904 - //toe_gmac_disable_rx(dev);
1905 - //wait_event_interruptible_timeout(freeq_wait,
1906 - //(rx_pkts_num == 100), CMTP_INTEROP_TIMEOUT);
1907 - //printk("\n%s:: return 22222=======> rx_pkts_num =%d, rwptr.bits.rptr=%d, rwptr.bits.wptr = %d ====---------=======>JKJKJKJKJK\n",
1908 - //__func__,rx_pkts_num,rwptr.bits.rptr,rwptr.bits.wptr);
1909 -// return 1;
1910 -// }
1911 -
1912 - if (rwptr.bits.rptr == rwptr.bits.wptr)
1913 + /* Receive queue is empty now */
1914 + if (quota >= rx_pkts_num)
1915 {
1916 - // unsigned int data32;
1917 - //printk("%s:---[rwptr.bits.rptr == rwptr.bits.wptr] rx_pkts_num=%d------rwptr.bits.rptr=0x%x------->Default_Q [rwptr.bits.rptr(SW)=0x%x, rwptr.bits.wptr(HW) = 0x%x ]---->Free_Q(SW_HW) = 0x%8x \n",__func__,rx_pkts_num,rwptr.bits.rptr,rwptr.bits.rptr,rwptr.bits.wptr,fq_rwptr.bits32 );
1918 -
1919 - /* Receive descriptor is empty now */
1920 -#if 1
1921 - if (status4 & 0x1)
1922 - {
1923 - do_again =1;
1924 - //writel(0x40400000, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_ENABLE_4_REG); //disable SWFQ empty interrupt
1925 - //toe_gmac_disable_interrupt(tp->irq);
1926 - tp->sw_fq_empty_cnt++;
1927 - //toe_gmac_disable_rx(dev);
1928 - writel(0x07960202, TOE_GMAC0_BASE+GMAC_CONFIG0);
1929 - writel(0x07960202, TOE_GMAC1_BASE+GMAC_CONFIG0);
1930 - //printk("\n%s :: freeq int-----tp->sw_fq_empty_cnt =%d---------====================----------------->\n",__func__,tp->sw_fq_empty_cnt);
1931 - //while ((fq_rwptr.bits.wptr >= (fq_rwptr.bits.rptr+256)) || (fq_rwptr.bits.wptr <= (fq_rwptr.bits.rptr+256)))
1932 - //{
1933 - //gmac_write_reg(TOE_GLOBAL_BASE, GLOBAL_INTERRUPT_STATUS_4_REG, status4,
1934 - //0x1);
1935 - //printk("\n%s::fq_rwptr.wrptr = %x =======> ===========>here \n", __func__,fq_rwptr.bits32);
1936 - //if ((status4 & 0x1) == 0)
1937 - //break;
1938 - return 1;
1939 - //}
1940 + unsigned long flags;
1941
1942 + netif_rx_complete(dev);
1943 + rx_poll_enabled = 0;
1944 +#if 0
1945 + status1 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_1_REG);
1946 + if (status1 & 1) {
1947 + if (netif_rx_reschedule(dev, rx_pkts_num)) {
1948 + rx_poll_enabled = 1;
1949 + return 1;
1950 }
1951 + }
1952 #endif
1953 - //toe_gmac_fill_free_q();
1954 - netif_rx_complete(dev);
1955 -
1956 - rx_poll_enabled = 0;
1957
1958 - data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
1959 - if (tp->port_id == 0)
1960 - data32 |= DEFAULT_Q0_INT_BIT;
1961 - else
1962 - data32 |= DEFAULT_Q1_INT_BIT;
1963 - writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
1964 + spin_lock_irqsave(&gmac_fq_lock, flags);
1965
1966 data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_4_REG);
1967 if (tp->port_id == 0)
1968 - data32 |= DEFAULT_Q0_INT_BIT;
1969 + data32 |= DEFAULT_Q0_INT_BIT;
1970 else
1971 - data32 |= DEFAULT_Q1_INT_BIT;
1972 + data32 |= DEFAULT_Q1_INT_BIT;
1973 writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_4_REG);
1974
1975 - data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG);
1976 + data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
1977 if (tp->port_id == 0)
1978 - data32 |= DEFAULT_Q0_INT_BIT;
1979 + data32 |= DEFAULT_Q0_INT_BIT;
1980 else
1981 - data32 |= DEFAULT_Q1_INT_BIT;
1982 - writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG);
1983 + data32 |= DEFAULT_Q1_INT_BIT;
1984 + writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
1985
1986 - // enable GMAC-0 rx interrupt
1987 - // class-Q & TOE-Q are implemented in future
1988 - //data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
1989 - //if (tp->port_id == 0)
1990 - //data32 |= DEFAULT_Q0_INT_BIT;
1991 - //else
1992 - //data32 |= DEFAULT_Q1_INT_BIT;
1993 - //writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
1994 - writel(0x3, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_ENABLE_1_REG);
1995 - //printk("\n%s::netif_rx_complete--> rx_pkts_num =%d, rwptr.bits.rptr=0x%x, rwptr.bits.wptr = 0x%x ====---------=======>JKJKJKJKJK\n",
1996 - //__func__,rx_pkts_num,rwptr.bits.rptr,rwptr.bits.wptr);
1997 - writel(0x07960200, TOE_GMAC0_BASE+GMAC_CONFIG0);
1998 - writel(0x07960200, TOE_GMAC1_BASE+GMAC_CONFIG0);
1999 - return 0;
2000 - }
2001 - else
2002 - {
2003 - //printk("\n%s:: return 1 -->status4= 0x%x,rx_pkts_num =%d, rwptr.bits.rptr=0x%x, rwptr.bits.wptr = 0x%x ======> \n", __func__,status4,rx_pkts_num,rwptr.bits.rptr,rwptr.bits.wptr);
2004 - return 1;
2005 - }
2006 + spin_unlock_irqrestore(&gmac_fq_lock, flags);
2007 +
2008 + return 0;
2009 + }
2010 + else
2011 + {
2012 + /* not done, will call ->poll() later. */
2013 + return 1;
2014 + }
2015 }
2016 #endif
2017
2018 @@ -5114,6 +4475,7 @@
2019 {
2020 sl351x_nat_workaround_cnt++;
2021 sl351x_nat_workaround_handler();
2022 + printk("%():%d - workaround\n", __func__, __LINE__);
2023 }
2024 #endif
2025 #endif
2026 @@ -5124,6 +4486,7 @@
2027 }
2028
2029 do_workaround:
2030 + printk("doing workaround ?!\n");
2031
2032 gmac_initialized = 0;
2033 if (hanged_state)
2034 @@ -5290,6 +4653,7 @@
2035 GMAC_SWTXQ_T *swtxq;
2036 DMA_RWPTR_T rwptr;
2037
2038 + printk("**** %s():%d\n", __func__, __LINE__);
2039 toe = (TOE_INFO_T *)&toe_private_data;
2040 tp = (GMAC_INFO_T *)&toe->gmac[0];
2041 for (i=0; i<GMAC_NUM; i++, tp++)
2042 @@ -5341,6 +4705,7 @@
2043 volatile GMAC_RXDESC_T *curr_desc;
2044 struct sk_buff *skb;
2045
2046 + printk("**** %s():%d\n", __func__, __LINE__);
2047 toe = (TOE_INFO_T *)&toe_private_data;
2048 tp = (GMAC_INFO_T *)&toe->gmac[0];
2049 for (i=0; i<GMAC_NUM; i++, tp++)
2050 @@ -5374,6 +4739,7 @@
2051 volatile GMAC_RXDESC_T *curr_desc;
2052 struct sk_buff *skb;
2053
2054 + printk("**** %s():%d\n", __func__, __LINE__);
2055 toe = (TOE_INFO_T *)&toe_private_data;
2056 classq = (CLASSQ_INFO_T *)&toe->classq[0];
2057 for (i=0; i<TOE_CLASS_QUEUE_NUM; i++, classq++)
2058 @@ -5410,6 +4776,7 @@
2059 GMAC_RXDESC_T *toe_curr_desc;
2060 struct sk_buff *skb;
2061
2062 + printk("**** %s():%d\n", __func__, __LINE__);
2063 toe = (TOE_INFO_T *)&toe_private_data;
2064 toe_qhdr = (TOE_QHDR_T *)TOE_TOE_QUE_HDR_BASE;
2065 for (i=0; i<TOE_TOE_QUEUE_NUM; i++, toe_qhdr++)
2066 --- a/include/asm-arm/arch-sl2312/sl351x_gmac.h
2067 +++ b/include/asm-arm/arch-sl2312/sl351x_gmac.h
2068 @@ -107,7 +107,7 @@
2069 * The base address and descriptor number are configured at
2070 * DMA Queues Descriptor Ring Base Address/Size Register (offset 0x0004)
2071 **********************************************************************/
2072 -#define TOE_SW_FREEQ_DESC_POWER 10
2073 +#define TOE_SW_FREEQ_DESC_POWER 8
2074 #define TOE_SW_FREEQ_DESC_NUM (1<<TOE_SW_FREEQ_DESC_POWER)
2075 #define TOE_HW_FREEQ_DESC_POWER 8
2076 #define TOE_HW_FREEQ_DESC_NUM (1<<TOE_HW_FREEQ_DESC_POWER)
2077 @@ -123,12 +123,12 @@
2078 #define TOE_DEFAULT_Q0_DESC_NUM (1<<TOE_DEFAULT_Q0_DESC_POWER)
2079 #define TOE_DEFAULT_Q1_DESC_POWER 8
2080 #define TOE_DEFAULT_Q1_DESC_NUM (1<<TOE_DEFAULT_Q1_DESC_POWER)
2081 -#define TOE_TOE_DESC_POWER 8
2082 -#define TOE_TOE_DESC_NUM (1<<TOE_TOE_DESC_POWER)
2083 +#define TOE_TOE_DESC_POWER 8
2084 +#define TOE_TOE_DESC_NUM (1<<TOE_TOE_DESC_POWER)
2085 #define TOE_CLASS_DESC_POWER 8
2086 -#define TOE_CLASS_DESC_NUM (1<<TOE_CLASS_DESC_POWER)
2087 -#define TOE_INTR_DESC_POWER 8
2088 -#define TOE_INTR_DESC_NUM (1<<TOE_INTR_DESC_POWER)
2089 +#define TOE_CLASS_DESC_NUM (1<<TOE_CLASS_DESC_POWER)
2090 +#define TOE_INTR_DESC_POWER 8
2091 +#define TOE_INTR_DESC_NUM (1<<TOE_INTR_DESC_POWER)
2092
2093 #define TOE_TOE_QUEUE_MAX 64
2094 #define TOE_TOE_QUEUE_NUM 64
OpenWrt Source Repository