target/linux/sunxi/patches-3.13/109-dt-sun6i-add-reset-ctrler.patch

   1 From f88dc0623908b574d9dcdae8815ccd0829fc6828 Mon Sep 17 00:00:00 2001
   2 From: Maxime Ripard <maxime.ripard@free-electrons.com>
   3 Date: Tue, 24 Sep 2013 11:10:41 +0300
   4 Subject: [PATCH] ARM: sun6i: Add the reset controller to the DTSI
   5
   6 The A31 has a reset controller IP that maintains a few other IPs in
   7 reset, among which we can find the UARTs, high speed timers or the I2C.
   8 Now that we have support for them, add the reset controllers to the DTSI.
   9
  10 Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
  11 Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
  12 ---
  13  arch/arm/boot/dts/sun6i-a31.dtsi | 24 ++++++++++++++++++++++++
  14  1 file changed, 24 insertions(+)
  15
  16 --- a/arch/arm/boot/dts/sun6i-a31.dtsi
  17 +++ b/arch/arm/boot/dts/sun6i-a31.dtsi
  18 @@ -212,6 +212,24 @@
  19                         };
  20                 };
  21
  22 +               ahb1_rst: reset@01c202c0 {
  23 +                       #reset-cells = <1>;
  24 +                       compatible = "allwinner,sun6i-a31-ahb1-reset";
  25 +                       reg = <0x01c202c0 0xc>;
  26 +               };
  27 +
  28 +               apb1_rst: reset@01c202d0 {
  29 +                       #reset-cells = <1>;
  30 +                       compatible = "allwinner,sun6i-a31-clock-reset";
  31 +                       reg = <0x01c202d0 0x4>;
  32 +               };
  33 +
  34 +               apb2_rst: reset@01c202d8 {
  35 +                       #reset-cells = <1>;
  36 +                       compatible = "allwinner,sun6i-a31-clock-reset";
  37 +                       reg = <0x01c202d8 0x4>;
  38 +               };
  39 +
  40                 timer@01c20c00 {
  41                         compatible = "allwinner,sun4i-timer";
  42                         reg = <0x01c20c00 0xa0>;
  43 @@ -235,6 +253,7 @@
  44                         reg-shift = <2>;
  45                         reg-io-width = <4>;
  46                         clocks = <&apb2_gates 16>;
  47 +                       resets = <&apb2_rst 16>;
  48                         status = "disabled";
  49                 };
  50
  51 @@ -245,6 +264,7 @@
  52                         reg-shift = <2>;
  53                         reg-io-width = <4>;
  54                         clocks = <&apb2_gates 17>;
  55 +                       resets = <&apb2_rst 17>;
  56                         status = "disabled";
  57                 };
  58
  59 @@ -255,6 +275,7 @@
  60                         reg-shift = <2>;
  61                         reg-io-width = <4>;
  62                         clocks = <&apb2_gates 18>;
  63 +                       resets = <&apb2_rst 18>;
  64                         status = "disabled";
  65                 };
  66
  67 @@ -265,6 +286,7 @@
  68                         reg-shift = <2>;
  69                         reg-io-width = <4>;
  70                         clocks = <&apb2_gates 19>;
  71 +                       resets = <&apb2_rst 19>;
  72                         status = "disabled";
  73                 };
  74
  75 @@ -275,6 +297,7 @@
  76                         reg-shift = <2>;
  77                         reg-io-width = <4>;
  78                         clocks = <&apb2_gates 20>;
  79 +                       resets = <&apb2_rst 20>;
  80                         status = "disabled";
  81                 };
  82
  83 @@ -285,6 +308,7 @@
  84                         reg-shift = <2>;
  85                         reg-io-width = <4>;
  86                         clocks = <&apb2_gates 21>;
  87 +                       resets = <&apb2_rst 21>;
  88                         status = "disabled";
  89                 };
  90