target/linux/sunxi/patches-3.13/116-clk-sunxi-add-pll4.patch

   1 From ff0b5fdb65bc7f10af7e83bb0919cb6bec2dc624 Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
   3 Date: Mon, 23 Dec 2013 00:32:35 -0300
   4 Subject: [PATCH] ARM: sunxi: add PLL4 support
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 This commit adds the PLL4 definition to the sun4i, sun5i and sun7i
  10 device trees. PLL4 is compatible with PLL1.
  11
  12 Signed-off-by: Emilio López <emilio@elopez.com.ar>
  13 Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
  14 ---
  15  arch/arm/boot/dts/sun4i-a10.dtsi  | 7 +++++++
  16  arch/arm/boot/dts/sun5i-a10s.dtsi | 7 +++++++
  17  arch/arm/boot/dts/sun5i-a13.dtsi  | 7 +++++++
  18  arch/arm/boot/dts/sun7i-a20.dtsi  | 7 +++++++
  19  4 files changed, 28 insertions(+)
  20
  21 diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
  22 index 0bf70ee..1d6346c 100644
  23 --- a/arch/arm/boot/dts/sun4i-a10.dtsi
  24 +++ b/arch/arm/boot/dts/sun4i-a10.dtsi
  25 @@ -70,6 +70,13 @@
  26                         clocks = <&osc24M>;
  27                 };
  28
  29 +               pll4: pll4@01c20018 {
  30 +                       #clock-cells = <0>;
  31 +                       compatible = "allwinner,sun4i-pll1-clk";
  32 +                       reg = <0x01c20018 0x4>;
  33 +                       clocks = <&osc24M>;
  34 +               };
  35 +
  36                 /* dummy is 200M */
  37                 cpu: cpu@01c20054 {
  38                         #clock-cells = <0>;
  39 diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
  40 index 924a2c1..64d6d75 100644
  41 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi
  42 +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
  43 @@ -67,6 +67,13 @@
  44                         clocks = <&osc24M>;
  45                 };
  46
  47 +               pll4: pll4@01c20018 {
  48 +                       #clock-cells = <0>;
  49 +                       compatible = "allwinner,sun4i-pll1-clk";
  50 +                       reg = <0x01c20018 0x4>;
  51 +                       clocks = <&osc24M>;
  52 +               };
  53 +
  54                 /* dummy is 200M */
  55                 cpu: cpu@01c20054 {
  56                         #clock-cells = <0>;
  57 diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
  58 index 1ccd75d..2c355c8 100644
  59 --- a/arch/arm/boot/dts/sun5i-a13.dtsi
  60 +++ b/arch/arm/boot/dts/sun5i-a13.dtsi
  61 @@ -67,6 +67,13 @@
  62                         clocks = <&osc24M>;
  63                 };
  64
  65 +               pll4: pll4@01c20018 {
  66 +                       #clock-cells = <0>;
  67 +                       compatible = "allwinner,sun4i-pll1-clk";
  68 +                       reg = <0x01c20018 0x4>;
  69 +                       clocks = <&osc24M>;
  70 +               };
  71 +
  72                 /* dummy is 200M */
  73                 cpu: cpu@01c20054 {
  74                         #clock-cells = <0>;
  75 diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
  76 index c74147a..18144f0 100644
  77 --- a/arch/arm/boot/dts/sun7i-a20.dtsi
  78 +++ b/arch/arm/boot/dts/sun7i-a20.dtsi
  79 @@ -66,6 +66,13 @@
  80                         clocks = <&osc24M>;
  81                 };
  82
  83 +               pll4: pll4@01c20018 {
  84 +                       #clock-cells = <0>;
  85 +                       compatible = "allwinner,sun4i-pll1-clk";
  86 +                       reg = <0x01c20018 0x4>;
  87 +                       clocks = <&osc24M>;
  88 +               };
  89 +
  90                 /*
  91                  * This is a dummy clock, to be used as placeholder on
  92                  * other mux clocks when a specific parent clock is not
  93 --
  94 1.8.5.1
  95