target/linux/sunxi/patches-3.13/122-1-dt-sun4i-add-mod0.patch

   1 From dda274b6f95902b619af1fb14f26e231bb420371 Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
   3 Date: Mon, 23 Dec 2013 00:32:41 -0300
   4 Subject: [PATCH] ARM: sun4i: dt: mod0 clocks
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 This commit adds all the mod0 clocks present on sun4i to its device tree
  10
  11 Signed-off-by: Emilio López <emilio@elopez.com.ar>
  12 Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
  13 ---
  14  arch/arm/boot/dts/sun4i-a10.dtsi | 120 +++++++++++++++++++++++++++++++++++++++
  15  1 file changed, 120 insertions(+)
  16
  17 --- a/arch/arm/boot/dts/sun4i-a10.dtsi
  18 +++ b/arch/arm/boot/dts/sun4i-a10.dtsi
  19 @@ -180,6 +180,126 @@
  20                                 "apb1_uart4", "apb1_uart5", "apb1_uart6",
  21                                 "apb1_uart7";
  22                 };
  23 +
  24 +               nand_clk: clk@01c20080 {
  25 +                       #clock-cells = <0>;
  26 +                       compatible = "allwinner,sun4i-mod0-clk";
  27 +                       reg = <0x01c20080 0x4>;
  28 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
  29 +                       clock-output-names = "nand";
  30 +               };
  31 +
  32 +               ms_clk: clk@01c20084 {
  33 +                       #clock-cells = <0>;
  34 +                       compatible = "allwinner,sun4i-mod0-clk";
  35 +                       reg = <0x01c20084 0x4>;
  36 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
  37 +                       clock-output-names = "ms";
  38 +               };
  39 +
  40 +               mmc0_clk: clk@01c20088 {
  41 +                       #clock-cells = <0>;
  42 +                       compatible = "allwinner,sun4i-mod0-clk";
  43 +                       reg = <0x01c20088 0x4>;
  44 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
  45 +                       clock-output-names = "mmc0";
  46 +               };
  47 +
  48 +               mmc1_clk: clk@01c2008c {
  49 +                       #clock-cells = <0>;
  50 +                       compatible = "allwinner,sun4i-mod0-clk";
  51 +                       reg = <0x01c2008c 0x4>;
  52 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
  53 +                       clock-output-names = "mmc1";
  54 +               };
  55 +
  56 +               mmc2_clk: clk@01c20090 {
  57 +                       #clock-cells = <0>;
  58 +                       compatible = "allwinner,sun4i-mod0-clk";
  59 +                       reg = <0x01c20090 0x4>;
  60 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
  61 +                       clock-output-names = "mmc2";
  62 +               };
  63 +
  64 +               mmc3_clk: clk@01c20094 {
  65 +                       #clock-cells = <0>;
  66 +                       compatible = "allwinner,sun4i-mod0-clk";
  67 +                       reg = <0x01c20094 0x4>;
  68 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
  69 +                       clock-output-names = "mmc3";
  70 +               };
  71 +
  72 +               ts_clk: clk@01c20098 {
  73 +                       #clock-cells = <0>;
  74 +                       compatible = "allwinner,sun4i-mod0-clk";
  75 +                       reg = <0x01c20098 0x4>;
  76 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
  77 +                       clock-output-names = "ts";
  78 +               };
  79 +
  80 +               ss_clk: clk@01c2009c {
  81 +                       #clock-cells = <0>;
  82 +                       compatible = "allwinner,sun4i-mod0-clk";
  83 +                       reg = <0x01c2009c 0x4>;
  84 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
  85 +                       clock-output-names = "ss";
  86 +               };
  87 +
  88 +               spi0_clk: clk@01c200a0 {
  89 +                       #clock-cells = <0>;
  90 +                       compatible = "allwinner,sun4i-mod0-clk";
  91 +                       reg = <0x01c200a0 0x4>;
  92 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
  93 +                       clock-output-names = "spi0";
  94 +               };
  95 +
  96 +               spi1_clk: clk@01c200a4 {
  97 +                       #clock-cells = <0>;
  98 +                       compatible = "allwinner,sun4i-mod0-clk";
  99 +                       reg = <0x01c200a4 0x4>;
 100 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 101 +                       clock-output-names = "spi1";
 102 +               };
 103 +
 104 +               spi2_clk: clk@01c200a8 {
 105 +                       #clock-cells = <0>;
 106 +                       compatible = "allwinner,sun4i-mod0-clk";
 107 +                       reg = <0x01c200a8 0x4>;
 108 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 109 +                       clock-output-names = "spi2";
 110 +               };
 111 +
 112 +               pata_clk: clk@01c200ac {
 113 +                       #clock-cells = <0>;
 114 +                       compatible = "allwinner,sun4i-mod0-clk";
 115 +                       reg = <0x01c200ac 0x4>;
 116 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 117 +                       clock-output-names = "pata";
 118 +               };
 119 +
 120 +               ir0_clk: clk@01c200b0 {
 121 +                       #clock-cells = <0>;
 122 +                       compatible = "allwinner,sun4i-mod0-clk";
 123 +                       reg = <0x01c200b0 0x4>;
 124 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 125 +                       clock-output-names = "ir0";
 126 +               };
 127 +
 128 +               ir1_clk: clk@01c200b4 {
 129 +                       #clock-cells = <0>;
 130 +                       compatible = "allwinner,sun4i-mod0-clk";
 131 +                       reg = <0x01c200b4 0x4>;
 132 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 133 +                       clock-output-names = "ir1";
 134 +               };
 135 +
 136 +               spi3_clk: clk@01c200d4 {
 137 +                       #clock-cells = <0>;
 138 +                       compatible = "allwinner,sun4i-mod0-clk";
 139 +                       reg = <0x01c200d4 0x4>;
 140 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 141 +                       clock-output-names = "spi3";
 142 +               };
 143         };
 144
 145         soc@01c00000 {