target/linux/sunxi/patches-3.13/127-1-dt-sun4i-rename-clock-node-names.patch

   1 From dfb12c0c35b6cca5e55f40870b65af87988adb3e Mon Sep 17 00:00:00 2001
   2 From: Chen-Yu Tsai <wens@csie.org>
   3 Date: Mon, 3 Feb 2014 09:51:41 +0800
   4 Subject: [PATCH] ARM: dts: sun4i: rename clock node names to clk@N
   5
   6 Device tree naming conventions state that node names should match
   7 node function. Change fully functioning clock nodes to match and
   8 add clock-output-names to all sunxi clock nodes.
   9
  10 Signed-off-by: Chen-Yu Tsai <wens@csie.org>
  11 Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
  12 ---
  13  arch/arm/boot/dts/sun4i-a10.dtsi | 30 ++++++++++++++++++++----------
  14  1 file changed, 20 insertions(+), 10 deletions(-)
  15
  16 diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
  17 index 28273f9..26cf191 100644
  18 --- a/arch/arm/boot/dts/sun4i-a10.dtsi
  19 +++ b/arch/arm/boot/dts/sun4i-a10.dtsi
  20 @@ -58,34 +58,38 @@
  21                         clock-frequency = <0>;
  22                 };
  23
  24 -               osc24M: osc24M@01c20050 {
  25 +               osc24M: clk@01c20050 {
  26                         #clock-cells = <0>;
  27                         compatible = "allwinner,sun4i-osc-clk";
  28                         reg = <0x01c20050 0x4>;
  29                         clock-frequency = <24000000>;
  30 +                       clock-output-names = "osc24M";
  31                 };
  32
  33 -               osc32k: osc32k {
  34 +               osc32k: clk@0 {
  35                         #clock-cells = <0>;
  36                         compatible = "fixed-clock";
  37                         clock-frequency = <32768>;
  38 +                       clock-output-names = "osc32k";
  39                 };
  40
  41 -               pll1: pll1@01c20000 {
  42 +               pll1: clk@01c20000 {
  43                         #clock-cells = <0>;
  44                         compatible = "allwinner,sun4i-pll1-clk";
  45                         reg = <0x01c20000 0x4>;
  46                         clocks = <&osc24M>;
  47 +                       clock-output-names = "pll1";
  48                 };
  49
  50 -               pll4: pll4@01c20018 {
  51 +               pll4: clk@01c20018 {
  52                         #clock-cells = <0>;
  53                         compatible = "allwinner,sun4i-pll1-clk";
  54                         reg = <0x01c20018 0x4>;
  55                         clocks = <&osc24M>;
  56 +                       clock-output-names = "pll4";
  57                 };
  58
  59 -               pll5: pll5@01c20020 {
  60 +               pll5: clk@01c20020 {
  61                         #clock-cells = <1>;
  62                         compatible = "allwinner,sun4i-pll5-clk";
  63                         reg = <0x01c20020 0x4>;
  64 @@ -93,7 +97,7 @@
  65                         clock-output-names = "pll5_ddr", "pll5_other";
  66                 };
  67
  68 -               pll6: pll6@01c20028 {
  69 +               pll6: clk@01c20028 {
  70                         #clock-cells = <1>;
  71                         compatible = "allwinner,sun4i-pll6-clk";
  72                         reg = <0x01c20028 0x4>;
  73 @@ -107,6 +111,7 @@
  74                         compatible = "allwinner,sun4i-cpu-clk";
  75                         reg = <0x01c20054 0x4>;
  76                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
  77 +                       clock-output-names = "cpu";
  78                 };
  79
  80                 axi: axi@01c20054 {
  81 @@ -114,9 +119,10 @@
  82                         compatible = "allwinner,sun4i-axi-clk";
  83                         reg = <0x01c20054 0x4>;
  84                         clocks = <&cpu>;
  85 +                       clock-output-names = "axi";
  86                 };
  87
  88 -               axi_gates: axi_gates@01c2005c {
  89 +               axi_gates: clk@01c2005c {
  90                         #clock-cells = <1>;
  91                         compatible = "allwinner,sun4i-axi-gates-clk";
  92                         reg = <0x01c2005c 0x4>;
  93 @@ -129,9 +135,10 @@
  94                         compatible = "allwinner,sun4i-ahb-clk";
  95                         reg = <0x01c20054 0x4>;
  96                         clocks = <&axi>;
  97 +                       clock-output-names = "ahb";
  98                 };
  99
 100 -               ahb_gates: ahb_gates@01c20060 {
 101 +               ahb_gates: clk@01c20060 {
 102                         #clock-cells = <1>;
 103                         compatible = "allwinner,sun4i-ahb-gates-clk";
 104                         reg = <0x01c20060 0x8>;
 105 @@ -154,9 +161,10 @@
 106                         compatible = "allwinner,sun4i-apb0-clk";
 107                         reg = <0x01c20054 0x4>;
 108                         clocks = <&ahb>;
 109 +                       clock-output-names = "apb0";
 110                 };
 111
 112 -               apb0_gates: apb0_gates@01c20068 {
 113 +               apb0_gates: clk@01c20068 {
 114                         #clock-cells = <1>;
 115                         compatible = "allwinner,sun4i-apb0-gates-clk";
 116                         reg = <0x01c20068 0x4>;
 117 @@ -171,6 +179,7 @@
 118                         compatible = "allwinner,sun4i-apb1-mux-clk";
 119                         reg = <0x01c20058 0x4>;
 120                         clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
 121 +                       clock-output-names = "apb1_mux";
 122                 };
 123
 124                 apb1: apb1@01c20058 {
 125 @@ -178,9 +187,10 @@
 126                         compatible = "allwinner,sun4i-apb1-clk";
 127                         reg = <0x01c20058 0x4>;
 128                         clocks = <&apb1_mux>;
 129 +                       clock-output-names = "apb1";
 130                 };
 131
 132 -               apb1_gates: apb1_gates@01c2006c {
 133 +               apb1_gates: clk@01c2006c {
 134                         #clock-cells = <1>;
 135                         compatible = "allwinner,sun4i-apb1-gates-clk";
 136                         reg = <0x01c2006c 0x4>;
 137 --
 138 1.8.5.5
 139