target/linux/sunxi/patches-3.13/127-2-dt-sun5i-rename-clock-node-names.patch

   1 From 3dce8324949eaa1ab4b750e8422ce78ddceb7aa4 Mon Sep 17 00:00:00 2001
   2 From: Chen-Yu Tsai <wens@csie.org>
   3 Date: Mon, 3 Feb 2014 09:51:42 +0800
   4 Subject: [PATCH] ARM: dts: sun5i: rename clock node names to clk@N
   5
   6 Device tree naming conventions state that node names should match
   7 node function. Change fully functioning clock nodes to match and
   8 add clock-output-names to all sunxi clock nodes.
   9
  10 Signed-off-by: Chen-Yu Tsai <wens@csie.org>
  11 Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
  12 ---
  13  arch/arm/boot/dts/sun5i-a10s.dtsi | 30 ++++++++++++++++++++----------
  14  arch/arm/boot/dts/sun5i-a13.dtsi  | 30 ++++++++++++++++++++----------
  15  2 files changed, 40 insertions(+), 20 deletions(-)
  16
  17 diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
  18 index 2318082..b114be7 100644
  19 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi
  20 +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
  21 @@ -51,34 +51,38 @@
  22                         clock-frequency = <0>;
  23                 };
  24
  25 -               osc24M: osc24M@01c20050 {
  26 +               osc24M: clk@01c20050 {
  27                         #clock-cells = <0>;
  28                         compatible = "allwinner,sun4i-osc-clk";
  29                         reg = <0x01c20050 0x4>;
  30                         clock-frequency = <24000000>;
  31 +                       clock-output-names = "osc24M";
  32                 };
  33
  34 -               osc32k: osc32k {
  35 +               osc32k: clk@0 {
  36                         #clock-cells = <0>;
  37                         compatible = "fixed-clock";
  38                         clock-frequency = <32768>;
  39 +                       clock-output-names = "osc32k";
  40                 };
  41
  42 -               pll1: pll1@01c20000 {
  43 +               pll1: clk@01c20000 {
  44                         #clock-cells = <0>;
  45                         compatible = "allwinner,sun4i-pll1-clk";
  46                         reg = <0x01c20000 0x4>;
  47                         clocks = <&osc24M>;
  48 +                       clock-output-names = "pll1";
  49                 };
  50
  51 -               pll4: pll4@01c20018 {
  52 +               pll4: clk@01c20018 {
  53                         #clock-cells = <0>;
  54                         compatible = "allwinner,sun4i-pll1-clk";
  55                         reg = <0x01c20018 0x4>;
  56                         clocks = <&osc24M>;
  57 +                       clock-output-names = "pll4";
  58                 };
  59
  60 -               pll5: pll5@01c20020 {
  61 +               pll5: clk@01c20020 {
  62                         #clock-cells = <1>;
  63                         compatible = "allwinner,sun4i-pll5-clk";
  64                         reg = <0x01c20020 0x4>;
  65 @@ -86,7 +90,7 @@
  66                         clock-output-names = "pll5_ddr", "pll5_other";
  67                 };
  68
  69 -               pll6: pll6@01c20028 {
  70 +               pll6: clk@01c20028 {
  71                         #clock-cells = <1>;
  72                         compatible = "allwinner,sun4i-pll6-clk";
  73                         reg = <0x01c20028 0x4>;
  74 @@ -100,6 +104,7 @@
  75                         compatible = "allwinner,sun4i-cpu-clk";
  76                         reg = <0x01c20054 0x4>;
  77                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
  78 +                       clock-output-names = "cpu";
  79                 };
  80
  81                 axi: axi@01c20054 {
  82 @@ -107,9 +112,10 @@
  83                         compatible = "allwinner,sun4i-axi-clk";
  84                         reg = <0x01c20054 0x4>;
  85                         clocks = <&cpu>;
  86 +                       clock-output-names = "axi";
  87                 };
  88
  89 -               axi_gates: axi_gates@01c2005c {
  90 +               axi_gates: clk@01c2005c {
  91                         #clock-cells = <1>;
  92                         compatible = "allwinner,sun4i-axi-gates-clk";
  93                         reg = <0x01c2005c 0x4>;
  94 @@ -122,9 +128,10 @@
  95                         compatible = "allwinner,sun4i-ahb-clk";
  96                         reg = <0x01c20054 0x4>;
  97                         clocks = <&axi>;
  98 +                       clock-output-names = "ahb";
  99                 };
 100
 101 -               ahb_gates: ahb_gates@01c20060 {
 102 +               ahb_gates: clk@01c20060 {
 103                         #clock-cells = <1>;
 104                         compatible = "allwinner,sun5i-a10s-ahb-gates-clk";
 105                         reg = <0x01c20060 0x8>;
 106 @@ -143,9 +150,10 @@
 107                         compatible = "allwinner,sun4i-apb0-clk";
 108                         reg = <0x01c20054 0x4>;
 109                         clocks = <&ahb>;
 110 +                       clock-output-names = "apb0";
 111                 };
 112
 113 -               apb0_gates: apb0_gates@01c20068 {
 114 +               apb0_gates: clk@01c20068 {
 115                         #clock-cells = <1>;
 116                         compatible = "allwinner,sun5i-a10s-apb0-gates-clk";
 117                         reg = <0x01c20068 0x4>;
 118 @@ -159,6 +167,7 @@
 119                         compatible = "allwinner,sun4i-apb1-mux-clk";
 120                         reg = <0x01c20058 0x4>;
 121                         clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
 122 +                       clock-output-names = "apb1_mux";
 123                 };
 124
 125                 apb1: apb1@01c20058 {
 126 @@ -166,9 +175,10 @@
 127                         compatible = "allwinner,sun4i-apb1-clk";
 128                         reg = <0x01c20058 0x4>;
 129                         clocks = <&apb1_mux>;
 130 +                       clock-output-names = "apb1";
 131                 };
 132
 133 -               apb1_gates: apb1_gates@01c2006c {
 134 +               apb1_gates: clk@01c2006c {
 135                         #clock-cells = <1>;
 136                         compatible = "allwinner,sun5i-a10s-apb1-gates-clk";
 137                         reg = <0x01c2006c 0x4>;
 138 diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
 139 index 6de40b6..5c121fc 100644
 140 --- a/arch/arm/boot/dts/sun5i-a13.dtsi
 141 +++ b/arch/arm/boot/dts/sun5i-a13.dtsi
 142 @@ -52,34 +52,38 @@
 143                         clock-frequency = <0>;
 144                 };
 145
 146 -               osc24M: osc24M@01c20050 {
 147 +               osc24M: clk@01c20050 {
 148                         #clock-cells = <0>;
 149                         compatible = "allwinner,sun4i-osc-clk";
 150                         reg = <0x01c20050 0x4>;
 151                         clock-frequency = <24000000>;
 152 +                       clock-output-names = "osc24M";
 153                 };
 154
 155 -               osc32k: osc32k {
 156 +               osc32k: clk@0 {
 157                         #clock-cells = <0>;
 158                         compatible = "fixed-clock";
 159                         clock-frequency = <32768>;
 160 +                       clock-output-names = "osc32k";
 161                 };
 162
 163 -               pll1: pll1@01c20000 {
 164 +               pll1: clk@01c20000 {
 165                         #clock-cells = <0>;
 166                         compatible = "allwinner,sun4i-pll1-clk";
 167                         reg = <0x01c20000 0x4>;
 168                         clocks = <&osc24M>;
 169 +                       clock-output-names = "pll1";
 170                 };
 171
 172 -               pll4: pll4@01c20018 {
 173 +               pll4: clk@01c20018 {
 174                         #clock-cells = <0>;
 175                         compatible = "allwinner,sun4i-pll1-clk";
 176                         reg = <0x01c20018 0x4>;
 177                         clocks = <&osc24M>;
 178 +                       clock-output-names = "pll4";
 179                 };
 180
 181 -               pll5: pll5@01c20020 {
 182 +               pll5: clk@01c20020 {
 183                         #clock-cells = <1>;
 184                         compatible = "allwinner,sun4i-pll5-clk";
 185                         reg = <0x01c20020 0x4>;
 186 @@ -87,7 +91,7 @@
 187                         clock-output-names = "pll5_ddr", "pll5_other";
 188                 };
 189
 190 -               pll6: pll6@01c20028 {
 191 +               pll6: clk@01c20028 {
 192                         #clock-cells = <1>;
 193                         compatible = "allwinner,sun4i-pll6-clk";
 194                         reg = <0x01c20028 0x4>;
 195 @@ -101,6 +105,7 @@
 196                         compatible = "allwinner,sun4i-cpu-clk";
 197                         reg = <0x01c20054 0x4>;
 198                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
 199 +                       clock-output-names = "cpu";
 200                 };
 201
 202                 axi: axi@01c20054 {
 203 @@ -108,9 +113,10 @@
 204                         compatible = "allwinner,sun4i-axi-clk";
 205                         reg = <0x01c20054 0x4>;
 206                         clocks = <&cpu>;
 207 +                       clock-output-names = "axi";
 208                 };
 209
 210 -               axi_gates: axi_gates@01c2005c {
 211 +               axi_gates: clk@01c2005c {
 212                         #clock-cells = <1>;
 213                         compatible = "allwinner,sun4i-axi-gates-clk";
 214                         reg = <0x01c2005c 0x4>;
 215 @@ -123,9 +129,10 @@
 216                         compatible = "allwinner,sun4i-ahb-clk";
 217                         reg = <0x01c20054 0x4>;
 218                         clocks = <&axi>;
 219 +                       clock-output-names = "ahb";
 220                 };
 221
 222 -               ahb_gates: ahb_gates@01c20060 {
 223 +               ahb_gates: clk@01c20060 {
 224                         #clock-cells = <1>;
 225                         compatible = "allwinner,sun5i-a13-ahb-gates-clk";
 226                         reg = <0x01c20060 0x8>;
 227 @@ -143,9 +150,10 @@
 228                         compatible = "allwinner,sun4i-apb0-clk";
 229                         reg = <0x01c20054 0x4>;
 230                         clocks = <&ahb>;
 231 +                       clock-output-names = "apb0";
 232                 };
 233
 234 -               apb0_gates: apb0_gates@01c20068 {
 235 +               apb0_gates: clk@01c20068 {
 236                         #clock-cells = <1>;
 237                         compatible = "allwinner,sun5i-a13-apb0-gates-clk";
 238                         reg = <0x01c20068 0x4>;
 239 @@ -158,6 +166,7 @@
 240                         compatible = "allwinner,sun4i-apb1-mux-clk";
 241                         reg = <0x01c20058 0x4>;
 242                         clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
 243 +                       clock-output-names = "apb1_mux";
 244                 };
 245
 246                 apb1: apb1@01c20058 {
 247 @@ -165,9 +174,10 @@
 248                         compatible = "allwinner,sun4i-apb1-clk";
 249                         reg = <0x01c20058 0x4>;
 250                         clocks = <&apb1_mux>;
 251 +                       clock-output-names = "apb1";
 252                 };
 253
 254 -               apb1_gates: apb1_gates@01c2006c {
 255 +               apb1_gates: clk@01c2006c {
 256                         #clock-cells = <1>;
 257                         compatible = "allwinner,sun5i-a13-apb1-gates-clk";
 258                         reg = <0x01c2006c 0x4>;
 259 --
 260 1.8.5.5
 261