target/linux/sunxi/patches-3.13/161-ahci-add-sunxi-to-ahci_platform.patch

   1 From 93dd2c512a24c552f1146d746aac112da7677430 Mon Sep 17 00:00:00 2001
   2 From: Olliver Schinagl <oliver@schinagl.nl>
   3 Date: Sat, 18 Jan 2014 15:00:45 +0100
   4 Subject: [PATCH] ARM: sunxi: Add support for Allwinner SUNXi SoCs sata to
   5  ahci_platform
   6
   7 This patch adds support for the ahci sata controler found on Allwinner A10
   8 and A20 SoCs to the ahci_platform driver.
   9
  10 Orignally written by Olliver Schinagl using the approach of having a platform
  11 device which probe method creates a new child platform device which gets
  12 driven by ahci_platform.c, as done by ahci_imx.c .
  13
  14 Refactored by Hans de Goede to add most of the non sunxi specific functionality
  15 to ahci_platform.c and use a platform_data pointer from of_device_id for the
  16 sunxi specific bits.
  17
  18 Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
  19 Signed-off-by: Hans de Goede <hdegoede@redhat.com>
  20 ---
  21  .../devicetree/bindings/ata/ahci-platform.txt      |  15 +-
  22  drivers/ata/Kconfig                                |   9 +
  23  drivers/ata/Makefile                               |   1 +
  24  drivers/ata/ahci_sunxi.c                           | 249 +++++++++++++++++++++
  25  4 files changed, 271 insertions(+), 3 deletions(-)
  26  create mode 100644 drivers/ata/ahci_sunxi.c
  27
  28 diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.txt b/Documentation/devicetree/bindings/ata/ahci-platform.txt
  29 index 1ac807f..499bfed 100644
  30 --- a/Documentation/devicetree/bindings/ata/ahci-platform.txt
  31 +++ b/Documentation/devicetree/bindings/ata/ahci-platform.txt
  32 @@ -4,7 +4,9 @@ SATA nodes are defined to describe on-chip Serial ATA controllers.
  33  Each SATA controller should have its own node.
  34
  35  Required properties:
  36 -- compatible        : compatible list, contains "snps,spear-ahci"
  37 +- compatible        : compatible list, one of "snps,spear-ahci",
  38 +                      "snps,exynos5440-ahci", "ibm,476gtr-ahci", or
  39 +                      "allwinner,sun4i-a10-ahci"
  40  - interrupts        : <interrupt mapping for SATA IRQ>
  41  - reg               : <registers mapping>
  42
  43 @@ -13,10 +15,17 @@ Optional properties:
  44  - clocks            : a list of phandle + clock specifier pairs
  45  - target-supply     : regulator for SATA target power
  46
  47 -Example:
  48 +Examples:
  49          sata@ffe08000 {
  50                 compatible = "snps,spear-ahci";
  51                 reg = <0xffe08000 0x1000>;
  52                 interrupts = <115>;
  53 -
  54          };
  55 +
  56 +       ahci: sata@01c18000 {
  57 +               compatible = "allwinner,sun4i-a10-ahci";
  58 +               reg = <0x01c18000 0x1000>;
  59 +               interrupts = <56>;
  60 +               clocks = <&pll6 0>, <&ahb_gates 25>;
  61 +               target-supply = <&reg_ahci_5v>;
  62 +       };
  63 diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
  64 index 4e73772..cc67cc0 100644
  65 --- a/drivers/ata/Kconfig
  66 +++ b/drivers/ata/Kconfig
  67 @@ -106,6 +106,15 @@ config AHCI_IMX
  68
  69           If unsure, say N.
  70
  71 +config AHCI_SUNXI
  72 +       tristate "Allwinner sunxi AHCI SATA support"
  73 +       depends on ARCH_SUNXI && SATA_AHCI_PLATFORM
  74 +       help
  75 +         This option enables support for the Allwinner sunxi SoC's
  76 +         onboard AHCI SATA.
  77 +
  78 +         If unsure, say N.
  79 +
  80  config SATA_FSL
  81         tristate "Freescale 3.0Gbps SATA support"
  82         depends on FSL_SOC
  83 diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
  84 index 46518c6..246050b 100644
  85 --- a/drivers/ata/Makefile
  86 +++ b/drivers/ata/Makefile
  87 @@ -11,6 +11,7 @@ obj-$(CONFIG_SATA_SIL24)      += sata_sil24.o
  88  obj-$(CONFIG_SATA_DWC)         += sata_dwc_460ex.o
  89  obj-$(CONFIG_SATA_HIGHBANK)    += sata_highbank.o libahci.o
  90  obj-$(CONFIG_AHCI_IMX)         += ahci_imx.o
  91 +obj-$(CONFIG_AHCI_SUNXI)       += ahci_sunxi.o
  92
  93  # SFF w/ custom DMA
  94  obj-$(CONFIG_PDC_ADMA)         += pdc_adma.o
  95 diff --git a/drivers/ata/ahci_sunxi.c b/drivers/ata/ahci_sunxi.c
  96 new file mode 100644
  97 index 0000000..001f7dfc
  98 --- /dev/null
  99 +++ b/drivers/ata/ahci_sunxi.c
 100 @@ -0,0 +1,249 @@
 101 +/*
 102 + * Allwinner sunxi AHCI SATA platform driver
 103 + * Copyright 2013 Olliver Schinagl <oliver@schinagl.nl>
 104 + * Copyright 2014 Hans de Goede <hdegoede@redhat.com>
 105 + *
 106 + * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
 107 + * Based on code from Allwinner Technology Co., Ltd. <www.allwinnertech.com>,
 108 + * Daniel Wang <danielwang@allwinnertech.com>
 109 + *
 110 + * This program is free software; you can redistribute it and/or modify it
 111 + * under the terms and conditions of the GNU General Public License,
 112 + * version 2, as published by the Free Software Foundation.
 113 + *
 114 + * This program is distributed in the hope it will be useful, but WITHOUT
 115 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 116 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
 117 + * more details.
 118 + */
 119 +
 120 +#include <linux/ahci_platform.h>
 121 +#include <linux/clk.h>
 122 +#include <linux/errno.h>
 123 +#include <linux/kernel.h>
 124 +#include <linux/module.h>
 125 +#include <linux/of_device.h>
 126 +#include <linux/platform_device.h>
 127 +#include <linux/regulator/consumer.h>
 128 +#include "ahci.h"
 129 +
 130 +#define AHCI_BISTAFR 0x00a0
 131 +#define AHCI_BISTCR 0x00a4
 132 +#define AHCI_BISTFCTR 0x00a8
 133 +#define AHCI_BISTSR 0x00ac
 134 +#define AHCI_BISTDECR 0x00b0
 135 +#define AHCI_DIAGNR0 0x00b4
 136 +#define AHCI_DIAGNR1 0x00b8
 137 +#define AHCI_OOBR 0x00bc
 138 +#define AHCI_PHYCS0R 0x00c0
 139 +#define AHCI_PHYCS1R 0x00c4
 140 +#define AHCI_PHYCS2R 0x00c8
 141 +#define AHCI_TIMER1MS 0x00e0
 142 +#define AHCI_GPARAM1R 0x00e8
 143 +#define AHCI_GPARAM2R 0x00ec
 144 +#define AHCI_PPARAMR 0x00f0
 145 +#define AHCI_TESTR 0x00f4
 146 +#define AHCI_VERSIONR 0x00f8
 147 +#define AHCI_IDR 0x00fc
 148 +#define AHCI_RWCR 0x00fc
 149 +#define AHCI_P0DMACR 0x0170
 150 +#define AHCI_P0PHYCR 0x0178
 151 +#define AHCI_P0PHYSR 0x017c
 152 +
 153 +static void sunxi_clrbits(void __iomem *reg, u32 clr_val)
 154 +{
 155 +       u32 reg_val;
 156 +
 157 +       reg_val = readl(reg);
 158 +       reg_val &= ~(clr_val);
 159 +       writel(reg_val, reg);
 160 +}
 161 +
 162 +static void sunxi_setbits(void __iomem *reg, u32 set_val)
 163 +{
 164 +       u32 reg_val;
 165 +
 166 +       reg_val = readl(reg);
 167 +       reg_val |= set_val;
 168 +       writel(reg_val, reg);
 169 +}
 170 +
 171 +static void sunxi_clrsetbits(void __iomem *reg, u32 clr_val, u32 set_val)
 172 +{
 173 +       u32 reg_val;
 174 +
 175 +       reg_val = readl(reg);
 176 +       reg_val &= ~(clr_val);
 177 +       reg_val |= set_val;
 178 +       writel(reg_val, reg);
 179 +}
 180 +
 181 +static u32 sunxi_getbits(void __iomem *reg, u8 mask, u8 shift)
 182 +{
 183 +       return (readl(reg) >> shift) & mask;
 184 +}
 185 +
 186 +static int ahci_sunxi_phy_init(struct device *dev, void __iomem *reg_base)
 187 +{
 188 +       u32 reg_val;
 189 +       int timeout;
 190 +
 191 +       /* This magic is from the original code */
 192 +       writel(0, reg_base + AHCI_RWCR);
 193 +       mdelay(5);
 194 +
 195 +       sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(19));
 196 +       sunxi_clrsetbits(reg_base + AHCI_PHYCS0R,
 197 +                        (0x7 << 24),
 198 +                        (0x5 << 24) | BIT(23) | BIT(18));
 199 +       sunxi_clrsetbits(reg_base + AHCI_PHYCS1R,
 200 +                        (0x3 << 16) | (0x1f << 8) | (0x3 << 6),
 201 +                        (0x2 << 16) | (0x6 << 8) | (0x2 << 6));
 202 +       sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(28) | BIT(15));
 203 +       sunxi_clrbits(reg_base + AHCI_PHYCS1R, BIT(19));
 204 +       sunxi_clrsetbits(reg_base + AHCI_PHYCS0R,
 205 +                        (0x7 << 20), (0x3 << 20));
 206 +       sunxi_clrsetbits(reg_base + AHCI_PHYCS2R,
 207 +                        (0x1f << 5), (0x19 << 5));
 208 +       mdelay(5);
 209 +
 210 +       sunxi_setbits(reg_base + AHCI_PHYCS0R, (0x1 << 19));
 211 +
 212 +       timeout = 250; /* Power up takes aprox 50 us */
 213 +       do {
 214 +               reg_val = sunxi_getbits(reg_base + AHCI_PHYCS0R, 0x7, 28);
 215 +               if (reg_val == 0x02)
 216 +                       break;
 217 +
 218 +               if (--timeout == 0) {
 219 +                       dev_err(dev, "PHY power up failed.\n");
 220 +                       return -EIO;
 221 +               }
 222 +               udelay(1);
 223 +       } while (1);
 224 +
 225 +       sunxi_setbits(reg_base + AHCI_PHYCS2R, (0x1 << 24));
 226 +
 227 +       timeout = 100; /* Calibration takes aprox 10 us */
 228 +       do {
 229 +               reg_val = sunxi_getbits(reg_base + AHCI_PHYCS2R, 0x1, 24);
 230 +               if (reg_val == 0x00)
 231 +                       break;
 232 +
 233 +               if (--timeout == 0) {
 234 +                       dev_err(dev, "PHY calibration failed.\n");
 235 +                       return -EIO;
 236 +               }
 237 +               udelay(1);
 238 +       } while (1);
 239 +
 240 +       mdelay(15);
 241 +
 242 +       writel(0x7, reg_base + AHCI_RWCR);
 243 +
 244 +       return 0;
 245 +}
 246 +
 247 +static void ahci_sunxi_start_engine(struct ata_port *ap)
 248 +{
 249 +       void __iomem *port_mmio = ahci_port_base(ap);
 250 +       struct ahci_host_priv *hpriv = ap->host->private_data;
 251 +
 252 +       /* Setup DMA before DMA start */
 253 +       sunxi_clrsetbits(hpriv->mmio + AHCI_P0DMACR, 0x0000ff00, 0x00004400);
 254 +
 255 +       /* Start DMA */
 256 +       sunxi_setbits(port_mmio + PORT_CMD, PORT_CMD_START);
 257 +}
 258 +
 259 +static const struct ata_port_info ahci_sunxi_port_info = {
 260 +       AHCI_HFLAGS(AHCI_HFLAG_32BIT_ONLY | AHCI_HFLAG_NO_MSI |
 261 +                         AHCI_HFLAG_NO_PMP | AHCI_HFLAG_YES_NCQ),
 262 +       .flags          = AHCI_FLAG_COMMON | ATA_FLAG_NCQ,
 263 +       .pio_mask       = ATA_PIO4,
 264 +       .udma_mask      = ATA_UDMA6,
 265 +       .port_ops       = &ahci_platform_ops,
 266 +};
 267 +
 268 +static int ahci_sunxi_probe(struct platform_device *pdev)
 269 +{
 270 +       struct device *dev = &pdev->dev;
 271 +       struct ahci_host_priv *hpriv;
 272 +       int rc;
 273 +
 274 +       hpriv = ahci_platform_get_resources(pdev);
 275 +       if (IS_ERR(hpriv))
 276 +               return PTR_ERR(hpriv);
 277 +
 278 +       hpriv->start_engine = ahci_sunxi_start_engine;
 279 +
 280 +       rc = ahci_platform_enable_resources(hpriv);
 281 +       if (rc)
 282 +               return rc;
 283 +
 284 +       rc = ahci_sunxi_phy_init(dev, hpriv->mmio);
 285 +       if (rc)
 286 +               goto disable_resources;
 287 +
 288 +       rc = ahci_platform_init_host(pdev, hpriv, &ahci_sunxi_port_info, 0, 0);
 289 +       if (rc)
 290 +               goto disable_resources;
 291 +
 292 +       return 0;
 293 +
 294 +disable_resources:
 295 +       ahci_platform_disable_resources(hpriv);
 296 +       return rc;
 297 +}
 298 +
 299 +#ifdef CONFIG_PM_SLEEP
 300 +int ahci_sunxi_resume(struct device *dev)
 301 +{
 302 +       struct ata_host *host = dev_get_drvdata(dev);
 303 +       struct ahci_host_priv *hpriv = host->private_data;
 304 +       int rc;
 305 +
 306 +       rc = ahci_platform_enable_resources(hpriv);
 307 +       if (rc)
 308 +               return rc;
 309 +
 310 +       rc = ahci_sunxi_phy_init(dev, hpriv->mmio);
 311 +       if (rc)
 312 +               goto disable_resources;
 313 +
 314 +       rc = ahci_platform_resume_host(dev);
 315 +       if (rc)
 316 +               goto disable_resources;
 317 +
 318 +       return 0;
 319 +
 320 +disable_resources:
 321 +       ahci_platform_disable_resources(hpriv);
 322 +       return rc;
 323 +}
 324 +#endif
 325 +
 326 +static SIMPLE_DEV_PM_OPS(ahci_sunxi_pm_ops, ahci_platform_suspend,
 327 +                        ahci_sunxi_resume);
 328 +
 329 +static const struct of_device_id ahci_sunxi_of_match[] = {
 330 +       { .compatible = "allwinner,sun4i-a10-ahci", },
 331 +       { },
 332 +};
 333 +MODULE_DEVICE_TABLE(of, ahci_sunxi_of_match);
 334 +
 335 +static struct platform_driver ahci_sunxi_driver = {
 336 +       .probe = ahci_sunxi_probe,
 337 +       .remove = ata_platform_remove_one,
 338 +       .driver = {
 339 +               .name = "ahci-sunxi",
 340 +               .owner = THIS_MODULE,
 341 +               .of_match_table = ahci_sunxi_of_match,
 342 +               .pm = &ahci_sunxi_pm_ops,
 343 +       },
 344 +};
 345 +module_platform_driver(ahci_sunxi_driver);
 346 +
 347 +MODULE_DESCRIPTION("Allwinner sunxi AHCI SATA driver");
 348 +MODULE_AUTHOR("Olliver Schinagl <oliver@schinagl.nl>");
 349 +MODULE_LICENSE("GPL");
 350 --
 351 1.8.5.5
 352