target/linux/sunxi/patches-3.13/161-sunxi-ahci-add-driver.patch

   1 From 22345cc059de4a6ea1dc7657dd6ad86ca16a8814 Mon Sep 17 00:00:00 2001
   2 From: Oliver Schinagl <oliver@schinagl.nl>
   3 Date: Tue, 3 Dec 2013 12:07:01 +0100
   4 Subject: [PATCH] ARM: sunxi: Add ahci-sunxi driver for the Allwinner SUNXi
   5  SoCs sata
   6
   7 This patch adds support for the ahci sata controler found on Allwinner A10
   8 and A20 SoCs.
   9
  10 Orignally written by Olliver Schinagl using the approach of having a platform
  11 device which probe method creates a new child platform device which gets
  12 driven by ahci_platform.c, as done by ahci_imx.c .
  13
  14 Given that almost all functionality already is shared through libahci /
  15 ata-core, and that ahci_platform.c cannot cleanly handle somewhat more complex
  16 platform specific ahci cases, such as the sunxi case, it was refactored into
  17 a stand-alone platform driver by Hans de Goede.
  18
  19 Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
  20 Signed-off-by: Hans de Goede <hdegoede@redhat.com>
  21 ---
  22  .../devicetree/bindings/ata/ahci-sunxi.txt         |  24 ++
  23  drivers/ata/Kconfig                                |   9 +
  24  drivers/ata/Makefile                               |   1 +
  25  drivers/ata/ahci_sunxi.c                           | 349 +++++++++++++++++++++
  26  4 files changed, 383 insertions(+)
  27  create mode 100644 Documentation/devicetree/bindings/ata/ahci-sunxi.txt
  28  create mode 100644 drivers/ata/ahci_sunxi.c
  29
  30 --- /dev/null
  31 +++ b/Documentation/devicetree/bindings/ata/ahci-sunxi.txt
  32 @@ -0,0 +1,24 @@
  33 +Allwinner SUNXI AHCI SATA Controller
  34 +
  35 +SATA nodes are defined to describe on-chip Serial ATA controllers.
  36 +Each SATA controller should have its own node.
  37 +
  38 +Required properties:
  39 +- compatible   : compatible list, contains "allwinner,sun4i-a10-ahci"
  40 +- reg          : <registers mapping>
  41 +- interrupts   : <interrupt mapping for AHCI IRQ>
  42 +- clocks       : clocks for ACHI
  43 +- clock-names  : clock names for AHCI
  44 +
  45 +Optional properties:
  46 +- pwr-supply   : regulator to control the power supply GPIO
  47 +
  48 +Example:
  49 +       ahci@01c18000 {
  50 +               compatible = "allwinner,sun4i-a10-ahci";
  51 +               reg = <0x01c18000 0x1000>;
  52 +               interrupts = <0 56 1>;
  53 +               clocks = <&ahb_gates 25>, <&pll6 0>;
  54 +               clock-names = "ahb_sata", "pll6_sata";
  55 +               pwr-supply = <&reg_ahci_5v>;
  56 +       };
  57 --- a/drivers/ata/Kconfig
  58 +++ b/drivers/ata/Kconfig
  59 @@ -106,6 +106,15 @@ config AHCI_IMX
  60
  61           If unsure, say N.
  62
  63 +config AHCI_SUNXI
  64 +       tristate "Allwinner sunxi AHCI SATA support"
  65 +       depends on ARCH_SUNXI
  66 +       help
  67 +         This option enables support for the Allwinner sunxi SoC's
  68 +         onboard AHCI SATA.
  69 +
  70 +         If unsure, say N.
  71 +
  72  config SATA_FSL
  73         tristate "Freescale 3.0Gbps SATA support"
  74         depends on FSL_SOC
  75 --- a/drivers/ata/Makefile
  76 +++ b/drivers/ata/Makefile
  77 @@ -11,6 +11,7 @@ obj-$(CONFIG_SATA_SIL24)      += sata_sil24.o
  78  obj-$(CONFIG_SATA_DWC)         += sata_dwc_460ex.o
  79  obj-$(CONFIG_SATA_HIGHBANK)    += sata_highbank.o libahci.o
  80  obj-$(CONFIG_AHCI_IMX)         += ahci_imx.o
  81 +obj-$(CONFIG_AHCI_SUNXI)       += ahci_sunxi.o libahci.o
  82
  83  # SFF w/ custom DMA
  84  obj-$(CONFIG_PDC_ADMA)         += pdc_adma.o
  85 --- /dev/null
  86 +++ b/drivers/ata/ahci_sunxi.c
  87 @@ -0,0 +1,349 @@
  88 +/*
  89 + * Allwinner sunxi AHCI SATA platform driver
  90 + * Copyright 2013 Olliver Schinagl <oliver@schinagl.nl>
  91 + * Copyright 2014 Hans de Goede <hdegoede@redhat.com>
  92 + *
  93 + * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
  94 + * Based on code from Allwinner Technology Co., Ltd. <www.allwinnertech.com>,
  95 + * Daniel Wang <danielwang@allwinnertech.com>
  96 + *
  97 + * This program is free software; you can redistribute it and/or modify it
  98 + * under the terms and conditions of the GNU General Public License,
  99 + * version 2, as published by the Free Software Foundation.
 100 + *
 101 + * This program is distributed in the hope it will be useful, but WITHOUT
 102 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 103 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
 104 + * more details.
 105 + */
 106 +
 107 +#include <linux/clk.h>
 108 +#include <linux/errno.h>
 109 +#include <linux/kernel.h>
 110 +#include <linux/module.h>
 111 +#include <linux/of_device.h>
 112 +#include <linux/platform_device.h>
 113 +#include <linux/regulator/consumer.h>
 114 +#include "ahci.h"
 115 +
 116 +#define AHCI_BISTAFR 0x00a0
 117 +#define AHCI_BISTCR 0x00a4
 118 +#define AHCI_BISTFCTR 0x00a8
 119 +#define AHCI_BISTSR 0x00ac
 120 +#define AHCI_BISTDECR 0x00b0
 121 +#define AHCI_DIAGNR0 0x00b4
 122 +#define AHCI_DIAGNR1 0x00b8
 123 +#define AHCI_OOBR 0x00bc
 124 +#define AHCI_PHYCS0R 0x00c0
 125 +#define AHCI_PHYCS1R 0x00c4
 126 +#define AHCI_PHYCS2R 0x00c8
 127 +#define AHCI_TIMER1MS 0x00e0
 128 +#define AHCI_GPARAM1R 0x00e8
 129 +#define AHCI_GPARAM2R 0x00ec
 130 +#define AHCI_PPARAMR 0x00f0
 131 +#define AHCI_TESTR 0x00f4
 132 +#define AHCI_VERSIONR 0x00f8
 133 +#define AHCI_IDR 0x00fc
 134 +#define AHCI_RWCR 0x00fc
 135 +#define AHCI_P0DMACR 0x0170
 136 +#define AHCI_P0PHYCR 0x0178
 137 +#define AHCI_P0PHYSR 0x017c
 138 +
 139 +struct sunxi_ahci {
 140 +       struct ahci_host_priv hpriv;
 141 +       struct regulator *pwr;
 142 +       struct clk *sata_clk;
 143 +       struct clk *ahb_clk;
 144 +};
 145 +
 146 +static void sunxi_clrbits(void __iomem *reg, u32 clr_val)
 147 +{
 148 +       u32 reg_val;
 149 +
 150 +       reg_val = readl(reg);
 151 +       reg_val &= ~(clr_val);
 152 +       writel(reg_val, reg);
 153 +}
 154 +
 155 +static void sunxi_setbits(void __iomem *reg, u32 set_val)
 156 +{
 157 +       u32 reg_val;
 158 +
 159 +       reg_val = readl(reg);
 160 +       reg_val |= set_val;
 161 +       writel(reg_val, reg);
 162 +}
 163 +
 164 +static void sunxi_clrsetbits(void __iomem *reg, u32 clr_val, u32 set_val)
 165 +{
 166 +       u32 reg_val;
 167 +
 168 +       reg_val = readl(reg);
 169 +       reg_val &= ~(clr_val);
 170 +       reg_val |= set_val;
 171 +       writel(reg_val, reg);
 172 +}
 173 +
 174 +static u32 sunxi_getbits(void __iomem *reg, u8 mask, u8 shift)
 175 +{
 176 +       return (readl(reg) >> shift) & mask;
 177 +}
 178 +
 179 +static int sunxi_ahci_phy_init(struct device *dev, void __iomem *reg_base)
 180 +{
 181 +       u32 reg_val;
 182 +       int timeout;
 183 +
 184 +       /* This magic is from the original code */
 185 +       writel(0, reg_base + AHCI_RWCR);
 186 +       mdelay(5);
 187 +
 188 +       sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(19));
 189 +       sunxi_clrsetbits(reg_base + AHCI_PHYCS0R,
 190 +                        (0x7 << 24),
 191 +                        (0x5 << 24) | BIT(23) | BIT(18));
 192 +       sunxi_clrsetbits(reg_base + AHCI_PHYCS1R,
 193 +                        (0x3 << 16) | (0x1f << 8) | (0x3 << 6),
 194 +                        (0x2 << 16) | (0x6 << 8) | (0x2 << 6));
 195 +       sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(28) | BIT(15));
 196 +       sunxi_clrbits(reg_base + AHCI_PHYCS1R, BIT(19));
 197 +       sunxi_clrsetbits(reg_base + AHCI_PHYCS0R,
 198 +                        (0x7 << 20), (0x3 << 20));
 199 +       sunxi_clrsetbits(reg_base + AHCI_PHYCS2R,
 200 +                        (0x1f << 5), (0x19 << 5));
 201 +       mdelay(5);
 202 +
 203 +       sunxi_setbits(reg_base + AHCI_PHYCS0R, (0x1 << 19));
 204 +
 205 +       timeout = 0x100000;
 206 +       do {
 207 +               reg_val = sunxi_getbits(reg_base + AHCI_PHYCS0R, 0x7, 28);
 208 +       } while (--timeout && (reg_val != 0x2));
 209 +       if (!timeout) {
 210 +               dev_err(dev, "PHY power up failed.\n");
 211 +               return -EIO;
 212 +       }
 213 +
 214 +       sunxi_setbits(reg_base + AHCI_PHYCS2R, (0x1 << 24));
 215 +
 216 +       timeout = 0x100000;
 217 +       do {
 218 +               reg_val = sunxi_getbits(reg_base + AHCI_PHYCS2R, 0x1, 24);
 219 +       } while (--timeout && reg_val);
 220 +       if (!timeout) {
 221 +               dev_err(dev, "PHY calibration failed.\n");
 222 +               return -EIO;
 223 +       }
 224 +       mdelay(15);
 225 +
 226 +       writel(0x7, reg_base + AHCI_RWCR);
 227 +
 228 +       return 0;
 229 +}
 230 +
 231 +void sunxi_ahci_pre_start_engine(struct ata_port *ap)
 232 +{
 233 +       struct ahci_host_priv *hpriv = ap->host->private_data;
 234 +
 235 +       /* Setup DMA before DMA start */
 236 +       sunxi_clrsetbits(hpriv->mmio + AHCI_P0DMACR, 0x0000ff00, 0x00004400);
 237 +}
 238 +
 239 +static int sunxi_ahci_enable_clks(struct sunxi_ahci *ahci)
 240 +{
 241 +       int ret;
 242 +
 243 +       ret = clk_prepare_enable(ahci->sata_clk);
 244 +       if (ret)
 245 +               return ret;
 246 +
 247 +       ret = clk_prepare_enable(ahci->ahb_clk);
 248 +       if (ret)
 249 +               clk_disable_unprepare(ahci->sata_clk);
 250 +
 251 +       return ret;
 252 +}
 253 +
 254 +static void sunxi_ahci_disable_clks(struct sunxi_ahci *ahci)
 255 +{
 256 +       clk_disable_unprepare(ahci->ahb_clk);
 257 +       clk_disable_unprepare(ahci->sata_clk);
 258 +}
 259 +
 260 +static void sunxi_ahci_host_stop(struct ata_host *host)
 261 +{
 262 +       struct ahci_host_priv *hpriv = host->private_data;
 263 +       struct sunxi_ahci *ahci = hpriv->plat_data;
 264 +
 265 +       if (!IS_ERR(ahci->pwr))
 266 +               regulator_disable(ahci->pwr);
 267 +
 268 +       sunxi_ahci_disable_clks(ahci);
 269 +}
 270 +
 271 +static struct ata_port_operations sunxi_ahci_platform_ops = {
 272 +       .inherits       = &ahci_ops,
 273 +       .host_stop      = sunxi_ahci_host_stop,
 274 +};
 275 +
 276 +static const struct ata_port_info sunxiahci_port_info = {
 277 +       AHCI_HFLAGS(AHCI_HFLAG_32BIT_ONLY | AHCI_HFLAG_NO_MSI |
 278 +                         AHCI_HFLAG_NO_PMP | AHCI_HFLAG_YES_NCQ),
 279 +       .flags          = AHCI_FLAG_COMMON | ATA_FLAG_NCQ,
 280 +       .pio_mask       = ATA_PIO4,
 281 +       .udma_mask      = ATA_UDMA6,
 282 +       .port_ops       = &sunxi_ahci_platform_ops,
 283 +};
 284 +
 285 +static struct scsi_host_template sunxi_ahci_platform_sht = {
 286 +       AHCI_SHT("sunxi_ahci"),
 287 +};
 288 +
 289 +static int sunxi_ahci_probe(struct platform_device *pdev)
 290 +{
 291 +       struct device *dev = &pdev->dev;
 292 +       const struct ata_port_info *ppi[] = { &sunxiahci_port_info, NULL };
 293 +       struct sunxi_ahci *ahci;
 294 +       struct ata_host *host;
 295 +       int ret;
 296 +
 297 +       ahci = devm_kzalloc(&pdev->dev, sizeof(*ahci), GFP_KERNEL);
 298 +       if (!ahci)
 299 +               return -ENOMEM;
 300 +
 301 +       ahci->pwr = devm_regulator_get_optional(dev, "pwr");
 302 +       if (IS_ERR(ahci->pwr) && PTR_ERR(ahci->pwr) == -EPROBE_DEFER)
 303 +               return -EPROBE_DEFER;
 304 +
 305 +       host = ata_host_alloc_pinfo(dev, ppi, 1);
 306 +       if (!host)
 307 +               return -ENOMEM;
 308 +
 309 +       host->private_data = &ahci->hpriv;
 310 +       host->flags |= ATA_HOST_PARALLEL_SCAN;
 311 +
 312 +       ahci->hpriv.flags = (unsigned long)ppi[0]->private_data;
 313 +       ahci->hpriv.plat_data = ahci;
 314 +       ahci->hpriv.pre_start_engine = sunxi_ahci_pre_start_engine;
 315 +       ahci->hpriv.mmio = devm_ioremap_resource(dev,
 316 +                             platform_get_resource(pdev, IORESOURCE_MEM, 0));
 317 +       if (IS_ERR(ahci->hpriv.mmio))
 318 +               return PTR_ERR(ahci->hpriv.mmio);
 319 +
 320 +       ahci->ahb_clk = devm_clk_get(&pdev->dev, "ahb_sata");
 321 +       if (IS_ERR(ahci->ahb_clk))
 322 +               return PTR_ERR(ahci->ahb_clk);
 323 +
 324 +       ahci->sata_clk = devm_clk_get(&pdev->dev, "pll6_sata");
 325 +       if (IS_ERR(ahci->sata_clk))
 326 +               return PTR_ERR(ahci->sata_clk);
 327 +
 328 +       ret = sunxi_ahci_enable_clks(ahci);
 329 +       if (ret)
 330 +               return ret;
 331 +
 332 +       if (!IS_ERR(ahci->pwr)) {
 333 +               ret = regulator_enable(ahci->pwr);
 334 +               if (ret) {
 335 +                       sunxi_ahci_disable_clks(ahci);
 336 +                       return ret;
 337 +               }
 338 +       }
 339 +
 340 +       ret = sunxi_ahci_phy_init(dev, ahci->hpriv.mmio);
 341 +       if (ret) {
 342 +               sunxi_ahci_host_stop(host);
 343 +               return ret;
 344 +       }
 345 +
 346 +       ahci_save_initial_config(dev, &ahci->hpriv, 0, 0);
 347 +
 348 +       ret = ahci_reset_controller(host);
 349 +       if (ret) {
 350 +               sunxi_ahci_host_stop(host);
 351 +               return ret;
 352 +       }
 353 +
 354 +       ahci_init_controller(host);
 355 +       ahci_print_info(host, "sunxi");
 356 +
 357 +       ret = ata_host_activate(host, platform_get_irq(pdev, 0),
 358 +                               ahci_interrupt, 0, &sunxi_ahci_platform_sht);
 359 +       if (ret)
 360 +               sunxi_ahci_host_stop(host);
 361 +
 362 +       return ret;
 363 +}
 364 +
 365 +#ifdef CONFIG_PM_SLEEP
 366 +static int sunxi_ahci_susp(struct device *dev)
 367 +{
 368 +       struct ata_host *host = dev_get_drvdata(dev);
 369 +       struct ahci_host_priv *hpriv = host->private_data;
 370 +       struct sunxi_ahci *ahci = hpriv->plat_data;
 371 +       int ret;
 372 +
 373 +       /*
 374 +        * AHCI spec rev1.1 section 8.3.3:
 375 +        * Software must disable interrupts prior to requesting a
 376 +        * transition of the HBA to D3 state.
 377 +        */
 378 +       sunxi_clrbits(hpriv->mmio + HOST_CTL, HOST_IRQ_EN);
 379 +
 380 +       ret = ata_host_suspend(host, PMSG_SUSPEND);
 381 +       if (ret)
 382 +               return ret;
 383 +
 384 +       sunxi_ahci_disable_clks(ahci);
 385 +
 386 +       return 0;
 387 +}
 388 +
 389 +static int sunxi_ahci_resume(struct device *dev)
 390 +{
 391 +       struct ata_host *host = dev_get_drvdata(dev);
 392 +       struct ahci_host_priv *hpriv = host->private_data;
 393 +       struct sunxi_ahci *ahci = hpriv->plat_data;
 394 +       int ret;
 395 +
 396 +       ret = sunxi_ahci_enable_clks(ahci);
 397 +       if (ret)
 398 +               return ret;
 399 +
 400 +       if (dev->power.power_state.event == PM_EVENT_SUSPEND) {
 401 +               ret = ahci_reset_controller(host);
 402 +               if (ret)
 403 +                       return ret;
 404 +
 405 +               ahci_init_controller(host);
 406 +       }
 407 +
 408 +       ata_host_resume(host);
 409 +
 410 +       return 0;
 411 +}
 412 +#endif
 413 +
 414 +static SIMPLE_DEV_PM_OPS(sunxi_ahci_pmo, sunxi_ahci_susp, sunxi_ahci_resume);
 415 +
 416 +static const struct of_device_id sunxi_ahci_of_match[] = {
 417 +       { .compatible = "allwinner,sun4i-a10-ahci" },
 418 +       { /* sentinel */ },
 419 +};
 420 +MODULE_DEVICE_TABLE(of, sunxi_ahci_of_match);
 421 +
 422 +static struct platform_driver sunxi_ahci_driver = {
 423 +       .probe = sunxi_ahci_probe,
 424 +       .remove = ata_platform_remove_one,
 425 +       .driver = {
 426 +               .name = "sunxi-ahci",
 427 +               .owner = THIS_MODULE,
 428 +               .of_match_table = sunxi_ahci_of_match,
 429 +               .pm = &sunxi_ahci_pmo,
 430 +       },
 431 +};
 432 +module_platform_driver(sunxi_ahci_driver);
 433 +
 434 +MODULE_DESCRIPTION("Allwinner sunxi AHCI SATA platform driver");
 435 +MODULE_AUTHOR("Olliver Schinagl <oliver@schinagl.nl>");
 436 +MODULE_LICENSE("GPL");