target/linux/sunxi/patches-3.13/182-usb-add-ehci-driver.patch

   1 From ac74dd1167924c412498a651edda63df49941f10 Mon Sep 17 00:00:00 2001
   2 From: Hans de Goede <hdegoede@redhat.com>
   3 Date: Sat, 4 Jan 2014 23:56:17 +0100
   4 Subject: [PATCH] ARM: sunxi: Add driver for sunxi usb phy
   5
   6 The Allwinner A1x / A2x SoCs have 2 or 3 usb phys which are all accessed
   7 through a single set of registers. Besides this there are also some other
   8 phy related bits which need poking, which are per phy, but shared between the
   9 ohci and ehci controllers, so these are also controlled from this new phy
  10 driver.
  11
  12 Signed-off-by: Hans de Goede <hdegoede@redhat.com>
  13 ---
  14  .../devicetree/bindings/phy/sun4i-usb-phy.txt      |  26 ++
  15  drivers/phy/Kconfig                                |  11 +
  16  drivers/phy/Makefile                               |   1 +
  17  drivers/phy/phy-sun4i-usb.c                        | 329 +++++++++++++++++++++
  18  4 files changed, 367 insertions(+)
  19  create mode 100644 Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
  20  create mode 100644 drivers/phy/phy-sun4i-usb.c
  21
  22 diff --git a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
  23 new file mode 100644
  24 index 0000000..a82361b
  25 --- /dev/null
  26 +++ b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
  27 @@ -0,0 +1,26 @@
  28 +Allwinner sun4i USB PHY
  29 +-----------------------
  30 +
  31 +Required properties:
  32 +- compatible : should be one of "allwinner,sun4i-a10-usb-phy",
  33 +  "allwinner,sun5i-a13-usb-phy" or "allwinner,sun7i-a20-usb-phy"
  34 +- reg : a list of offset + length pairs
  35 +- reg-names : "phy_ctrl", "pmu1" and for sun4i or sun7i "pmu2"
  36 +- #phy-cells : from the generic phy bindings, must be 1
  37 +- clocks : phandle + clock specifier for the phy clock
  38 +- clock-names : "usb_phy"
  39 +- resets : a list of phandle + reset specifier pairs
  40 +- reset-names : "usb0_reset", "usb1_reset" and for sun4i or sun7i "usb2_reset"
  41 +
  42 +Example:
  43 +       usbphy: phy@0x01c13400 {
  44 +               #phy-cells = <1>;
  45 +               compatible = "allwinner,sun4i-a10-usb-phy";
  46 +               /* phy base regs, phy1 pmu reg, phy2 pmu reg */
  47 +               reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
  48 +               reg-names = "phy_ctrl", "pmu1", "pmu2";
  49 +               clocks = <&usb_clk 8>;
  50 +               clock-names = "usb_phy";
  51 +               resets = <&usb_clk 1>, <&usb_clk 2>;
  52 +               reset-names = "usb1_reset", "usb2_reset";
  53 +       };
  54 diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
  55 index 4ef8755..6e336b4 100644
  56 --- a/drivers/phy/Kconfig
  57 +++ b/drivers/phy/Kconfig
  58 @@ -64,4 +64,15 @@ config BCM_KONA_USB2_PHY
  59         help
  60           Enable this to support the Broadcom Kona USB 2.0 PHY.
  61
  62 +config PHY_SUN4I_USB
  63 +       tristate "Allwinner sunxi SoC USB PHY driver"
  64 +       depends on ARCH_SUNXI
  65 +       select GENERIC_PHY
  66 +       help
  67 +         Enable this to support the transceiver that is part of Allwinner
  68 +         sunxi SoCs.
  69 +
  70 +         This driver controls the entire USB PHY block, both the USB OTG
  71 +         parts, as well as the 2 regular USB 2 host PHYs.
  72 +
  73  endmenu
  74 diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
  75 index b57c253..9d4f8bb 100644
  76 --- a/drivers/phy/Makefile
  77 +++ b/drivers/phy/Makefile
  78 @@ -9,3 +9,4 @@ obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO)     += phy-exynos-mipi-video.o
  79  obj-$(CONFIG_PHY_MVEBU_SATA)           += phy-mvebu-sata.o
  80  obj-$(CONFIG_OMAP_USB2)                        += phy-omap-usb2.o
  81  obj-$(CONFIG_TWL4030_USB)              += phy-twl4030-usb.o
  82 +obj-$(CONFIG_PHY_SUN4I_USB)            += phy-sun4i-usb.o
  83 diff --git a/drivers/phy/phy-sun4i-usb.c b/drivers/phy/phy-sun4i-usb.c
  84 new file mode 100644
  85 index 0000000..31c4611
  86 --- /dev/null
  87 +++ b/drivers/phy/phy-sun4i-usb.c
  88 @@ -0,0 +1,329 @@
  89 +/*
  90 + * Allwinner sun4i USB phy driver
  91 + *
  92 + * Copyright (C) 2014 Hans de Goede <hdegoede@redhat.com>
  93 + *
  94 + * Based on code from
  95 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
  96 + *
  97 + * Modelled after: Samsung S5P/EXYNOS SoC series MIPI CSIS/DSIM DPHY driver
  98 + * Copyright (C) 2013 Samsung Electronics Co., Ltd.
  99 + * Author: Sylwester Nawrocki <s.nawrocki@samsung.com>
 100 + *
 101 + * This program is free software; you can redistribute it and/or modify
 102 + * it under the terms of the GNU General Public License as published by
 103 + * the Free Software Foundation; either version 2 of the License, or
 104 + * (at your option) any later version.
 105 + *
 106 + * This program is distributed in the hope that it will be useful,
 107 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 108 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 109 + * GNU General Public License for more details.
 110 + */
 111 +
 112 +#include <linux/clk.h>
 113 +#include <linux/io.h>
 114 +#include <linux/kernel.h>
 115 +#include <linux/module.h>
 116 +#include <linux/mutex.h>
 117 +#include <linux/of.h>
 118 +#include <linux/of_address.h>
 119 +#include <linux/phy/phy.h>
 120 +#include <linux/platform_device.h>
 121 +#include <linux/regulator/consumer.h>
 122 +#include <linux/reset.h>
 123 +
 124 +#define REG_ISCR                       0x00
 125 +#define REG_PHYCTL                     0x04
 126 +#define REG_PHYBIST                    0x08
 127 +#define REG_PHYTUNE                    0x0c
 128 +
 129 +#define SUNXI_AHB_ICHR8_EN             BIT(10)
 130 +#define SUNXI_AHB_INCR4_BURST_EN       BIT(9)
 131 +#define SUNXI_AHB_INCRX_ALIGN_EN       BIT(8)
 132 +#define SUNXI_ULPI_BYPASS_EN           BIT(0)
 133 +
 134 +/* Common Control Bits for Both PHYs */
 135 +#define PHY_PLL_BW                     0x03
 136 +#define PHY_RES45_CAL_EN               0x0c
 137 +
 138 +/* Private Control Bits for Each PHY */
 139 +#define PHY_TX_AMPLITUDE_TUNE          0x20
 140 +#define PHY_TX_SLEWRATE_TUNE           0x22
 141 +#define PHY_VBUSVALID_TH_SEL           0x25
 142 +#define PHY_PULLUP_RES_SEL             0x27
 143 +#define PHY_OTG_FUNC_EN                        0x28
 144 +#define PHY_VBUS_DET_EN                        0x29
 145 +#define PHY_DISCON_TH_SEL              0x2a
 146 +
 147 +#define MAX_PHYS                       3
 148 +
 149 +struct sun4i_usb_phy_data {
 150 +       struct clk *clk;
 151 +       void __iomem *base;
 152 +       struct mutex mutex;
 153 +       int num_phys;
 154 +       u32 disc_thresh;
 155 +       struct sun4i_usb_phy {
 156 +               struct phy *phy;
 157 +               void __iomem *pmu;
 158 +               struct regulator *vbus;
 159 +               struct reset_control *reset;
 160 +               int index;
 161 +       } phys[MAX_PHYS];
 162 +};
 163 +
 164 +#define to_sun4i_usb_phy_data(phy) \
 165 +       container_of((phy), struct sun4i_usb_phy_data, phys[(phy)->index])
 166 +
 167 +static void sun4i_usb_phy_write(struct sun4i_usb_phy *phy, u32 addr, u32 data,
 168 +                               int len)
 169 +{
 170 +       struct sun4i_usb_phy_data *phy_data = to_sun4i_usb_phy_data(phy);
 171 +       u32 temp, usbc_bit = BIT(phy->index * 2);
 172 +       int i;
 173 +
 174 +       mutex_lock(&phy_data->mutex);
 175 +
 176 +       for (i = 0; i < len; i++) {
 177 +               temp = readl(phy_data->base + REG_PHYCTL);
 178 +
 179 +               /* clear the address portion */
 180 +               temp &= ~(0xff << 8);
 181 +
 182 +               /* set the address */
 183 +               temp |= ((addr + i) << 8);
 184 +               writel(temp, phy_data->base + REG_PHYCTL);
 185 +
 186 +               /* set the data bit and clear usbc bit*/
 187 +               temp = readb(phy_data->base + REG_PHYCTL);
 188 +               if (data & 0x1)
 189 +                       temp |= BIT(7);
 190 +               else
 191 +                       temp &= ~BIT(7);
 192 +               temp &= ~usbc_bit;
 193 +               writeb(temp, phy_data->base + REG_PHYCTL);
 194 +
 195 +               /* pulse usbc_bit */
 196 +               temp = readb(phy_data->base + REG_PHYCTL);
 197 +               temp |= usbc_bit;
 198 +               writeb(temp, phy_data->base + REG_PHYCTL);
 199 +
 200 +               temp = readb(phy_data->base + REG_PHYCTL);
 201 +               temp &= ~usbc_bit;
 202 +               writeb(temp, phy_data->base + REG_PHYCTL);
 203 +
 204 +               data >>= 1;
 205 +       }
 206 +       mutex_unlock(&phy_data->mutex);
 207 +}
 208 +
 209 +static void sun4i_usb_phy_passby(struct sun4i_usb_phy *phy, int enable)
 210 +{
 211 +       u32 bits, reg_value;
 212 +
 213 +       if (!phy->pmu)
 214 +               return;
 215 +
 216 +       bits = SUNXI_AHB_ICHR8_EN | SUNXI_AHB_INCR4_BURST_EN |
 217 +               SUNXI_AHB_INCRX_ALIGN_EN | SUNXI_ULPI_BYPASS_EN;
 218 +
 219 +       reg_value = readl(phy->pmu);
 220 +
 221 +       if (enable)
 222 +               reg_value |= bits;
 223 +       else
 224 +               reg_value &= ~bits;
 225 +
 226 +       writel(reg_value, phy->pmu);
 227 +}
 228 +
 229 +static int sun4i_usb_phy_init(struct phy *_phy)
 230 +{
 231 +       struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
 232 +       struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
 233 +       int ret;
 234 +
 235 +       ret = clk_prepare_enable(data->clk);
 236 +       if (ret)
 237 +               return ret;
 238 +
 239 +       ret = reset_control_deassert(phy->reset);
 240 +       if (ret) {
 241 +               clk_disable_unprepare(data->clk);
 242 +               return ret;
 243 +       }
 244 +
 245 +       /* Adjust PHY's magnitude and rate */
 246 +       sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE, 0x14, 5);
 247 +
 248 +       /* Disconnect threshold adjustment */
 249 +       sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL, data->disc_thresh, 2);
 250 +
 251 +       sun4i_usb_phy_passby(phy, 1);
 252 +
 253 +       return 0;
 254 +}
 255 +
 256 +static int sun4i_usb_phy_exit(struct phy *_phy)
 257 +{
 258 +       struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
 259 +       struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
 260 +
 261 +       sun4i_usb_phy_passby(phy, 0);
 262 +       reset_control_assert(phy->reset);
 263 +       clk_disable_unprepare(data->clk);
 264 +
 265 +       return 0;
 266 +}
 267 +
 268 +static int sun4i_usb_phy_power_on(struct phy *_phy)
 269 +{
 270 +       struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
 271 +       int ret = 0;
 272 +
 273 +       if (phy->vbus)
 274 +               ret = regulator_enable(phy->vbus);
 275 +
 276 +       return ret;
 277 +}
 278 +
 279 +static int sun4i_usb_phy_power_off(struct phy *_phy)
 280 +{
 281 +       struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
 282 +
 283 +       if (phy->vbus)
 284 +               regulator_disable(phy->vbus);
 285 +
 286 +       return 0;
 287 +}
 288 +
 289 +static struct phy_ops sun4i_usb_phy_ops = {
 290 +       .init           = sun4i_usb_phy_init,
 291 +       .exit           = sun4i_usb_phy_exit,
 292 +       .power_on       = sun4i_usb_phy_power_on,
 293 +       .power_off      = sun4i_usb_phy_power_off,
 294 +       .owner          = THIS_MODULE,
 295 +};
 296 +
 297 +static struct phy *sun4i_usb_phy_xlate(struct device *dev,
 298 +                                       struct of_phandle_args *args)
 299 +{
 300 +       struct sun4i_usb_phy_data *data = dev_get_drvdata(dev);
 301 +
 302 +       if (WARN_ON(args->args[0] == 0 || args->args[0] >= data->num_phys))
 303 +               return ERR_PTR(-ENODEV);
 304 +
 305 +       return data->phys[args->args[0]].phy;
 306 +}
 307 +
 308 +static int sun4i_usb_phy_probe(struct platform_device *pdev)
 309 +{
 310 +       struct sun4i_usb_phy_data *data;
 311 +       struct device *dev = &pdev->dev;
 312 +       struct device_node *np = dev->of_node;
 313 +       void __iomem *pmu = NULL;
 314 +       struct phy_provider *phy_provider;
 315 +       struct reset_control *reset;
 316 +       struct regulator *vbus;
 317 +       struct resource *res;
 318 +       struct phy *phy;
 319 +       char name[16];
 320 +       int i;
 321 +
 322 +       data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
 323 +       if (!data)
 324 +               return -ENOMEM;
 325 +
 326 +       mutex_init(&data->mutex);
 327 +
 328 +       if (of_device_is_compatible(np, "allwinner,sun5i-a13-usb-phy"))
 329 +               data->num_phys = 2;
 330 +       else
 331 +               data->num_phys = 3;
 332 +
 333 +       if (of_device_is_compatible(np, "allwinner,sun4i-a10-usb-phy"))
 334 +               data->disc_thresh = 3;
 335 +       else
 336 +               data->disc_thresh = 2;
 337 +
 338 +       res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy_ctrl");
 339 +       data->base = devm_ioremap_resource(dev, res);
 340 +       if (IS_ERR(data->base))
 341 +               return PTR_ERR(data->base);
 342 +
 343 +       data->clk = devm_clk_get(dev, "usb_phy");
 344 +       if (IS_ERR(data->clk)) {
 345 +               dev_err(dev, "could not get usb_phy clock\n");
 346 +               return PTR_ERR(data->clk);
 347 +       }
 348 +
 349 +       /* Skip 0, 0 is the phy for otg which is not yet supported. */
 350 +       for (i = 1; i < data->num_phys; i++) {
 351 +               snprintf(name, sizeof(name), "usb%d_vbus", i);
 352 +               vbus = devm_regulator_get_optional(dev, name);
 353 +               if (IS_ERR(vbus)) {
 354 +                       if (PTR_ERR(vbus) == -EPROBE_DEFER)
 355 +                               return -EPROBE_DEFER;
 356 +                       vbus = NULL;
 357 +               }
 358 +
 359 +               snprintf(name, sizeof(name), "usb%d_reset", i);
 360 +               reset = devm_reset_control_get(dev, name);
 361 +               if (IS_ERR(reset)) {
 362 +                       dev_err(dev, "failed to get reset %s\n", name);
 363 +                       return PTR_ERR(phy);
 364 +               }
 365 +
 366 +               if (i) { /* No pmu for usbc0 */
 367 +                       snprintf(name, sizeof(name), "pmu%d", i);
 368 +                       res = platform_get_resource_byname(pdev,
 369 +                                                       IORESOURCE_MEM, name);
 370 +                       pmu = devm_ioremap_resource(dev, res);
 371 +                       if (IS_ERR(pmu))
 372 +                               return PTR_ERR(pmu);
 373 +               }
 374 +
 375 +               phy = devm_phy_create(dev, &sun4i_usb_phy_ops, NULL);
 376 +               if (IS_ERR(phy)) {
 377 +                       dev_err(dev, "failed to create PHY %d\n", i);
 378 +                       return PTR_ERR(phy);
 379 +               }
 380 +
 381 +               data->phys[i].phy = phy;
 382 +               data->phys[i].pmu = pmu;
 383 +               data->phys[i].vbus = vbus;
 384 +               data->phys[i].reset = reset;
 385 +               data->phys[i].index = i;
 386 +               phy_set_drvdata(phy, &data->phys[i]);
 387 +       }
 388 +
 389 +       dev_set_drvdata(dev, data);
 390 +       phy_provider = devm_of_phy_provider_register(dev, sun4i_usb_phy_xlate);
 391 +       if (IS_ERR(phy_provider))
 392 +               return PTR_ERR(phy_provider);
 393 +
 394 +       return 0;
 395 +}
 396 +
 397 +static const struct of_device_id sun4i_usb_phy_of_match[] = {
 398 +       { .compatible = "allwinner,sun4i-a10-usb-phy" },
 399 +       { .compatible = "allwinner,sun5i-a13-usb-phy" },
 400 +       { .compatible = "allwinner,sun7i-a20-usb-phy" },
 401 +       { },
 402 +};
 403 +MODULE_DEVICE_TABLE(of, sun4i_usb_phy_of_match);
 404 +
 405 +static struct platform_driver sun4i_usb_phy_driver = {
 406 +       .probe  = sun4i_usb_phy_probe,
 407 +       .driver = {
 408 +               .of_match_table = sun4i_usb_phy_of_match,
 409 +               .name  = "sun4i-usb-phy",
 410 +               .owner = THIS_MODULE,
 411 +       }
 412 +};
 413 +module_platform_driver(sun4i_usb_phy_driver);
 414 +
 415 +MODULE_DESCRIPTION("Allwinner sun4i USB phy driver");
 416 +MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>");
 417 +MODULE_LICENSE("GPL v2");
 418 --
 419 1.8.5.5
 420