target/linux/sunxi/patches-3.14/114-dt-sun7i-rename-clocknodes.patch

   1 From c57b781689bba48dad635caf005962cc9c8e5e3d Mon Sep 17 00:00:00 2001
   2 From: Chen-Yu Tsai <wens@csie.org>
   3 Date: Mon, 3 Feb 2014 09:51:44 +0800
   4 Subject: [PATCH] ARM: dts: sun7i: rename clock node names to clk@N
   5
   6 Device tree naming conventions state that node names should match
   7 node function. Change fully functioning clock nodes to match and
   8 add clock-output-names to all sunxi clock nodes.
   9
  10 Signed-off-by: Chen-Yu Tsai <wens@csie.org>
  11 Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
  12 ---
  13  arch/arm/boot/dts/sun7i-a20.dtsi | 25 +++++++++++++++++--------
  14  1 file changed, 17 insertions(+), 8 deletions(-)
  15
  16 --- a/arch/arm/boot/dts/sun7i-a20.dtsi
  17 +++ b/arch/arm/boot/dts/sun7i-a20.dtsi
  18 @@ -62,11 +62,12 @@
  19                 #size-cells = <1>;
  20                 ranges;
  21
  22 -               osc24M: osc24M@01c20050 {
  23 +               osc24M: clk@01c20050 {
  24                         #clock-cells = <0>;
  25                         compatible = "allwinner,sun4i-osc-clk";
  26                         reg = <0x01c20050 0x4>;
  27                         clock-frequency = <24000000>;
  28 +                       clock-output-names = "osc24M";
  29                 };
  30
  31                 osc32k: clk@0 {
  32 @@ -76,21 +77,23 @@
  33                         clock-output-names = "osc32k";
  34                 };
  35
  36 -               pll1: pll1@01c20000 {
  37 +               pll1: clk@01c20000 {
  38                         #clock-cells = <0>;
  39                         compatible = "allwinner,sun4i-pll1-clk";
  40                         reg = <0x01c20000 0x4>;
  41                         clocks = <&osc24M>;
  42 +                       clock-output-names = "pll1";
  43                 };
  44
  45 -               pll4: pll4@01c20018 {
  46 +               pll4: clk@01c20018 {
  47                         #clock-cells = <0>;
  48                         compatible = "allwinner,sun4i-pll1-clk";
  49                         reg = <0x01c20018 0x4>;
  50                         clocks = <&osc24M>;
  51 +                       clock-output-names = "pll4";
  52                 };
  53
  54 -               pll5: pll5@01c20020 {
  55 +               pll5: clk@01c20020 {
  56                         #clock-cells = <1>;
  57                         compatible = "allwinner,sun4i-pll5-clk";
  58                         reg = <0x01c20020 0x4>;
  59 @@ -98,7 +101,7 @@
  60                         clock-output-names = "pll5_ddr", "pll5_other";
  61                 };
  62
  63 -               pll6: pll6@01c20028 {
  64 +               pll6: clk@01c20028 {
  65                         #clock-cells = <1>;
  66                         compatible = "allwinner,sun4i-pll6-clk";
  67                         reg = <0x01c20028 0x4>;
  68 @@ -111,6 +114,7 @@
  69                         compatible = "allwinner,sun4i-cpu-clk";
  70                         reg = <0x01c20054 0x4>;
  71                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
  72 +                       clock-output-names = "cpu";
  73                 };
  74
  75                 axi: axi@01c20054 {
  76 @@ -118,6 +122,7 @@
  77                         compatible = "allwinner,sun4i-axi-clk";
  78                         reg = <0x01c20054 0x4>;
  79                         clocks = <&cpu>;
  80 +                       clock-output-names = "axi";
  81                 };
  82
  83                 ahb: ahb@01c20054 {
  84 @@ -125,9 +130,10 @@
  85                         compatible = "allwinner,sun4i-ahb-clk";
  86                         reg = <0x01c20054 0x4>;
  87                         clocks = <&axi>;
  88 +                       clock-output-names = "ahb";
  89                 };
  90
  91 -               ahb_gates: ahb_gates@01c20060 {
  92 +               ahb_gates: clk@01c20060 {
  93                         #clock-cells = <1>;
  94                         compatible = "allwinner,sun7i-a20-ahb-gates-clk";
  95                         reg = <0x01c20060 0x8>;
  96 @@ -152,9 +158,10 @@
  97                         compatible = "allwinner,sun4i-apb0-clk";
  98                         reg = <0x01c20054 0x4>;
  99                         clocks = <&ahb>;
 100 +                       clock-output-names = "apb0";
 101                 };
 102
 103 -               apb0_gates: apb0_gates@01c20068 {
 104 +               apb0_gates: clk@01c20068 {
 105                         #clock-cells = <1>;
 106                         compatible = "allwinner,sun7i-a20-apb0-gates-clk";
 107                         reg = <0x01c20068 0x4>;
 108 @@ -170,6 +177,7 @@
 109                         compatible = "allwinner,sun4i-apb1-mux-clk";
 110                         reg = <0x01c20058 0x4>;
 111                         clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
 112 +                       clock-output-names = "apb1_mux";
 113                 };
 114
 115                 apb1: apb1@01c20058 {
 116 @@ -177,9 +185,10 @@
 117                         compatible = "allwinner,sun4i-apb1-clk";
 118                         reg = <0x01c20058 0x4>;
 119                         clocks = <&apb1_mux>;
 120 +                       clock-output-names = "apb1";
 121                 };
 122
 123 -               apb1_gates: apb1_gates@01c2006c {
 124 +               apb1_gates: clk@01c2006c {
 125                         #clock-cells = <1>;
 126                         compatible = "allwinner,sun7i-a20-apb1-gates-clk";
 127                         reg = <0x01c2006c 0x4>;