target/linux/sunxi/patches-3.14/146-2-spi-add-a10-spi.patch

   1 From 1ae7667375308c27023d793372d6be1f3b89f5b5 Mon Sep 17 00:00:00 2001
   2 From: Maxime Ripard <maxime.ripard@free-electrons.com>
   3 Date: Sat, 22 Feb 2014 22:35:53 +0100
   4 Subject: [PATCH] spi: sunxi: Add Allwinner A10 SPI controller driver
   5
   6 The older Allwinner SoCs (A10, A13, A10s and A20) all have the same SPI
   7 controller.
   8
   9 Unfortunately, this SPI controller, even though quite similar, is significantly
  10 different from the recently supported A31 SPI controller (different registers
  11 offset, split/merged registers, etc.). Supporting both controllers in a single
  12 driver would be unreasonable, hence the addition of a new driver.
  13
  14 Like its more recent counterpart, it supports DMA, but the driver only does PIO
  15 until we have a dmaengine driver for this platform.
  16
  17 Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
  18 ---
  19  .../devicetree/bindings/spi/spi-sun4i.txt          |  24 ++
  20  drivers/spi/Kconfig                                |   6 +
  21  drivers/spi/Makefile                               |   1 +
  22  drivers/spi/spi-sun4i.c                            | 477 +++++++++++++++++++++
  23  4 files changed, 508 insertions(+)
  24  create mode 100644 Documentation/devicetree/bindings/spi/spi-sun4i.txt
  25  create mode 100644 drivers/spi/spi-sun4i.c
  26
  27 --- /dev/null
  28 +++ b/Documentation/devicetree/bindings/spi/spi-sun4i.txt
  29 @@ -0,0 +1,24 @@
  30 +Allwinner A10 SPI controller
  31 +
  32 +Required properties:
  33 +- compatible: Should be "allwinner,sun4-a10-spi".
  34 +- reg: Should contain register location and length.
  35 +- interrupts: Should contain interrupt.
  36 +- clocks: phandle to the clocks feeding the SPI controller. Two are
  37 +          needed:
  38 +  - "ahb": the gated AHB parent clock
  39 +  - "mod": the parent module clock
  40 +- clock-names: Must contain the clock names described just above
  41 +
  42 +Example:
  43 +
  44 +spi1: spi@01c06000 {
  45 +       compatible = "allwinner,sun4i-a10-spi";
  46 +       reg = <0x01c06000 0x1000>;
  47 +       interrupts = <11>;
  48 +       clocks = <&ahb_gates 21>, <&spi1_clk>;
  49 +       clock-names = "ahb", "mod";
  50 +       status = "disabled";
  51 +       #address-cells = <1>;
  52 +       #size-cells = <0>;
  53 +};
  54 --- a/drivers/spi/Kconfig
  55 +++ b/drivers/spi/Kconfig
  56 @@ -455,6 +455,12 @@ config SPI_SIRF
  57         help
  58           SPI driver for CSR SiRFprimaII SoCs
  59
  60 +config SPI_SUN4I
  61 +       tristate "Allwinner A10 SoCs SPI controller"
  62 +       depends on ARCH_SUNXI || COMPILE_TEST
  63 +       help
  64 +         SPI driver for Allwinner sun4i, sun5i and sun7i SoCs
  65 +
  66  config SPI_SUN6I
  67         tristate "Allwinner A31 SPI controller"
  68         depends on ARCH_SUNXI || COMPILE_TEST
  69 --- a/drivers/spi/Makefile
  70 +++ b/drivers/spi/Makefile
  71 @@ -71,6 +71,7 @@ obj-$(CONFIG_SPI_SH_HSPI)             += spi-sh-hsp
  72  obj-$(CONFIG_SPI_SH_MSIOF)             += spi-sh-msiof.o
  73  obj-$(CONFIG_SPI_SH_SCI)               += spi-sh-sci.o
  74  obj-$(CONFIG_SPI_SIRF)         += spi-sirf.o
  75 +obj-$(CONFIG_SPI_SUN4I)                        += spi-sun4i.o
  76  obj-$(CONFIG_SPI_SUN6I)                        += spi-sun6i.o
  77  obj-$(CONFIG_SPI_TEGRA114)             += spi-tegra114.o
  78  obj-$(CONFIG_SPI_TEGRA20_SFLASH)       += spi-tegra20-sflash.o
  79 --- /dev/null
  80 +++ b/drivers/spi/spi-sun4i.c
  81 @@ -0,0 +1,477 @@
  82 +/*
  83 + * Copyright (C) 2012 - 2014 Allwinner Tech
  84 + * Pan Nan <pannan@allwinnertech.com>
  85 + *
  86 + * Copyright (C) 2014 Maxime Ripard
  87 + * Maxime Ripard <maxime.ripard@free-electrons.com>
  88 + *
  89 + * This program is free software; you can redistribute it and/or
  90 + * modify it under the terms of the GNU General Public License as
  91 + * published by the Free Software Foundation; either version 2 of
  92 + * the License, or (at your option) any later version.
  93 + */
  94 +
  95 +#include <linux/clk.h>
  96 +#include <linux/delay.h>
  97 +#include <linux/device.h>
  98 +#include <linux/interrupt.h>
  99 +#include <linux/io.h>
 100 +#include <linux/module.h>
 101 +#include <linux/platform_device.h>
 102 +#include <linux/pm_runtime.h>
 103 +#include <linux/workqueue.h>
 104 +
 105 +#include <linux/spi/spi.h>
 106 +
 107 +#define SUN4I_FIFO_DEPTH               64
 108 +
 109 +#define SUN4I_RXDATA_REG               0x00
 110 +
 111 +#define SUN4I_TXDATA_REG               0x04
 112 +
 113 +#define SUN4I_CTL_REG                  0x08
 114 +#define SUN4I_CTL_ENABLE                       BIT(0)
 115 +#define SUN4I_CTL_MASTER                       BIT(1)
 116 +#define SUN4I_CTL_CPHA                         BIT(2)
 117 +#define SUN4I_CTL_CPOL                         BIT(3)
 118 +#define SUN4I_CTL_CS_ACTIVE_LOW                        BIT(4)
 119 +#define SUN4I_CTL_LMTF                         BIT(6)
 120 +#define SUN4I_CTL_TF_RST                       BIT(8)
 121 +#define SUN4I_CTL_RF_RST                       BIT(9)
 122 +#define SUN4I_CTL_XCH                          BIT(10)
 123 +#define SUN4I_CTL_CS_MASK                      0x3000
 124 +#define SUN4I_CTL_CS(cs)                       (((cs) << 12) & SUN4I_CTL_CS_MASK)
 125 +#define SUN4I_CTL_DHB                          BIT(15)
 126 +#define SUN4I_CTL_CS_MANUAL                    BIT(16)
 127 +#define SUN4I_CTL_CS_LEVEL                     BIT(17)
 128 +#define SUN4I_CTL_TP                           BIT(18)
 129 +
 130 +#define SUN4I_INT_CTL_REG              0x0c
 131 +#define SUN4I_INT_CTL_TC                       BIT(16)
 132 +
 133 +#define SUN4I_INT_STA_REG              0x10
 134 +
 135 +#define SUN4I_DMA_CTL_REG              0x14
 136 +
 137 +#define SUN4I_WAIT_REG                 0x18
 138 +
 139 +#define SUN4I_CLK_CTL_REG              0x1c
 140 +#define SUN4I_CLK_CTL_CDR2_MASK                        0xff
 141 +#define SUN4I_CLK_CTL_CDR2(div)                        ((div) & SUN4I_CLK_CTL_CDR2_MASK)
 142 +#define SUN4I_CLK_CTL_CDR1_MASK                        0xf
 143 +#define SUN4I_CLK_CTL_CDR1(div)                        (((div) & SUN4I_CLK_CTL_CDR1_MASK) << 8)
 144 +#define SUN4I_CLK_CTL_DRS                      BIT(12)
 145 +
 146 +#define SUN4I_BURST_CNT_REG            0x20
 147 +#define SUN4I_BURST_CNT(cnt)                   ((cnt) & 0xffffff)
 148 +
 149 +#define SUN4I_XMIT_CNT_REG             0x24
 150 +#define SUN4I_XMIT_CNT(cnt)                    ((cnt) & 0xffffff)
 151 +
 152 +#define SUN4I_FIFO_STA_REG             0x28
 153 +#define SUN4I_FIFO_STA_RF_CNT_MASK             0x7f
 154 +#define SUN4I_FIFO_STA_RF_CNT_BITS             0
 155 +#define SUN4I_FIFO_STA_TF_CNT_MASK             0x7f
 156 +#define SUN4I_FIFO_STA_TF_CNT_BITS             16
 157 +
 158 +struct sun4i_spi {
 159 +       struct spi_master       *master;
 160 +       void __iomem            *base_addr;
 161 +       struct clk              *hclk;
 162 +       struct clk              *mclk;
 163 +
 164 +       struct completion       done;
 165 +
 166 +       const u8                *tx_buf;
 167 +       u8                      *rx_buf;
 168 +       int                     len;
 169 +};
 170 +
 171 +static inline u32 sun4i_spi_read(struct sun4i_spi *sspi, u32 reg)
 172 +{
 173 +       return readl(sspi->base_addr + reg);
 174 +}
 175 +
 176 +static inline void sun4i_spi_write(struct sun4i_spi *sspi, u32 reg, u32 value)
 177 +{
 178 +       writel(value, sspi->base_addr + reg);
 179 +}
 180 +
 181 +static inline void sun4i_spi_drain_fifo(struct sun4i_spi *sspi, int len)
 182 +{
 183 +       u32 reg, cnt;
 184 +       u8 byte;
 185 +
 186 +       /* See how much data is available */
 187 +       reg = sun4i_spi_read(sspi, SUN4I_FIFO_STA_REG);
 188 +       reg &= SUN4I_FIFO_STA_RF_CNT_MASK;
 189 +       cnt = reg >> SUN4I_FIFO_STA_RF_CNT_BITS;
 190 +
 191 +       if (len > cnt)
 192 +               len = cnt;
 193 +
 194 +       while (len--) {
 195 +               byte = readb(sspi->base_addr + SUN4I_RXDATA_REG);
 196 +               if (sspi->rx_buf)
 197 +                       *sspi->rx_buf++ = byte;
 198 +       }
 199 +}
 200 +
 201 +static inline void sun4i_spi_fill_fifo(struct sun4i_spi *sspi, int len)
 202 +{
 203 +       u8 byte;
 204 +
 205 +       if (len > sspi->len)
 206 +               len = sspi->len;
 207 +
 208 +       while (len--) {
 209 +               byte = sspi->tx_buf ? *sspi->tx_buf++ : 0;
 210 +               writeb(byte, sspi->base_addr + SUN4I_TXDATA_REG);
 211 +               sspi->len--;
 212 +       }
 213 +}
 214 +
 215 +static void sun4i_spi_set_cs(struct spi_device *spi, bool enable)
 216 +{
 217 +       struct sun4i_spi *sspi = spi_master_get_devdata(spi->master);
 218 +       u32 reg;
 219 +
 220 +       reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
 221 +
 222 +       reg &= ~SUN4I_CTL_CS_MASK;
 223 +       reg |= SUN4I_CTL_CS(spi->chip_select);
 224 +
 225 +       if (enable)
 226 +               reg |= SUN4I_CTL_CS_LEVEL;
 227 +       else
 228 +               reg &= ~SUN4I_CTL_CS_LEVEL;
 229 +
 230 +       /*
 231 +        * Even though this looks irrelevant since we are supposed to
 232 +        * be controlling the chip select manually, this bit also
 233 +        * controls the levels of the chip select for inactive
 234 +        * devices.
 235 +        *
 236 +        * If we don't set it, the chip select level will go low by
 237 +        * default when the device is idle, which is not really
 238 +        * expected in the common case where the chip select is active
 239 +        * low.
 240 +        */
 241 +       if (spi->mode & SPI_CS_HIGH)
 242 +               reg &= ~SUN4I_CTL_CS_ACTIVE_LOW;
 243 +       else
 244 +               reg |= SUN4I_CTL_CS_ACTIVE_LOW;
 245 +
 246 +       sun4i_spi_write(sspi, SUN4I_CTL_REG, reg);
 247 +}
 248 +
 249 +static int sun4i_spi_transfer_one(struct spi_master *master,
 250 +                                 struct spi_device *spi,
 251 +                                 struct spi_transfer *tfr)
 252 +{
 253 +       struct sun4i_spi *sspi = spi_master_get_devdata(master);
 254 +       unsigned int mclk_rate, div, timeout;
 255 +       unsigned int tx_len = 0;
 256 +       int ret = 0;
 257 +       u32 reg;
 258 +
 259 +       /* We don't support transfer larger than the FIFO */
 260 +       if (tfr->len > SUN4I_FIFO_DEPTH)
 261 +               return -EINVAL;
 262 +
 263 +       reinit_completion(&sspi->done);
 264 +       sspi->tx_buf = tfr->tx_buf;
 265 +       sspi->rx_buf = tfr->rx_buf;
 266 +       sspi->len = tfr->len;
 267 +
 268 +       /* Clear pending interrupts */
 269 +       sun4i_spi_write(sspi, SUN4I_INT_STA_REG, ~0);
 270 +
 271 +
 272 +       reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
 273 +
 274 +       /* Reset FIFOs */
 275 +       sun4i_spi_write(sspi, SUN4I_CTL_REG,
 276 +                       reg | SUN4I_CTL_RF_RST | SUN4I_CTL_TF_RST);
 277 +
 278 +       /*
 279 +        * Setup the transfer control register: Chip Select,
 280 +        * polarities, etc.
 281 +        */
 282 +       if (spi->mode & SPI_CPOL)
 283 +               reg |= SUN4I_CTL_CPOL;
 284 +       else
 285 +               reg &= ~SUN4I_CTL_CPOL;
 286 +
 287 +       if (spi->mode & SPI_CPHA)
 288 +               reg |= SUN4I_CTL_CPHA;
 289 +       else
 290 +               reg &= ~SUN4I_CTL_CPHA;
 291 +
 292 +       if (spi->mode & SPI_LSB_FIRST)
 293 +               reg |= SUN4I_CTL_LMTF;
 294 +       else
 295 +               reg &= ~SUN4I_CTL_LMTF;
 296 +
 297 +
 298 +       /*
 299 +        * If it's a TX only transfer, we don't want to fill the RX
 300 +        * FIFO with bogus data
 301 +        */
 302 +       if (sspi->rx_buf)
 303 +               reg &= ~SUN4I_CTL_DHB;
 304 +       else
 305 +               reg |= SUN4I_CTL_DHB;
 306 +
 307 +       /* We want to control the chip select manually */
 308 +       reg |= SUN4I_CTL_CS_MANUAL;
 309 +
 310 +       sun4i_spi_write(sspi, SUN4I_CTL_REG, reg);
 311 +
 312 +       /* Ensure that we have a parent clock fast enough */
 313 +       mclk_rate = clk_get_rate(sspi->mclk);
 314 +       if (mclk_rate < (2 * spi->max_speed_hz)) {
 315 +               clk_set_rate(sspi->mclk, 2 * spi->max_speed_hz);
 316 +               mclk_rate = clk_get_rate(sspi->mclk);
 317 +       }
 318 +
 319 +       /*
 320 +        * Setup clock divider.
 321 +        *
 322 +        * We have two choices there. Either we can use the clock
 323 +        * divide rate 1, which is calculated thanks to this formula:
 324 +        * SPI_CLK = MOD_CLK / (2 ^ (cdr + 1))
 325 +        * Or we can use CDR2, which is calculated with the formula:
 326 +        * SPI_CLK = MOD_CLK / (2 * (cdr + 1))
 327 +        * Wether we use the former or the latter is set through the
 328 +        * DRS bit.
 329 +        *
 330 +        * First try CDR2, and if we can't reach the expected
 331 +        * frequency, fall back to CDR1.
 332 +        */
 333 +       div = mclk_rate / (2 * spi->max_speed_hz);
 334 +       if (div <= (SUN4I_CLK_CTL_CDR2_MASK + 1)) {
 335 +               if (div > 0)
 336 +                       div--;
 337 +
 338 +               reg = SUN4I_CLK_CTL_CDR2(div) | SUN4I_CLK_CTL_DRS;
 339 +       } else {
 340 +               div = ilog2(mclk_rate) - ilog2(spi->max_speed_hz);
 341 +               reg = SUN4I_CLK_CTL_CDR1(div);
 342 +       }
 343 +
 344 +       sun4i_spi_write(sspi, SUN4I_CLK_CTL_REG, reg);
 345 +
 346 +       /* Setup the transfer now... */
 347 +       if (sspi->tx_buf)
 348 +               tx_len = tfr->len;
 349 +
 350 +       /* Setup the counters */
 351 +       sun4i_spi_write(sspi, SUN4I_BURST_CNT_REG, SUN4I_BURST_CNT(tfr->len));
 352 +       sun4i_spi_write(sspi, SUN4I_XMIT_CNT_REG, SUN4I_XMIT_CNT(tx_len));
 353 +
 354 +       /* Fill the TX FIFO */
 355 +       sun4i_spi_fill_fifo(sspi, SUN4I_FIFO_DEPTH);
 356 +
 357 +       /* Enable the interrupts */
 358 +       sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, SUN4I_INT_CTL_TC);
 359 +
 360 +       /* Start the transfer */
 361 +       reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
 362 +       sun4i_spi_write(sspi, SUN4I_CTL_REG, reg | SUN4I_CTL_XCH);
 363 +
 364 +       timeout = wait_for_completion_timeout(&sspi->done,
 365 +                                             msecs_to_jiffies(1000));
 366 +       if (!timeout) {
 367 +               ret = -ETIMEDOUT;
 368 +               goto out;
 369 +       }
 370 +
 371 +       sun4i_spi_drain_fifo(sspi, SUN4I_FIFO_DEPTH);
 372 +
 373 +out:
 374 +       sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, 0);
 375 +
 376 +       return ret;
 377 +}
 378 +
 379 +static irqreturn_t sun4i_spi_handler(int irq, void *dev_id)
 380 +{
 381 +       struct sun4i_spi *sspi = dev_id;
 382 +       u32 status = sun4i_spi_read(sspi, SUN4I_INT_STA_REG);
 383 +
 384 +       /* Transfer complete */
 385 +       if (status & SUN4I_INT_CTL_TC) {
 386 +               sun4i_spi_write(sspi, SUN4I_INT_STA_REG, SUN4I_INT_CTL_TC);
 387 +               complete(&sspi->done);
 388 +               return IRQ_HANDLED;
 389 +       }
 390 +
 391 +       return IRQ_NONE;
 392 +}
 393 +
 394 +static int sun4i_spi_runtime_resume(struct device *dev)
 395 +{
 396 +       struct spi_master *master = dev_get_drvdata(dev);
 397 +       struct sun4i_spi *sspi = spi_master_get_devdata(master);
 398 +       int ret;
 399 +
 400 +       ret = clk_prepare_enable(sspi->hclk);
 401 +       if (ret) {
 402 +               dev_err(dev, "Couldn't enable AHB clock\n");
 403 +               goto out;
 404 +       }
 405 +
 406 +       ret = clk_prepare_enable(sspi->mclk);
 407 +       if (ret) {
 408 +               dev_err(dev, "Couldn't enable module clock\n");
 409 +               goto err;
 410 +       }
 411 +
 412 +       sun4i_spi_write(sspi, SUN4I_CTL_REG,
 413 +                       SUN4I_CTL_ENABLE | SUN4I_CTL_MASTER | SUN4I_CTL_TP);
 414 +
 415 +       return 0;
 416 +
 417 +err:
 418 +       clk_disable_unprepare(sspi->hclk);
 419 +out:
 420 +       return ret;
 421 +}
 422 +
 423 +static int sun4i_spi_runtime_suspend(struct device *dev)
 424 +{
 425 +       struct spi_master *master = dev_get_drvdata(dev);
 426 +       struct sun4i_spi *sspi = spi_master_get_devdata(master);
 427 +
 428 +       clk_disable_unprepare(sspi->mclk);
 429 +       clk_disable_unprepare(sspi->hclk);
 430 +
 431 +       return 0;
 432 +}
 433 +
 434 +static int sun4i_spi_probe(struct platform_device *pdev)
 435 +{
 436 +       struct spi_master *master;
 437 +       struct sun4i_spi *sspi;
 438 +       struct resource *res;
 439 +       int ret = 0, irq;
 440 +
 441 +       master = spi_alloc_master(&pdev->dev, sizeof(struct sun4i_spi));
 442 +       if (!master) {
 443 +               dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
 444 +               return -ENOMEM;
 445 +       }
 446 +
 447 +       platform_set_drvdata(pdev, master);
 448 +       sspi = spi_master_get_devdata(master);
 449 +
 450 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 451 +       sspi->base_addr = devm_ioremap_resource(&pdev->dev, res);
 452 +       if (IS_ERR(sspi->base_addr)) {
 453 +               ret = PTR_ERR(sspi->base_addr);
 454 +               goto err_free_master;
 455 +       }
 456 +
 457 +       irq = platform_get_irq(pdev, 0);
 458 +       if (irq < 0) {
 459 +               dev_err(&pdev->dev, "No spi IRQ specified\n");
 460 +               ret = -ENXIO;
 461 +               goto err_free_master;
 462 +       }
 463 +
 464 +       ret = devm_request_irq(&pdev->dev, irq, sun4i_spi_handler,
 465 +                              0, "sun4i-spi", sspi);
 466 +       if (ret) {
 467 +               dev_err(&pdev->dev, "Cannot request IRQ\n");
 468 +               goto err_free_master;
 469 +       }
 470 +
 471 +       sspi->master = master;
 472 +       master->set_cs = sun4i_spi_set_cs;
 473 +       master->transfer_one = sun4i_spi_transfer_one;
 474 +       master->num_chipselect = 4;
 475 +       master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
 476 +       master->dev.of_node = pdev->dev.of_node;
 477 +       master->auto_runtime_pm = true;
 478 +
 479 +       sspi->hclk = devm_clk_get(&pdev->dev, "ahb");
 480 +       if (IS_ERR(sspi->hclk)) {
 481 +               dev_err(&pdev->dev, "Unable to acquire AHB clock\n");
 482 +               ret = PTR_ERR(sspi->hclk);
 483 +               goto err_free_master;
 484 +       }
 485 +
 486 +       sspi->mclk = devm_clk_get(&pdev->dev, "mod");
 487 +       if (IS_ERR(sspi->mclk)) {
 488 +               dev_err(&pdev->dev, "Unable to acquire module clock\n");
 489 +               ret = PTR_ERR(sspi->mclk);
 490 +               goto err_free_master;
 491 +       }
 492 +
 493 +       init_completion(&sspi->done);
 494 +
 495 +       /*
 496 +        * This wake-up/shutdown pattern is to be able to have the
 497 +        * device woken up, even if runtime_pm is disabled
 498 +        */
 499 +       ret = sun4i_spi_runtime_resume(&pdev->dev);
 500 +       if (ret) {
 501 +               dev_err(&pdev->dev, "Couldn't resume the device\n");
 502 +               goto err_free_master;
 503 +       }
 504 +
 505 +       pm_runtime_set_active(&pdev->dev);
 506 +       pm_runtime_enable(&pdev->dev);
 507 +       pm_runtime_idle(&pdev->dev);
 508 +
 509 +       ret = devm_spi_register_master(&pdev->dev, master);
 510 +       if (ret) {
 511 +               dev_err(&pdev->dev, "cannot register SPI master\n");
 512 +               goto err_pm_disable;
 513 +       }
 514 +
 515 +       return 0;
 516 +
 517 +err_pm_disable:
 518 +       pm_runtime_disable(&pdev->dev);
 519 +       sun4i_spi_runtime_suspend(&pdev->dev);
 520 +err_free_master:
 521 +       spi_master_put(master);
 522 +       return ret;
 523 +}
 524 +
 525 +static int sun4i_spi_remove(struct platform_device *pdev)
 526 +{
 527 +       pm_runtime_disable(&pdev->dev);
 528 +
 529 +       return 0;
 530 +}
 531 +
 532 +static const struct of_device_id sun4i_spi_match[] = {
 533 +       { .compatible = "allwinner,sun4i-a10-spi", },
 534 +       {}
 535 +};
 536 +MODULE_DEVICE_TABLE(of, sun4i_spi_match);
 537 +
 538 +static const struct dev_pm_ops sun4i_spi_pm_ops = {
 539 +       .runtime_resume         = sun4i_spi_runtime_resume,
 540 +       .runtime_suspend        = sun4i_spi_runtime_suspend,
 541 +};
 542 +
 543 +static struct platform_driver sun4i_spi_driver = {
 544 +       .probe  = sun4i_spi_probe,
 545 +       .remove = sun4i_spi_remove,
 546 +       .driver = {
 547 +               .name           = "sun4i-spi",
 548 +               .owner          = THIS_MODULE,
 549 +               .of_match_table = sun4i_spi_match,
 550 +               .pm             = &sun4i_spi_pm_ops,
 551 +       },
 552 +};
 553 +module_platform_driver(sun4i_spi_driver);
 554 +
 555 +MODULE_AUTHOR("Pan Nan <pannan@allwinnertech.com>");
 556 +MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
 557 +MODULE_DESCRIPTION("Allwinner A1X/A20 SPI controller driver");
 558 +MODULE_LICENSE("GPL");