target/linux/sunxi/patches-3.14/186-clk-sunxi-add-new-clock-compats.patch

   1 From 45ff9697ed1668e82ca3902b32309e157464e745 Mon Sep 17 00:00:00 2001
   2 From: Maxime Ripard <maxime.ripard@free-electrons.com>
   3 Date: Thu, 6 Feb 2014 09:55:57 +0100
   4 Subject: [PATCH] clk: sunxi: Add new clock compatibles
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 The Allwinner A10 compatibles were following a slightly different compatible
  10 patterns than the rest of the SoCs for historical reasons. Add compatibles
  11 matching the other pattern to the clock driver for consistency, and keep the
  12 older one for backward compatibility.
  13
  14 Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
  15 Signed-off-by: Emilio López <emilio@elopez.com.ar>
  16 ---
  17  Documentation/devicetree/bindings/clock/sunxi.txt | 36 +++++++++++------------
  18  drivers/clk/sunxi/clk-sunxi.c                     | 30 +++++++++----------
  19  2 files changed, 33 insertions(+), 33 deletions(-)
  20
  21 --- a/Documentation/devicetree/bindings/clock/sunxi.txt
  22 +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
  23 @@ -6,37 +6,37 @@ This binding uses the common clock bindi
  24
  25  Required properties:
  26  - compatible : shall be one of the following:
  27 -       "allwinner,sun4i-osc-clk" - for a gatable oscillator
  28 -       "allwinner,sun4i-pll1-clk" - for the main PLL clock and PLL4
  29 +       "allwinner,sun4i-a10-osc-clk" - for a gatable oscillator
  30 +       "allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4
  31         "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
  32 -       "allwinner,sun4i-pll5-clk" - for the PLL5 clock
  33 -       "allwinner,sun4i-pll6-clk" - for the PLL6 clock
  34 +       "allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock
  35 +       "allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock
  36         "allwinner,sun6i-a31-pll6-clk" - for the PLL6 clock on A31
  37 -       "allwinner,sun4i-cpu-clk" - for the CPU multiplexer clock
  38 -       "allwinner,sun4i-axi-clk" - for the AXI clock
  39 -       "allwinner,sun4i-axi-gates-clk" - for the AXI gates
  40 -       "allwinner,sun4i-ahb-clk" - for the AHB clock
  41 -       "allwinner,sun4i-ahb-gates-clk" - for the AHB gates on A10
  42 +       "allwinner,sun4i-a10-cpu-clk" - for the CPU multiplexer clock
  43 +       "allwinner,sun4i-a10-axi-clk" - for the AXI clock
  44 +       "allwinner,sun4i-a10-axi-gates-clk" - for the AXI gates
  45 +       "allwinner,sun4i-a10-ahb-clk" - for the AHB clock
  46 +       "allwinner,sun4i-a10-ahb-gates-clk" - for the AHB gates on A10
  47         "allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13
  48         "allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s
  49         "allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20
  50         "allwinner,sun6i-a31-ahb1-mux-clk" - for the AHB1 multiplexer on A31
  51         "allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
  52 -       "allwinner,sun4i-apb0-clk" - for the APB0 clock
  53 -       "allwinner,sun4i-apb0-gates-clk" - for the APB0 gates on A10
  54 +       "allwinner,sun4i-a10-apb0-clk" - for the APB0 clock
  55 +       "allwinner,sun4i-a10-apb0-gates-clk" - for the APB0 gates on A10
  56         "allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13
  57         "allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s
  58         "allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20
  59 -       "allwinner,sun4i-apb1-clk" - for the APB1 clock
  60 -       "allwinner,sun4i-apb1-mux-clk" - for the APB1 clock muxing
  61 -       "allwinner,sun4i-apb1-gates-clk" - for the APB1 gates on A10
  62 +       "allwinner,sun4i-a10-apb1-clk" - for the APB1 clock
  63 +       "allwinner,sun4i-a10-apb1-mux-clk" - for the APB1 clock muxing
  64 +       "allwinner,sun4i-a10-apb1-gates-clk" - for the APB1 gates on A10
  65         "allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13
  66         "allwinner,sun5i-a10s-apb1-gates-clk" - for the APB1 gates on A10s
  67         "allwinner,sun6i-a31-apb1-gates-clk" - for the APB1 gates on A31
  68         "allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20
  69         "allwinner,sun6i-a31-apb2-div-clk" - for the APB2 gates on A31
  70         "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
  71 -       "allwinner,sun4i-mod0-clk" - for the module 0 family of clocks
  72 +       "allwinner,sun4i-a10-mod0-clk" - for the module 0 family of clocks
  73         "allwinner,sun7i-a20-out-clk" - for the external output clocks
  74         "allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31
  75         "allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20
  76 @@ -68,21 +68,21 @@ For example:
  77
  78  osc24M: osc24M@01c20050 {
  79         #clock-cells = <0>;
  80 -       compatible = "allwinner,sun4i-osc-clk";
  81 +       compatible = "allwinner,sun4i-a10-osc-clk";
  82         reg = <0x01c20050 0x4>;
  83         clocks = <&osc24M_fixed>;
  84  };
  85
  86  pll1: pll1@01c20000 {
  87         #clock-cells = <0>;
  88 -       compatible = "allwinner,sun4i-pll1-clk";
  89 +       compatible = "allwinner,sun4i-a10-pll1-clk";
  90         reg = <0x01c20000 0x4>;
  91         clocks = <&osc24M>;
  92  };
  93
  94  cpu: cpu@01c20054 {
  95         #clock-cells = <0>;
  96 -       compatible = "allwinner,sun4i-cpu-clk";
  97 +       compatible = "allwinner,sun4i-a10-cpu-clk";
  98         reg = <0x01c20054 0x4>;
  99         clocks = <&osc32k>, <&osc24M>, <&pll1>;
 100  };
 101 --- a/drivers/clk/sunxi/clk-sunxi.c
 102 +++ b/drivers/clk/sunxi/clk-sunxi.c
 103 @@ -80,7 +80,7 @@ err_free_gate:
 104  err_free_fixed:
 105         kfree(fixed);
 106  }
 107 -CLK_OF_DECLARE(sun4i_osc, "allwinner,sun4i-osc-clk", sun4i_osc_clk_setup);
 108 +CLK_OF_DECLARE(sun4i_osc, "allwinner,sun4i-a10-osc-clk", sun4i_osc_clk_setup);
 109
 110
 111
 112 @@ -1207,52 +1207,52 @@ free_clkdata:
 113
 114  /* Matches for factors clocks */
 115  static const struct of_device_id clk_factors_match[] __initconst = {
 116 -       {.compatible = "allwinner,sun4i-pll1-clk", .data = &sun4i_pll1_data,},
 117 +       {.compatible = "allwinner,sun4i-a10-pll1-clk", .data = &sun4i_pll1_data,},
 118         {.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,},
 119         {.compatible = "allwinner,sun6i-a31-pll6-clk", .data = &sun6i_a31_pll6_data,},
 120 -       {.compatible = "allwinner,sun4i-apb1-clk", .data = &sun4i_apb1_data,},
 121 -       {.compatible = "allwinner,sun4i-mod0-clk", .data = &sun4i_mod0_data,},
 122 +       {.compatible = "allwinner,sun4i-a10-apb1-clk", .data = &sun4i_apb1_data,},
 123 +       {.compatible = "allwinner,sun4i-a10-mod0-clk", .data = &sun4i_mod0_data,},
 124         {.compatible = "allwinner,sun7i-a20-out-clk", .data = &sun7i_a20_out_data,},
 125         {}
 126  };
 127
 128  /* Matches for divider clocks */
 129  static const struct of_device_id clk_div_match[] __initconst = {
 130 -       {.compatible = "allwinner,sun4i-axi-clk", .data = &sun4i_axi_data,},
 131 -       {.compatible = "allwinner,sun4i-ahb-clk", .data = &sun4i_ahb_data,},
 132 -       {.compatible = "allwinner,sun4i-apb0-clk", .data = &sun4i_apb0_data,},
 133 +       {.compatible = "allwinner,sun4i-a10-axi-clk", .data = &sun4i_axi_data,},
 134 +       {.compatible = "allwinner,sun4i-a10-ahb-clk", .data = &sun4i_ahb_data,},
 135 +       {.compatible = "allwinner,sun4i-a10-apb0-clk", .data = &sun4i_apb0_data,},
 136         {.compatible = "allwinner,sun6i-a31-apb2-div-clk", .data = &sun6i_a31_apb2_div_data,},
 137         {}
 138  };
 139
 140  /* Matches for divided outputs */
 141  static const struct of_device_id clk_divs_match[] __initconst = {
 142 -       {.compatible = "allwinner,sun4i-pll5-clk", .data = &pll5_divs_data,},
 143 -       {.compatible = "allwinner,sun4i-pll6-clk", .data = &pll6_divs_data,},
 144 +       {.compatible = "allwinner,sun4i-a10-pll5-clk", .data = &pll5_divs_data,},
 145 +       {.compatible = "allwinner,sun4i-a10-pll6-clk", .data = &pll6_divs_data,},
 146         {}
 147  };
 148
 149  /* Matches for mux clocks */
 150  static const struct of_device_id clk_mux_match[] __initconst = {
 151 -       {.compatible = "allwinner,sun4i-cpu-clk", .data = &sun4i_cpu_mux_data,},
 152 -       {.compatible = "allwinner,sun4i-apb1-mux-clk", .data = &sun4i_apb1_mux_data,},
 153 +       {.compatible = "allwinner,sun4i-a10-cpu-clk", .data = &sun4i_cpu_mux_data,},
 154 +       {.compatible = "allwinner,sun4i-a10-apb1-mux-clk", .data = &sun4i_apb1_mux_data,},
 155         {.compatible = "allwinner,sun6i-a31-ahb1-mux-clk", .data = &sun6i_a31_ahb1_mux_data,},
 156         {}
 157  };
 158
 159  /* Matches for gate clocks */
 160  static const struct of_device_id clk_gates_match[] __initconst = {
 161 -       {.compatible = "allwinner,sun4i-axi-gates-clk", .data = &sun4i_axi_gates_data,},
 162 -       {.compatible = "allwinner,sun4i-ahb-gates-clk", .data = &sun4i_ahb_gates_data,},
 163 +       {.compatible = "allwinner,sun4i-a10-axi-gates-clk", .data = &sun4i_axi_gates_data,},
 164 +       {.compatible = "allwinner,sun4i-a10-ahb-gates-clk", .data = &sun4i_ahb_gates_data,},
 165         {.compatible = "allwinner,sun5i-a10s-ahb-gates-clk", .data = &sun5i_a10s_ahb_gates_data,},
 166         {.compatible = "allwinner,sun5i-a13-ahb-gates-clk", .data = &sun5i_a13_ahb_gates_data,},
 167         {.compatible = "allwinner,sun6i-a31-ahb1-gates-clk", .data = &sun6i_a31_ahb1_gates_data,},
 168         {.compatible = "allwinner,sun7i-a20-ahb-gates-clk", .data = &sun7i_a20_ahb_gates_data,},
 169 -       {.compatible = "allwinner,sun4i-apb0-gates-clk", .data = &sun4i_apb0_gates_data,},
 170 +       {.compatible = "allwinner,sun4i-a10-apb0-gates-clk", .data = &sun4i_apb0_gates_data,},
 171         {.compatible = "allwinner,sun5i-a10s-apb0-gates-clk", .data = &sun5i_a10s_apb0_gates_data,},
 172         {.compatible = "allwinner,sun5i-a13-apb0-gates-clk", .data = &sun5i_a13_apb0_gates_data,},
 173         {.compatible = "allwinner,sun7i-a20-apb0-gates-clk", .data = &sun7i_a20_apb0_gates_data,},
 174 -       {.compatible = "allwinner,sun4i-apb1-gates-clk", .data = &sun4i_apb1_gates_data,},
 175 +       {.compatible = "allwinner,sun4i-a10-apb1-gates-clk", .data = &sun4i_apb1_gates_data,},
 176         {.compatible = "allwinner,sun5i-a10s-apb1-gates-clk", .data = &sun5i_a10s_apb1_gates_data,},
 177         {.compatible = "allwinner,sun5i-a13-apb1-gates-clk", .data = &sun5i_a13_apb1_gates_data,},
 178         {.compatible = "allwinner,sun6i-a31-apb1-gates-clk", .data = &sun6i_a31_apb1_gates_data,},