target/linux/sunxi/patches-3.14/205-nmi-add-driver.patch

   1 From b9ad0253e6c68ac3d37fd2ed8ed9bf8a334e4b65 Mon Sep 17 00:00:00 2001
   2 From: Carlo Caione <carlo@caione.org>
   3 Date: Sat, 15 Mar 2014 14:40:59 +0100
   4 Subject: [PATCH] ARM: sun7i/sun6i: irqchip: Add irqchip driver for NMI
   5  controller
   6
   7 Allwinner A20/A31 SoCs have special registers to control / (un)mask /
   8 acknowledge NMI. This NMI controller is separated and independent from GIC.
   9 This patch adds a new irqchip to manage NMI.
  10
  11 Signed-off-by: Carlo Caione <carlo@caione.org>
  12 Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
  13 ---
  14  drivers/irqchip/Makefile        |   1 +
  15  drivers/irqchip/irq-sunxi-nmi.c | 208 ++++++++++++++++++++++++++++++++++++++++
  16  2 files changed, 209 insertions(+)
  17  create mode 100644 drivers/irqchip/irq-sunxi-nmi.c
  18
  19 --- a/drivers/irqchip/Makefile
  20 +++ b/drivers/irqchip/Makefile
  21 @@ -12,6 +12,7 @@ obj-$(CONFIG_METAG_PERFCOUNTER_IRQS)  +=
  22  obj-$(CONFIG_ARCH_MOXART)              += irq-moxart.o
  23  obj-$(CONFIG_ORION_IRQCHIP)            += irq-orion.o
  24  obj-$(CONFIG_ARCH_SUNXI)               += irq-sun4i.o
  25 +obj-$(CONFIG_ARCH_SUNXI)               += irq-sunxi-nmi.o
  26  obj-$(CONFIG_ARCH_SPEAR3XX)            += spear-shirq.o
  27  obj-$(CONFIG_ARM_GIC)                  += irq-gic.o
  28  obj-$(CONFIG_ARM_NVIC)                 += irq-nvic.o
  29 --- /dev/null
  30 +++ b/drivers/irqchip/irq-sunxi-nmi.c
  31 @@ -0,0 +1,208 @@
  32 +/*
  33 + * Allwinner A20/A31 SoCs NMI IRQ chip driver.
  34 + *
  35 + * Carlo Caione <carlo.caione@gmail.com>
  36 + *
  37 + * This file is licensed under the terms of the GNU General Public
  38 + * License version 2.  This program is licensed "as is" without any
  39 + * warranty of any kind, whether express or implied.
  40 + */
  41 +
  42 +#include <linux/bitops.h>
  43 +#include <linux/device.h>
  44 +#include <linux/io.h>
  45 +#include <linux/irq.h>
  46 +#include <linux/interrupt.h>
  47 +#include <linux/irqdomain.h>
  48 +#include <linux/of_irq.h>
  49 +#include <linux/of_address.h>
  50 +#include <linux/of_platform.h>
  51 +#include <linux/irqchip/chained_irq.h>
  52 +#include "irqchip.h"
  53 +
  54 +#define SUNXI_NMI_SRC_TYPE_MASK        0x00000003
  55 +
  56 +enum {
  57 +       SUNXI_SRC_TYPE_LEVEL_LOW = 0,
  58 +       SUNXI_SRC_TYPE_EDGE_FALLING,
  59 +       SUNXI_SRC_TYPE_LEVEL_HIGH,
  60 +       SUNXI_SRC_TYPE_EDGE_RISING,
  61 +};
  62 +
  63 +struct sunxi_sc_nmi_reg_offs {
  64 +       u32 ctrl;
  65 +       u32 pend;
  66 +       u32 enable;
  67 +};
  68 +
  69 +static struct sunxi_sc_nmi_reg_offs sun7i_reg_offs = {
  70 +       .ctrl   = 0x00,
  71 +       .pend   = 0x04,
  72 +       .enable = 0x08,
  73 +};
  74 +
  75 +static struct sunxi_sc_nmi_reg_offs sun6i_reg_offs = {
  76 +       .ctrl   = 0x00,
  77 +       .pend   = 0x04,
  78 +       .enable = 0x34,
  79 +};
  80 +
  81 +static inline void sunxi_sc_nmi_write(struct irq_chip_generic *gc, u32 off,
  82 +                                     u32 val)
  83 +{
  84 +       irq_reg_writel(val, gc->reg_base + off);
  85 +}
  86 +
  87 +static inline u32 sunxi_sc_nmi_read(struct irq_chip_generic *gc, u32 off)
  88 +{
  89 +       return irq_reg_readl(gc->reg_base + off);
  90 +}
  91 +
  92 +static void sunxi_sc_nmi_handle_irq(unsigned int irq, struct irq_desc *desc)
  93 +{
  94 +       struct irq_domain *domain = irq_desc_get_handler_data(desc);
  95 +       struct irq_chip *chip = irq_get_chip(irq);
  96 +       unsigned int virq = irq_find_mapping(domain, 0);
  97 +
  98 +       chained_irq_enter(chip, desc);
  99 +       generic_handle_irq(virq);
 100 +       chained_irq_exit(chip, desc);
 101 +}
 102 +
 103 +static int sunxi_sc_nmi_set_type(struct irq_data *data, unsigned int flow_type)
 104 +{
 105 +       struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
 106 +       struct irq_chip_type *ct = gc->chip_types;
 107 +       u32 src_type_reg;
 108 +       u32 ctrl_off = ct->regs.type;
 109 +       unsigned int src_type;
 110 +       unsigned int i;
 111 +
 112 +       irq_gc_lock(gc);
 113 +
 114 +       switch (flow_type & IRQF_TRIGGER_MASK) {
 115 +       case IRQ_TYPE_EDGE_FALLING:
 116 +               src_type = SUNXI_SRC_TYPE_EDGE_FALLING;
 117 +               break;
 118 +       case IRQ_TYPE_EDGE_RISING:
 119 +               src_type = SUNXI_SRC_TYPE_EDGE_RISING;
 120 +               break;
 121 +       case IRQ_TYPE_LEVEL_HIGH:
 122 +               src_type = SUNXI_SRC_TYPE_LEVEL_HIGH;
 123 +               break;
 124 +       case IRQ_TYPE_NONE:
 125 +       case IRQ_TYPE_LEVEL_LOW:
 126 +               src_type = SUNXI_SRC_TYPE_LEVEL_LOW;
 127 +               break;
 128 +       default:
 129 +               irq_gc_unlock(gc);
 130 +               pr_err("%s: Cannot assign multiple trigger modes to IRQ %d.\n",
 131 +                       __func__, data->irq);
 132 +               return -EBADR;
 133 +       }
 134 +
 135 +       irqd_set_trigger_type(data, flow_type);
 136 +       irq_setup_alt_chip(data, flow_type);
 137 +
 138 +       for (i = 0; i <= gc->num_ct; i++, ct++)
 139 +               if (ct->type & flow_type)
 140 +                       ctrl_off = ct->regs.type;
 141 +
 142 +       src_type_reg = sunxi_sc_nmi_read(gc, ctrl_off);
 143 +       src_type_reg &= ~SUNXI_NMI_SRC_TYPE_MASK;
 144 +       src_type_reg |= src_type;
 145 +       sunxi_sc_nmi_write(gc, ctrl_off, src_type_reg);
 146 +
 147 +       irq_gc_unlock(gc);
 148 +
 149 +       return IRQ_SET_MASK_OK;
 150 +}
 151 +
 152 +static int __init sunxi_sc_nmi_irq_init(struct device_node *node,
 153 +                                       struct sunxi_sc_nmi_reg_offs *reg_offs)
 154 +{
 155 +       struct irq_domain *domain;
 156 +       struct irq_chip_generic *gc;
 157 +       unsigned int irq;
 158 +       unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
 159 +       int ret;
 160 +
 161 +
 162 +       domain = irq_domain_add_linear(node, 1, &irq_generic_chip_ops, NULL);
 163 +       if (!domain) {
 164 +               pr_err("%s: Could not register interrupt domain.\n", node->name);
 165 +               return -ENOMEM;
 166 +       }
 167 +
 168 +       ret = irq_alloc_domain_generic_chips(domain, 1, 2, node->name,
 169 +                                            handle_fasteoi_irq, clr, 0,
 170 +                                            IRQ_GC_INIT_MASK_CACHE);
 171 +       if (ret) {
 172 +                pr_err("%s: Could not allocate generic interrupt chip.\n",
 173 +                        node->name);
 174 +                goto fail_irqd_remove;
 175 +       }
 176 +
 177 +       irq = irq_of_parse_and_map(node, 0);
 178 +       if (irq <= 0) {
 179 +               pr_err("%s: unable to parse irq\n", node->name);
 180 +               ret = -EINVAL;
 181 +               goto fail_irqd_remove;
 182 +       }
 183 +
 184 +       gc = irq_get_domain_generic_chip(domain, 0);
 185 +       gc->reg_base = of_iomap(node, 0);
 186 +       if (!gc->reg_base) {
 187 +               pr_err("%s: unable to map resource\n", node->name);
 188 +               ret = -ENOMEM;
 189 +               goto fail_irqd_remove;
 190 +       }
 191 +
 192 +       gc->chip_types[0].type                  = IRQ_TYPE_LEVEL_MASK;
 193 +       gc->chip_types[0].chip.irq_mask         = irq_gc_mask_clr_bit;
 194 +       gc->chip_types[0].chip.irq_unmask       = irq_gc_mask_set_bit;
 195 +       gc->chip_types[0].chip.irq_eoi          = irq_gc_ack_set_bit;
 196 +       gc->chip_types[0].chip.irq_set_type     = sunxi_sc_nmi_set_type;
 197 +       gc->chip_types[0].chip.flags            = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED;
 198 +       gc->chip_types[0].regs.ack              = reg_offs->pend;
 199 +       gc->chip_types[0].regs.mask             = reg_offs->enable;
 200 +       gc->chip_types[0].regs.type             = reg_offs->ctrl;
 201 +
 202 +       gc->chip_types[1].type                  = IRQ_TYPE_EDGE_BOTH;
 203 +       gc->chip_types[1].chip.name             = gc->chip_types[0].chip.name;
 204 +       gc->chip_types[1].chip.irq_ack          = irq_gc_ack_set_bit;
 205 +       gc->chip_types[1].chip.irq_mask         = irq_gc_mask_clr_bit;
 206 +       gc->chip_types[1].chip.irq_unmask       = irq_gc_mask_set_bit;
 207 +       gc->chip_types[1].chip.irq_set_type     = sunxi_sc_nmi_set_type;
 208 +       gc->chip_types[1].regs.ack              = reg_offs->pend;
 209 +       gc->chip_types[1].regs.mask             = reg_offs->enable;
 210 +       gc->chip_types[1].regs.type             = reg_offs->ctrl;
 211 +       gc->chip_types[1].handler               = handle_edge_irq;
 212 +
 213 +       sunxi_sc_nmi_write(gc, reg_offs->enable, 0);
 214 +       sunxi_sc_nmi_write(gc, reg_offs->pend, 0x1);
 215 +
 216 +       irq_set_handler_data(irq, domain);
 217 +       irq_set_chained_handler(irq, sunxi_sc_nmi_handle_irq);
 218 +
 219 +       return 0;
 220 +
 221 +fail_irqd_remove:
 222 +       irq_domain_remove(domain);
 223 +
 224 +       return ret;
 225 +}
 226 +
 227 +static int __init sun6i_sc_nmi_irq_init(struct device_node *node,
 228 +                                       struct device_node *parent)
 229 +{
 230 +       return sunxi_sc_nmi_irq_init(node, &sun6i_reg_offs);
 231 +}
 232 +IRQCHIP_DECLARE(sun6i_sc_nmi, "allwinner,sun6i-a31-sc-nmi", sun6i_sc_nmi_irq_init);
 233 +
 234 +static int __init sun7i_sc_nmi_irq_init(struct device_node *node,
 235 +                                       struct device_node *parent)
 236 +{
 237 +       return sunxi_sc_nmi_irq_init(node, &sun7i_reg_offs);
 238 +}
 239 +IRQCHIP_DECLARE(sun7i_sc_nmi, "allwinner,sun7i-a20-sc-nmi", sun7i_sc_nmi_irq_init);