target/linux/sunxi/patches-4.14/020-ARM-dts-sunxi-Restore-EMAC-changes-boards.patch

   1 From 4904337fe34fa7fc529d6f4d9ee8b96fe7db310a Mon Sep 17 00:00:00 2001
   2 From: Corentin Labbe <clabbe.montjoie@gmail.com>
   3 Date: Tue, 31 Oct 2017 09:19:12 +0100
   4 Subject: [PATCH] ARM: dts: sunxi: Restore EMAC changes (boards)
   5
   6 The original dwmac-sun8i DT bindings have some issue on how to handle
   7 integrated PHY and was reverted in last RC of 4.13.
   8 But now we have a solution so we need to get back that was reverted.
   9
  10 This patch restore all boards DT about dwmac-sun8i
  11 This reverts partially commit fe45174b72ae ("arm: dts: sunxi: Revert EMAC changes")
  12
  13 Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
  14 Acked-by: Florian Fainelli <f.fainelli@gmail.com>
  15 Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
  16 ---
  17  arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts |  9 +++++++
  18  arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts   | 19 +++++++++++++++
  19  arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts     | 29 +++++++++++++++++++++++
  20  arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts         |  7 ++++++
  21  arch/arm/boot/dts/sun8i-h3-orangepi-2.dts         |  8 +++++++
  22  arch/arm/boot/dts/sun8i-h3-orangepi-one.dts       |  8 +++++++
  23  arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts   |  5 ++++
  24  arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts        |  8 +++++++
  25  arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts      | 22 +++++++++++++++++
  26  arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts    | 16 +++++++++++++
  27  10 files changed, 131 insertions(+)
  28
  29 --- a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
  30 +++ b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
  31 @@ -56,6 +56,8 @@
  32
  33         aliases {
  34                 serial0 = &uart0;
  35 +               /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */
  36 +               ethernet0 = &emac;
  37                 ethernet1 = &xr819;
  38         };
  39
  40 @@ -102,6 +104,13 @@
  41         status = "okay";
  42  };
  43
  44 +&emac {
  45 +       phy-handle = <&int_mii_phy>;
  46 +       phy-mode = "mii";
  47 +       allwinner,leds-active-low;
  48 +       status = "okay";
  49 +};
  50 +
  51  &mmc0 {
  52         pinctrl-names = "default";
  53         pinctrl-0 = <&mmc0_pins_a>;
  54 --- a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
  55 +++ b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
  56 @@ -52,6 +52,7 @@
  57         compatible = "sinovoip,bpi-m2-plus", "allwinner,sun8i-h3";
  58
  59         aliases {
  60 +               ethernet0 = &emac;
  61                 serial0 = &uart0;
  62                 serial1 = &uart1;
  63         };
  64 @@ -114,6 +115,24 @@
  65         status = "okay";
  66  };
  67
  68 +&emac {
  69 +       pinctrl-names = "default";
  70 +       pinctrl-0 = <&emac_rgmii_pins>;
  71 +       phy-supply = <&reg_gmac_3v3>;
  72 +       phy-handle = <&ext_rgmii_phy>;
  73 +       phy-mode = "rgmii";
  74 +
  75 +       allwinner,leds-active-low;
  76 +       status = "okay";
  77 +};
  78 +
  79 +&external_mdio {
  80 +       ext_rgmii_phy: ethernet-phy@1 {
  81 +               compatible = "ethernet-phy-ieee802.3-c22";
  82 +               reg = <0>;
  83 +       };
  84 +};
  85 +
  86  &ir {
  87         pinctrl-names = "default";
  88         pinctrl-0 = <&ir_pins_a>;
  89 --- a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
  90 +++ b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
  91 @@ -45,6 +45,16 @@
  92  / {
  93         model = "FriendlyArm NanoPi M1 Plus";
  94         compatible = "friendlyarm,nanopi-m1-plus", "allwinner,sun8i-h3";
  95 +
  96 +       reg_gmac_3v3: gmac-3v3 {
  97 +               compatible = "regulator-fixed";
  98 +               regulator-name = "gmac-3v3";
  99 +               regulator-min-microvolt = <3300000>;
 100 +               regulator-max-microvolt = <3300000>;
 101 +               startup-delay-us = <100000>;
 102 +               enable-active-high;
 103 +               gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
 104 +       };
 105  };
 106
 107  &ehci1 {
 108 @@ -55,6 +65,25 @@
 109         status = "okay";
 110  };
 111
 112 +&emac {
 113 +       pinctrl-names = "default";
 114 +       pinctrl-0 = <&emac_rgmii_pins>;
 115 +       phy-supply = <&reg_gmac_3v3>;
 116 +       phy-handle = <&ext_rgmii_phy>;
 117 +       phy-mode = "rgmii";
 118 +
 119 +       allwinner,leds-active-low;
 120 +
 121 +       status = "okay";
 122 +};
 123 +
 124 +&external_mdio {
 125 +       ext_rgmii_phy: ethernet-phy@1 {
 126 +               compatible = "ethernet-phy-ieee802.3-c22";
 127 +               reg = <7>;
 128 +       };
 129 +};
 130 +
 131  &ohci1 {
 132         status = "okay";
 133  };
 134 --- a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
 135 +++ b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
 136 @@ -46,3 +46,10 @@
 137         model = "FriendlyARM NanoPi NEO";
 138         compatible = "friendlyarm,nanopi-neo", "allwinner,sun8i-h3";
 139  };
 140 +
 141 +&emac {
 142 +       phy-handle = <&int_mii_phy>;
 143 +       phy-mode = "mii";
 144 +       allwinner,leds-active-low;
 145 +       status = "okay";
 146 +};
 147 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
 148 +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
 149 @@ -54,6 +54,7 @@
 150         aliases {
 151                 serial0 = &uart0;
 152                 /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */
 153 +               ethernet0 = &emac;
 154                 ethernet1 = &rtl8189;
 155         };
 156
 157 @@ -117,6 +118,13 @@
 158         status = "okay";
 159  };
 160
 161 +&emac {
 162 +       phy-handle = <&int_mii_phy>;
 163 +       phy-mode = "mii";
 164 +       allwinner,leds-active-low;
 165 +       status = "okay";
 166 +};
 167 +
 168  &ir {
 169         pinctrl-names = "default";
 170         pinctrl-0 = <&ir_pins_a>;
 171 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
 172 +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
 173 @@ -52,6 +52,7 @@
 174         compatible = "xunlong,orangepi-one", "allwinner,sun8i-h3";
 175
 176         aliases {
 177 +               ethernet0 = &emac;
 178                 serial0 = &uart0;
 179         };
 180
 181 @@ -97,6 +98,13 @@
 182         status = "okay";
 183  };
 184
 185 +&emac {
 186 +       phy-handle = <&int_mii_phy>;
 187 +       phy-mode = "mii";
 188 +       allwinner,leds-active-low;
 189 +       status = "okay";
 190 +};
 191 +
 192  &mmc0 {
 193         pinctrl-names = "default";
 194         pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
 195 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts
 196 +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts
 197 @@ -53,6 +53,11 @@
 198         };
 199  };
 200
 201 +&emac {
 202 +       /* LEDs changed to active high on the plus */
 203 +       /delete-property/ allwinner,leds-active-low;
 204 +};
 205 +
 206  &mmc1 {
 207         pinctrl-names = "default";
 208         pinctrl-0 = <&mmc1_pins_a>;
 209 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
 210 +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
 211 @@ -52,6 +52,7 @@
 212         compatible = "xunlong,orangepi-pc", "allwinner,sun8i-h3";
 213
 214         aliases {
 215 +               ethernet0 = &emac;
 216                 serial0 = &uart0;
 217         };
 218
 219 @@ -113,6 +114,13 @@
 220         status = "okay";
 221  };
 222
 223 +&emac {
 224 +       phy-handle = <&int_mii_phy>;
 225 +       phy-mode = "mii";
 226 +       allwinner,leds-active-low;
 227 +       status = "okay";
 228 +};
 229 +
 230  &ir {
 231         pinctrl-names = "default";
 232         pinctrl-0 = <&ir_pins_a>;
 233 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
 234 +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
 235 @@ -47,6 +47,10 @@
 236         model = "Xunlong Orange Pi Plus / Plus 2";
 237         compatible = "xunlong,orangepi-plus", "allwinner,sun8i-h3";
 238
 239 +       aliases {
 240 +               ethernet0 = &emac;
 241 +       };
 242 +
 243         reg_gmac_3v3: gmac-3v3 {
 244                 compatible = "regulator-fixed";
 245                 regulator-name = "gmac-3v3";
 246 @@ -74,6 +78,24 @@
 247         status = "okay";
 248  };
 249
 250 +&emac {
 251 +       pinctrl-names = "default";
 252 +       pinctrl-0 = <&emac_rgmii_pins>;
 253 +       phy-supply = <&reg_gmac_3v3>;
 254 +       phy-handle = <&ext_rgmii_phy>;
 255 +       phy-mode = "rgmii";
 256 +
 257 +       allwinner,leds-active-low;
 258 +       status = "okay";
 259 +};
 260 +
 261 +&external_mdio {
 262 +       ext_rgmii_phy: ethernet-phy@1 {
 263 +               compatible = "ethernet-phy-ieee802.3-c22";
 264 +               reg = <0>;
 265 +       };
 266 +};
 267 +
 268  &mmc2 {
 269         pinctrl-names = "default";
 270         pinctrl-0 = <&mmc2_8bit_pins>;
 271 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts
 272 +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts
 273 @@ -61,3 +61,19 @@
 274                 gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */
 275         };
 276  };
 277 +
 278 +&emac {
 279 +       pinctrl-names = "default";
 280 +       pinctrl-0 = <&emac_rgmii_pins>;
 281 +       phy-supply = <&reg_gmac_3v3>;
 282 +       phy-handle = <&ext_rgmii_phy>;
 283 +       phy-mode = "rgmii";
 284 +       status = "okay";
 285 +};
 286 +
 287 +&external_mdio {
 288 +       ext_rgmii_phy: ethernet-phy@1 {
 289 +               compatible = "ethernet-phy-ieee802.3-c22";
 290 +               reg = <1>;
 291 +       };
 292 +};