x86: Add sp5100_tco AMD patches
[openwrt/openwrt.git] / target / linux / x86 / patches-4.4 / 097-0003-sp5100_tco-fix-the-device-check-for-SB800-and-later-chipsets.patch
1 From bdecfcdb5461834aab24002bb18d3cbdd907b7fb Mon Sep 17 00:00:00 2001
2 From: Huang Rui <ray.huang@amd.com>
3 Date: Mon, 23 Nov 2015 18:07:35 +0800
4 Subject: [PATCH] sp5100_tco: fix the device check for SB800 and later chipsets
5
6 For SB800 and later chipsets, the register definitions are the same
7 with SB800. And for SB700 and older chipsets, the definitions should
8 be same with SP5100/SB7x0.
9
10 Signed-off-by: Huang Rui <ray.huang@amd.com>
11 Cc: Denis Turischev <denis.turischev@compulab.co.il>
12 Signed-off-by: Guenter Roeck <linux@roeck-us.net>
13 Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
14 ---
15 drivers/watchdog/sp5100_tco.c | 28 ++++++++++++++++------------
16 1 file changed, 16 insertions(+), 12 deletions(-)
17
18 diff --git a/drivers/watchdog/sp5100_tco.c b/drivers/watchdog/sp5100_tco.c
19 index 0ccadb4..6467b91 100644
20 --- a/drivers/watchdog/sp5100_tco.c
21 +++ b/drivers/watchdog/sp5100_tco.c
22 @@ -335,21 +335,24 @@ static unsigned char sp5100_tco_setupdevice(void)
23 if (!sp5100_tco_pci)
24 return 0;
25
26 - pr_info("PCI Revision ID: 0x%x\n", sp5100_tco_pci->revision);
27 + pr_info("PCI Vendor ID: 0x%x, Device ID: 0x%x, Revision ID: 0x%x\n",
28 + sp5100_tco_pci->vendor, sp5100_tco_pci->device,
29 + sp5100_tco_pci->revision);
30
31 /*
32 * Determine type of southbridge chipset.
33 */
34 - if (sp5100_tco_pci->revision >= 0x40) {
35 - dev_name = SB800_DEVNAME;
36 - index_reg = SB800_IO_PM_INDEX_REG;
37 - data_reg = SB800_IO_PM_DATA_REG;
38 - base_addr = SB800_PM_WATCHDOG_BASE;
39 - } else {
40 + if (sp5100_tco_pci->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS &&
41 + sp5100_tco_pci->revision < 0x40) {
42 dev_name = SP5100_DEVNAME;
43 index_reg = SP5100_IO_PM_INDEX_REG;
44 data_reg = SP5100_IO_PM_DATA_REG;
45 base_addr = SP5100_PM_WATCHDOG_BASE;
46 + } else {
47 + dev_name = SB800_DEVNAME;
48 + index_reg = SB800_IO_PM_INDEX_REG;
49 + data_reg = SB800_IO_PM_DATA_REG;
50 + base_addr = SB800_PM_WATCHDOG_BASE;
51 }
52
53 /* Request the IO ports used by this driver */
54 @@ -385,7 +388,12 @@ static unsigned char sp5100_tco_setupdevice(void)
55 * Secondly, Find the watchdog timer MMIO address
56 * from SBResource_MMIO register.
57 */
58 - if (sp5100_tco_pci->revision >= 0x40) {
59 + if (sp5100_tco_pci->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS &&
60 + sp5100_tco_pci->revision < 0x40) {
61 + /* Read SBResource_MMIO from PCI config(PCI_Reg: 9Ch) */
62 + pci_read_config_dword(sp5100_tco_pci,
63 + SP5100_SB_RESOURCE_MMIO_BASE, &val);
64 + } else {
65 /* Read SBResource_MMIO from AcpiMmioEn(PM_Reg: 24h) */
66 outb(SB800_PM_ACPI_MMIO_EN+3, SB800_IO_PM_INDEX_REG);
67 val = inb(SB800_IO_PM_DATA_REG);
68 @@ -395,10 +403,6 @@ static unsigned char sp5100_tco_setupdevice(void)
69 val = val << 8 | inb(SB800_IO_PM_DATA_REG);
70 outb(SB800_PM_ACPI_MMIO_EN+0, SB800_IO_PM_INDEX_REG);
71 val = val << 8 | inb(SB800_IO_PM_DATA_REG);
72 - } else {
73 - /* Read SBResource_MMIO from PCI config(PCI_Reg: 9Ch) */
74 - pci_read_config_dword(sp5100_tco_pci,
75 - SP5100_SB_RESOURCE_MMIO_BASE, &val);
76 }
77
78 /* The SBResource_MMIO is enabled and mapped memory space? */
79 --
80 2.7.4