#define OM2P_GPIO_LED_YELLOW 15
#define OM2P_GPIO_LED_LAN 16
#define OM2P_GPIO_LED_WAN 17
-#define OM2P_GPIO_BTN_RESET 11
+#define OM2P_GPIO_BTN_RESET 1
#define OM2P_KEYS_POLL_INTERVAL 20 /* msecs */
#define OM2P_KEYS_DEBOUNCE_INTERVAL (3 * OM2P_KEYS_POLL_INTERVAL)
ARRAY_SIZE(om2p_gpio_keys),
om2p_gpio_keys);
- ath79_init_mac(ath79_eth1_data.mac_addr, mac1, 0);
- ath79_init_mac(ath79_eth0_data.mac_addr, mac2, 0);
+ ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0);
+ ath79_init_mac(ath79_eth1_data.mac_addr, mac2, 0);
ath79_register_mdio(0, 0x0);
}
MIPS_MACHINE(ATH79_MACH_OM2P_LC, "OM2P-LC", "OpenMesh OM2P LC", om2p_lc_setup);
-
-
-static void __init om2p_hs_gmac_setup(void)
-{
- void __iomem *base;
- u32 t;
-
- base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE);
-
- t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
-
- t &= ~(AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_MII_GMAC0 |
- AR934X_ETH_CFG_GMII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE |
- AR934X_ETH_CFG_SW_PHY_SWAP);
-
- t |= AR934X_ETH_CFG_SW_PHY_SWAP;
- __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG);
- t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
-
- iounmap(base);
-}
+MIPS_MACHINE(ATH79_MACH_OM2Pv2, "OM2Pv2", "OpenMesh OM2Pv2", om2p_lc_setup);
static void __init om2p_hs_setup(void)
{
/* enable reset button */
ath79_gpio_output_select(OM2P_GPIO_BTN_RESET, AR934X_GPIO_OUT_GPIO);
- ath79_gpio_function_enable(AR933X_GPIO_FUNC_JTAG_DISABLE);
+ ath79_gpio_function_enable(AR934X_GPIO_FUNC_JTAG_DISABLE);
om2p_leds_gpio[4].gpio = OM2P_GPIO_LED_WAN;
om2p_leds_gpio[5].gpio = OM2P_GPIO_LED_LAN;
ath79_register_wmac(art, NULL);
- om2p_hs_gmac_setup();
+ ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_PHY_SWAP);
ath79_register_mdio(1, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0);
}
MIPS_MACHINE(ATH79_MACH_OM2P_HS, "OM2P-HS", "OpenMesh OM2P HS", om2p_hs_setup);
+MIPS_MACHINE(ATH79_MACH_OM2P_HSv2, "OM2P-HSv2", "OpenMesh OM2P HSv2", om2p_hs_setup);
+MIPS_MACHINE(ATH79_MACH_OM2P_HSv3, "OM2P-HSv3", "OpenMesh OM2P HSv3", om2p_hs_setup);