Revert "ar71xx: fix Archer C7 LED colour names"

[openwrt/openwrt.git] / target / linux / ar71xx / files / arch / mips / ath79 / mach-om5p.c

diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-om5p.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-om5p.c
index 7f1d8117588168a6d02e0fdfadb330345bd01cd7..49acd3b67f659ed7ce54d1ea29dac78d609feae5 100644 (file)
--- a/target/linux/ar71xx/files/arch/mips/ath79/mach-om5p.c
+++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-om5p.c
@@ -16,6 +16,7 @@
 #include <linux/i2c.h>
 #include <linux/i2c-algo-bit.h>
 #include <linux/i2c-gpio.h>
+#include <linux/platform_data/phy-at803x.h>
 
 #include <asm/mach-ath79/ar71xx_regs.h>
 #include <asm/mach-ath79/ath79.h>
@@ -150,6 +151,20 @@ static struct i2c_board_info om5pan_i2c_devs[] __initdata = {
        },
 };
 
+static struct at803x_platform_data om5p_an_at803x_data = {
+       .disable_smarteee = 1,
+       .enable_rgmii_rx_delay = 1,
+       .enable_rgmii_tx_delay = 1,
+};
+
+static struct mdio_board_info om5p_an_mdio0_info[] = {
+       {
+               .bus_id = "ag71xx-mdio.0",
+               .phy_addr = 7,
+               .platform_data = &om5p_an_at803x_data,
+       },
+};
+
 static void __init om5p_an_setup(void)
 {
        u8 *art = (u8 *)KSEG1ADDR(0x1fff0000);
@@ -172,9 +187,13 @@ static void __init om5p_an_setup(void)
        ath79_register_wmac(art + OM5P_WMAC_CALDATA_OFFSET, mac);
 
        ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0);
+       ath79_setup_ar934x_eth_rx_delay(2, 2);
        ath79_register_mdio(0, 0x0);
        ath79_register_mdio(1, 0x0);
 
+       mdiobus_register_board_info(om5p_an_mdio0_info,
+                                   ARRAY_SIZE(om5p_an_mdio0_info));
+
        ath79_init_mac(ath79_eth0_data.mac_addr, art, 0x00);
        ath79_init_mac(ath79_eth1_data.mac_addr, art, 0x01);
 
@@ -182,7 +201,7 @@ static void __init om5p_an_setup(void)
        ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
        ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
        ath79_eth0_data.phy_mask = BIT(7);
-       ath79_eth0_pll_data.pll_1000 = 0x1a000000;
+       ath79_eth0_pll_data.pll_1000 = 0x02000000;
        ath79_eth0_pll_data.pll_100 = 0x00000101;
        ath79_eth0_pll_data.pll_10 = 0x00001313;
        ath79_register_eth(0);